LH28F008SC-V/SCH-V LH28F008SC-V/SCH-V 8 M-bit (1 MB x 8) Smart 5 Flash Memories DESCRIPTION The LH28F008SC-V/SCH-V flash memories with Smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SC-V/SCH-V offer three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. FEATURES • Smart 5 technology – 5 V VCC – 5 V or 12 V VPP • High performance read access time LH28F008SC-V85/SCH-V85 – 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V) LH28F008SC-V12/SCH-V12 – 120 ns (5.0±0.5 V) • Enhanced automated suspend options – Byte write suspend to read – Block erase suspend to byte write – Block erase suspend to read • Enhanced data protection features – Absolute protection with VPP = GND – Flexible block locking – Block erase/byte write lockout during power transitions • SRAM-compatible write interface • High-density symmetrically-blocked architecture – Sixteen 64 k-byte erasable blocks • Enhanced cycling capability – 100 000 block erase cycles – 1.6 million block erase cycles/chip • Low power management – Deep power-down mode – Automatic power saving mode decreases ICC in static mode • Automated byte write and block erase – Command user interface – Status register • ETOXTM∗ V nonvolatile flash technology • Packages – 40-pin TSOP Type I (TSOP040-P-1020) Normal bend/Reverse bend – 44-pin SOP (SOP044-P-0600) – 48-ball CSP (FBGA048-P-0608) ∗ ETOX is a trademark of Intel Corporation. COMPARISON TABLE VERSIONS LH28F008SC-V LH28F008SCH-V OPERATING TEMPERATURE DC CHARACTERISTICS VCC deep power-down current (MAX.) 0 to +70˚C 10 µA –25 to +85˚C 20 µA In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. -1- LH28F008SC-V/SCH-V PIN CONNECTIONS 40-PIN TSOP (Type I) A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 TOP VIEW 44-PIN SOP 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 GND GND (TSOP040-P-1020) 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 (SOP044-P-0600) NOTE : Reverse bend available on request. 48-BALL CSP 1 2 3 4 5 6 7 8 A A5 A8 A11 VPP VCC A12 A15 A18 B A6 A9 RP# NC NC CE# A14 A17 C A4 A7 A10 NC NC A13 A16 A19 D A3 A0 DQ2 NC NC DQ6 RY/BY# NC E A1 DQ1 GND NC NC DQ4 DQ7 OE# F A2 DQ0 DQ3 GND VCC DQ5 NC WE# (FBGA048-P-0608) -2- VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC LH28F008SC-V/SCH-V BLOCK DIAGRAM DQ0-DQ7 INPUT BUFFER I/O LOGIC IDENTIFIER REGISTER STATUS REGISTER DATA REGISTER OUTPUT MULTIPLEXER OUTPUT BUFFER CE# WE# COMMAND USER INTERFACE OE# RP# DATA COMPARATOR A0-A19 INPUT BUFFER ADDRESS LATCH Y DECODER X DECODER Y GATING 16 64 k-BYTE BLOCKS ADDRESS COUNTER -3- VCC WRITE STATE MACHINE RY/BY# PROGRAM/ERASE VOLTAGE SWITCH VPP VCC GND LH28F008SC-V/SCH-V PIN DESCRIPTION SYMBOL TYPE A0-A19 INPUT NAME AND FUNCTION ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs DQ0-DQ7 INPUT/ OUTPUT data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense CE# INPUT amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provide data protection during power transitions. Exit from deep RP# INPUT power-down sets the device to read array mode. RP# at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIH ≤ RP# ≤ VHH produce spurious results and should not be attempted. OE# INPUT WE# INPUT OUTPUT ENABLE : Gates the device's outputs during a read cycle. WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, byte write, or lock-bit configuration). RY/BY# OUTPUT RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For VPP SUPPLY erasing array blocks, writing bytes, or configuring lock-bits. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase, byte write, and lock-bit configuration with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation. VCC SUPPLY GND SUPPLY NC Do not float any power pins. With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. GROUND : Do not float any ground pins. NO CONNECT : Lead is not internal connected; recommend to be floated. -4- LH28F008SC-V/SCH-V 1 INTRODUCTION This datasheet contains LH28F008SC-V/SCH-V specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SC-V/ SCH-V flash memories documentation also includes ordering information which is referenced in Section 7. 1.1 New Features LH28F008SC-V/SCH-V Smart 5 flash memories maintain backwards-compatibility with the LH28F008SA. Key enhancements over the LH28F008SA include : Smart 5 technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. VPP at 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK. Table 1 VCC and VPP Voltage Combinations Offered by Smart 5 Technology • Smart 5 Technology • Enhanced Suspend Capabilities • In-System Block Locking Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the LH28F008SA to LH28F008SC-V/SCH-V. When upgrading, it is important to note the following differences : • Because of new feature support, the two devices have different device codes. This allows for software optimization. • VPPLK has been lowered from 6.5 V to 1.5 V to support 5 V block erase, byte write, and lock-bit configuration operations. Designs that switch VPP off during read operations should make sure that the VPP voltage transitions to GND. • To take advantage of Smart 5 technology, allow VPP connection to 5 V. 1.2 erasable, lockable, and unlockable in-system. The memory map is shown in Fig.1. Product Overview The LH28F008SC-V/SCH-V are high-performance 8 M-bit Smart 5 flash memories organized as 1 Mbyte of 8 bits. The 1 M-byte of data is arranged in sixteen 64 k-byte blocks which are individually -5- VCC VOLTAGE VPP VOLTAGE 5V 5 V, 12 V Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the device’s 64 k-byte blocks typically within 1 second (5 V VCC, 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. Writing memory data is performed in byte increments typically within 6 µs (5 V VCC, 12 V VPP). Byte write suspend mode enables the system LH28F008SC-V/SCH-V to read data from, or write data to any other flash memory array location. Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM’s block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF The access time is 85 ns (tAVQV) at the VCC supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70˚C (LH28F008SC-V)/ –25 to +85˚C (LH28F008SCH-V). At 4.5 to 5.5 V VCC, the access time is 90 ns or 120 ns. 40000 3FFFF 30000 2FFFF 20000 1FFFF The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC. -6- 10000 0FFFF 64 k-Byte Block 15 64 k-Byte Block 14 64 k-Byte Block 13 64 k-Byte Block 12 64 k-Byte Block 11 64 k-Byte Block 10 64 k-Byte Block 9 64 k-Byte Block 8 64 k-Byte Block 7 64 k-Byte Block 6 64 k-Byte Block 5 64 k-Byte Block 4 64 k-Byte Block 3 64 k-Byte Block 2 64 k-Byte Block 1 64 k-Byte Block 0 00000 Fig. 1 Memory Map LH28F008SC-V/SCH-V 2 PRINCIPLES OF OPERATION The LH28F008SC-V/SCH-V Smart 5 flash memories include an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contents—block erase, byte write, lock-bit configuration, status, and identifier codes—are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system -7- software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. 2.1 Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to VPPH1/2. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. 3 BUS OPERATION The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep powerdown mode, the device automatically resets to read LH28F008SC-V/SCH-V array mode. Four control pins dictate the data flow in and out of the component : CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 12 illustrates a read cycle. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ7 are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at VIL initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. -8- During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. LH28F008SC-V/SCH-V 3.5 Read Identifier Codes Operation 3.6 The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. FFFFF F0004 Reserved for Future Implementation F0003 F0002 F0001 F0000 The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 13 and Fig. 14 illustrate WE# and CE#-controlled write operations. Reserved for Future Implementation Block 15 1FFFF Reserved for Future Implementation 10003 10002 Block 1 Lock Configuration Code 10001 Reserved for Future Implementation 10000 Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VPP = VPPH1/2, the CUI additionally controls block erasure, byte write, and lock-bit configuration. Block 15 Lock Configuration Code (Blocks 2 through 14) 10004 Write 4 COMMAND DEFINITIONS When the VPP voltage ≤ VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2 on VPP enables successful block erase, byte write and lock-bit configuration operations. Block 1 0FFFF Reserved for Future Implementation 00004 00003 Master Lock Configuration Code 00002 Block 0 Lock Configuration Code 00001 Device Code 00000 Manufacture Code Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Block 0 Fig. 2 Device Identifier Code Memory Map -9- LH28F008SC-V/SCH-V Table 2 Bus Operations MODE Read NOTE RP# 1, 2, 3, 8 VIH or VHH CE# VIL OE# VIL WE# VIH ADDRESS X VPP X DQ0-7 DOUT RY/BY# X X Output Disable 3 VIH or VHH VIL VIH VIH X X High Z Standby 3 VIH or VHH VIH X X X X High Z X Deep Power-Down 4 VIL X X X X X High Z VOH VIL VIL VIL VIH VIH VIL See Fig. 2 X X X (NOTE 5) DIN VOH X Read Identifier Codes Write 8 VIH or VHH 3, 6, 7, 8 VIH or VHH NOTES : 1. 2. 3. Refer to Section 6.2.3 "DC CHARACTERISTICS". When VPP ≤ VPPLK, memory contents can be read, but not altered. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2 voltages. RY/BY# is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. 4. 5. 6. 7. 8. - 10 - RP# at GND±0.2 V ensures the lowest deep powerdown current. See Section 4.2 for read identifier code data. Command writes involving block erase, byte write, or lock-bit configuration are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2. Block erase, byte write, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted. Refer to Table 3 for valid DIN during a write operation. Don’t use the timing both OE# and WE# are VIL. LH28F008SC-V/SCH-V Table 3 Command Definitions (NOTE 9) COMMAND Read Array/Reset BUS CYCLES REQ’D. 1 NOTE FIRST BUS CYCLE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Write X FFH Write Write X X 90H 70H Write X 50H SECOND BUS CYCLE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Read Identifier Codes Read Status Register ≥2 2 Clear Status Register 1 Block Erase 2 5 Write BA 20H Byte Write 2 5, 6 Write WA 40H or 10H Block Erase and Byte Write Suspend 1 5 Write X B0H 1 5 Write X D0H 2 7 Write BA 60H Write BA 01H 2 2 7 8 Write Write X X 60H 60H Write Write X X F1H D0H Block Erase and Byte Write Resume Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bits 4 Read Read IA X ID SRD Write BA D0H Write WA WD NOTES : 1. 2. 3. 4. 5. Bus operations are defined in Table 2. X = Any valid address within the device. IA = Identifier code address : see Fig. 2. BA = Address within the block being erased or locked. WA = Address of memory location to be written. SRD = Data read from status register. See Table 6 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and master lock codes. See Section 4.2 for read identifier code data. If the block is locked, RP# must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is VIH. 6. 7. 8. 9. - 11 - Either 40H or 10H is recognized by the WSM as the byte write setup. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LH28F008SC-V/SCH-V 4.1 Read Array Command 4.3 Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH. 4.2 The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RP# can be VIH or VHH. Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and master lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read : CODE Manufacture Code Device Code Block Lock Configuration • Block is Unlocked • Block is Locked • Reserved for Future Use Master Lock Configuration • Device is Unlocked • Device is Locked • Reserved for Future Use ADDRESS 00000H 00001H X0002H (NOTE 1) 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or byte write suspend modes. Table 4 Identifier Codes DATA 89 A6 DQ0 = 0 DQ0 = 1 DQ1-7 4.5 00003H DQ0 = 0 DQ0 = 1 DQ1-7 NOTE : 1. Read Status Register Command X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map. Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, - 12 - LH28F008SC-V/SCH-V the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to "1". Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.6 Byte Write Command Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the byte write and write verify algorithms internally. After the byte write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the completion of the byte write event by analyzing the RY/BY# pin or status register bit SR.7. When byte write is complete, status register bit SR.4 should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable byte writes can only occur when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, memory contents are protected against byte writes. If byte write is attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful byte write requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If byte write is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1". Byte write operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block erase interruption to read or byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte - 13 - LH28F008SC-V/SCH-V Write Suspend command (see Section 4.8), a byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 5). VPP must remain at VPPH1/2 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until byte write operations initiated during block erase suspend have completed. 4.8 Byte Write Suspend Command The Byte Write Suspend command allows byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH1 defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Fig. 6). VPP must remain at VPPH1/2 (the same VPP level used for byte write) while in byte write suspend mode. RP# must also remain at VIH or VHH (the same RP# level used for byte write). 4.9 Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are executed by a two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Fig. 7). The CPU can detect the completion of the set lockbit event by analyzing the RY/BY# pin output or status register bit SR.7. - 14 - LH28F008SC-V/SCH-V When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. written, the device automatically outputs status register data when read (see Fig. 8). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VCC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, lock-bit contents are protected against alteration. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP# = VHH. If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block LockBits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VCC = VCC1/2 and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are protected against alteration. A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPP or VCC transition out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lockbits setup is first written. After the command is - 15 - LH28F008SC-V/SCH-V Table 5 Write Protection Alternatives OPERATION MASTER BLOCK RP# LOCK-BIT LOCK-BIT Block Erase or Byte Write Set Block Lock-Bit Set Master Lock-Bit Clear Block Lock-Bits 0 X VIH or VHH Block Erase and Byte Write Enabled VIH VHH 1 0 X 1 X X X 0 X 1 X EFFECT Block is Locked. Block Erase and Byte Write Disabled Block Lock-Bit Override. Block Erase and Byte Write Enabled VIH or VHH Set Block Lock-Bit Enabled VIH VHH Master Lock-Bit is Set. Set Block Lock-Bit Disabled VIH Set Master Lock-Bit Disabled VHH Set Master Lock-Bit Enabled Master Lock-Bit Override. Set Block Lock-Bit Enabled VIH or VHH Clear Block Lock-Bits Enabled VIH VHH Master Lock-Bit is Set. Clear Block Lock-Bits Disabled Master Lock-Bit Override. Clear Block Lock-Bits Enabled Table 6 Status Register Definition WSMS 7 ESS 6 ECLBS 5 BWSLBS 4 VPPS 3 BWSS 2 DPS 1 R 0 NOTES : SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready Check RY/BY# or SR.7 to determine block erase, byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0". 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) 1 = Error in Block Erase or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS (BWSLBS) 1 = Error in Byte Write or Set Master/Block Lock-Bit 0 = Successful Byte Write or Set Master/Block Lock-Bit SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPP ≠ VPPH1/2. SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lockbit, block lock-bit, and RP# only after Block Erase, Byte Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not VHH. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = BYTE WRITE SUSPEND STATUS (BWSS) 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock SR.0 is reserved for future use and should be masked out Detected, Operation Abort when polling the status register. 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) - 16 - LH28F008SC-V/SCH-V BUS OPERATION COMMAND Start Write 20H, Block Address Write D0H, Block Address Read Status Register No 0 Suspend Block Erase Loop Suspend Block Erase SR.7 = Yes 1 COMMENTS Write Erase Setup Data = 20H Addr = Within Block to be Erased Write Erase Confirm Data = D0H Addr = Within Block to be Erased Read Status Register Data Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last block erase operation to place device in read array mode. Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = 1 BUS OPERATION COMMAND SR.1 = 1 Standby Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error VPP Range Error 0 Device Protect Error 0 SR.4, 5 = 1 Command Sequence Error 0 SR.5 = 1 Block Erase Error COMMENTS SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. 0 Block Erase Successful Fig. 3 Automated Block Erase Flowchart - 17 - LH28F008SC-V/SCH-V BUS OPERATION COMMAND Start Write 40H, Address Write Byte Data and Address Read Status Register No 0 Suspend Byte Write Loop Suspend Byte Write SR.7 = Yes COMMENTS Write Setup Byte Write Data = 40H Addr = Location to be Written Write Byte Write Data = Data to be Written Addr = Location to be Written Read Status Register Data Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Repeat for subsequent byte writes. SR full status check can be done after each byte write or after a sequence of byte writes. Write FFH after the last byte write operation to place device in read array mode. 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = 1 BUS OPERATION COMMAND SR.1 = 1 Standby Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Standby Check SR.4 1 = Data Write Error VPP Range Error 0 Device Protect Error 0 SR.4 = 0 1 Byte Write Error COMMENTS SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. Byte Write Successful Fig. 4 Automated Byte Write Flowchart - 18 - LH28F008SC-V/SCH-V BUS OPERATION Start Write Write B0H Read Status Register SR.7 = 0 1 SR.6 = Erase Suspend Data = B0H Addr = X Read Status Register Data Addr = X Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Write 0 COMMENTS COMMAND Erase Resume Data = D0H Addr = X Block Erase Completed 1 Read Read or Byte Write? Read Array Data Byte Write Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Fig. 5 Block Erase Suspend/Resume Flowchart - 19 - LH28F008SC-V/SCH-V BUS OPERATION Start Write Write B0H Read Status Register 0 SR.7 = 1 SR.2 = Byte Write Completed 1 Byte Write Suspend Data = B0H Addr = X Read Status Register Data Addr = X Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 = Byte Write Suspended 0 = Byte Write Completed Write 0 COMMENTS COMMAND Read Array Read array locations other than that being written. Read Write Data = FFH Addr = X Byte Write Resume Data = D0H Addr = X Write FFH Read Array Data Done Reading No Yes Write D0H Write FFH Byte Write Resumed Read Array Data Fig. 6 Byte Write Suspend/Resume Flowchart - 20 - LH28F008SC-V/SCH-V BUS OPERATION Start COMMAND COMMENTS Write 60H, Block/Device Address Write Set Block/Master Lock-Bit Setup Data = 60H Addr = Block Address (Block), Device Address (Master) Write 01H/F1H, Block/Device Address Write Set Block or Master Lock-Bit Confirm Data = 01H (Block), F1H (Master) Addr = Block Address (Block), Device Address (Master) Read Status Register Read Status Register Data Standby Check SR.7 1 = WSM Ready 0 = WSM Busy 0 Repeat for subsequent lock-bit set operations. SR.7 = Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. 1 Write FFH after the last lock-bit set operation to place device in read array mode. Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = 1 BUS OPERATION COMMAND SR.1 = 1 1 Command Sequence Error 0 SR.4 = 1 Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP# = VIH (Set Master Lock-Bit Operation) RP# = VIH, Master Lock-Bit is Set (Set Block Lock-Bit Operation) Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.4 1 = Set Lock-Bit Error Device Protect Error 0 SR.4, 5 = Standby VPP Range Error 0 Set Lock-Bit Error COMMENTS SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. 0 Set Lock-Bit Successful Fig. 7 Set Block and Master Lock-Bit Flowchart - 21 - LH28F008SC-V/SCH-V BUS OPERATION Start Write 60H Write Clear Block Lock-Bits Setup Data = 60H Addr = X Write Clear Block Lock-Bits Confirm Data = D0H Addr = X Write D0H Read Status Register SR.7 = COMMENTS COMMAND Read Status Register Data Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Write FFH after the last clear block lock-bits operation to place device in read array mode. 0 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) BUS OPERATION COMMAND Standby Check SR.3 1 = VPP Error Detect Standby Check SR.1 1 = Device Protect Detect RP# = VIH, Master Lock-Bit is Set Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Clear Block Lock-Bits Error 1 SR.3 = VPP Range Error 0 SR.1 = 1 Device Protect Error 0 1 SR.4, 5 = Command Sequence Error 0 SR.5 = 1 COMMENTS SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the status register before attempting retry or other error recovery. Clear Block Lock-Bits Error 0 Clear Block Lock-Bits Successful Fig. 8 Clear Block Lock-Bits Flowchart - 22 - LH28F008SC-V/SCH-V 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Threeline control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 RY/BY# and Block Erase, Byte Write, and Lock-Bit Configuration Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. It transitions low after block erase, byte write, or lockbit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also VOH when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 VPP Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. 5.5 VCC, VPP, RP# Transitions Block erase, byte write and lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2 range, VCC falls outside of a valid VCC1/2 range, or RP# ≠ VIH or VHH. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, byte write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal - 23 - LH28F008SC-V/SCH-V operation is restored. Device power-off or RP# transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO. After block erase, byte write, or lock-bit configuration, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon powerup, the device is indifferent as to which power supply (VPP or VCC) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. 5.7 Power Consumption When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solidstate storage can consume negligible power by lowering RP# to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after RP# is first raised to VIH. See Section 6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and Fig. 12, Fig. 13 and Fig. 14 for more information. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI’s two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = VIL regardless of its control inputs state. - 24 - LH28F008SC-V/SCH-V 6 ELECTRICAL SPECIFICATIONS 6.1 NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. Absolute Maximum Ratings∗ Operating Temperature • LH28F008SC-V During Read, Block Erase, Byte Write and Lock-Bit Configuration ........ 0 to +70°C (NOTE 1) Temperature under Bias ............. –10 to +80°C • LH28F008SCH-V During Read, Block Erase, Byte Write and Lock-Bit Configuration ... –25 to +85°C (NOTE 2) Temperature under Bias............. –25 to +85°C ∗WARNING : Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES : 1. Storage Temperature ........................ –65 to +125°C Voltage On Any Pin (except VCC, VPP, and RP#) .... –2.0 to +7.0 V (NOTE 3) 2. 3. VCC Supply Voltage ................. –2.0 to +7.0 V (NOTE 3) VPP Update Voltage during Block Erase, Byte Write and Lock-Bit Configuration .. –2.0 to +14.0 V (NOTE 3, 4) 4. 5. RP# Voltage with Respect to GND during Lock-Bit Configuration Operations .. –2.0 to +14.0 V (NOTE 3, 4) Operating temperature is for commercial product defined by this specification. Operating temperature is for extended temperature product defined by this specification. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and – 0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5 V which, during transitions, may overshoot to VCC+2.0 V for periods < 20 ns. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods < 20 ns. Output shorted for no more than one second. No more than one output shorted at a time. Output Short Circuit Current .............. 100 mA (NOTE 5) 6.2 Operating Conditions SYMBOL PARAMETER TA Operating Temperature VCC1 VCC2 VCC Supply Voltage (5.0±0.25 V) VCC Supply Voltage (5.0±0.5 V) NOTE 1 MIN. 0 MAX. +70 –25 +85 UNIT ˚C ˚C 4.75 4.50 5.25 5.50 V V NOTE : 1. Test condition : Ambient temperature - 25 - VERSIONS LH28F008SC-V LH28F008SCH-V LH28F008SC-V85/SCH-V85 LH28F008SC-V/SCH-V 6.2.1 CAPACITANCE (NOTE 1) TA = +25˚C, f = 1 MHz SYMBOL CIN COUT PARAMETER TYP. MAX. UNIT 6 8 8 12 pF pF Input Capacitance Output Capacitance CONDITION VIN = 0.0 V VOUT = 0.0 V NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 3.0 1.5 INPUT TEST POINTS 1.5 OUTPUT 0.0 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. Fig. 9 Transient Input/Output Reference Waveform for VCC = 5.0±0.25 V (High Speed Testing Configuration) 2.4 2.0 INPUT 2.0 TEST POINTS 0.8 0.45 OUTPUT 0.8 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. Fig. 10 Transient Input/Output Reference Waveform for VCC = 5.0±0.5 V (Standard Testing Configuration) Test Configuration Capacitance Loading Value TEST CONFIGURATION CL (pF) VCC = 5.0±0.25 V (NOTE 1) 30 VCC = 5.0±0.5 V 100 1.3 V 1N914 NOTE : 1. RL = 3.3 kΩ DEVICE UNDER TEST OUT CL CL Includes Jig Capacitance Fig. 11 Transient Equivalent Testing Load Circuit - 26 - Applied to high-speed products, LH28F008SC-V85 and LH28F008SCH-V85. LH28F008SC-V/SCH-V 6.2.3 DC CHARACTERISTICS SYMBOL PARAMETER NOTE VCC = 5.0±0.5 V TYP. MAX. UNIT ILI Input Load Current 1 ±1 µA ILO Output Leakage Current 1 ±10 µA 100 µA 25 ICCS VCC Standby Current ICCD LH28F008SC-V LH28F008SCH-V VCC = VCC Max. VIN = VCC or GND VCC = VCC Max. VOUT = VCC or GND CMOS Inputs VCC = VCC Max. CE# = RP# = VCC±0.2 V TTL Inputs 1, 3, 6 0.4 VCC Deep PowerDown Current TEST CONDITIONS 2 10 1 20 mA µA VCC = VCC Max. CE# = RP# = VIH RP# = GND±0.2 V IOUT (RY/BY#) = 0 mA CMOS Inputs VCC = VCC Max. 17 ICCR VCC Read Current 35 mA CE# = GND f = 8 MHz IOUT = 0 mA TTL Inputs 1, 5, 6 VCC = VCC Max. 20 ICCW ICCE VCC Byte Write or Set Lock-Bit Current VCC Block Erase or Clear Block Lock-Bits Current ICCWS VCC Byte Write or ICCES Block Erase Suspend Current IPPS IPPR IPPD mA 35 mA IOUT = 0 mA VPP = 5.0±0.5 V 30 30 mA mA VPP = 12.0±0.6 V VPP = 5.0±0.5 V 25 mA VPP = 12.0±0.6 V 1 10 mA CE# = VIH ±2 ±15 µA 10 0.1 200 5 µA µA VPP ≤ VCC VPP > VCC RP# = GND±0.2 V 40 mA 15 mA 20 mA 15 mA VPP = 5.0±0.5 V VPP = 12.0±0.6 V 200 µA VPP = VPPH1/2 1, 7 1, 7 1, 2 VPP Standby or Read Current 1 VPP Deep Power-Down Current 1 IPPW VPP Byte Write or Set Lock-Bit Current 1, 7 IPPE VPP Block Erase or Clear Block Lock-Bits Current 1, 7 IPPWS VPP Byte Write or IPPES Block Erase Suspend Current 50 1 10 - 27 - CE# = GND f = 8 MHz VPP = 5.0±0.5 V VPP = 12.0±0.6 V LH28F008SC-V/SCH-V 6.2.3 DC CHARACTERISTICS (contd.) SYMBOL VIL PARAMETER Input Low Voltage VCC = 5.0±0.5 V MIN. MAX. – 0.5 0.8 NOTE 7 VIH Input High Voltage 7 VOL Output Low Voltage 3, 7 VOH1 Output High Voltage (TTL) 3, 7 VCC 2.0 +0.5 0.45 2.4 0.85 VOH2 VPPLK Output High Voltage (CMOS) VPP Lockout Voltage during Normal Operations VCC – 0.4 4, 7 TEST CONDITIONS V V V VCC = VCC Min. IOL = 5.8 mA V VCC = VCC Min. IOH = –2.5 mA V VCC 3, 7 UNIT V 1.5 V VPPH1 VPP Voltage during Byte Write, Block Erase or Lock-Bit Operations 4.5 5.5 V VPPH2 VPP Voltage during Byte Write, Block Erase or Lock-Bit Operations 11.4 12.6 V VLKO VCC Lockout Voltage 2.0 VHH RP# Unlock Voltage VCC = VCC Min. IOH = –2.5 mA VCC = VCC Min. IOH = –100 µA V Set master lock-bit 8, 9 11.4 12.6 V Override master and block lock-bit NOTES : 1. 2. 3. 4. 5. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25˚C. These currents are valid for all product versions (packages and speeds). ICCWS and ICCES are specified with the device deselected. If reading or byte writing in erase suspend mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. Includes RY/BY#. Block erases, byte writes, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.), and above VPPH2 (max.). Automatic Power Saving (APS) reduces typical ICCR to 1 mA at 5 V VCC in static operation. 6. 7. 8. 9. - 28 - CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL inputs are either VIL or VIH. Sampled, not 100% tested. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and byte writes are inhibited when the corresponding block lock-bit is set and RP# = VIH. Block erase, byte write, and lock-bit configuration operations are not guaranteed with VIH < RP# < VHH and should not be attempted. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. LH28F008SC-V/SCH-V 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1) • VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –25 to +85˚C (NOTE 4) VCC±0.25 V LH28F008SC-V85/ LH28F008SCH-V85 VERSIONS (NOTE 5) SYMBOL PARAMETER tAVAV Read Cycle Time NOTE tAVQV tELQV Address to Output Delay CE# to Output Delay tPHQV RP# High to Output Delay tGLQV tELQX OE# to Output Delay CE# to Output in Low Z 2 3 tEHQZ CE# High to Output in High Z 3 tGLQX OE# to Output in Low Z 3 tGHQZ OE# High to Output in High Z 3 tOH Output Hold from Address, CE# or OE# Change, 3 UNIT (NOTE 5) LH28F008SC-V85/ LH28F008SC-V12/ LH28F008SCH-V85 LH28F008SCH-V12 VCC±0.5 V MIN. 85 MAX. 2 MIN. 90 MAX. MAX. ns 85 85 90 90 120 120 400 400 400 ns 40 45 50 ns ns 55 ns 0 0 55 0 0 55 0 10 0 MIN. 120 0 10 0 ns 15 0 ns ns ns ns Whichever Occurs First NOTES : 1. 2. 3. 4. See AC Input/Output Reference Waveform (Fig. 9 and Fig. 10) for maximum allowable input slew rate. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, not 100% tested. See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. 5. - 29 - See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. LH28F008SC-V/SCH-V Standby Device Address Selection Data Valid VIH Address Stable ADDRESSES (A) VIL tAVAV VIH CE# (E) VIL OE# (G) tEHQZ VIH tGHQZ VIL tELQV VIH tGLQV WE# (W) VIL tGLQX tOH tELQX DATA (D/Q) (DQ0 - DQ7) VOH High Z Valid Output VOL tAVQV VCC tPHQV VIH RP# (P) VIL Fig. 12 AC Waveform for Read Operations - 30 - High Z LH28F008SC-V/SCH-V 6.2.5 AC CHARACTERISTICS - WRITE OPERATION (NOTE 1) • VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –25 to +85˚C (NOTE 5) VCC±0.25 V LH28F008SC-V85/ LH28F008SCH-V85 VERSIONS (NOTE 6) VCC±0.5 V SYMBOL PARAMETER tAVAV Write Cycle Time tPHWL RP# High Recovery to WE# Going Low tELWL CE# Setup to WE# Going Low NOTE UNIT (NOTE 6) LH28F008SC-V85/ LH28F008SC-V12/ LH28F008SCH-V85 LH28F008SCH-V12 MIN. 85 MAX. MIN. 90 MAX. MAX. ns 2 1 10 10 10 ns tWLWH WE# Pulse Width tPHHWH RP# VHH Setup to WE# Going High 2 40 100 40 100 40 100 ns ns tVPWH VPP Setup to WE# Going High 2 100 100 100 ns tAVWH Address Setup to WE# Going High 3 40 40 40 ns tDVWH Data Setup to WE# Going High 3 40 40 40 ns tWHDX tWHAX Data Hold from WE# High Address Hold from WE# High 5 5 5 5 5 5 ns ns tWHEH tWHWL CE# Hold from WE# High WE# Pulse Width High 10 30 10 30 10 30 ns ns tWHRL WE# High to RY/BY# Going Low tWHGL Write Recovery before Read tQVVL tQVPH VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 1 MIN. 120 90 1 90 µs 90 ns 0 0 0 ns 2, 4 0 0 0 ns 2, 4 0 0 0 ns NOTES : 1. 2. 3. 4. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. 6. - 31 - See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (High Seed Configuration) for testing characteristics. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. LH28F008SC-V/SCH-V (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) VIH ADDRESSES (A) AIN VIL AIN tAVWH tAVAV tWHAX VIH CE# (E) VIL tELWL tWHEH tWHGL VIH OE# (G) VIL tWHWL tWHQV1/2/3/4 VIH WE# (W) tWLWH tDVWH tWHDX VIL VIH High Z DATA (D/Q) VIL DIN DIN tPHWL Valid SRD tWHRL VOH RY/BY# (R) VOL tPHHWH tQVPH VHH RP# (P) VIH VIL tVPWH tQVVL VPPH1/2 VPP (V) VPPLK VIL NOTES : 1. 2. 3. 4. 5. 6. VCC power-up and standby. Write block erase or byte write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. Fig. 13 AC Waveform for WE#-Controlled Write Operations - 32 - DIN LH28F008SC-V/SCH-V 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1) • VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –25 to +85˚C (NOTE 5) VCC±0.25 V LH28F008SC-V85/ LH28F008SCH-V85 VERSIONS (NOTE 6) VCC±0.5 V SYMBOL PARAMETER tAVAV Write Cycle Time tPHEL RP# High Recovery to CE# Going Low tWLEL tELEH tPHHEH NOTE UNIT (NOTE 6) LH28F008SC-V85/ LH28F008SC-V12/ LH28F008SCH-V85 LH28F008SCH-V12 MIN. 85 MAX. MIN. 90 MAX. MAX. ns 2 1 WE# Setup to CE# Going Low 0 0 0 ns CE# Pulse Width RP# VHH Setup to CE# Going High 2 50 100 50 100 50 100 ns ns tVPEH VPP Setup to CE# Going High 2 100 100 100 ns tAVEH Address Setup to CE# Going High 3 40 40 40 ns tDVEH Data Setup to CE# Going High 3 40 40 40 ns tEHDX tEHAX Data Hold from CE# High Address Hold from CE# High 5 5 5 5 5 5 ns ns tEHWH tEHEL WE# Hold from CE# High CE# Pulse Width High 0 25 0 25 0 25 ns ns tEHRL CE# High to RY/BY# Going Low tEHGL Write Recovery before Read tQVVL tQVPH VPP Hold from Valid SRD, RY/BY# High RP# VHH Hold from Valid SRD, RY/BY# High 1 MIN. 120 90 1 90 µs 90 ns 0 0 0 ns 2, 4 0 0 0 ns 2, 4 0 0 0 ns NOTES : 1. 2. 3. 4. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. Sampled, not 100% tested. Refer to Table 3 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. 6. - 33 - See Fig. 9 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (High Seed Configuration) for testing characteristics. See Fig. 10 "Transient Input/Output Reference Waveform" and Fig. 11 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. LH28F008SC-V/SCH-V (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) VIH ADDRESSES (A) AIN VIL AIN tAVEH tAVAV tEHAX VIH WE# (W) VIL tWLEL tEHWH tEHGL VIH OE# (G) VIL tEHEL tEHQV1/2/3/4 VIH CE# (E) tELEH tDVEH tEHDX VIL High Z VIH DATA (D/Q) DIN Valid SRD DIN tPHEL VIL tEHRL VOH RY/BY# (R) VOL tPHHEH tQVPH VHH RP# (P) VIH VIL tVPEH tQVVL VPPH1/2 VPP (V) VPPLK VIL NOTES : 1. 2. 3. 4. 5. 6. VCC power-up and standby. Write block erase or byte write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. Fig. 14 AC Waveform for CE#-Controlled Write Operations - 34 - DIN LH28F008SC-V/SCH-V 6.2.7 RESET OPERATIONS VOH RY/BY# (R) VOL VIH RP# (P) VIL tPLPH (A) Reset During Read Array Mode VOH RY/BY# (R) VOL tPLRH VIH RP# (P) VIL tPLPH (B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration 5V VCC VIL t5VPH VIH RP# (P) VIL (C) RP# Rising Timing Fig. 15 AC Waveform for Reset Operation Reset AC Specifications (NOTE 1) SYMBOL tPLPH tPLRH t5VPH PARAMETER NOTE RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) VCC = 5.0±0.5 V MIN. MAX. 100 RP# Low to Reset during Block Erase, Byte Write or Lock-Bit Configuration VCC 4.5 V to RP# High 2, 3 4 ns 12 100 UNIT µs ns NOTES : 1. 2. These specifications are valid for all product versions (packages and speeds). If RP# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. 4. - 35 - A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. When the device power-up, holding RP#-low minimum 100 ns is required after VCC has been in predefined range and also has been in stable there. LH28F008SC-V/SCH-V 6.2.8 BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4) • VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –25 to +85˚C VPP = 5.0±0.5 V VPP = 12.0±0.6 V MIN. TYP.(NOTE 1) MAX. MIN. TYP.(NOTE 1) MAX. 2 6.5 8 TBD 4.8 6 TBD µs Block Write Time 2 0.4 0.5 TBD 0.3 0.4 TBD s Block Erase Time 2 0.9 1.1 TBD 0.3 1.0 TBD s tWHQV3 Set Lock-Bit Time tEHQV3 2 9.5 12 TBD 7.8 10 TBD µs tWHQV4 Clear Block Lock-Bits Time tEHQV4 2 0.9 1.1 TBD 0.3 1.0 TBD s 5.6 7 5.2 7.5 µs 9.4 13.1 9.8 12.6 µs SYMBOL PARAMETER NOTE tWHQV1 Byte Write Time tEHQV1 tWHQV2 tEHQV2 tWHRH1 Byte Write Suspend Latency Time to Read tEHRH1 tWHRH2 tEHRH2 Erase Suspend Latency Time to Read UNIT NOTES : 1. 2. Typical values measured at TA = +25˚C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. Excludes system-level overhead. 3. 4. - 36 - These performance numbers are valid for all speed versions. Sampled, not 100% tested. LH28F008SC-V/SCH-V 7 ORDERING INFORMATION Product line designator for all SHARP Flash products L H 2 8 F 0 0 8 S C (H) T - V 8 5 Device Density 008 = 8 M-bit Access Speed (ns) 85 : 85 ns (5.0±0.25 V), 90 ns (5.0±0.5 V), 12 : 120 ns (5.0±0.5 V) Architecture S = Symmetrical Block Power Supply Type C = Smart 5 Technology Operating Temperature Blank = 0 to +70°C H = –25 to +85°C OPTION 1 2 ORDER CODE LH28F008SCXX-V85 LH28F008SCXX-V12 Limited Voltage Option V = 5 V VCC only Package T = 40-pin TSOP (I) (TSOP040-P-1020) Normal bend R = 40-pin TSOP (I) (TSOP040-P-1020) Reverse bend N = 44-pin SOP (SOP044-P-0600) B = 48-ball CSP (FBGA048-P-0608) VALID OPERATIONAL COMBINATIONS VCC = 5.0±0.5 V VCC = 5.0±0.25 V 100 pF load, 30 pF load, TTL I/O Levels 1.5 V I/O Levels 90 ns 120 ns 85 ns - 37 - 20.0 ±0.3 18.4±0.2 19.0±0.3 1.20MAX. P _ 0.5 TYP. 21 0.995 ±0.1 20 0.435 0.10 10.0 ±0.2 0.08 M 40 _ 0.2 ±0.08 40 0.125 1 0.115 ±0.1 0.125 ±0.05 PACKAGING 40 TSOP (TSOP040-P-1020) Package base plane PACKAGING 44 SOP (SOP044-P-0600) 44_ 0.4±0.1 1.27TYP. 44 0.15 M 2.7 ±0.2 22 0.15 28.2 ±0.2 1.275 1 (14.4) 13.2 ±0.2 16.0 ±0.4 23 0.15 ±0.05 0.15±0.1 Package base plane 0.1 PACKAGING 48 CSP (FBGA048-P-0608) A 6.00 + 0.2 B 1.2MAX. / / 0.1 S ∗0.4TYP. S ∗Land hole diameter 0.1 S 0.35±0.05 for ball mounting +0.2 8.00 0.8TYP. 0.4TYP. 0.4TYP. 0.8TYP. 1.0TYP. C F D A 1 8 1.2TYP. 0.45±0.03 0.30 M S AB 0.15 M S CD