INTEL RD28F1602C3T70

3 Volt Intel® Advanced+ Boot Block
Flash Memory (C3) Stacked-Chip Scale
Package Family
Datasheet
Product Features
■
■
■
■
Flash Memory Plus SRAM
— Reduces Memory Board Space
Required, Simplifying PCB Design
Complexity
Stacked-Chip Scale Package (StackedCSP) Technology
— Smallest Memory Subsystem Footprint
— Area : 8 x 10 mm for 16Mbit (0.13 µm)
Flash + 2Mbit or 4Mbit SRAM
— Area : 8 x 12 mm for 32Mbit (0.13 µm)
Flash + 4Mbit or 8Mbit SRAM
— Height : 1.20 mm for 16Mbit (0.13 µm)
Flash + 2Mbit or 4Mbit SRAM and
32Mbit (0.13um) Flash + 8Mbit SRAM
— Height : 1.40 mm for 32Mbit (0.13 µm)
Flash + 4Mbit SRAM
— This Family also includes 0.25 µm and
0.18 µm technologies
Advanced SRAM Technology
— 70 ns Access Time
— Low Power Operation
— Low Voltage Data Retention Mode
Intel® Flash Data Integrator (FDI)
Software
— Real-Time Data Storage and Code
Execution in the Same Memory Device
— Full Flash File Manager Capability
■
■
■
■
Advanced+ Boot Block Flash Memory
— 70 ns Access Time at 2.7 V
— Instant, Individual Block Locking
— 128 bit Protection Register
— 12 V Production Programming
— Ultra Fast Program and Erase Suspend
— Extended Temperature –25 °C to +85 °C
Blocking Architecture
— Block Sizes for Code + Data Storage
— 4-Kword Parameter Blocks (for data)
— 64-Kbyte Main Blocks (for code)
— 100,000 Erase Cycles per Block
Low Power Operation
— Async Read Current: 9 mA (Flash)
— Standby Current: 7 µA (Flash)
— Automatic Power Saving Mode
Flash Technologies
— 0.25 µm ETOX™ VI, 0.18 µm ETOX™
VII and 0.13 µm ETOX™ VIII Flash
Technologies
— 28F160xC3, 28F320xC3
The 3 Volt Intel® Advanced+ Boot Block Flash Memory (C3) Stacked-Chip Scale Package
(Stacked-CSP) device delivers a feature-rich solution for low-power applications. The C3
Stacked-CSP memory device incorporates flash memory and static RAM in one package with
low voltage capability to achieve the smallest system memory solution form-factor together with
high-speed, low-power operations. The C3 Stacked-CSP memory device offers a protection
register and flexible block locking to enable next generation security capability. Combined with
the Intel® Flash Data Integrator (Intel® FDI) software, the C3 Stacked-CSP memory device
provides a cost-effective, flexible, code plus data storage solution.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
252636-001
February, 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
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platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Additional information on this product family can be obtained by accessing the Intel®
Flash website: http://www.intel.com/design/flash.
Copyright © 2003 Intel Corporation.
*Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0
Introduction....................................................................................................................................7
1.1
1.2
1.3
1.4
2.0
Principles of Operation ...............................................................................................................11
2.1
3.0
3.4
3.5
3.6
3.7
3.8
Read Array (FFh) ................................................................................................................13
Read Identifier (90h) ...........................................................................................................13
Read Status Register (70h) ................................................................................................14
3.3.1 Clear Status Register (50h) ...................................................................................14
CFI Query (98h) ..................................................................................................................15
Word Program (40h/10h) ....................................................................................................15
3.5.1 Suspending and Resuming Program (B0h/D0h)....................................................15
Block Erase (20h) ...............................................................................................................16
3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................................16
Block Locking......................................................................................................................18
3.7.1 Block Locking Operation Summary........................................................................19
3.7.2 Locked State ..........................................................................................................19
3.7.3 Unlocked State ......................................................................................................19
3.7.4 Lock-Down State ...................................................................................................19
3.7.5 Reading a Block’s Lock Status ..............................................................................20
3.7.6 Locking Operation during Erase Suspend .............................................................20
3.7.7 Status Register Error Checking .............................................................................20
128 Bit Protection Register .................................................................................................21
3.8.1 Reading the Protection Register ............................................................................21
3.8.2 Programming the Protection Register (C0h)..........................................................21
3.8.3 Locking the Protection Register .............................................................................22
Power and Reset Considerations ..............................................................................................23
4.1
4.2
5.0
Bus Operation .....................................................................................................................11
2.1.1 Read ......................................................................................................................11
2.1.2 Output Disable .......................................................................................................12
2.1.3 Standby..................................................................................................................12
2.1.4 Flash Reset............................................................................................................13
2.1.5 Write ......................................................................................................................13
Flash Memory Modes of Operation............................................................................................13
3.1
3.2
3.3
4.0
Document Conventions ........................................................................................................7
Product Overview .................................................................................................................7
Package Ballout....................................................................................................................8
Signal Definitions ..................................................................................................................9
Power-Up/Down Characteristics.........................................................................................23
Additional Flash Features ...................................................................................................23
4.2.1 Improved 12 Volt Production Programming ...........................................................23
4.2.2 F-VPP < VPPLK for Complete Protection..............................................................23
Electrical Specifications .............................................................................................................24
5.1
5.2
5.3
Datasheet
Absolute Maximum Ratings ................................................................................................24
Operating Conditions ..........................................................................................................25
Capacitance ........................................................................................................................25
3
Contents
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
DC Characteristics.............................................................................................................. 26
Flash AC Characteristics. ................................................................................................... 29
Flash AC Characteristics—Write Operations...................................................................... 31
Flash Erase and Program Timings(1)................................................................................. 31
Flash Reset Operations ...................................................................................................... 34
SRAM AC Characteristics—Read Operations.................................................................... 35
SRAM AC Characteristics—Write Operations .................................................................... 37
SRAM Data Retention Characteristics—Extended Temperature ....................................... 39
6.0
Migration Guide Information ...................................................................................................... 40
7.0
System Design Considerations.................................................................................................. 41
7.1
7.2
7.3
7.4
7.5
7.6
Background......................................................................................................................... 41
7.1.1 Flash + SRAM Footprint Integration ...................................................................... 41
7.1.2 Advanced+ Boot Block Flash Memory Features ................................................... 41
Flash Control Considerations ............................................................................................. 41
7.2.1 F-RP# Connected to System Reset....................................................................... 42
7.2.2 F-VCC, F-VPP and F-RP# Transition .................................................................... 42
Noise Reduction ................................................................................................................. 43
Simultaneous Operation ..................................................................................................... 44
7.4.1 SRAM Operation during Flash “Busy” ................................................................... 45
7.4.2 Simultaneous Bus Operations ............................................................................... 45
Printed Circuit Board Notes ................................................................................................ 45
System Design Notes Summary......................................................................................... 45
Appendix A Program/Erase Flowcharts ............................................................................................. 46
Appendix B CFI Query Structure ........................................................................................................ 52
Appendix C Word-Wide Memory Map Diagrams ............................................................................... 59
Appendix D Device ID Table ................................................................................................................ 62
Appendix E Protection Register Addressing..................................................................................... 63
Appendix F Mechanical and Shipping Media Details........................................................................ 64
Appendix G Additional Information .................................................................................................... 68
Appendix H Ordering Information....................................................................................................... 69
4
Datasheet
Contents
Revision History
Datasheet
Date of
Revision
Version
02/11/03
-001
Description
Initial release, Stacked-Chip Scale Package
5
Contents
6
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
1.0
Introduction
This document contains the specifications for the 3 Volt Intel® Advanced+ Boot Block Flash
Memory (C3) Stacked-Chip Scale Package (Stacked-CSP) device. Stacked memory solutions are
offered in the following combinations: 32-Mbit flash + 8-Mbit SRAM, 32-Mbit flash + 4-Mbit
SRAM, 16-Mbit flash + 4-Mbit SRAM, or 16-Mbit flash memory + 2-Mbit SRAM.
1.1
Document Conventions
Throughout this document, the following conventions have been adopted.
• Voltages: “2.7 V” refers to the full voltage range, 2.7 V–3.3V; 12 V refers to 11.4 V to 12.6 V
• Main block(s): 32-Kword block
• Parameter block(s): 4-Kword block
1.2
Product Overview
The C3 Stacked-CSP device combines flash and SRAM into a single package, and provides secure
low-voltage memory solutions for portable applications. This memory family combines two
memory technologies, flash memory and SRAM, in one package. The flash memory delivers
enhanced security features, a block locking capability that allows instant locking/unlocking of any
flash block with zero-latency, and a 128-bit protection register that enable unique device
identification, to meet the needs of next generation portable applications. Improved 12 V
production programming can be used to improve factory throughput.
Table 1.
Block Organization (x16)
Memory Device
Kwords
32-Mbit Flash
2048
16-Mbit Flash
1024
2-Mbit SRAM
128
4-Mbit SRAM
256
8-Mbit SRAM
512
NOTE: All words are 16 bits each.
The flash memory is asymmetrically-blocked to enable system integration of code and data storage
in a single device. Each flash block can be erased independently of the others up to 100,000 times.
The flash has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or the
bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols
for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any
individual flash block can be locked or unlocked instantly to provide complete protection for code
or data (see Section 5.7, “Flash Erase and Program Timings(1)” on page 31 for details).
The flash contains both a Command User Interface (CUI) and a Write State Machine (WSM). The
CUI serves as the interface between the microcontroller and the internal operation of the flash
memory. The internal WSM automatically executes the algorithms and timings necessary for
Datasheet
7
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
program and erase operations, including verification, thereby unburdening the microprocessor or
microcontroller. The flash’s status register indicates the status of the WSM by signifying block
erase or word program completion and status.
Flash program and erase automation allows program and erase operations to be executed using an
industry-standard two-write command sequence to the CUI. Program operations are performed in
word increments. Erase operations erase all locations within a block simultaneously. Both program
and erase operations can be suspended by the system software in order to read from any other flash
block. In addition, data can be programmed to another flash block during an erase suspend.
The C3 Stacked-CSP memory device offers two low-power savings features: Automatic Power
Savings (APS) for flash memory and standby mode for flash and SRAM. The device automatically
enters APS mode following the completion of a read cycle from the flash memory. Standby mode
is initiated when the system deselects the device by driving F-CE# and S-CS1# or
S-CS2 inactive. Power savings features significantly reduce power consumption.
The flash memory can be reset by lowering F-RP# to GND. This provides CPU-memory reset
synchronization and additional protection against bus noise that may occur during system reset and
power-up/-down sequences.
1.3
Package Ballout
72-
Figure 1. 66-Ball Stacked Chip Scale Package
1
2
3
4
5
6
7
A20
A11
A15
A14
A13
A16
A8
A10
A9
F-WE# NC
A21
8
9
10
11
12
A
NC
A12 F-VSS F-VCCQ
NC
B
DQ15 S-WE# DQ14 DQ7
C
DQ13 DQ6
DQ4 DQ5
D
DQ12 S-CS2 S-VCC F-VCC
S-VSS F-RP# A22
E
F-WP# F-VPP A19
DQ11
DQ10
DQ2 DQ3
DQ9 DQ8
DQ0 DQ1
F
S-LB# S-UB# S-OE#
G
A18
A17
A7
A6
A3
A2
A1 S-CS1#
NC
A5
A4
A0 F-CE# F-VSS F-OE# NC
H
NC
NC
Top View, Balls Down
NOTES:
1. Flash upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash and SRAM
combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Ball
location A10 is “NC” on 16/2 devices only.
8
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
2. To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should
be connected directly to the land pad for ball G4 (A17).
1.4
Signal Definitions
Table 2. defines the signal definitions shown in the previous ballout.
Table 2.
Symbol
3 Volt Intel® Advanced+ Boot Block Stacked-CSP Ball Descriptions (Sheet 1 of 2)
Type
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
2-Mbit : A[16:0]
A[20:0]
INPUT
4-Mbit : A[18:0]
16-Mbit : A[19:0]
32-Mbit A[20:0]
INPUT /
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data for SRAM write operations and on the second F-CE#
and F-WE# cycle during a flash program command. Inputs commands to the flash’s Command
User Interface when F-CE# and F-WE# are asserted. Data is internally latched. Outputs array,
configuration and status register data. The data balls float to tri-state when the chip is de-selected
or the outputs are disabled.
F-CE#
INPUT
FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders and
sense amplifiers. F-CE# is active low. F-CE# high de-selects the flash memory device and reduces
power consumption to standby levels.
S-CS1#
INPUT
SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders and
sense amplifiers. S-CS1# is active low. S-CS1# high de-selects the SRAM memory device and
reduces power consumption to standby levels.
S-CS2
INPUT
SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders and
sense amplifiers. S-CS2 is active high. S-CS2 low de-selects the SRAM memory device and
reduces power consumption to standby levels.
F-OE#
INPUT
FLASH OUTPUT ENABLE: Enables flash’s outputs through the data buffers during a read
operation. F-OE# is active low.
S-OE#
INPUT
SRAM OUTPUT ENABLE: Enables SRAM’s outputs through the data buffers during a read
operation. S-OE# is active low.
F-WE#
INPUT
FLASH WRITE ENABLE: Controls writes to flash’s command register and memory array. F-WE#
is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse.
S-WE#
INPUT
SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low.
S-UB#
INPUT
SRAM UPPER BYTE ENABLE: Enables the upper byte for SRAM (DQ8–DQ15).
S-UB# is active low.
S-LB#
INPUT
SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ0–DQ7).
S-LB# is active low.
DQ[15:0]
FLASH RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep
power-down mode.
F-RP#
INPUT
When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives the
outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When F-RP# is at logic high, the device is in standard operation. When F-RP# transitions from
logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
Datasheet
9
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 2.
Symbol
3 Volt Intel® Advanced+ Boot Block Stacked-CSP Ball Descriptions (Sheet 2 of 2)
Type
Name and Function
FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature.
When F-WP# is a logic low, the lock-down mechanism is enabled and blocks marked lockdown cannot be unlocked through software.
F-WP#
INPUT
When F-WP# is logic high, the lock-down mechanism is disabled and blocks previously
locked-down are now locked and can be unlocked and locked through software. After F-WP# goes
low, any blocks previously marked lock-down revert to that state.
See Section 7.0, “System Design Considerations” on page 41 for details on block locking.
F-VCC
SUPPLY
FLASH POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device core operations.
F-VCCQ
SUPPLY
FLASH I/O POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device I/O operations.
S-VCC
SUPPLY
SRAM POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device operations.
See Section 7.2.2, “F-VCC, F-VPP and F-RP# Transition” on page 42 for details of power
connections.
FLASH PROGRAM/ERASE POWER SUPPLY: [1.65 V–3.3 V or 11.4 V–12.6 V] Operates as an
input at logic levels to control complete flash protection. Supplies power for accelerated flash
program and erase operations in 12 V ± 5% range. This ball cannot be left floating.
Lower F-VPP ≤ VPPLK, to protect all contents against Program and Erase commands.
F-VPP
INPUT /
SUPPLY
Set F-VPP = F-VCC for in-system read, program and erase operations. In this configuration,
F-VPP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note
that if F-VPP is driven by a logic signal, VIH = 1.65 V. That is, F-VPP must remain above 1.65 V to
perform in-system flash modifications.
Raise F-VPP to 12 V ± 5% for faster program and erase in a production environment. Applying
12 V ± 5% to F-VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500
cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum.
F-VSS
SUPPLY
FLASH GROUND: For all internal circuitry. All ground inputs must be connected.
S-VSS
SUPPLY
SRAM GROUND: For all internal circuitry. All ground inputs must be connected.
NC
10
NOT CONNECTED: Internally disconnected within the device.
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
2.0
Principles of Operation
The flash memory utilizes a CUI and automated algorithms to simplify program and erase
operations. The WSM automates program and erase operations by handling data and address
latches, WE#, and system status requests.
Figure 2. 3 Volt Intel® Advanced+ Boot Block Stacked Chip Scale Package Block Diagram
F-VCC
F-OE#
F-CE#
F-WP#
F-RP#
Flash
28F160C3
or
28F320C3
S-CS1
F-VPP
F-VSS
D[15:0]
A[Max:0]
S-VCC
F-VCCQ
F-WE#
SRAM
2-, 4- or 8-Mbit
S-VSS
S-WE#
S-CS2
S-UB#
S-OE#
S-LB#
.
2.1
Bus Operation
All bus cycles to or from the Stacked-CSP conform to standard microcontroller bus cycles. Four
control signals dictate the data flow in and out of the flash component: F-CE#, F-OE#, F-WE# and
F-RP#. Four separate control signals handle the data flow in and out of the SRAM component:
S-CS1#, S-CS2, S-OE#, and S-WE#. These bus operations are summarized in Table 2 and Table 3.
2.1.1
Read
The flash memory has four read modes: read array, read identifier, read status and CFI query. These
flash memory read modes are not dependent on the F-VPP voltage. Upon initial device power-up or
after exit from reset, the flash device automatically defaults to read array mode. F-CE# and F-OE#
must be asserted to obtain data from the flash component.
The SRAM has one read mode available. S-CS1#, S-CS2, and S-OE# must be asserted to obtain
data from the SRAM device. See Table 3, “3 Volt Intel Advanced+ Boot Block Flash Memory
Stacked-CSP Bus Operations” on page 12 for a summary of operations.
Datasheet
11
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
3 Volt Intel Advanced+ Boot Block Flash Memory Stacked-CSP Bus Operations
Memory Bus Control
H
S-UB#,S-LB#(1)
L
Memory Output
S-WE#
L
S-OE1#
F-WE#
H
S-CS1#
F-OE1#
Read
F-CE#
Modes
SRAM Signals
F-RP#
Flash Signals
S-CS2
Table 3.
D0–
D15
Flash
DOUT
2,3,4
FLASH
SRAM must be in High Z
Write
H
L
H
L
Flash
DIN
2,4
Standby
H
H
X
X
Other
High Z
5,6
Output Disable
H
L
H
H
Reset
L
X
X
X
Read
FLASH must be in High Z
Write
SRAM
Notes
Any SRAM mode is allowable
Other
High Z
5,6
Other
High Z
5,6
L
H
L
H
L
SRAM
DOUT
2,4
L
H
H
L
L
SRAM
DIN
2,4
H
X
X
X
X
Other
High Z
4,5,6
X
L
X
X
X
L
H
H
H
X
Other
High Z
4,5,6
Other
High Z
4,5,7
Standby
Any FLASH mode is allowable
Output Disable
Data Retention
same as a standby
NOTES:
1. Two devices may not drive the memory bus at the same time.
2. The SRAM may be placed into data retention mode by lowering the S-VCC to the VDR range, as specified.
2.1.2
Output Disable
With F-OE# and S-OE# deasserted, the Stacked-CSP outputs signals are placed in a highimpedance state.
2.1.3
Standby
With F-CE# and S-CS1# or S-CS2 deasserted, the Stacked-CSP enters a standby mode, which
substantially reduces device power consumption. In standby, outputs are placed in a highimpedance state independent of F-OE# and S-OE#. If the flash is deselected during a program or
erase operation, the flash continues to consume active power until the program or erase operation is
complete.
12
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
2.1.4
Flash Reset
The device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or
tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal
operation is restored. The device defaults to read array mode, the status register is set to 80h, and
the read configuration register defaults to asynchronous reads.
If RP# is taken low during a block erase or program operation, the operation will be aborted and the
memory contents at the aborted location are no longer valid.
2.1.5
Write
Writes to flash take place when both F-CE# and F-WE# are asserted and F-OE# is deasserted.
Writes to SRAM take place when both S-CS1# and S-WE# are asserted and S-OE# and S-CS2 are
deasserted. Commands are written to the flash memory’s Command User Interface (CUI) using
standard microprocessor write timings to control flash operations. The CUI does not occupy an
addressable memory location within the flash component. The address and data buses are latched
on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 and
Figure 7 for read and write waveforms.)
3.0
Flash Memory Modes of Operation
The flash memory has four read modes: read array, read configuration, read status, and CFI query.
The write modes are program and erase. Three additional modes (erase suspend to program, erase
suspend to read and program suspend to read) are available only during suspended operations.
These modes are reached using the commands summarized in Table 5, “Flash Memory Command
Definitions” on page 17.
3.1
Read Array (FFh)
When F-RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will
respond to the read control inputs without any additional CUI commands.
In addition, the address of the desired location must be applied to the address balls. If the device is
not in read array mode, as would be the case after a program or erase operation, the Read Array
command (FFh) must be written to the CUI before array reads can take place.
3.2
Read Identifier (90h)
The read configuration mode outputs the manufacturer/device identifier. The device is switched to
this mode by writing the read configuration command (90h). Once in this mode, read cycles from
addresses shown in Table 4, “Read Configuration Table” on page 14 retrieve the specified
information. To return to read array mode, write the Read Array command (FFh).
Datasheet
13
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
The Read Configuration mode outputs three types of information: the manufacturer/device
identifier, the block locking status, and the protection register. The device is switched to this mode
by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses
shown in Table 4 retrieve the specified information. To return to read array mode, write the Read
Array command (FFh).
Table 4.
Read Configuration Table
Item
Address
Data
Manufacturer Code (x16)
0x00000
0x0089
Device ID (See Appendix D)
0x00001
ID
Block Lock Configuration
0xXX002
LOCK
•
•
•
Block Is Unlocked
DQ0 = 0
Block Is Locked
DQ0 = 1
Block Is Locked-Down
DQ1 = 1
Protection Register Lock
0x80
PR-LK
Protection Register (x16)
0x81-0x88
PR
Notes
1, 2
3
NOTES:
1. See Section 3.7 for valid lock status outputs.
2. “XX” specifies the block address of lock configuration being read.
3. See Section 3.8 for protection register information.
Other locations within the configuration address space are reserved by Intel for future use.
3.3
Read Status Register (70h)
The status register indicates the status of device operations, and the success/failure of that
operation. The Read Status Register (70h) command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the array, issue a
Read Array (FFh) command.
The status register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h during a
Read Status Register command.
The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever
occurs last. This prevents possible bus errors which might occur if status register contents change
while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status
register will not indicate completion of a program or erase operation.
When the WSM is active, SR7 will indicate the status of the WSM; the remaining bits in the status
register indicate whether the WSM was successful in performing the desired operation (see
Table 6, “Flash Memory Status Register Definition” on page 18).
3.3.1
Clear Status Register (50h)
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these
bits can only be cleared through the use of the Clear Status Register (50h) command. By allowing
the system software to control the resetting of these bits, several operations may be performed
14
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
(such as cumulatively programming several addresses or erasing multiple blocks in sequence)
before reading the status register to determine if an error occurred during that series. Clear the
status register before beginning another command or sequence. Note that the Read Array command
must be issued before data can be read from the memory array. Resetting the device also clears the
status register.
3.4
CFI Query (98h)
The CFI query mode outputs Common Flash Interface (CFI) data when the device is read. This can
be accessed by writing the CFI Query Command (98h). The CFI data structure contains
information such as block size, density, command set and electrical specifications. Once in this
mode, read cycles from addresses shown in Appendix B retrieve the specified information. To
return to read array mode, write the Read Array command (FFh).
3.5
Word Program (40h/10h)
Programming is executed using a two-write sequence. The Program Setup command (40h) is
written to the CUI followed by a second write which specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program desired bits
of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If the user
attempts to program “1”s, the memory cell contents do not change and no error occurs.
The status register indicates programming status: while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling either F-CE# or F-OE#. While programming,
the only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If
SR.3 is set then F-VPP was not within acceptable limits, and the WSM did not execute the program
command. If SR.1 is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status register reads, be
sure to reset the CUI to read array mode.
3.5.1
Suspending and Resuming Program (B0h/D0h)
The Program Suspend command halts an in-progress program operation so that data can be read
from other locations of memory. Once the programming process starts, writing the Program
Suspend command to the CUI requests that the WSM suspend the program sequence (at
predetermined points in the program algorithm). The device continues to output status register data
after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will
determine when the program operation has been suspended (both will be set to “1”). tWHRH1/
tEHRH1 specify the program suspend latency.
A Read Array command can be written to the CUI to read data from any block other than the
suspended block. The only other valid commands, while program is suspended, are Read Status
Register, Read Configuration, CFI Query, and Program Resume. After the Program Resume
Datasheet
15
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
command is written to the flash memory, the WSM will continue with the programming process
and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically
outputs status register data when read (see Appendix A, Program Suspend/Resume Flowcharts)
after the Program Resume command is written. F-VPP must remain at the same F-VPP level used
for program while in program suspend mode. F-RP# must also remain at VIH.
3.6
Block Erase (20h)
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If F-VPP was not within acceptable limits
after the Erase Confirm command was issued, the WSM will not execute the erase sequence;
instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to
identify that F-VPP supply voltage was not within acceptable limits.
After an erase operation, clear the status register (50h) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.6.1
Suspending and Resuming Erase (B0h/D0h)
An erase operation can take several seconds to complete, therefore, the Erase Suspend command is
provided to allow erase-sequence interruption in order to read data from, or program data to,
another block in memory. Once an erase sequence has started, writing the Erase Suspend command
to the CUI causes the device to suspend the erase sequence at a predetermined point in the erase
algorithm. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 5.7, “Flash Erase and Program Timings” on page 31.
When an erase operation has been suspended, a Word Program or Read operation can be performed
within any block, except the block that is in an erase suspend state. An erase operation cannot be
nested within another erase suspend operation.
A suspended erase operation cannot resume until the nested program operation has completed.
Read Array, Read Status Register, Clear Status Register, Read Identifier, CFI Query, Erase
Resume, are all valid commands during Erase Suspend. Additionally, Program, Program Suspend,
Program Resume, Lock Block, Unlock Block and Lock-Down Block are valid commands during
Erase Suspend.
To resume an erase suspend operation, issue the Resume command. The Resume command can be
written to any device address. When a program operation is nested within an Erase Suspend
operation and the Program Suspend command is issued, the device will suspend the program
operation. When the resume command is issued, the device will resume the program operation
first. Once the nested program operation is completed, an additional Resume command is required
to complete the block operation.
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 5.
Flash Memory Command Definitions
First Bus Cycle
Command
Second Bus Cycle
Note
Operation
Address
Data
1
Write
X
FFh
Read Identifier
1, 2
Write
X
CFI Query
1, 2
Write
Read Status Register
1
Clear Status Register
1
Read Array
Word Program
Block Erase/Confirm
Operation
Address
Data
90h
Read
IA
ID
X
98h
Read
QA
QD
Write
X
70h
Read
X
SRD
Write
X
50h
1, 3
Write
X
40h/10h
Write
PA
PD
1
Write
X
20h
Write
BA
D0h
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Lock Block
1
Write
X
60h
Write
BA
01h
1, 4
Write
X
60h
Write
BA
D0h
Unlock Block
Lock-Down Block
1
Write
X
60h
Write
BA
2Fh
Protection Register Program
1
Write
X
C0h
Write
PA
PD
Lock Protection Register
1
Write
X
C0h
Write
PA
FFFD
X = Don’t Care
PA = Program Address
SRD = Status Register Data
PD = Program Data
BA = Block Address
IA = Identifier Address
QA = Query Address
ID = Identifier Data
QD = Query Data
NOTES:
1. When writing commands, the upper data bus [DQ8–DQ15] should be either VIL or VIH, to minimize current draw.
2. Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query
information, respectively.
3. Either 40h or 10h command is valid, but the Intel standard is 40h.
4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle).
Datasheet
17
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 6.
Flash Memory Status Register Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready (WSMS)
0 = Busy
Check Write State Machine bit first to determine Word Program or
Block Erase completion, before checking Program or Erase Status
bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an
Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number of
erase pulses and is still unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
SR.3 = F-VPP STATUS (VPPS)
1 = F-VPP Low Detect, Operation Abort
0 = F-VPP OK
The F-VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates F-VPP level only after the Program or
Erase command sequences have been entered, and informs the
system if F-VPP has not been switched on. The F-VPP is also
checked before the operation is verified by the WSM. The F-VPP
status bit is not guaranteed to report accurate feedback between
VPPLK and VPP1 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and sets
both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a
Program Resume command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked block; Operation
aborted.
0 = No operation to locked blocks
If a program or erase operation is attempted to one of the locked
blocks, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out when
polling the status register.
NOTE: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
3.7
Block Locking
The instant, individual block locking feature that allows any flash block to be locked or unlocked
with no latency, which enables instant code and data protection.
This locking offers two levels of protection. The first level allows software-only control of block
locking (useful for data blocks that change frequently), while the second level requires hardware
interaction before locking can be changed (useful for code blocks that change infrequently).
The following sections will discuss the operation of the locking system. The term “state [XYZ]”
will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ1 of
the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 8, “Block
Locking State Transitions” on page 21 defines all of these possible locking states.
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
3.7.1
Block Locking Operation Summary
The following concisely summarizes the locking functionality.
All blocks are locked when powered-up, and can be unlocked or locked with the Unlock and Lock
commands.
• The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0.
• When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down
blocks.
• When WP# returns to 0, locked-down blocks return to Lock-Down.
• Lock-Down is cleared only when the device is reset or powered-down.
The locking status of each block can set to Locked, Unlocked, and Lock-Down, each of which will
be described in the following sections. A comprehensive state table for the locking functions is
shown in Table 8 on page 21, and a flowchart for locking operations is shown in Figure 19 on
page 50.
3.7.2
Locked State
The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked
blocks are fully protected from alteration. Any program or erase operations attempted on a locked
block will return an error on bit SR.1 of the status register. The status of a locked block can be
changed to Unlocked or Lock-Down using the appropriate software commands. Unlocked blocks
can be locked issuing the “Lock” command sequence, 60h followed by 01h.
3.7.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks
return to the Locked state when the device is reset or powered down. The status of an unlocked
block can be changed to Locked or Locked-Down using the appropriate software commands. A
Locked block can be unlocked by writing the Unlock command sequence, 60h followed by D0h.
3.7.4
Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just
like Locked blocks), but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence,
60h followed by 2Fh. Locked-Down blocks revert to the Locked state when the device is reset or
powered down.
The Lock-Down function is dependent on the WP# input ball. When WP# = 0, blocks in LockDown [011] are protected from program, erase, and lock status changes. When WP# = 1, the LockDown function is disabled ([111]) and locked-down blocks can be individually unlocked by
software command to the [110] state, where they can be erased and programmed. These blocks can
then be re-locked [111] and unlocked [110] as desired while WP# remains high. When WP# goes
low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of
any changes made while WP# was high. Device reset or power-down resets all blocks, including
those in Lock-Down, to Locked state.
Datasheet
19
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
3.7.5
Reading a Block’s Lock Status
The lock status of every block can be read in the configuration read mode of the device. To enter
this mode, write 90h to the device. Subsequent reads at Block Address + 00002 will output the lock
status of that block. The lock status is represented by the least significant outputs, DQ0 and DQ1.
DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the
Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates LockDown status and is set by the Lock-Down command. It cannot be cleared by software, only by
device reset or power-down.
Table 7.
Block Lock Status
Item
Block Lock Configuration
Address
Data
XX002
LOCK
• Block Is Unlocked
• Block Is Locked
• Block Is Locked-Down
3.7.6
DQ0 = 0
DQ0 = 1
DQ1 = 1
Locking Operation during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard
locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when
another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the erase suspend command (B0h),
then check the status register until it indicates that the erase operation has been suspended. Next
write the desired lock command sequence to a block and the lock status will be changed. After
completing any desired lock, read, or program operations, resume the erase operation with the
Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the locking status
bits will be changed immediately, but when the erase is resumed, the erase operation will complete.
Locking operations cannot be performed during a program suspend.
3.7.7
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce
ambiguity into status register results.
Since locking changes are performed using a two cycle command sequence, e.g., 60h followed by
01h to lock a block, following the Configuration Setup command (60h) with an invalid command
will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock
command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1, and will remain at 1
after the erase is resumed. When erase is complete, any possible error during the erase cannot be
detected via the status register because of the previous locking command error.
A similar situation happens if an error occurs during a program operation error nested within an
erase suspend.
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 8.
Block Locking State Transitions
Current State
Next State after Command Input
WP#
DQ1
DQ0
Name
Erase/
Program
Allowed?
0
0
0
Unlocked
Yes
Go To [001]
–
Go To [011]
1
0
0
Unlocked
Yes
Go To [101]
–
Go To [111]
0
0
1
Locked (Default)
No
–
Go To [000]
Go To [011]
Lock
Unlock
Lock-Down
1
0
1
Locked
No
–
Go To [100]
Go To [111]
0
1
1
Locked-Down
No
–
–
–
1
1
0
Yes
Go To [111]
–
Go To [111]
1
1
1
Lock-Down
Disabled
No
-
Go To [110]
–
NOTES:
1. “–” indicates no change in the current state.
2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current
locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0 indicates if a
block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0).
3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the recommended
default.
4. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled (No) in
that block’s current locking state.
5. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock, Unlock,
Lock-Down) in the current locking state. For example, “Goes To [001]” would mean that writing the command to a block in the
current locking state would change it to [001].
6. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel
factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs to program
as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.
3.8
128 Bit Protection Register
The 3 Volt Intel® Advanced+ Stacked-CSP architecture includes a 128-bit protection register than
can be used to increase the security of a system design. For example, the number contained in the
protection register can be used to “mate” the flash component with other system components such
as the CPU or ASIC, preventing device substitution.
3.8.1
Reading the Protection Register
The protection register is read in the configuration read mode. The device is switched to this mode
by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses
shown in Appendix E retrieve the specified information. To return to read array mode, write the
Read Array command (FFh).
3.8.2
Programming the Protection Register (C0h)
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection
Program Setup command, C0h. The next write to the device will latch in address and data and
program the specified location. The allowable addresses are shown in Appendix E. See Figure 20,
“Protection Register Programming Flowchart” on page 51.
Datasheet
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Any attempt to address Protection Program commands outside the defined protection register
address space will result in a status register error (program error bit SR.4 will be set to 1).
Attempting to program or to a previously locked protection register segment will result in a status
register error (program error bit SR.4 and lock error bit SR.1 will be set to 1).
3.8.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming Bit 1 of the
PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the
unique device number. This bit is set using the Protection Program command to program FFFDh to
the PR-LOCK location. After these bits have been programmed, no further changes can be made to
the values stored in the protection register. A Protection Program command to locked words will
result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).
The protection register lockout state is not reversible.
Figure 3. Protection Register Memory Map
88H
4 Words
User Programmed
85H
84H
4 Words
Factory Programmed
81H
80H
PR-LOCK
0645_05
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
4.0
Power and Reset Considerations
4.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up F-VCC, F-VCCQ and S-VCC together. Conversely, F-VCC, F-VCCQ and
S-VCC must power-down together. It is also recommended to power-up F-VPP with or slightly after
F-VCC. Conversely, F-VPP must power down with or slightly before F-VCC.
If F-VCCQ and/or F-VPP are not connected to the F-VCC supply, then F-VCC should attain FVCCMin before applying F-VCCQ and F-VPP. Device inputs should not be driven before supply
voltage = F-VCCMin. Power supply transitions should only occur when F-RP# is low.
4.2
Additional Flash Features
Intel 3 Volt Advanced+ Stacked-CSP products provide in-system programming and erase in the
1.65 V–3.3 V range. For fast production programming, it also includes a low-cost, backwardcompatible 12 V programming feature.
4.2.1
Improved 12 Volt Production Programming
When F-VPP is between 1.65 V and 3.3 V, all program and erase current is drawn through the
F-VCC signal. Note that if F-VPP is driven by a logic signal, VIH min = 1.65 V. That is, F-VPP must
remain above 1.65 V to perform in-system flash modifications. When F-VPP is connected to a 12 V
power supply, the device draws program and erase current directly from the F-VPP signal. This
eliminates the need for an external switching transistor to control the voltage F-VPP. Figure 12,
“Example Power Supply Configurations” on page 42 shows examples of how the flash power
supplies can be configured for various usage models.
The 12 V F-VPP mode enhances programming performance during the short period of time
typically found in manufacturing processes; however, it is not intended for extended use. 12 V may
be applied to F-VPP during program and erase operations for a maximum of 1000 cycles on the
main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total
of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
4.2.2
F-VPP ≤ VPPLK for Complete Protection
In addition to the flexible block locking, the F-VPP programming voltage can be held low for
absolute hardware write protection of all blocks in the flash device. When F-VPP is below VPPLK,
any program or erase operation will result in a error, prompting the corresponding status register bit
(SR.3) to be set.
Datasheet
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.0
Electrical Specifications
5.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
NOTICE: This datasheet contains information on products in full production. The specifications are subject to
change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a
design.
Table 9.
Absolute Maximum Ratings
Parameter
Maximum Rating
Notes
Extended Operating Temperature
During Read
During Flash Block Erase and Program
–25°C to +85°C
Temperature under Bias
Storage Temperature
–65°C to +125°C
Voltage on Any Ball (except F-VCC /F-VCCQ / S-VCC and F-VPP) with
Respect to GND
–0.5 V to +3.3 V
1
F-VPP Voltage (for Block Erase and Program) with Respect to GND
–0.5 V to +13.5 V
1,2,4
F-VCC / F-VCCQ / S-VCC Supply Voltage with Respect to GND
–0.2V to +3.3 V
Output Short Circuit Current
100 mA
3
NOTES:
1. Minimum DC voltage is –0.5 V on input/output balls. During transitions, this level may undershoot to –
2.0 V for periods < 20 ns. Maximum DC voltage on input/output balls is F-VCC / F-VCCQ / S-VCC + 0.5 V
which, during transitions, may overshoot to
F-VCC / F-VCCQ / S-VCC + 2.0 V for periods < 20 ns.
2. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns.
3. F-VPP voltage is normally 1.65 V–3.3 V. Connection to supply of 11.4 V–12.6 V can only be done for
1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. F-VPP
may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for details
4. Output shorted for no more than one second. No more than one output shorted at a time.
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.2
Operating Conditions
Table 10. Temperature and Voltage Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
–25
+85
°C
TCASE
Operating Temperature
VCC / VCCQ
F-VCC /F-VCCQ /S-VCC Supply
Voltage
1
2.7
3.3
Volts
VPP1
Supply Voltage
1
1.65
3.3
Volts
1, 2
11.4
12.6
2
100,000
VPP2
Cycling
Block Erase Cycling
Volts
Cycles
NOTES:
1. F-VCC/F-VCCQ must share the same supply. F-VCC/S-VCC must share the same supply when not in data
retention.
2. Applying F-VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles
on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total
of 80 hours maximum. See Section 4.2.1 for details.
5.3
Capacitance
TCASE = +25°C, f = 1 MHz
Sym
Parameter
Notes
Typ
Max
Units
Conditions
CIN
Input Capacitance
1
16
18
pF
VIN = 0 V
COUT
Output Capacitance
1
20
22
pF
VOUT = 0 V
NOTE: Sampled, not 100% tested.
Datasheet
25
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.4
DC Characteristics
Table 11. DC Characteristics (Sheet 1 of 2)
2.7 V – 3.3 V
Symbol
Parameter
Device
Note
Unit
Typ
ILI
Input Load Current
Flash/
SRAM
1
ILO
Output Leakage Current
Flash/
SRAM
1
0.25µm
Flash
1
ICCS
ICCD
ICC
ICC2
ICCR
26
VCC Standby Current
VCC Deep Power-Down Current
Operating Power Supply Current
(cycle time = 1 µs)
Operating Power Supply Current
(min cycle time)
VCC Read Current
±2
µA
0.2
± 10
µA
10
25
0.13µm
and
0.18µm
Flash
1
7
15
2-Mb
SRAM
1
-
10
4-Mb
SRAM
1
-
15
µA
8-Mb
SRAM
1
-
25
µA
0.25µm
Flash
1
7
25
µA
µA
F-VCC/S-VCC = VCC Max
VIN = VCCMax or GND
F-VCC/S-VCC = VCC Max
VIN = VCC Max or GND
F-VCC = VCC Max
F-CE# = F-RP# = VCC
F-WP# = VCC or GND
VIN = VCC Max or GND
S-VCC = VCC Max
S-CS1# = VCC, S-CS2 = VCC
or S-CS2 = GND
VIN = VCC Max or GND
F-VCC = VCCMax
0.13µm
and
0.18µm
Flash
1
7
15
2-Mb
SRAM
1
-
7
µA
VIN = VCC Max or GND
F-RP# = GND ± 0.2 V
mA
IIO = 0 mA, S-CS1# = VIL
S-CS2 = S-WE# = VIH
VIN = VIL or VIH
4-Mb
SRAM
1
-
10
mA
8-Mb
SRAM
1
-
10
mA
2-Mb
SRAM
1
-
40
mA
4-Mb
SRAM
1
-
45
mA
8-Mb
SRAM
1
-
50
mA
0.25µm
Flash
1,2
10
18
mA
0.13µm
and
0.18µm
Flash
Test Conditions
Max
Cycle time = Min, 100% duty,
IIO = 0 mA, S-CS1# = VIL,
S-CS2 = VIH, VIN = VIL or VIH
F-VCC = VCCMax
F-OE# = VIH, F-CE# = VIL
1,2
9
18
mA
f = 5 MHz, IOUT = 0 mA
VIN = VIL or VIH
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 11. DC Characteristics (Sheet 2 of 2)
2.7 V – 3.3 V
Symbol
ICCW
ICCE
ICCES
ICCWS
Parameter
VCC Program Current
VCC Erase Current
VCC Erase Suspend Current
VCC Program Suspend Current
Device
Flash
Flash
Note
Unit
Typ
Max
18
55
mA
8
22
mA
16
45
mA
8
15
mA
µA
Test Conditions
F-VPP = VPP1
Program in Progress
1,3
F-VPP = VPP2 (12 V)
Program in Progress
F-VPP = VPP1
Erase in Progress
1,3
Flash
1,3,4
7
15
0.25µm
Flash
1,3,4
10
25
0.13µm
and
0.18µm
Flash
1,3,4
7
15
µA
F-VPP = VPP2 (12 V)
Erase in Progress
F-CE# = VCC, Erase Suspend
in Progress
F-CE# = VCC, Program
Suspend in Progress
F-RP# = GND ± 0.2 V
IPPD
F-VPP Deep Power-Down Current
Flash
1
0.2
5
µA
F-VPP ≤ VCC
IPPS
F-VPP Standby Current
Flash
1
0.2
5
µA
F-VPP ≤ VCC
1
2
F-VPP Read Current
Flash
±15
µA
IPPR
F-VPP ≤ VCC
1,2
50
200
µA
F-VPP ≥ VCC
0.05
0.1
mA
8
22
mA
0.05
0.1
ma
0.2
5
µA
50
200
µA
0.2
5
µA
50
200
µA
IPPW
IPPE
IPPES
IPPWS
F-VPP Program Current
F-VPP Erase Current
F-VPP Erase Suspend Current
F-VPP Program Suspend Current
Flash
Flash
Flash
Flash
F-VPP =VPP1
Program in Progress
1,2
1,2
F-VPP = VPP2 (12 V)
Program in Progress
F-VPP = VPP1
Erase in Progress
F-VPP = VPP1
Erase Suspend in Progress
1,2
1,2
F-VPP = VPP2 (12 V)
Erase Suspend in Progress
F-VPP = VPP1
Program Suspend in Progress
F-VPP = VPP2 (12 V)
Program Suspend in Progress
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal F-VCC/S-VCC, TCASE = +25 °C.
2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
3. Sampled, not 100% tested.
4. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES
and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR.
Datasheet
27
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 12. DC Characteristics
2.7 V – 3.3 V
Symbol
Parameter
Device
Note
Units
Min
Max
VIL
Input Low Voltage
Flash/
SRAM
–0.2
0.6
V
VIH
Input High Voltage
Flash/
SRAM
2.3
VCC
+0.2
V
VOL
Output Low Voltage
Flash/
SRAM
–0.10
0.10
V
VOH
Output High Voltage
Flash/
SRAM
VCC –
0.1
VPPLK
F-VPP Lock-Out Voltage
Flash
Flash
1
V
1.0
V
V
VPP1
F-VPP during Program / Erase
VPP2
Operations
1
1.65
3.3
1,2
11.4
12.6
VLKO
VCC Prog/Erase Lock Voltage
Flash
1.5
V
VLKO2
VCCQ Prog/Erase Lock Voltage
Flash
1.2
V
Test Conditions
F-VCC/S-VCC = VCC Min
IOL = 100 µA
F-VCC/S-VCC = VCC Min
IOH = –100 µA
Complete Write Protection
NOTES:
1. Erase and Program are inhibited when F-Vpp < VPPLK and not guaranteed outside the valid F-Vpp ranges of VPP1 and VPP2.
2. Applying F-Vpp = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. F-Vpp may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for
details.
Figure 4. Input/Output Reference Waveform
VCC
VCC
INPUT
2
VCC
TEST POINTS
2
OUTPUT
0.0
NOTE: AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
timing ends, at VCCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
when VCCQ = VCCQMin.
0645_07
Figure 5. Test Configuration
Device
Under Test
Out
CL
0666_05
NOTE: CL includes jig capacitance.
28
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Flash Test Configuration Component Values Table
Test Configuration
2.7 V–3.3 V Standard Test
5.5
CL (pF)
50
Flash AC Characteristics.
Table 13. Flash AC Characteristics—Read Operations
Density
16-Mbit
Product
#
Sym
-70
-90
-110
-70
-90
Parameter
Unit
Voltage Range
Note
R1
32-Mbit
tAVAV
Read Cycle Time
2.7 V - 3.3 V
Min
Max
70
Min
Max
90
Min
Max
110
Min
Max
70
Min
Max
90
ns
R2
tAVQV
Address to Output Delay
R3
tELQV
F-CE# to Output Delay
1
R4
tGLQV
F-OE# to Output Delay
1
R5
tPHQV
F-RP# to Output Delay
R6
tELQX
F-CE# to Output in Low Z
2
0
0
0
0
0
ns
R7
tGLQX
F-OE# to Output in Low Z
2
0
0
0
0
0
ns
70
90
110
70
90
ns
70
90
110
70
90
ns
20
30
30
20
20
ns
150
150
150
150
150
ns
R8
tEHQZ
F-CE# to Output in High Z
2
20
25
25
20
20
ns
R9
tGHQZ
F-OE# to Output in High Z
2
20
20
20
20
20
ns
R10
tOH
Output Hold from Address
F-CE#, or F-OE# Change,
Whichever Occurs First
2
0
0
0
0
0
ns
NOTES:
1. F-OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV
2. Sampled, but not 100% tested.
3. See Figure 6, “AC Waveform: Flash Read Operations” on page 30.
4. See Figure 4, “Input/Output Reference Waveform” on page 28 for timing measurements and maximum allowable input slew
rate.
Datasheet
29
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 6. AC Waveform: Flash Read Operations
VIH
ADDRESSES (A)
VIL
CE# (E)
Data
Valid
Device and
Address Selection
Standby
Address Stable
R1
VIH
VIL
R8
VIH
OE# (G)
VIL
R9
VIH
WE# (W)
VIL
VOH
DATA (D/Q)
VOL
RP#(P)
High Z
R4
R10
R3
R6
Valid Output
High Z
R2
VIH
VIL
30
R7
R5
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.6
Flash AC Characteristics—Write Operations
Table 14. Flash AC Characteristics—Write Operations
Density
Product
#
Sym
16-Mbit
-70
-90
32-Mbit
-110
-70
-90
Parameter
Unit
2.7 V - 3.3 V
Voltage Range
Note
Min
Min
Min
Min
Min
150
150
150
150
150
W1
tPHWL tPHEL
F-RP# High Recovery to F-WE# (F-CE#) Going Low
ns
W2
tELWL tWLEL
F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low
0
0
0
0
0
ns
W3
tELEH tWLWH
F-WE# (F-CE#) Pulse Width
1
45
60
70
45
60
ns
W4
tDVWH tDVEH
Data Setup to F-WE# (F-CE#) Going High
2
40
50
60
40
40
ns
W5
tAVWH tAVEH
Address Setup to F-WE# (F-CE#) Going High
2
50
60
70
50
60
ns
W6
tWHEH tEHWH
F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High
0
0
0
0
0
ns
W7
tWHDX tEHDX
Data Hold Time from F-WE# (F-CE#) High
2
0
0
0
0
0
ns
W8
tWHAX tEHAX
Address Hold Time from F-WE# (F-CE#) High
2
0
0
0
0
0
ns
W9
tWHWL tEHEL
F-WE# (F-CE#) Pulse Width High
1
25
30
30
25
30
ns
W10
tVPWH tVPEH
F-VPP Setup to F-WE# (F-CE#) Going High
3
200
200
200
200
200
ns
W11
tQVVL
F-VPP Hold from Valid SRD
3
0
0
0
0
0
ns
NOTES:
1. Write pulse width (tWP) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or
F-WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high
(tWPH) is defined from F-CE# or F-WE# going high (whichever goes high first) to F-CE# or
F-WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 5, “Flash Memory Command Definitions” on page 17 for valid AIN or DIN.
3. Sampled, but not 100% tested.
See Figure 4, “Input/Output Reference Waveform” on page 28 for timing measurements and maximum
allowable input slew rate.
See Figure 7, “AC Waveform: Flash Program and Erase Operations” on page 33.
5.7
Flash Erase and Program Timings(1)
Table 15. Flash Erase and Program Timings (Sheet 1 of 2)
F-VPP
Symbol
1.65 V– 3.3 V
11.4 V– 12.6 V
Parameter
Unit
Note
Typ(1)
Max
Typ(1)
Max
tBWPB
4-KW Parameter Block Program Time (Word)
2, 3
0.10
0.30
0.03
0.12
s
tBWMB
32-KW Main Block Program Time (Word)
2, 3
0.8
2.4
0.24
1
s
0.25 µm Word Program Time
2, 3
22
200
8
185
0.13 µm and 0.18 µm Word Program Time
2, 3
12
200
8
185
4-KW Parameter Block Erase Time (Word)
2, 3
0.5
4
0.4
4
tWHQV1 / tEHQV1
tWHQV2 / tEHQV2
Datasheet
µs
s
31
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 15. Flash Erase and Program Timings (Sheet 2 of 2)
F-VPP
Symbol
1.65 V– 3.3 V
11.4 V– 12.6 V
Parameter
Unit
Note
Typ(1)
Max
Typ(1)
Max
2, 3
1
5
0.6
5
s
tWHRH1 / tEHRH1 Program Suspend Latency
3
5
10
5
10
µs
tWHRH2 / tEHRH2 Erase Suspend Latency
3
5
20
5
20
µs
tWHQV3 / tEHQV3 32-KW Main Block Erase Time (Word)
NOTES:
1. Typical values measured at TCASE = +25 °C and nominal voltages.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
32
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 7. AC Waveform: Flash Program and Erase Operations
VIH
A
B
C
AIN
ADDRESSES [A]
VIL
VIH
D
E
F
AIN
W8
W5
CE#(WE#) [E(W)]
(Note 1)
VIL
W6
VIH W2
OE# [G]
VIL
W9
(Note 1)
VIH
WE#(CE#) [W(E)]
VIL
W3
W4
VIH
DATA [D/Q]
High Z
VIL
RP# [P]
W7
DIN
DIN
W1
Valid
SRD
DIN
VIH
VIL
VIH
WP#
V
[V]
PP
VIL
W10
W11
VPPH 2
VPPH1
VPPLK
VIL
NOTES:
1. F-CE# must be toggled low when reading Status Register Data. F-WE# must be inactive (high) when reading
Status Register Data.
A. F-VCC Power-Up and Standby.
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F. Write Read Array Command.
Datasheet
33
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.8
Flash Reset Operations
Figure 8. AC Waveform: Reset Operation
RP# (P)
VIH
VIL
t PLPH
(A) Reset during Read Mode
t PHQV
t PHWL
t PHEL
Abort
Complete
t PLRH
RP# (P)
VIH
t PHQV
t PHWL
t PHEL
V IL
t PLPH
(B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep
Complete PowerDown
RP# (P)
VIH
t PLRH
VIL
t PHQV
t PHWL
t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
Table 16. Reset Specifications(1)
F-VCC 2.7 V – 3.3 V
Symbol
Parameter
Note
Unit
Min
Max
tPLPH
F-RP# Low to Reset during Read (If F-RP# is tied
to VCC, this specification is not applicable)
2,4
tPLRH1
F-RP# Low to Reset during Block Erase
3,4
22
µs
tPLRH2
F-RP# Low to Reset during Program
3,4
12
µs
100
ns
NOTES:
1. See Section 2.1.4, “Flash Reset” on page 13 for a full description of these conditions.
2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete
within 100 ns.
4. Sampled, but not 100% tested.
34
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.9
SRAM AC Characteristics—Read Operations
Table 17. SRAM AC Characteristics—Read Operations(1)
Density
#
Sym
Parameter
Voltage Range
Note
2/4/8-Mbit
2.7 V– 3.3 V
Min
Max
Unit
R1
tRC
Read Cycle Time
70
–
ns
R2
tAA
Address to Output Delay
–
70
ns
R3
tCO1, tCO2
S-CS1#, S-CS2 to Output Delay
–
70
ns
R4
tOE
S-OE# to Output Delay
–
35
ns
R5
tBA
S-UB#, LB# to Output Delay
–
70
ns
R6
tLZ1, tLZ2
S-CS1#, S-CS2 to Output in Low Z
2,3
5
–
ns
R7
tOLZ
S-OE# to Output in Low Z
3
0
–
ns
R8
tHZ1, tHZ2
S-CS1#, S-CS2 to Output in High Z
R9
tOHZ
S-OE# to Output in High Z
R10
tOH
Output Hold from Address, S-CS1#,
S-CS2, or S-OE# Change, Whichever Occurs
First
R11
tBLZ
S-UB#, S-LB# to Output in Low Z
R12
tBHZ
S-UB#, S-LB# to Output in High Z
2,3,4
0
25
ns
3,4
0
25
ns
0
–
ns
3
0
–
ns
3
0
25
ns
NOTE:
1. See Figure 9, “AC Waveform: SRAM Read Operations” on page 36.
2. At any given temperature and voltage condition, tHZ (Max) is less than and tLZ (Max) both for a given
device and from device to device interconnection.
3. Sampled, but not 100% tested.
4. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referenced to output voltage levels.
Datasheet
35
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 9. AC Waveform: SRAM Read Operations
Standby
Device
Address Selection
Data Valid
VIH
ADDRESSES (A)
Address Stable
VIL
R1
VIH
CS1# (E1)
VIL
VIH
CS2 (E2)
R3
VIL
R2
OE# (G)
R8
VIH
VIL
WE# (W)
R9
VIH
R4
VIL
DATA (D/Q)
VOH
VOL
UB#, LB#
VIH
R7
High Z
R10
R6
High Z
Valid Output
R11
R5
R12
VIH
36
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.10
SRAM AC Characteristics—Write Operations
Table 18. SRAM AC Characteristics—Write Operations(1,2)
Density
#
Sym
Parameter
Volt
Note
2/4/8-Mbit
2.7 V – 3.3 V
Min
Max
70
–
Unit
W1
tWC
Write Cycle Time
W2
tAS
Address Setup to S-WE# (S-CS1#) and S-UB#,
S-LB# Going Low
3
0
–
W3
tWP
S-WE# (S-CS1#) Pulse Width
4
55
–
ns
W4
tDW
Data to Write Time Overlap
30
–
ns
W5
tAW
Address Setup to S-WE# (S-CS1#) Going High
60
–
ns
W6
tCW
S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going
High
60
–
W7
tDH
Data Hold Time from S-WE# (S-CS1#) High
0
–
ns
W8
tWR
Write Recovery
0
–
ns
W9
tBW
S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going
High
60
–
5
ns
ns
ns
ns
NOTES:
1. See Figure 10, “AC Waveform: SRAM Write Operations” on page 38.
2. A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1# goes
low and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or simultaneously
asserting
S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS1# goes high
and S-WE# goes high. The tWP is measured from the beginning of write to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWP is measured from S-CS1# going low to end of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1#
or S-WE# going high.
Datasheet
37
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 10. AC Waveform: SRAM Write Operations
Standby
Device
Address Selection
VIH
ADDRESSES (A)
Address Stable
VIL
W1
VIH
CS1# (E1)
W8
VIL
VIH
CS2 (E2)
OE# (G)
VIL
W6
VIH
W5
VIL
WE# (W)
W3
VIH
VIL
W7
W4
DATA (D/Q)
VOH
High Z
Data In
High Z
VOL
W2
VIH
UB#, LB#
38
W9
VIH
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.11
SRAM Data Retention Characteristics—Extended
Temperature
Table 19. SRAM Data Retention Characteristics(1)—Extended Temperature
Sym
VDR
Parameter
Note
S-VCC for Data Retention
Deep Retention Current 8-Mbit
Deep Retention Current -
IDR
2
4-Mbit
Deep Retention Current 2-Mbit
tSDR
Data Retention Set-up Time
tRDR
Recovery Time
Min
Typ
Max
Unit
1.5
–
3.3
V
–
–
6
µA
–
–
5
µA
–
–
4
µA
0
–
–
ns
tRC
–
–
ns
Test Conditions
CS1# ≥ VCC – 0.2 V
S-VCC = 1.5 V
CS1# ≥ VCC – 0.2 V
See Data Retention Waveform
NOTES:
1. Typical values at nominal S-VCC, TCASE = +25 °C.
2. S-CS1# ≥ VCC – 0.2 V, S-CS2 ≥ VCC – 0.2 V (S-CS1# controlled) or S-CS2 ≤ 0.2 V (S-CS2 controlled).
Figure 11. SRAM Data Retention Waveform
CS1# Controlled
tSDR
Data Retention Mode
tRDR
VCC
3.0/2.7V
CS1# (E1) 2.2V
VDR
GND
CS2 Controlled tSDR
Data Retention Mode
tRDR
VCC
3.0/2.7V
CS2 (E2)
VDR
0.4V
GND
Datasheet
39
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
6.0
Migration Guide Information
Typically, it is important to discuss footprint migration compatibility between a new product and
existing products. In this specific case, the Stacked-CSP allows the system designer to remove two
separate memory footprints for individual flash and SRAM and replace them with a single
footprint, thus resulting in an overall reduction in board space required. This implies that a new
printed circuit board would be used to take advantage of this feature.
Since the flash in Stacked-CSP shares the same features as the Advanced+ Boot Block Features,
conversions from the Advanced Boot Block are described in AP-658 Designing for Upgrade to the
Advanced+ Boot Block Flash Memory, order number 292216.
Please contact your local Intel representation for detailed information about specific Flash +
SRAM system migrations.
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.0
System Design Considerations
This section contains information that would have been contained in a product design guide in
earlier generations. In an effort to simplify the amount of documentation, relevant system design
considerations have been combined into this document.
7.1
Background
The Intel Advanced+ Boot Block Stacked chip scale package combines the features of the
Advanced+ Boot Block flash memory architecture with a low-power SRAM to achieve an overall
reduction in system board space. This enables applications to integrate security with simple
software and hardware configurations, while also combining the system SRAM and flash into one
common footprint. This section discusses how to take full advantage of the 3 Volt Advanced+ Boot
Block Stacked Chip Scale Package.
7.1.1
Flash + SRAM Footprint Integration
The Stacked Chip Scale Package memory solution can be used to replace a subset of the memory
subsystem within a design. Where a previous design may have used two separate footprints for
SRAM and Flash, you can now replace with the industry-standard I-ballout of the Stacked-CSP
device. This allows for an overall reduction in board space, which allows the design to integrate
both the flash and the SRAM into one component.
7.1.2
Advanced+ Boot Block Flash Memory Features
Advanced+ Boot Block adds the following new features to Intel Advanced Boot Block
architecture:
• Instant, individual block locking provides software/hardware controlled, independent locking/
unlocking of any block with zero latency to protect code and data.
• A 128-bit Protection Register enables system security implementations.
• Improved 12 V production programming simplifies the system configuration required to
implement 12 V fast programming.
• Common Flash Interface (CFI) provides component information on the chip to allow softwareindependent device upgrades.
For more information on specific advantages of the Advanced+ Boot Block Flash Memory, please
see AP-658 Designing with the Advanced+ Boot Block Flash Memory Architecture.
7.2
Flash Control Considerations
The flash device is protected against accidental block erasure or programming during power
transitions. Power supply sequencing is not required, since the device is indifferent as to which
power supply, F-VPP or F-VCC, powers-up first. Example flash power supply configurations are
shown in Figure 12, “Example Power Supply Configurations” on page 42.
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.2.1
F-RP# Connected to System Reset
The use of F-RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting F-RP# to
the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when F-VCC voltages are above VLKO. Since
both F-WE# and F-CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until F-RP# is brought to VIH, regardless of the state of its control
inputs.
By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
7.2.2
F-VCC, F-VPP and F-RP# Transition
The CUI latches commands as issued by system software and is not altered by F-VPP or F-CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
F-VCC transitions above VLKO (Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after F-VPP transitions down to
VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
Figure 12. Example Power Supply Configurations
System Supply
System Supply
12 V Supply
10 ≤ KΩ
VCC
VCC
VPP
Prot#
(Logic Signal)
VPP
12 V Fast Programming
Low-Voltage Programming
Absolute Write Protection With V PP ≤ VPPLK
Absolute Write Protection via Logic Signal
System Supply
(Note 1)
System Supply
VCC
VCC
VPP
VPP
12 V Supply
Low Voltage and 12 V Fast Programming
Low-Voltage Programming
NOTE: 1. A resistor can be used if the F-VCC supply can sink adequate current based on resistor value.
42
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.3
Noise Reduction
Stacked-CSP memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues for both the flash and SRAM:
1. Standby current levels (ICCS)
2. Read current levels (ICCR)
3. Transient peaks produced by falling and rising edges of F-CE#, S-CS1#, and S-CS2.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Twoline control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each device should have a capacitors between individual power (F-VCC, F-VCCQ, F-VPP,
S-VCC) and ground (GND) signals. High-frequency, inherently low-inductance capacitors should
be placed as close as possible to the package leads.
Noise issues within a system can cause devices to operate erratically if it is not adequately filtered.
In order to avoid any noise interaction issues within a system, it is recommended that the design
contain the appropriate number of decoupling capacitors in the system. Noise issues can also be
reduced if leads to the device are kept very short, in order to reduce inductance.
Decoupling capacitors between VCC and VSS reduce voltage spikes by supplying the extra current
needed during switching. Placing these capacitors as close to the device as possible reduces line
inductance. The capacitors should be low inductance capacitors; surface mount capacitors typically
exhibit lower inductance.
It is highly recommended that systems use a 0.1 µf capacitor for each of the D9, D10, A10 and E4
grid ballout locations (see Figure 1, “66-Ball Stacked Chip Scale Package” on page 8 for ballout).
These capacitors are necessary to avoid undesired conditions created by excess noise. Smaller
capacitors can be used to decouple higher frequencies.
Datasheet
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 13. Typical Flash + SRAM Substrate Power and Ground Connections
SUBSTRATE
FLASH DIE
SRAM DIE
S-V SSQ
A9
F-V SSQ
D3
S-VSS
S-V CC
D9
S-VCCQ
E4
F-VPP
XX
Substrate connection to package ball
S-X
SRAM die bond pad connection
F-X
Flash die bond pad connection
F-V CC
D10
F-VCCQ
A10
F-VSS
H8
NOTES:
1. Substrate connections refer to ballout locations shown in Figure 1, “66-Ball Stacked Chip Scale Package” on
page 8.
2. 0.1µf capacitors should be used with D9, D10, A10and E4.
3. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS.
4. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a VCC.
7.4
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while
also programming or erasing flash. In addition, F-CE#, S-CS1# and S-CS2 should not be enabled at
the same time. (See Table 2, “3 Volt Intel® Advanced+ Boot Block Stacked-CSP Ball
Descriptions” on page 9 for a summary of recommended operating modes.) Simultaneous
operation of the can be summarized by the following:
• SRAM read/write are during a Flash Program or Erase Operation are allowed.
• Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus
contention).
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.4.1
SRAM Operation during Flash “Busy”
This functionality provides the ability to use both the flash and the SRAM “at the same time”
within a system, similar to the operation of two devices with separate footprints. This operation can
be achieved by following the appropriate timing constraints within a system.
7.4.2
Simultaneous Bus Operations
Operations that require both the SRAM and Flash to be in active mode are disallowed. An example
of these cases would include simultaneous reads on both the flash and SRAM, which would result
in contention for the data bus. Finally, a read of one device while attempting to write to the other
(similar to the conditions of direct memory access (DMA) operation) are also not within the
recommended operating conditions. Basically, only one memory can drive the outputs out the
device at one given point in time.
7.5
Printed Circuit Board Notes
The Intel Stacked-CSP will save significant space on your PCB by combining two chips into one
BGA style package. Intel Stacked-CSP has a 0.8 mm pitch that can be routed on your Printed
Circuit Board with conventional design rules. Trace widths of 0.127 mm (0.005 inches) are typical.
Unused balls in the center of the package are not populated to further increase the routing options.
Standard surface mount process and equipment can be used for the Intel Stacked-CSP.
Figure 14. Standard PCB Design Rules Can be Used with Stacked-CSP Device
Land Pad Diameter: 0.35 mm (0.0138 in)
Solder Mask Opening: 0.50 mm (0.0198 in)
Trace Width: 0.127 mm (0.005 in)
Trace Spaces: 0.160 mm (0.00625 in)
Via Capture Pad: 0.51 mm (0.020 in)
Via Drill Size: 0.25 mm (0.010 in)
NOTE: Top View
7.6
System Design Notes Summary
The Advanced+ Boot Block Stacked-CSP allows higher levels of memory component integration.
Different power supply configurations can be used within the system to achieve different
objectives. At least three different 0.1 µf capacitors should be used to decouple the devices within a
system. SRAM reads or writes during a flash program or erase are supported operations. Standard
printed circuit board technology can be used.
Datasheet
45
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix A Program/Erase Flowcharts
Figure 15. Automated Word Programming Flowchart
Start
Write 40H
Bus Operation
Command
Write
Program Setup
Write
Program
Program Address/Data
Data = 40H
Data = Data to Program
Addr = Location to Program
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent programming operations.
No
SR.7 = 1?
Comments
SR Full Status Check can be done after each program or after a sequence of
program operations.
Yes
Write FFH after the last program operation to reset device to read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
VPP Range Error
Programming Error
0
1
SR.1 =
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = VPP Program Error
Standby
Check SR.1
1 = Attempted Program to
Locked Block - Program
Aborted
1
SR.4 =
Command
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
0
Program Successful
46
If an error is detected, clear the status register before attempting retry or other
error recovery.
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 16. Program Suspend/Resume Flowchart
Start
Bus
Operation
Command
Write
Program
Suspend
Data = B0H
Addr = X
Write
Read Status
Data = 70H
Addr = X
Comments
Write B0H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write 70H
Read
Read Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Program Suspended
0 = Program Completed
0
SR.7 =
Write
1
0
SR.2 =
Program Completed
Write
Data = FFH
Addr = X
Read array data from block
other than the one being
programmed.
Read
1
Write FFH
Read Array
Program
Resume
Data = D0H
Addr = X
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
0645_13
Datasheet
47
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 17. Automated Block Erase Flowchart
Start
Bus Operation
Write 20H
Write D0H and
Block Address
Command
Write
Erase Setup
Write
Erase Confirm
Data = D0H
Addr = Within Block to Be
Erased
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Suspend
Erase Loop
0
SR.7 =
No
Suspend Erase
Comments
Data = 20H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Yes
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
1
Full Status
Check if Desired
Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
1
Command Sequence
Error
0
1
SR.5 =
Block Erase Error
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4,5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Block Erase Error
Standby
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
VPP Range Error
SR.4,5 =
Command
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
0
1
SR.1 =
0
Attempted Erase of
Locked Block - Aborted
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
Block Erase
Successful
0645_14
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Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 18. Erase Suspend/Resume Flowchart
Start
Bus
Operation
Command
Write
Erase Suspend
Data = B0H
Addr = X
Write
Read Status
Data = 70H
Addr = X
Comments
Write B0H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write 70H
Read
Read Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Erase Suspended
0 = Erase Completed
0
SR.7 =
Write
1
0
SR.6 =
Erase Completed
Read Array
Read array data from block
other than the one being
erased.
Read
1
Write
Write FFH
Data = FFH
Addr = X
Erase Resume
Data = D0H
Addr = X
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
0645_15
Datasheet
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 19. Locking Operations Flowchart
Start
Write 60H
(Configuration Setup)
Write
01H, D0H, or 2FH
Write 90H
(Read Configuration)
Bus
Operation
Command
Write
Config. Setup
Data = 60H
Addr = X
Write
Lock, Unlock,
or Lockdown
Data= 01H (Lock Block)
D0H (Unlock Block)
2FH (Lockdown Block)
Addr=Within block to lock
Write
(Optional)
Read
Configuration
Data = 90H
Addr = X
Read
(Optional)
Block Lock
Status
Optional
Standby
(Optional)
Read Block Lock Status
Comments
Block Lock Status Data
Addr = Second addr of block
Confirm Locking Change on
DQ1, DQ0. (See Block Locking
State Table for valid
combinations.)
Locking
Change
Confirmed?
No
Write FFh
(Read Array)
Locking Change
Complete
0645_16
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Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 20. Protection Register Programming Flowchart
Start
Bus Operation
Command
Write C0H
(Protection Reg.
Program Setup)
Write
Protection Program
Setup
Data = C0H
Write
Protection Program
Data = Data to Program
Addr = Location to Program
Write Protect. Register
Address/Data
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Read Status Register
Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.
No
SR.7 = 1?
Comments
Repeat for subsequent programming operations.
Yes
SR Full Status Check can be done after each program or after a sequence of
program operations.
Full Status
Check if Desired
Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Read Status Register
Data (See Above)
VPP Range Error
0,1
SR.1, SR.4 =
Protection Register
Programming Error
Comments
Standby
SR.1 SR.3 SR.4
0
1
1
V PP Low
Standby
0
0
1
Prot. Reg.
Prog. Error
1
0
1
Register
Locked:
Aborted
1, 1
SR.3, SR.4 =
Command
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
1,1
SR.1, SR.4 =
Program Successful
Attempted Program to
Locked Register Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
0645_17
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix B CFI Query Structure
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query “database” allows system software to gain information for controlling the flash
component. This section describes the device’s CFI-compliant interface that allows the host system
to access Query data.
Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
family of devices, the Query table device starting address is a 10h, which is a word address for x16
devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data
on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high
byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 20. Summary of Query Structure Output as a Function of Device and Mode
Device
Device Address
52
Hex Offset
Code
ASCII Value
10:
11:
12:
51
52
59
“Q”
“R”
“Y”
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 21. Example of Query Structure Output of x16 and x8 Devices
Word Addressing
Offset
Hex Code
A15–A0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
B.2
Byte Addressing
Value
Offset
D15–D0
0051
0052
0059
P_IDLO
P_IDHI
PLO
PHI
A_IDLO
A_IDHI
...
Hex Code
A7–A0
“Q”
“R”
“Y”
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
...
10h
11h
12h
13h
14h
15h
16h
17h
18h
...
Value
D7–D0
51
52
59
P_IDLO
P_IDLO
P_IDHI
...
“Q”
“R”
“Y”
PrVendor
ID #
ID #
...
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table 22. Query Structure
Offset
Sub-Section Name
Description
Notes
00h
Manufacturer Code
1
01h
Device Code
1
(BA+2)h
Block Status Register
Block-specific information
1,2
04-0Fh
Reserved
Reserved for vendor-specific information
1
10h
CFI Query Identification String
Command set ID and vendor data offset
1
1Bh
System Interface Information
Device timing & voltage information
1
27h
Device Geometry Definition
Flash device layout
1
P
Primary Intel-Specific Extended
Query Table
Vendor-defined additional information specific to the
Primary Vendor Algorithm
1,3
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the
block size is 32 Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
Datasheet
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.3
Block Lock Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation. This bit is only reset by issuing another erase
operation to the block. The Block Status Register is accessed from word address 02h within each
block.
Table 23. Block Status Register
Offset
(BA+2)h
Length
1
Description
Address
Value
Notes
Block Lock Status Register
BA+2:
--00 or --01
1
BSR.0 Block Lock Status
0 = Unlocked
1 = Locked
BA+2:
(bit 0): 0 or 1
BSR.1 Block Lock-Down Status
0 = Not locked down
1 = Locked down
BA+2:
(bit 1): 0 or 1
BSR 2–7: Reserved for future use
BA+2:
(bit 2–7): 0
NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1
in word mode.)
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Table 24. CFI Identification
54
Offset
Length
Description
10h
3
Query-unique ASCII string “QRY“
13h
2
15h
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
17h
2
19h
2
Alternate vendor command set and control interface ID code
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Addr.
Hex
Code
10
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
--51
--52
--59
--03
--00
--35
--00
--00
--00
--00
--00
Value
“Q”
“R”
“Y”
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.5
System Interface Information
Table 25. System Interface Information
Offset
Length
1Bh
1
1Ch
1
1Dh
1
1Eh
1
1Fh
1
1Bh
1
1Ch
1
1Dh
1
1Eh
1
1Fh
1
1Bh
1
1Ch
1
1Dh
1
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
Datasheet
Description
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µs
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µs
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
“n” such that typical full chip erase time-out = 2n ms
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
Addr.
Hex
Code
Value
1B:
--27
2.7 V
1C:
--36
3.3 V
1D:
--B4
11.4 V
1E:
--C6
12.6 V
1F:
--05
32 µs
1B:
--27
2.7 V
1C:
--36
3.3 V
1D:
--B4
11.4 V
1E:
--C6
12.6 V
1F:
--05
32 µs
1B:
--27
2.7 V
1C:
--36
3.3 V
1D:
--B4
11.4 V
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
--04
--00
--03
--00
n/a
1s
n/a
512 µs
n/a
8s
NA
55
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.6
Device Geometry Definition
n
Table 26. Device Geometry Definition
Offset
Length
27h
28h
1
2
2Ah
2
Code
See Table Below
Description
“n” such that device size = 2n in number of bytes
Flash device interface: x8 async x16 async x8/x16 async
28:00,29:00 28:01,29:00 28:02,29:00
“n” such that maximum number of bytes in write buffer = 2n
27:
28:
29:
2A:
2B:
--01
--00
--00
--00
x16
2C:
--02
2
0
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2Ch
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks.
1
3. Symmetrically blocked partitions have one blocking region
2Dh
4
31h
4
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2D:
2E:
2F:
30:
31:
32:
33:
34:
Device Geometry Definition
16-Mbit
32-Mbit
Address
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
56
–B
–T
–B
–T
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
--15
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
--16
--01
--00
--00
--00
--02
--3E
--00
--00
--01
--07
--00
--20
--00
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
B.7
Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query table
specifies this and other similar types of information.
Table 27. Primary-Vendor Specific Extended Query
Offset(1)
P = 35h
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
Length
3
Primary extended query table
Unique ASCII string “PRI”
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is “1” then
another 31 bit field of optional features follows at the end of the bit-30
field.
(P+9)h
1
(P+A)h
(P+B)h
2
(P+C)h
1
(P+D)h
1
Datasheet
Description
(Optional Flash Features and Commands)
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Page mode read supported
bit 8 Synchronous read supported
Supported functions after suspend: read array, status, query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Addr.
Hex
Code
35:
--50
36:
--52
37:
--49
38:
--31
39:
--30
3A:
--66
3B:
--00
3C:
--00
3D:
--00
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
3E:
Value
“P”
“R”
“I”
“1”
“0”
No
Yes
Yes
No
No
Yes
Yes
No
No
--01
bit 0 = 1
3F:
--03
40:
--00
bit 0 = 1
bit 1 = 1
Yes
Yes
Yes
41:
--33
3.3 V
42:
--C0
12.0 V
57
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 28. Protection Register Information
Offset(1)
P = 35h
Length
(P+E)h
1
(P+F)h
(P+10)h
4
(P+11)h
Description
(Optional Flash Features and Commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with deviceunique serial numbers. Others are user programmable. Bits 0–15 point
to the Protection register Lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
bits 16–23 = “n” such that 2n = factory pre- programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+12)h
(P+13)h
Reserved for future use
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
58
Addr.
Hex
Code
Value
43:
--01
01
44:
--80
80h
45:
--00
00h
46:
--03
8 byte
47:
48:
--03
8 byte
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix C Word-Wide Memory Map Diagrams
16-Mbit, 32-Mbit 64-Mbit [future], Word-Wide Memory Addressing
Top Boot
Size
(KW)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16-Mbit
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
Datasheet
32-Mbit
Bottom Boot
64-Mbit
1FF000-1FFFFF
3FF000-3FFFFF
1FE000-1FEFFF
3FE000-3FEFFF
1FD000-1FDFFF
3FD000-3FDFFF
1FC000-1FCFFF
3FC000-3FCFFF
1FB000-1FBFFF
3FB000-3FBFFF
1FA000-1FAFFF
3FA000-3FAFFF
1F9000-1F9FFF
3F9000-3F9FFF
1F8000-1F8FFF
3F8000-3F8FFF
1F0000-1F7FFF
3F0000-3F7FFF
1E8000-1EFFFF
3E8000-3EFFFF
1E0000-1E7FFF
3E0000-3E7FFF
1D8000-1DFFFF
3D8000-3DFFFF
1D0000-1D7FFF
3D0000-3D7FFF
1C8000-1CFFFF
3C8000-3CFFFF
1C0000-1C7FFF
3C0000-3C7FFF
1B8000-1BFFFF
3B8000-3BFFFF
1B0000-1B7FFF
3B0000-3B7FFF
1A8000-1AFFFF
3A8000-3AFFFF
1A0000-1A7FFF
3A0000-3A7FFF
198000-19FFFF
398000-39FFFF
190000-197FFF
390000-397FFF
188000-18FFFF
388000-38FFFF
180000-187FFF
380000-387FFF
178000-17FFFF
378000-37FFFF
170000-177FFF
370000-377FFF
168000-16FFFF
368000-36FFFF
160000-167FFF
360000-367FFF
158000-15FFFF
358000-35FFFF
150000-157FFF
350000-357FFF
148000-14FFFF
348000-34FFFF
140000-147FFF
340000-347FFF
138000-13FFFF
338000-33FFFF
130000-137FFF
330000-337FFF
128000-12FFFF
328000-32FFFF
120000-127FFF
320000-327FFF
118000-11FFFF
318000-31FFFF
110000-117FFF
310000-317FFF
108000-10FFFF
308000-30FFFF
100000-107FFF
300000-307FFF
0F8000-0FFFFF
2F8000-2FFFFF
0F0000-0F7FFF
2F0000-2F7FFF
0E8000-0EFFFF
2E8000-2EFFFF
0E0000-0E7FFF
2E0000-2E7FFF
0D8000-0DFFFF
2D8000-2DFFFF
0D0000-0D7FFF
2D0000-2D7FFF
0C8000-0CFFFF
2C8000-2CFFFF
0C0000-0C7FFF
2C0000-2C7FFF
0B8000-0BFFFF
2B8000-2BFFFF
0B0000-0B7FFF
2B0000-2B7FFF
0A8000-0AFFFF
2A8000-2AFFFF
This column continues on next page
Size
(KW)
16-Mbit
32-Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
64-Mbit
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
This column continues on next page
59
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
16-Mbit, 32-Mbit, and 64-Mbit [future], Word-Wide Memory Addressing
Top Boot
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
60
16-Mbit
32-Mbit
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
Bottom Boot
64-Mbit
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-21FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
This column continues on next page
Size
(KW)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16-Mbit
32-Mbit
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
F8000-FFFFF
F0000-F7FFF
F0000-F7FFF
E8000-EFFFF
E8000-EFFFF
E0000-E7FFF
E0000-E7FFF
D8000-DFFFF
D8000-DFFFF
D0000-D7FFF
D0000-D7FFF
C8000-CFFFF
C8000-CFFFF
C0000-C7FFF
C0000-C7FFF
This column continues on next page
64-Mbit
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot
Size
(KW)
16-Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Datasheet
32-Mbit
Bottom Boot
64-Mbit
Size
(KW)
16-Mbit
32-Mbit
64-Mbit
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
61
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix D Device ID Table
Table 29. Device ID
Read Configuration Address and Data
Item
Address
Data
x16
00000
0089
16-Mbit x 16-T
x16
00001
88C2
16-Mbit x 16-B
x16
00001
88C3
Manufacturer Code
Device Code
32-Mbit x 16-T
x16
00001
88C4
32-Mbit x 16-B
x16
00001
88C5
NOTE: Other locations within the configuration address space are reserved by Intel for future
use.
62
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix E Protection Register Addressing
Table 30. Protection Register Addressing
Word-Wide Protection Register Addressing
Word
Use
A7
A6
A5
A4
A3
A2
A1
A0
LOCK
Both
1
0
0
0
0
0
0
0
0
Factory
1
0
0
0
0
0
0
1
1
Factory
1
0
0
0
0
0
1
0
2
Factory
1
0
0
0
0
0
1
1
3
Factory
1
0
0
0
0
1
0
0
4
User
1
0
0
0
0
1
0
1
5
User
1
0
0
0
0
1
1
0
6
User
1
0
0
0
0
1
1
1
7
User
1
0
0
0
1
0
0
0
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection
Register, i.e., A21–A8 = 0.
Datasheet
63
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix F Mechanical and Shipping Media Details
F.1
Mechanical Specification
Figure 21. Stacked-CSP: 12 x 8 Ball Matrix
A1
Index
1
2
S2
3
4
5
6
7
8
9
10
11
12
12
11
10
9
8
7
6
5
4
3
E
2
S1
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
b
e
D
Top View - Ball Down
Bottom View - Ball Up
A2
A
Y
A1
NOTE:
64
Shaded pins indicate upper address balls for 64-Mbit and 128-Mbit devices. In all Flash and SRAM combinations, 66
balls are populated on lower density devices. (Upper address balls are not populated).
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 31. Packaging Specifications (0.18µm and 0.25µm)
Millimeters
Sym
Package Height
A
Ball Height
A1
Package Body Thickness
A2
Ball Lead Diameter
b
Package Body Length – 16-Mbit/2-Mbit
Package Body Length –
32-Mbit/4-Mbit, 16-Mbit/4-Mbit
D
Package Body Length –
32-Mbit/8-Mbit
Min
Nom
Inches
Max
Min
Nom
1. 400
0.250
Max
0.0551
0.0098
0.960
0.0378
0.350
0.400
0.450
0.0138
0.0157
0.0177
9.900
10.00
10.100
0.3898
0.3937
0.3976
11.900
12.000
12.100
0.4685
0.4724
0.4764
13.900
14.000
14.100
0.5472
0.5512
0.5551
7.900
8.000
8.100
0.3110
0.3150
0.3189
Package Body Width –
16-Mbit/2-Mbit, 16-Mbit/4-Mbit,
E
32-Mbit/4-Mbit, 32-Mbit/8-Mbit
Pitch
e
0.800
0.0315
Ball (Lead) Count
N
66
66
Seating Plane Coplanarity
Y
0.100
0.0039
Corner to Ball A1 Distance Along E
16-Mbit/2-Mbit, 16-Mbit/4-Mbit,
S1
1.100
1.200
1.300
0.0433
0.0472
0.0512
0.500
0.600
0.700
0.0197
0.0236
0.0276
1.500
1.600
1.700
0.0591
0.0630
0.0669
2.500
2.600
2.700
0.0984
0.1024
0.1063
32-Mbit/4-Mbit, 32-Mbit/8-Mbit
Corner to Ball A1 Distance Along D
16-Mbit/2-Mbit
Corner to Ball A1 Distance Along D
32-Mbit/4-Mbit, 16-Mbit/4-Mbit
Corner to Ball A1 Distance Along D
32-Mbit/8-Mbit
Datasheet
S2
65
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 32. Packaging Specifications (0.13µm)
Millimeters
Sym
Min
Nom
Package Height
16/02-Mb, 16/04-Mb, 32/08-Mb
Inches
Max
Min
Nom
Max
1. 200
0.0472
1. 400
0.0551
A
Package Height
32/04-Mb
Ball Height
16/02-Mb, 16/04-Mb, 32/08-Mb
0.200
0.0079
0.250
0.0098
A1
Ball Height
32/04-Mb
Package Body Thickness
16/02-Mb, 16/04-Mb, 32/08-Mb
0.860
0.0339
0.960
0.0378
A2
Package Body Thickness
32/04-Mb
Ball (Lead) Width
16/02-Mb, 16/04-Mb, 32/08-Mb
0.325
0.375
0.425
0.0128
0.0148
0.0167
0.350
0.40
0.450
0.0138
0.0157
0.0177
9.900
10.000
10.100
0.3898
0.3937
0.3976
11.900
12.000
12.100
0.4685
0.4724
0.4764
7.900
8.000
8.100
0.3110
0.3150
0.3189
b
Ball (Lead) Width
32/04-Mb
Package Body Length
16/02-Mb, 16/04-Mb
D
Package Body Length
32/04-Mb, 32/08-Mb
Package Body Width
16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb
E
Pitch
e
0.800
0.0315
Ball (Lead) Count
N
66
66
Seating Plane Coplanarity
Y
Corner to Ball A1 Distance Along E
0.100
0.0039
S1
1.100
1.200
1.300
0.0433
0.0472
0.0512
S2
0.500
0.600
0.700
0.0197
0.0236
0.0276
S2
1.500
1.600
1.700
0.0591
0.0630
0.0669
16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb
Corner to Ball A1 Distance Along D
16/02-Mb, 16/04-Mb
Corner to Ball A1 Distance Along D
32/04-Mb, 32/08-Mb
66
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
F.2
Media Information
Figure 22. Stacked-CSP Device in Tray Orientation (8 mm x 10 mm and 8 mm x 12 mm
Device Pin 1
Tray Chamfer
NOTE: Drawing is not to scale and is only designed to show orientation of devices.
Figure 23. Stacked-CSP Device in 24 mm Tape (8 mm x 10 mm and 8 mm x 12 mm)
Device Pin 1
Datasheet
67
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix G Additional Information
Order Number
Document/Tool
292216
AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
292215
AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture
Contact Your Intel
Representative
297874
Flash Data Integrator (FDI) Software Developer’s Kit
FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for
technical documentation and tools.
68
Datasheet
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix H Ordering Information
Table 33. Ordering Information for 0.25 µm and 0.18 µm
R D 2 8 F 3 2 0 8 C 3 T 7 0
Package
RD = 8x12 Ball Matrix CSP
Product Line Designator
for all Intel Flash products
Access Speed (ns)
16 Mbit = 70, 90, 110
32 Mbit = 70, 90
T = Top Blocking
B = Bottom Blocking
Flash Density
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
SRAM Device Density
8 = x16 (8 Mbit)
4 = x16 (4 Mbit)
2 = x16 (2 Mbit)
Product Family
C3 = 3 V Advanced+ Boot Block
VCC = 2.7 V - 3.3 V
VPP = 1.65 V - 3.3 V or
11.4 V - 12.6 V
.
Table 34. Ordering Information for Combinations with 16M 0.13 µm Flash
R D 2 8 F 1 6 0 2 C 3 T D 7 0
Package
Access Speed (ns)
RD = Stacked-CSP
16 Mbit = 70 ns
Product Line Designator
38F = Intel  Flash Stacked Memory
Technology
Differentiator
D = 0.13µm
Flash Density
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
SRAM Device Density
4 = x16 (4 Mbit)
2 = x16 (2 Mbit)
Datasheet
Parameter Location
T = Top Blocking
B = Bottom Blocking
Product Family
C = Advanced+ Boot Block
Flash Memory
69
3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 35. Ordering Information for Combinations with 32M 0.13 µm Flash
R D 3 8 F 1 0 1 0 C 0 Z T L 0
Package
Device Details
RD = Stacked-CSP
0 = Original Version of
this product:
Flash Speed = 70 ns
Flash Process = 0.13 µm
Vccq = 2.7 V to 3.3 V
Product Line Designator
38F = Intel Flash Stacked Memory
Density
Flash #1 = 1 = 32 Mbit
Flash #2 = 0 = No Die
Flash #3 = 1 = 4 Mbit SRAM
= 2 = 8 Mbit SRAM
Flash #4 = 0 = No Die
Pinout Indicator
L = 72 ball "I"-ballout
Parameter Location
T = Top Blocking
B = Bottom Blocking
Product Family
C = Advanced+ Boot Block Flash Memory
Voltage
Z = 3.0V I/O
Table 36. Ordering Information Valid Combinations
0.25µm C3
Stacked-CSP
No longer available.
32-Mbit
0.18µm C3
Stacked-CSP
0.13µm C3
Stacked-CSP
RD28F3208C3T70
RD38F1010C0ZTL0
RD28F3208C3B70
RD38F1010C0ZBL0
RD28F3208C3T90
RD38F1020C0ZTL0
RD28F3208C3B90
RD38F1020C0ZBL0
RD28F3204C3T70
RD28F3204C3B70
16-Mbit
RD28F1604C3T90
RD28F1602C3T70
RD28F1602C3TD70
RD28F1604C3B90
RD28F1602C3B70
RD28F1602C3BD70
RD28F1604C3T110
RD28F1604C3TD70
RD28F1604C3B110
RD28F1604C3BD70
RD28F1602C3T90
RD28F1602C3B90
RD28F1602C3T110
RD28F1602C3B110
70
Datasheet