Revised November 1999 74AC169 4-Stage Synchronous Bidirectional Counter General Description Features The AC169 is fully synchronous 4-stage up/down counter. The AC169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock. ■ ICC reduced by 50% ■ Synchronous counting and loading ■ Built-In lookahead carry capability ■ Presettable for programmable operation ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description 74AC169SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC169SJ 74AC169MTC MTC16 74AC169PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names CEP Description Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input P0–P3 Parallel Data Inputs PE Parallel Enable Input U/D Up-Down Count Control Input Q0–Q3 Flip-Flop Outputs TC Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009934 www.fairchildsemi.com 74AC169 4-Stage Synchronous Bidirectional Counter November 1988 74AC169 Functional Description Mode Select Table The AC169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0–P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state occurs, the AC169 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). Action on Rising PE CEP CET U/D Clock Edge L X X X Load (Pn to Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial State Diagram 1. Count Enable = CEP •CET • PE 2. Up: TC = Q0•Q1•Q 2Q3•(Up)•CET 3. Down: TC = Q0• Q1•Q2•Q3 •(Down)•CET Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 2.0V to 6.0V Input Voltage (VI) VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ±50 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC (V) TA = +25°C Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA V IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) IIN Maximum Input (Note 4) Leakage Current IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent (Note 4) Supply Current 40.0 µA 5.5 4.0 VI = VCC, GND VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC169 Absolute Maximum Ratings(Note 1) 74AC169 AC Electrical Characteristics TA = +25°C, CL = 50 pF VCC (V) (Note 5) Min Typ 3.3 75 118 Frequency 5.0 100 154 Propagation Delay 3.3 2.5 9.5 Symbol Parameter fMAX Maximum Clock tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL TA = −40°C to +85°C, CL = 50 pF Max Min Max 65 MHz 90 13.0 2.0 14.5 CP to Qn (PE HIGH or LOW) 5.0 1.5 7.0 10.0 1.5 11.0 Propagation Delay 3.3 2.5 10.5 14.5 2.0 16.0 CP to Qn (PE HIGH or LOW) 5.0 1.5 7.5 11.0 1.5 12.0 Propagation Delay 3.3 4.5 13.5 18.0 3.5 22.0 CP to TC 5.0 3.0 9.5 13.0 2.0 14.0 Propagation Delay 3.3 3.5 13.5 18.0 3.0 20.5 CP to TC 5.0 2.5 9.5 13.0 2.0 14.5 Propagation Delay 3.3 3.5 11.0 15.0 3.0 16.5 CET to TC 5.0 3.0 8.0 10.5 2.5 12.0 Propagation Delay 3.3 3.0 9.5 12.5 2.5 14.5 CET to TC 5.0 2.0 7.0 9.0 1.5 10.0 Propagation Delay 3.3 3.5 11.0 15.0 3.0 17.0 U/D to TC 5.0 2.5 8.0 10.5 2.0 12.0 Propagation Delay 3.3 2.5 10.0 13.5 2.0 15.5 5.0 1.5 7.0 9.5 1.5 10.5 U/D to TC Note 5: Voltage Range 3.3 is 3.3V ± 0.3V Units ns ns ns ns ns ns ns ns Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS tH tS tH tS tH tS tH tS tH tW VCC (V) Parameter TA = +25°C, CL = 50 pF TA = −40°C to +85°C, CL = 50 pF (Note 6) Typ Setup Time, HIGH or LOW 3.3 3.0 4.5 5.0 Pn to CP 5.0 1.5 2.5 2.5 Hold Time, HIGH or LOW 3.3 −1.5 0.5 0.5 Pn to CP 5.0 −0.5 1.5 1.5 Setup Time, HIGH or LOW 3.3 7.5 10.5 12.5 CEP to CP 5.0 4.5 7.0 8.0 Hold Time, HIGH or LOW 3.3 −4.5 0 0 CEP to CP 5.0 −2.0 0.5 1.0 Setup Time, HIGH or LOW 3.3 7.0 10.0 12.0 CET to CP 5.0 4.0 6.5 8.0 Hold Time, HIGH or LOW 3.3 −6.0 0 0 CET to CP 5.0 −4.0 0.5 1.0 Setup Time, HIGH or LOW 3.3 3.5 5.5 6.5 PE to CP 5.0 2.0 3.5 4.0 Hold Time, HIGH or LOW 3.3 −3.5 0 0 PE to CP 5.0 −1.5 0.5 0.5 Setup Time, HIGH or LOW 3.3 7.0 10.0 11.5 U/D to CP 5.0 4.5 6.5 7.5 Hold Time, HIGH or LOW 3.3 −7.0 0 0 U/D to CP 5.0 −4.0 0.5 0.5 CP Pulse Width, 3.3 2.0 3.0 4.0 HIGH or LOW 5.0 2.0 3.0 3.0 Note 6: Voltage Range 3.3 is 3.3V ± 0.3V Guaranteed Minimum ns ns ns ns ns ns ns ns ns ns ns Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 60.0 pF VCC = 5.0V www.fairchildsemi.com 4 Units Conditions 74AC169 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 1.150” Narrow Body Package Number M16A 5 www.fairchildsemi.com 74AC169 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74AC169 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com 74AC169 4-Stage Synchronous Bidirectional Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8