74LVX86 LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.8 ns (TYP.) at VCC = 3.3V INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 86 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVX86 is a low voltage CMOS QUAD EXCLUSIVE OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVX86M 74LVX86T It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS March 1999 1/8 74LVX86 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 4, 9, 12 1A to 4A NAME AND FUNCT ION Data Inputs 2, 5, 10, 13 1B to 4B Data Inputs 3, 6, 8, 11 1Y to 4Y Data Outputs 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE A B Y L L L L H H H L H H H L ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to 7.0 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA VCC ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Unit Supply Voltage (note 1) 2 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage Top Operating Temperature: VCC dt/dv Input Rise and Fall Time (VCC = 3V) (note 2) 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 2/8 Valu e 0 to VCC -40 to +85 0 to 100 V o C ns/V 74LVX86 DC SPECIFICATIONS Symb ol VIH VIL Parameter High Level Input Voltage Low Level Input Voltage Test Co nditions Valu e T A = 25 oC Min. 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 T yp. Max. ICC V 2.4 0.5 3.0 0.8 0.8 0.8 0.8 High Level Output Voltage 2.0 Low Level Output Voltage 2.0 3.0 3.0 VI = V IH or V IL I O =-50 µA 1.9 2.0 1.9 IO=-50 µA 2.9 3.0 2.9 IO=-4 mA 2.58 V I (* ) = V IH or V IL IO=50 µA 0.0 0.1 0.1 IO=50 µA 0.0 0.1 0.1 (* ) V V 2.48 IO=4 mA V 0.36 0.44 Input Leakage Current 3.6 VI = 5V or GND ±0.1 ±1 µA Quiescent Supply Current 3.6 VI = VCC or GND 2 20 µA 3.0 II Max. 0.5 3.0 VOL Min. 2.0 3.6 VOH Un it -40 to 85 o C V CC (V) (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Co nditions Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 VIHD Dynamic High Voltage Input (note 1, 3) 3.3 VILD Dynamic Low Voltage Input (note 1, 3) 3.3 VOLP VOLV Valu e o -40 to 85 C Min. T yp. Max. 0.3 0.5 -0.5 -0.3 2 C L = 50 pF Un it o T A = 25 C V CC (V) Min. Max. V 0.8 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 3/8 74LVX86 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter T est Con ditio n CL (pF) V CC (V) tPLH tPHL tOSLH tOSHL Propagation Delay Time Output to Output Skew Time (note 1, 2) 2.7 2.7 15 50 3.3(*) 3.3(*) 2.7 3.3(*) 15 50 50 Valu e T A = 25 oC -40 to Min. T yp. Max. Min. 7.5 14.5 1.0 10.0 18.0 1.0 5.8 8.3 50 9.3 12.8 1.5 1.5 1.0 1.0 Un it 85 o C Max. 17.5 21.0 11.0 14.5 1.5 1.5 ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions V CC (V) Valu e T A = 25 oC Min. Un it -40 to 85 o C T yp. Max. C IN Input Capacitance 3.3 4 10 CPD Power Dissipation Capacitance (note 1) 3.3 18 Min. Max. 10 pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/4(per Gate) 4/8 74LVX86 TEST CIRCUIT CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 5/8 74LVX86 SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 6/8 74LVX86 TSSOP14 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7/8 74LVX86 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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