74LVX240 LOW VOLTAGE OCTAL BUS BUFFER (3-STATE INV.) WITH 5V TOLERANT INPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.7 ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 240 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVX240 is a low voltage CMOS OCTAL BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVX240M 74LVX240T It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. G output control governs four BUS BUFFERs. This device is designed to be used with 3 state memory address drivers, etc. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1999 1/9 74LVX240 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 1G NAME AND FUNCT ION 2, 4,6, 8 1A1 to 1A4 Data Inputs 9, 7,5, 3 2Y1 to 2Y4 Data Outputs 11, 13, 15, 17 2A1 to 2A4 Data Inputs 18, 16, 14, 12 1Y1 to 1Y4 Data Outputs Output Enable Input 19 2G 10 GND Ground (0V) Output Enable Input 20 VCC Positive Supply Voltage TRUTH TABLE INPUT G OUTPUT An Yn L L H L H L H X Z X:”H” or ”L” Z: High impedance ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7.0 V -0.5 to 7.0 V -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA DC VCC or Ground Current ± 50 mA ICC orIGND Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Unit 2 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage 0 to VCC V Top Operating Temperature: dt/dv Input Rise and Fall Time (VCC = 3V) (note 2) 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 2/9 Valu e -40 to +85 0 to 100 o C ns/V 74LVX240 DC SPECIFICATIONS Symb ol VIH VIL Parameter High Level Input Voltage Low Level Input Voltage Test Co nditions Valu e T A = 25 oC Min. 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 T yp. Max. High Level Output Voltage Low Level Output Voltage Max. V 2.4 0.5 0.5 3.0 0.8 0.8 0.8 0.8 2.0 VI(*) = IO=-50 µA 1.9 2.0 1.9 3.0 VIH or VIL IO=-50 µA 2.9 3.0 2.9 IO=-4 mA 2.58 VI(*) = VIH or VIL IO=50 µA 0.0 0.1 0.1 IO=50 µA 0.0 0.1 0.1 3.0 VOL Min. 2.0 3.6 VOH Un it -40 to 85 o C V CC (V) 2.0 3.0 V V 2.48 V IO=4 mA 0.36 0.44 Input Leakage Current 3.6 VI = 5.5Vor GND ±0.1 ±1 µA IOZ 3 State Output Leakage Current 3.6 VI = VIH orVIL VO = VCC orGND ±0.25 ±2.5 µA ICC Quiescent Supply Current 3.6 VI = VCC orGND 4 40 µA 3.0 II (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Co nditions Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 VIHD Dynamic High Voltage Input (note 1, 3) 3.3 VILD Dynamic Low Voltage Input (note 1, 3) 3.3 VOLP VOLV Valu e T A = 25 oC V CC (V) Min. T yp. Max. 0.3 0.5 -0.5 -0.3 2 CL = 50 pF Un it -40 to 85 o C Min. Max. V 0.8 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 3/9 74LVX240 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter T est Con ditio n CL (p F) V CC (V) tPLH tPHL Propagation Delay Time tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time tOSLH tOSHL Output to Output Skew Time (note 1, 2) 2.7 15 2.7 3.3(*) 3.3(*) 2.7 2.7 50 15 50 15 50 3.3 3.3(*) (*) 15 50 2.7 3.3(*) 2.7 3.3(*) 50 50 50 Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 5.7 10.1 1.0 12.5 RL = 1 KΩ RL = 1 KΩ 8.2 4.3 6.8 7.1 9.6 13.6 6.2 9.7 13.8 17.3 1.0 1.0 1.0 1.0 1.0 16.0 7.5 11.0 16.5 20.0 5.5 8.0 8.8 12.3 1.0 1.0 10.5 14.0 11.6 9.7 16.0 11.4 1.5 1.5 1.0 1.0 19.0 13.0 1.5 1.5 50 Un it ns ns ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions Input Capacitance -40 to 85 C T yp. Max. 3.3 4 10 6 pF 17 pF COUT Output Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 Min. Un it o T A = 25 C V CC (V) CIN Valu e o fIN = 10 MHz Min. Max. 10 pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n(per circuit) 4/9 74LVX240 TEST CIRCUIT T EST tPLH , tPHL SW IT CH Open tPZL , tPLZ VCC tPZH , tPHZ GND CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cicle) 5/9 74LVX240 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cicle) 6/9 74LVX240 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 7/9 74LVX240 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e E1 PIN 1 IDENTIFICATION 1 L E c D 8/9 MAX. 74LVX240 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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