Revised April 1999 74VHC123A Dual Retriggerable Monostable Multivibrator General Description An input protection circuit ensures that 0 to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. The VHC123A is an advanced high speed CMOS Monostable Multivibrator fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one-shot. The VHC123A can be triggered on the positive transition of the clear while A is held low and B is held high. The output pulse width is determined by the equation: PW = (Rx)(Cx); where PW is in seconds, R is in ohms, and C is in farads. ■ Active State: ICC = 600 µA (Max) at TA = 25°C Limits for Rx and Cx are: ■ High Noise Immunity: VNIH = VNIL = 28% VCC (min) External capacitor, Cx No limit External resistors, Rx Features ■ High Speed: tPD = 8.1 ns (typ) at TA = 25°C ■ Low Power Dissipation: ICC = 4 µA (Max) at TA = 25°C ■ Power down protection is provided on all inputs VCC = 2.0V, 5 kΩ min ■ Pin and function compatible with 74HC123A VCC > 3.0V, 1 kΩ min Ordering Code: Order Number Package Number 74VHC123AM 74VHC123ASJ 74VHC123AMTC 74VHC123AN Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS011621.prf www.fairchildsemi.com 74VHC123A Dual Retriggerable Monostable Multivibrator July 1993 74VHC123A Pin Descriptions Pin Names Truth Table Description A Trigger Inputs (Negative Edge) B Trigger Inputs (Positive Edge) CLR Reset Inputs Cx Rx Q, Q Outputs Inputs Outputs B CLR H H X L H External Capacitor H External Resistor L A X L H X X Q Q L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care H L H H L L H Function Output Enable Inhibit Inhibit Output Enable Output Enable Reset = HIGH-to-LOW Transition = LOW-to-HIGH Transition Block Diagrams Note A: Cx, Rx, Dx are external Capacitor, Resistor, and Diode, respectively. Note B: External clamping diode, Dx; External capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied. If the supply voltage is turned off, Cx discharges mainly through the internal (parasitic) diode. If C x is sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the in rush current is automatically limited and damage to the IC is avoided. The maximum value of forward current through the parasitic diode is ±20 mA. In the case of a large Cx, the limit of fall time of the supply voltage is determined as follows: tf ≥ (VCC −0.7) Cx/20 mA (tf is the time between the supply voltage turn off and the supply voltage reaching 0.4 VCC) In the event a system does not satisfy the above condition, an external clamping diode (Dx) is needed to protect the IC from rush current. System Diagram www.fairchildsemi.com 2 74VHC123A Timing Chart Functional Description voltage VrefH, the output of C2 becomes LOW, the output Q goes LOW and C2 stops its operation. That means, after triggering, when the voltage level of the Rx/Cx node reaches VrefH, the IC returns to its MONOSTABLE state. With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal delays of the IC, the width of the output pulse, t W (OUT), is as follows: tW (OUT) = 1.0 Cx Rx 1. Stand-by State The external capacitor (Cx) is fully charged to VCC in the Stand-by State. That means, before triggering, the QP and QN transistors which are connected to the Rx/ Cx node are in the off state. Two comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply current is only leakage current. 2. Trigger Operation Trigger operation is effective in any of the following three cases. First, the condition where the A input is LOW, and B input has a rising signal; second, where the B input is HIGH, and the A input has a falling signal; and third, where the A input is LOW and the B input is HIGH, and the CLR input has a rising signal. After a trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The external capacitor discharges through QN. The voltage level at the Rx/Cx node drops. If the Rx/Cx voltage level falls to the internal reference voltage VrefL, the output of C1 becomes LOW. The flip-flop is then reset and QN turns off. At that moment C1 stops but C2 continues operating. 3. Retrigger operation (74VHC123A) When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is effective only if the IC is charging Cx. The voltage level of the Rx/Cx node then falls to VrefL level again. Therefore the Q output stays HIGH if the next trigger comes in before the time period set by Cx and Rx. If the new trigger is very close to a previous trigger, such as an occurrence during the discharge cycle, it will have no effect. The minimum time for a trigger to be effective 2nd trigger, tRR (Min), depends on VCC and Cx. 4. Reset Operation After QN turns off, the voltage at the Rx/Cx node starts rising at a rate determined by the time constant of external capacitor Cx and resistor Rx. In normal operation, the CLR input is held HIGH. If CLR is LOW, a trigger has no affect because the Q output is held LOW and the trigger control F/F is reset. Also, Qp turns on and Cx is charged rapidly to VCC. Upon triggering, output Q becomes HIGH, following some delay time of the internal F/F and gates. It stays HIGH even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches the internal reference This means if CLR is set LOW, the IC goes into a wait state. 3 www.fairchildsemi.com 74VHC123A Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5 to VCC +0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature DC Output Current (IOUT) ±25 mA DC VCC/Current (ICC) ±50 mA −40° to +85°C (Topr) Input Rise and Fall Time (tr, tf) −65°C to 150°C Storage Temperature (TSTG) 0V to VCC (CLR only) VCC = 3.3V ± 0.3V Lead Temperature (TL) Soldering, 10 seconds 0 ∼ 100 ns/V VCC = 5.0V ± 0.5V 260°C 0 ∼ 20 ns/V No Limitation (Note 3) F External Capacitor - Cx >5 kΩ (Note 3) (VCC = 2.0V) External Resistor - Rx >1 kΩ (Note 3) (VCC > 3.0V) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommended operation outside data book specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float. Note 3: The maximum allowable values of Cx and Rx are a function of the leakage of capacitor Cx, the leakage of the device, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for Rx> 1 MΩ. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL VCC (V) TA = 25°C Min Typ TA = −40° to 85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 Output Voltage IIN Input Leakage Current IIN Rx/Cx Terminal 2.0 Units Conditions V 3.0 − 5.5 HIGH Level LOW Level Max V VIN = VIH V IOH = −50 µA or VIL 4.4 0.0 0.1 IOH = −4 mA V 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 IOH = −8 mA VIN = VIH 0.1 IOL = 50 µA or VIL V 3.0 0.36 0.44 IOL = 4 mA 4.5 0.36 0.44 IOL = 8 mA 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 ±0.25 ±2.50 µA VIN = VCC or GND µA VIN = VCC or GND µA Rx/Cx = 0.5 VCC Off-State Current ICC Quiescent Supply Current 5.5 4.0 40.0 ICC Active—State 3.0 160 250 280 (Note 4) 4.5 380 500 650 Supply Current 5.5 560 750 975 Note 4: Per Circuit www.fairchildsemi.com 4 VIN = VCC or GND Symbol tPLH tPHL TA = 25°C Parameter VCC (V) Propagation Delay Time 3.3 ± 0.3 Min (A, B–Q, Q) Max Min Max 13.4 20.6 1.0 24.0 15.9 24.1 1.0 27.5 5.0 ± 0.5 tPLH tPHL Propagation Delay Time 3.3 ± 0.3 (CLR Trigger—Q, Q \) 8.1 12.0 1.0 14.0 9.6 14.0 1.0 16.0 14.5 22.4 1.0 26.0 17.0 25.9 1.0 29.5 5.0 ± 0.5 tPLH tPHL Propagation Delay Time 8.7 12.9 1.0 15.0 10.2 14.9 1.0 17.0 10.3 15.8 1.0 18.5 12.8 19.3 1.0 22.0 6.3 9.4 1.0 11.0 7.8 11.4 1.0 13.0 3.3 ± 0.3 160 240 300 5.0 ± 0.5 133 200 240 3.3 ± 0.3 (CLR—Q, Q) 5.0 ± 0.5 tWOUT ∆tWOUT Output Pulse Width TA = −40°C to +85°C Typ 3.3 ± 0.3 90 100 110 90 110 5.0 ± 0.5 90 100 110 90 110 3.3 ± 0.3 0.9 1.0 1.1 0.9 1.1 5.0 ± 0.5 0.9 1.0 1.1 0.9 1.1 Units ns ns ns ns ns ns ns µs ms Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF Cx = 28 pF Rx = 2 kΩ CL = 50 pF Cx = 0.01 µF Rx = 10 kΩ CL = 50 pF Cx = 0.1 µF Rx = 10 kΩ Output Pulse Width Error ±1 Between Circuits % (In same Package) CIN Input Capacitance 4 CPD Power Dissipation 73 10 10 pF VCC = Open pF (Note 6) Capacitance Note 5: Refer to Timing Chart. Note 6: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD*VCC*fIN+ I CC1*Duty/100 + ICC/2 (per Circuit) ICC1: Active Supply Current Duty:% AC Operating Requirement Symbol tW(L) Parameter Minimum Trigger (Note 7) TA = 25°C VCC (V) Min 3.3 5.0 Typ TA = −40°C to +85°C Max Min 5.0 tW(H) Pulse Width 5.0 5.0 5.0 tW(L) Minimum Clear 3.3 5.0 5.0 5.0 5.0 Pulse Width tRR Max Units Conditions ns ns 5.0 Minimum 3.3 ± 0.3 60 Retrigger Time 5.0 ± 0.5 39 3.3 1.5 5.0 1.2 ns Rx = 1 kΩ µs Rx = 1 kΩ CX = 100 pF CX = 0.01 µF Note 7: Refer to Timing Chart. 5 www.fairchildsemi.com 74VHC123A AC Electrical Characteristics (Note 5) 74VHC123A Device Characteristics twout*Cx Characteristics (typ) tRR*VCC Characteristics (typ) Output Pulse Width Constant K-Supply Voltage (Typical) Input Equivalent Circuit www.fairchildsemi.com 6 74VHC123A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74VHC123A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC123A Dual Retriggerable Monostable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued)