Full Duplex 80C25 80C25 AutoDUPLEXTM CMOS Ethernet Interface Adapter in 28L Package 96345 Functional Features Note: Check for latest Data Sheet revision before starting any designs. ■ Low Power CMOS Technology Ethernet Serial Interface Adapter with Integrated Manchester Code Converter (MCCTM), AUI and 10Base-T Transceiver with Output Wave Shaping and on chip filters. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. ■ Meets IEEE 802.3 10Base-5, 10Base-2, 10Base-T Standards ■ Direct Interface to SEEQ & INTEL Controllers, See the 80C26 Data Sheet for Direct Interface to AMD and NSC Controllers Interface Features ■ Meets IEEE 10Base-T Standards and IEEE 802.3 standards for AUI. ■ Automatic or Manual Selection of AUI/10Base-T Interface ■ On Chip Transmit Wave Shaping and Low Pass Filter Circuits - No External Filters Required ■ Provides AutoDUPLEXTM Detect Function for SEEQ LAN Controllers, Doubling Bandwidth to 20 MBits/sec for Switched Networks ■ Link Integrity Test Disable, Selectable Coded Link Pulse for AutoDUPLEX Mode ■ Direct AUI interface to the Manchester Code Converter. General Description DO – 5 25 TPO + CI + 6 24 TPO – CI – 7 23 TPI + 28 Pin PLCC Top View TXD FDPLX_DET 11 19 RXD The SEEQ 80C25 is a CMOS single chip Ethernet serial interface adapter with a integrated Manchester Code Converter (MCC), AUI & 10Base-T transceiver with wave shaping & filters eliminating the need for external filters. The 80C25 is designed to interface directly with SEEQ and Intel Ethernet data link controllers. The chip provides automatic polarity correction, automatic port selection, separate analog & digital ground pins & a link disable feature. It also provides a selectable coded link pulse to implement AutoDUPLEX function together with SEEQ family of controllers allowing seamless full duplex operation in switched network implementations doubling network bandwidth to 20 Mbps in 10Base-T. The 80C25 is typically suitable for adapter boards, motherboards and stand-alone TP transceiver designs & switching hubs. RXC 18 20 X1 17 LNK_LED/LNK_DIS 10 GND 2 16 TXEN VCC2 15 TPI – 21 COL 14 22 9 TXC 13 8 DI – 12 DI + CSN ■ Low differential and common mode noise on TP transmit outputs. 26 REXT FDPLX 28 GND 1 27 1 3 2 4 VCC1 ■ Differential Transmit Drivers to support 50 Meters of AUI Cable Lengths. CIS Pin Configuration TP/AUI ■ Automatic Polarity Correction DO + ■ Separate Analog/Digital Power and Ground Pins to Minimize Noise MCC and AutoDUPLEX are trademarks of SEEQ Technology, Inc. 1 MD400142/D 80C25 80C25 Pin Description Pin Name I/O 1 VCC1 — 2 TP/AUI I Pullup To VCC/2 Description Power Supply. +5 Volts. TP or AUI or Autoport Select Input. This pin selects the interface to the ENDEC. This pin is a three state input that is internally biased at VCC/2. TP/AUI 1 float 0 3 CIS I Pulldown TP Port Autoport AUI Port Controller Interface Select Input. CIS 0 1 SEEQ Intel The 80C26 Provides interface to NSC and AMD Controllers. 4 DO + O AUI Transmit Output, Positive. 5 DO – O AUI Transmit Output, Negative. 6 CI + I AUI Collision Input, Positive. 7 CI – I AUI Collision Input, Negative. 8 DI + I AUI Receive Input, Positive. 9 DI – I AUI Receive Input, Negative. 10 LNK_LED I/O /LNK_DIS Link Detect Output and Link Disable Input. This pin consists of an open drain output transistor. If the pin is tied to DGND, the link test function is disabled. Otherwise, the pin is a Link Pulse Detect output and can drive an LED. LNK_LED = 1 Output Link Pulse Not Detected LNK_LED = 0 Output Link Pulse Detected LNK_LED = DGND Input Link Test Function Disabled 11 FDPLX_DET O Full Duplex Detect Output. When FDPLX_DET = 0, the device has been placed in the full duplex mode by either selection or by the AutoDUPLEX feature. 12 CSN O Carrier Sense Output. This controller interface output indicates valid data and collisions on the receive TP or AUI inputs. 13 TXC O Transmit Clock Output. This controller interface output provides a 10 MHz clock to the controller. Transmit data from the controller on TXD is clocked in on edges of TXC. 2 MD400142/D 80C25 Pin Description cont’d Pin Name I/O Description 14 COL O Collision Output. This controller interface output is asserted when collision transmit and receive data occurs and during SQE test. 15 VCC2 — Power Supply. +5 Volts. 16 GND2 — Ground. 0 Volts. 17 X1 I Crystal Oscillator Input. The master clock for the device is generated by either placing a crystal between X1 and DGND, or by applying an external clock to X1. If a crystal is used as the clock source, connect a 1M Ω resistor between X1 and GND. For external oscillator operation, connect a 470 Ω resistor in series between X1 and clock source. 18 RXC O Receive Clock Output. This controller interface output provides a 10 MHz clock to the controller. Receive data on RXD is clocked out on edges of RXC. 19 RXD O Receive Data Output. This controller interface output contains receive data decoded from the receive TP/AUI inputs and is clock out on edges of RXC. 20 TXD I Transmit Data Input. This controller interface input contains data to be transmitted on either TP or AUI transmit outputs and is clocked in on edges of TXC. 21 TXEN I Transmit Enable Input. This controller interface input has to be asserted when data on TXD is valid. 22 TPI– I Twisted Pair Receive Input, Negative. 23 TPI+ I Twisted Pair Receive Input, Positive. 24 TPO– O Twisted Pair Transmit Output, Negative. 25 TPO+ O Twisted Pair Transmit Output, Positive. 26 REXT — Transmit Current Set. An external resistor tied between this pin and AGND sets the twisted pair transmit output current level on TPO±. 27 FDPLX I Pullup to VCC/2 Full Duplex/AutoDUPLEX Mode Select Input. This pin is a three state input that is internally biased to VCC/2. FDPLX 1 float 0 28 GND1 — Full Duplex Mode AutoDUPLEX Mode Normal Ground. 0 Volts. 3 MD400142/D 80C25 BLOCK DESCRIPTION Functional Description The Encoder/Decoder Manchester encoding is a process of combining the clock & the data stream together so that they can be transmitted on the twisted pair interface or AUI at the transceiver side. Once encoded, the first half contains the complement of the data and the second half contains the true data, so that a transition is always guaranteed at the middle of a bit cell. Data encoding and transmission begins with TXEN going active, and the subsequent data is clocked on the edges of TXC and then gets encoded. The end of a transmit packet occurs at a bit cell center if the last bit is a "ONE" or at a bit boundary if the last bit is a "ZERO". The 80C25 is an Ethernet adapter with a integrated Manchester Code Converter, 10Base-T transceiver with on chip filters. The device contains both 10Base-T and AUI interfaces compliant with IEEE 802.3 specifications. The chip is divided into four major blocks, namely (i) The controller interface (ii) The Encoder / Decoder (iii) The twisted pair interface and (iv) The AUI. The input signals are received on the TP or AUI receivers depending on which is selected. Both the twisted pair and AUI receivers contain a threshold comparator to validate the signal and a zero crossing comparator for checking the transitions. Then the data is sent to the PLL in the decoder to separate the data from the clock. On the other side, digital transmit data is clocked into the device via the controller interface. The data is then sent to the Manchester encoder to be encoded. Encoded data is then transmitted on the twisted pair or AUI based on the selected port. The decoding is a process of recovering the encoded data stream coming from the receiver side and decoding it back into the clock and data outputs using the phase locked loop technique. The PLL is designed to lock into the preamble of the incoming signal at less than 15 bit times with a maximum jitter of ±13.5 ns at the TPI or AUI inputs and can also sample the incoming data with this amount of jitter. The ENDEC asserts the CSN signal to indicate to the controller that the data and clock received are valid and available. There is an inhibit period after the end of a frame after a node has finished transmitting for 4.4 µs during which CSN is deasserted irregardless of the state of the receiver and collision status. The Controller Interface The 80C25 is designed to interface directly to all of SEEQ's Ethernet controllers, and INTEL's 82586/596/592/593 LAN controllers, with the use of CIS Pin. The controller interface consists of the Transmit/Receive data (TXD/ RXD), transmit/receive Clocks (TXC/RXC), the Transmit Enable (TXEN) input, the collision output (COLL), the Full Duplex acknowledgment (FDPLX_DET) and the Carrier Sense Output (CSN) pins. On the transmit side, data on TXD is clocked into the device on the edges of TXC clock output only when the data valid signal (TXEN) is asserted. On the receive side, data on RXD is clocked out on edges of RXC. In the SEEQ mode, RXC follows TXC for 1.5 µs and then switches to the recovered clock. In the Intel mode, RXC is held low for 1.5 µs while the PLL is acquiring lock and then switches to the recovered lock. The FDPLX_DET pin signifies to the controller that full duplex channels have been established. Twisted Pair Interface (a) The transmitter function The transmitter transfers Manchester encoded data from the ENDEC to the twisted pair cable. The circuit consists of a set of functional blocks to provide pre-coded waveshaped, pre-equalized and smoothed waveforms so that the outputs are made to appear as though it had passed through a 5-7th order external elliptic passive filter, thereby eliminating the need for an external filter. The waveform generator consists of a ROM, DAC, PLL, filter and a output driver to preshape the output waveform transmitted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE STD 802.3 and illustrated in figure 12. The DAC first converts the data pulse into a stair stepped representation of the desired output waveform, which goes through a second order low-pass filter. The DAC values are determined from the ROM addresses, which are chosen to have different values for long and short data bits so as to shape the pulse to meet the 10Base-T waveform template. The line driver takes the smoothed current waveform and converts it into an high current output that can drive the TP directly without any external filters. The current output is guaranteed to have a The 80C25 supports SEEQ and INTEL Controllers according to Table 1. Table 1. CIS Pin Description CIS Controller Interface 0 SEEQ 1 INTEL 4 MD400142/D GND 2 V CC2 GND 1 V CC1 LNK_LED/LNK_DIS FDPLX_DET FDPLX CIS TP/AUI COLL CSN RXD RXC TXEN TXD TXC MODE INPUTS AND OUTPUTS CONTROLLER INTERFACE RECEIVE DATA TRANSMIT DATA POLARITY DETECT LINK PULSE DETECT TP SQUELCH LINK PULSE DETECT PORT DETECT AUTO DUPLEX DETECT DAC AUI SQUELCH SOI DETECT SOI GEN CLOCK GEN (PLL) ROM TP INTERFACE COLLISION DATA Figure 1. 80C25 Block Diagram COLLISION DETECT MANCHESTER DECODER (PLL) MANCHESTER ENCODER ENDEC JABBER DETECT – + +/–Vth LP FILTER –Vth –Vth – 5 + – + + OSCILLATOR – + + – MD400142/D + – + + X1 LP FILTER – + CI– CI+ RX– RX+ TX– TX+ TPI– TPI+ TPO– TPO+ REXT 80C25 80C25 The 80C25 is switched on to the AutoDUPLEX mode when FDPLX is left floating. In this configuration, Full duplex mode is automatically established by the successful detection of double pulses embedded within the regular link pulses. The 80C25 sends the double pulses in 16 pulse intervals constantly on the TPO ± pins and continually monitors the TPI ± pins for similar type of double pulses within a time window of 210 ± 6ms. Once the double pulses are detected, the FDPLX_DET will go low to acknowledge to the controller that the network will allow simultaneous transmission and reception on the TP port. The maximum distance between two consecutive pulses in a double pulse is 5.4 µs. very low common mode and differential noise. The interface to the twisted pair cable requires a transformer with a ratio of 2:1 on transmit and a 1:1 on receive, with two 200 ohm resistors connected as shown in figure 2. The output driver is a current source. The output current level is set by the values of the resistor tied between the REXT and AGND. The current level is determined by the following equation. I = (REXT/10K)* 50 mA OUT Though a 10K resistor will meet the template requirements specified with a no load condition, a capacitive or inductive loading can influence the level, because the transmitter has a current source output. So, in a actual application, it might be necessary to adjust the value to compensate the loading involved. For example, the bias resistance value for a loading of 10 pf will be approximately 8K. The Forced Full-Duplex mode can be established by setting FDPLX to high. In this combination, forced full duplex is effectively established and Collision, SQE & the LoopBack functions are disabled. (b) The receiver function The receiver receives the Manchester-encoded data from the twisted pair lines( TPI ±) and passes it on to the ENDEC side, where it gets decoded back into the receive clock RXC and the receive data RXD. The inputs first go through a receive filter, which is a continuous time 3rd order low pass filter with a typical 3 dB cutoff frequency of 20-25 Mhz. The filter's output then passes through two different types of comparators, namely threshold and zero crossing. The threshold comparator compares the TPI ± inputs with fixed positive and negative thresholds called the squelch levels. The zero crossing comparator senses the transition point on the TPI ± inputs without introducing excess jitter and the outputs go to the PLL in the decoder. The receiver is transformer coupled and needs to be terminated with a 100 Ω resistor or two 50 Ω resistors and a capacitor as described in figure 2. (d) Squelch functions The squelch function is used to discriminate noise from link test pulses and valid data to prevent the noise from activating the receiver. It is accomplished by a squelch comparator which compares the TPI± signals with a fixed positive and negative squelch value. The output from the comparator goes to a receive squelch circuit which determines whether the input data is valid or not. If the data is invalid, the transceiver enters into an squelched state. The input voltage should exceed ±300mV p-p for five bit times max. (with alternating polarity) for unsquelching to occur. In the Unsquelch state, the value of the threshold in the comparator is reduced to take care of hysteresis effects. While in the unsquelch state, the receive squelch circuit looks for the SOI (Start of Idle) signal at the end of the packet. When the SOI signal is detected, the receive squelch is turned on again. (c) Full Duplex Functions The Full Duplex scheme allows the simultaneous transmission on the TPO ± and simultaneous reception on the TPI ± without interruption, effectively doubling the bandwidth to 20 MBPS in switched network implementations on 10Base-T. The 80C25 can be made to operate either in the AutoDUPLEX or in the Forced FullDuplex scheme according to Table 2. (e) The Link integrity functions The 80C25 monitors the TPI± pins continuously for valid data and link pulse activity. If neither data nor link test pulse is detected for a minimum time, the transceiver enters into a Link Test Fail State and disables the transmitter, receiver, collision presence and the SQE functions. For the transceiver to exit this state, it should receive three consecutive link pulses or valid data at the TPI ± inputs to resume normal packet transmission and reception. Additionally, the transmitter generates link pulses periodically when it's not transmitting data to indicate to the network that the link is intact. Please refer to figure 14 for the diagram illustrating the Transmit Link Pulse Voltage Tem- Table 2. FDPLX Pin Description FDPLX 1 float 0 MODE Full Duplex Mode Enabled AutoDUPLEX Enabled Normal 6 MD400142/D 80C25 plate as specified in the IEEE 802.3. The Link Pulse Detect Output and Link Pulse Disable Function are combined on one pin, LNK_LED/LNK_DIS according to Table 3. (i) Loopback functions Loopback in the TP mode is internally enabled when Manchester encoded data is transmitted on TPO ± and no data is received on the TPI ± in order to simulate Coax Ethernet behavior. When internal loopback is enabled, the transmitted data is loopbacked into the RXD and sent to the controller. The loopback function is disabled during Link Fail State, Jabber State and during Full-Duplex Operation. Table 3. LNK_LED/LNK_DIS Pin Description LNK_LED/LNK_DIS I/O Function 1 Output LinkPulseNotDetected 0 Output LinkPulseDetected Input LinkTestFunctionDisabled TietoGND2 (l) Signal Quality Error Test The Signal Quality Error test is used to indicate a successful transmission (i,e A transmission without interruptions such as Collision, jabber or Link failure) to the DTE.[1] (f) The Start of Idle (SOI) pulse The transmit SOI pulse is a positive pulse inserted at the end of every transmission to signal the end and the start of idle period to corresponding receivers. The output pulse is also shaped by the transmit waveshaper to meet the pulse requirements specified in IEEE 802.3. Please refer to figure 13 for the Transmit Start Of Idle Pulse voltage template diagram. The receiver detects the SOI pulse by sensing the missing data transitions with the zero crossing comparator. Once the SOI pulse is detected, another SOI pulse is generated and sent to the Controller interface outputs. AUI Interface The differential transmit output pair DO± sends the encoded data on to an external transceiver that is capable of driving 50 meters of 78 ohm shielded AUI cable directly with a jitter of 0.5 ns max. The receive input differential pair DI± goes through the AUI squelch comparator and the zero crossing comparator. The AUI squelch comparator compares the input signals with fixed minimum and maximum values of -175 mv and -325 mv respectively, and passes it on to the squelch circuit to determine data validity. The zero crossing comparator senses the transition point of the input pair without introducing excess jitter and passes the data to the phase locked loop of the decoder. The CI+/CI- are the collision input pair signals which expect a 5 Mhz or a 10 Mhz square wave from an external transceiver. (g) Automatic Polarity Correction The 80C25 provides autopolarity detection and correction functions for the twisted pair receiver peak detectors to determine whether normal or inverted data is received over the TPI ± pins. A polarity reversed condition is sensed and corrected when four opposite link pulses are detected without the expected polarity or if 3-4 frames are received with a reversed start-of-idle. Collisions Collisions are generated when two stations contend for the network at the same time, resulting in simultaneous activity detected on the TPO ± and TPI ±. When this happens, COLL will be asserted indicating to the controller the simultaneous transmission of two or more stations on the network. CSN is also asserted during collision. For further details about timing, refer to figures 7 and 8. (h) Jabber functions The jabber function detects abnormally long streams of Manchester-encoded data on the TXD input with the help of a Jabber detect circuit. The jabber circuit uses a Jabber timer, which monitors the TXEN pin. It starts counting at the beginning of each transmission. If the timer expires before TXEN goes inactive, the 80C25 enters a jabber state disabling the transmit/loopback functions and enabling the collision functions. If TXEN goes inactive before the timer expires, the timer is reset and becomes ready for the next transmission. Note: 1. Since SQE is internally enabled on the 80C25, on successful transmission, a collision signal is presented to the controller as an indication when the transmitter goes idle on the twisted pair network. 7 MD400142/D 80C25 Oscillator Power Supply Decoupling The internal clock generator is controlled either by an external parallel resonant crystal connected across X1 & GND2 , or by connecting a clock to the input pin X1. This external 20 Mhz clock is used by the clock circuitry and the PLL to generate a 10 Mhz ± 0.01% transmit clock. The manchester encoding process uses both the 10Mhz and 20Mhz clocks. There are two VCC's on the 80C25 (VCC1 and VCC2 ) and two GND's (GND1 and GND2). VCC1 and VCC2 should be connected together as close as possible to the device with a large VCC plane. GND1 and GND2 should also be connected together as close as possible to the device with a large ground plane. Crystal Specification: 1. Parallel resonant mode 2. Frequency ............. 20 MHz ±0.01% @ 0 – 70 °C 3. Equivalent Series Resistance ............ 25 Ω max. 4. Load Capacitance ............................. 20 pf max. 5. Case Capacitance .............................. 7 pf max. A 0.1 µF decoupling capacitor should be connected between VCC1 and GND1 as close as possible to the device pins, preferably within 0.5". The same should be repeated for VCC2 and GND2 . Automatic Port Selection The interface to the Manchester encoder can be selected to be either TP, AUI or Autoport. Port selection is done with the TP/AUI pin as described in Table 4. Table 4. TP/AUI Pin Description TP/AUI Port 1 TP float Autoport 0 AUI The Autoport mode automatically selects either the TP or AUI port by detecting the presence or absence of activity on the TPI± and DI± inputs. If autoport mode is selected, the device powers up with TP port active. If no packets or LINK pulses are detected on the TP port, the device switches to AUI port. The device will stay in AUI mode as long as no activity is detected on TP port. 8 MD400142/D 0.01 µF TxO RxI RX– RX+ CI– CI+ TX– TX+ a. Valor b. Coilcraft c. PCA d. Bel Hybrids and Magnetics e. FEE Fil-mag f. NANO Pulse 3. Transformers are available from PT4152 Q4430-A EPE6047S A553-1084-01 23Z435 000-6115-00 DI– DI+ CI– CI+ DO– DO+ 10 9 8 7 6 5 4 VCC1 1 15 80C25 16 20 MHZ 3 27 2 20 21 22 23 24 25 26 23 27 28 29 ETHERNET CONTROLLER 21 19 22 20 GND 1 2 CIS TxD TxEN TPI– TPI+ TPO– TPO+ REXT 10 K [3] Figure 2. 80C25 in Typical TP/Coax Adapter Board Application Tel: (619) 537-2500 Tel: (708) 639-6400 Tel: (818) 892-0761 Tel: (201) 432-0463 Tel: (619) 569-6577 Tel: (714) 529-2600 VCC LNK_LED / LNK_DIS 2. This resistance value will meet the template requirements specified on a no load condition. However, a capacitive or inductive loading can influence the current level. Hence it may be necessary to adjust the value to compensate the loading involved. 1. The EM2 is an Ethernet transceiver module with on board isolation transformer and a DC-DC converter. Notes: 1M CDS EM2 [2] 1K VCC2 CSN 13 CSN 12 TxC TxC 14 COLL 11 FDPLX_DET ADUPLX 9 COLL GND 2 X1 17 FDPLX 18 RxC RxC 19 RxD RxD TP/AUI TxD 0.1 µF TxEN V CC 200Ω MD400142/D 50Ω 200Ω OPTIONAL 0.1µF 50Ω 0.1 µF 0.1µF 1:1 2CT:1 TRANSFORMER RJ-45 6 3 2 1 [4] 80C25 80C25 Absolute Maximum Ratings VCC1 , VCC2 Supply Voltage .......................... –0.3V to 7V All Inputs and Outputs ..................... –0.3 to VCC + 0.3 V Latchup Current ................................................ ±25 mA Package Power Dissipation .................. 1 Watt @ 25°C Storage Temperature ............................. –65 to +150°C Operating Temperature .......................... –65 to +125°C Lead Temperature (Soldering, 10 sec) ............... 250 °C *COMMENT: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Supply Characteristics Test conditions are as follows: 1. T = 0 –70°C 2. VCC = 5V ±5% 3. 20 MHZ ±.01% 4. REXT = 10K, with no load. Limit Sym. Parameter ICC VCC Power Supply Current Min Typ Max Unit Conditions 110 85 150 110 mA mA Transmitting, TP selected Transmitting, AUI selected Max Unit Conditions 0.8 Volt All except X1, TP / AUI, FDPLX 0.8 Volt TP / AUI, FDPLX 1.5 Volt X1 VCC/2 +0.5 V Volt TP / AUI, FDPLX DC Digital I/O Characteristics Test conditions are as follows: 1. T = 0–70°C 2. VCC = 5V ±5% 3. 20 MHZ ±.01% 4. REXT = 10K, with no load. Limit Sym. Parameter VIL Input Low Voltage Min Typ VIM Input Intermediate Voltage VCC/2 –0.5 V VIH Input High Voltage 2 Volt All except X1, TP / AUI, FDPLX VCC–0.8 Volt TP/AUI, FDPLX 3.5 Volt X1 VIL Input Low Level 1.1 1.5 1.9 Volt TP/AUI, FDPLX IIH Input High Current 15 60 120 µA VIN= VCC All Except LNK_LED/LNK_DIS IIL Input Low Current –15 –60 –120 µA VIN= GND All Except CIS [1] 10 MD400142/D 80C25 DC Digital I/O Characteristics cont’d Limit Sym. Parameter VOL Output Low Voltage Min Typ Max Unit 0.4 Volt Conditions IOL= 2.1 mA FDPLX_DET, LNK_LED/LNK_DIS 1.2 Volt IOL= –20 mA LNK_LED/LNK_DIS VOH Output High Voltage 4 Volt IOH= –1 mA FDPLX_DET CIN Input Capacitance 5 pF COUT Output Capacitance 5 pF Notes: 1. Not measured due to internal pull-down to GND. 11 MD400142/D 80C25 Twisted Pair Interface Characteristics Unless otherwise specified, all test conditions are as follows: 1. T = 0–70°C 2. VCC = 5V ±5% 3. 20MHZ ±.01% 4. REXT = 10K, with no load. 5. 50 ohm load from TPO± to VCC 6. 10Mhz sine wave on TPI± Limit Sym. Parameter Min Typ Max Unit TOV TPO± Differential Output Voltage 2.2 2.5 2.8 Vpk TOVT TPO± Differential Output Voltage Template See Figure 12 TSOI TPO± SOI Output Voltage Template See Figure 13 TLPT TPO± Link Pulse Output Voltage Template See Figure 14 TOIV TPO± Differential Output Idle Voltage ±50 mV TOIA TPO± Output Current 44 50 56 mA pk TOIR TPO± Output Current Adjustment Range 30 50 80 mA pk TCMA TPO± Common Mode AC Output Voltage 10 50 mV pk THD TPO± Harmonic Distortion –27 dB TOR TPO± Output Resistance TOC TPO± Output Capacitance RST TPI± Squelch Threshold 310 540 mVpk RUT TPI± Unsquelch Threshold 190 330 mVpk RZT TPI± Zero Cross Switching Threshold 20 mVpk ROCV TPI± Input Open Circuit Voltage (VCC/3)+0.25 Volt RCMR TPI± Input Common Mode Voltage Range VCC/3+1.0 Volt (VCC/3)–0.25 10K ohms 15 pF VCC/3 VCC/3–1.0 12 MD400142/D Conditions Measured on Secondary Side of XFMR on Figure 2. VCC = 5V Adjustable with REXT 80C25 Twisted Pair Interface Characteristics cont’d Limit Sym. Parameter RDR Min Typ Max Unit TPI+/– Input Differential Voltage Range VCC Volt RCRR TPI+/– Input Common Mode Rejection Ratio –20 dB RIR TPI+/– Input Resistance RIC TPI+/– Input Capacitance 5K ohm 10 13 MD400142/D pF Conditions 0–10Mhz 80C25 AUI Characteristics Unless otherwise specified, all test conditions are as follows: 1. T = 0–70°C 2. VCC = 5V ±5% 3. 20 MHZ ±.01% 4. REXT = 10K with no load. 5. 78 ohm, 27µH load on DO± 6. 10 Mhz sine wave on DI±, CI± Limit Sym. Parameter Min AOV DO±, Differential Output Voltage 550 AORF DO±, Output Rise And Fall Time AOIV Max Unit 1200 mVpk 5 ns DO±, Differential Output Idle Voltage ±40 mV AOVU DO±, Differential Output Voltage Undershoot During Idle –100 mV AOCD DO±, Common Mode DC Output Voltage VCC/2.1 Volt AOCA DO±, Common Mode AC Output Voltage 40 mV pk AOR DO±, Output Resistance 75 ohms AOC DO±, Output Capacitance AIST DI±, CI± Squelch Threshold -175 -325 mV AIUT DI±, CI± Unsquelch Threshold -100 -225 mV AIZT DI±, CI± Zero Cross Switching Threshold 20 mVpk AIOC DI±, CI± Input Open Circuit Voltage (VCC/2)–.25 (VCC/2)+.25 Volt AICR DI±, CI± Input Common Mode Voltage Range (VCC/2)–1.0 (VCC/2)+1.0 Volt AIVR DI±, CI± Input Differential Voltage Range 0 VCC Volt AIR DI±, CI± Input Resistance 5K AIC DI±, CI± Input Capacitance VCC/3.5 Typ VCC/3.0 15 VCC/2 10K ohm 10 pF 14 MD400142/D pF Conditions tR, tF measured at 10-90% points 80C25 AC Test Timing Conditions Unless otherwise specified, all test conditions for timing characteristics are as follows: 1. T = 0 – 70°C 2. VCC = 5v ±5% 3. 20MHZ ±.01% 4. REXT = 10K, with no load. 5. Input Conditions All Inputs: tR, tF< = 10ns from 20-80% points 6. Output Loading TPO±: 50 ohms to VCC on each output, 10pF DO±: 78 ohms differentially, 10pF Open Drain Digital Outputs: 1K pullup, 50pF All Other Digital Outputs: 50pF 7. Measurement Points TPO±, TPI±, DO±, DI±, CI±: Zero crossing during data and ±.3V point at start/end of signal X1: VCC/2 All other inputs and outputs: 1.5 Volts 20 MHZ Input Clock Timing Characteristics Limit Sym. Parameter t1 X1 Cycle Time Min Typ Max Unit 49.995 50.000 50.005 ns Conditions Refer to Figure 3 for timing diagram. X1 t1 Figure 3. 20 MHZ Input Clock Timing 15 MD400142/D 80C25 Transmit Timing Characteristics Parameter Min Limit Typ Max Unit t11 TXC Cycle Time 99.99 100 100.01 ns t12 TXC High Time 40 60 ns t13 TXC Low Time 40 60 ns t14 TXC Rise Time 5 ns t15 TXC Fall Time 5 ns t16 TXEN Setup Time 30 ns t17 TXEN Hold Time 0 ns t18 TXD Setup Time 30 ns t19 TXD Hold Time 0 t20 Transmit Bit Loss 2 Bits TP and AUI t21 Transmit Propagation Delay 2 Bits TP and AUI t22 Transmit Output Jitter 8 ns TP 0.5 ns AUI Sym. t24 t25A t25B Transmit Output Rise And Fall Time Transmit SOI Pulse Width to 0.3V Point Transmit SOI Pulse Width to 40 mV Point ns See Figure 12 ns TP ns AUI 250 ns TP Measure TPO± from last zero cross to 0.3V point. 200 ns AUI Measure DO± from last zero cross to 0.3V point. 4500 ns TP Measure TPO± from last zero cross to 40mV point. 7000 ns AUI Measure DO± from last zero cross to 40 mV point. 5 Refer to Figure 4 for timing diagram. 16 MD400142/D Conditions 80C25 t 12 t 13 SEEQ t14 t15 TxC t 16 t 11 t 17 TxEN t19 t 18 TxD B0 B1 B2 B3 t 21 t25b t 25a t 20 TPO± or DO± B0 B0 B1 B1 B2 t 22 INTEL B2 B3 t 24 SAME AS SEEQ EXCEPT TxEN IS INVERTED (ACTIVE LOW). Figure 4. Transmit Timing 17 MD400142/D B3 80C25 Receive Timing Characteristics Limit Sym. Parameter t31 CSN Assert Delay Time Min Typ Max Unit Conditions 600 ns TP 240 ns AUI t32 CSN Assert Setup Time 30 ns t33 CSN Deassert Hold Time 20 40 ns SEEQ Controller 10 35 ns INTEL Controller t35 RXC to RXD Setup Time 40 t36 RXC to RXD Hold Time 30 t38 RXD Propagation Delay t39 RXC High Time 40 40 60 ns INTEL Controller t40 RXC Low Time 40 60 ns SEEQ Controller 40 1500 ns INTEL Controller, Start of Packet 40 250 ns INTEL Controller, End of Packet CSN Assert To RXC Switchover From TX Clock To RX Clock 1500 ns TP 1500 ns AUI t42 CSN Deassert To RXC Switchover From Rx Clock To Tx Clock 200 ns t43 SOI Pulse Width Required For Idle Detection 125 200 ns TP Measure TPI± from last zero cross to .3v point. 125 160 ns AUI Measure RX± from last zero cross to .45v point. ±13.5 ns Data ±8.5 ns Preamble 10 ns t41 t44 Receive Input Jitter t49 RXC, RXD, CSN Output Rise And Fall Times ns ns 200 ns 200 ns SEEQ Controller Refer to Figures 5 and 6 for timing diagram. NOTES: 1. 2. 3. 4. CI+ and CI– asserts and deasserts COLL, asynchronously, and asserts and deasserts CSN synchronously with RxC. If CI+ and CI– arrives within 4.5 µs from the time CSN was deasserted; CSN will not be reasserted (on transmission node only). When CI+ and CI– terminates, CSN will not be deasserted if DI± are still active. When the node finishes transmitting and CSN is deasserted, it cannot be asserted again for 4.5 µs. 18 MD400142/D 80C25 SEEQ 1 0 1 0 1 0 1 0 1 0 TPI± or DI± t 31 t 44 CSN t41 t 39 t 32 Tx RxC t 38 Tx t40 Tx Rx Rx Rx Rx t36 t35 RxD Rx 1 0 1 0 Figure 5a. Receive Timing — Start of Packet for SEEQ’s Controllers INTEL 1 TPI± or DI± 0 1 0 1 0 1 0 1 0 1 Rx Rx t31 t44 CSN t 41 t 40 t 32 RxC Tx Tx t38 t39 Rx Tx Rx t35 0 RxD Rx Rx t36 1 0 1 NOTE: SAME AS SEEQ EXCEPT CSN IS INVERTED (ACTIVE LOW), RxC IS INVERTED (FALLING EDGE TRIGGERED), RxC IS SHUTOFF DURING t 41 ACQUISITION TIME, RxD IS HIGH DURING t 41 ACQUISITION TIME AND DURING IDLE TIME. Figure 5b. Receive Timing — Start of Packet for Intel’s Controllers 19 MD400142/D 0 1 80C25 SEEQ B N–2 TPI± or DI± B N–1 SOI BN t 43 CSN t 42 t39 t 33 RxC Rx Rx B N–5 RxD Rx B N–4 Rx B N–3 Rx B N–2 Rx B N–1 t 40 Rx Tx BN Figure 6a. Receive Timing — End of Packet for SEEQ’s Controllers. INTEL B N-2 B N-1 BN SOI TPI± or DI± t 43 CSN t 42 t 40 t33 RxC Rx Rx B N-5 RxD Rx B N-4 Rx B N-3 Rx Rx B N-2 B N-1 t39 Tx Tx Tx BN NOTE: SAME AS SEEQ EXCEPT TxEN IS INVERTED (ACTIVE LOW), RxC IS INVERTED RxC IS SHUTOFF DURING t 41 ACQUISITION TIME, RxD IS HIGH DURING t 41 ACQUISITION TIME, REFER TO FIGURE 6a. Figure 6b. Receive Timing — End of Packet for Intel’s Controllers. 20 MD400142/D Tx 80C25 Collision Timing Characteristics Sym. Parameter t51 COLL Assert Delay Time Rcv After Xmt t52 t53 t54 Min Limit Typ COLL Assert Delay Time Xmt After Rcv COLL Deassert Delay Time - Rcv After Xmt COLL Deassert Delay Time - Xmt After Rcv Max Unit 600 ns TP TPI± to COLL 300 ns AUI CI± to COLL 600 ns TP TPO± to COLL 300 ns AUI CI± to COLL 500 ns TP TPI± to COLL 500 ns AUI CI± to COLL 500 ns TP TPO± to COLL 500 ns AUI CI± to COLL 10 ns t55 COLL Rise And Fall Time t56 CI± Cycle Time 80 117 ns t57 CI± Low Or High Time 35 70 ns t58 CI± Rise And Fall Time 10 ns Refer to Figures 7 and 8 for timing diagram. 21 MD400142/D Conditions 80C25 SEEQ TPO± or DO± TPI± (TP Only) t 57 t 57 CI± (AUI Only) t t 51 t t 56 t51 53 58 t 58 t 53 COLL t55 INTEL t55 SAME AS SEEQ EXCEPT COLL IS INVERTED (ACTIVE LOW) Figure 7. Collision Timing — Receive After Transmit SEEQ SEEQ TPI± or DI± TPO± (TP Only) t 57 t 57 CI± (AUI Only) t t 52 t 56 t52 54 t 58 t58 t 54 COLL t INTEL t 55 55 SAME AS SEEQ EXCEPT COLL IS INVERTED (ACTIVE LOW) Figure 8. Collision Timing — Transmit After Receive 22 MD400142/D 80C25 Link Pulse Timing Characteristics Min Limit Typ Sym. Parameter Max Unit t61 Transmit Link Pulse Width 75 125 ns t62 Transmit Link Pulse Period 11 15 ms t63 Transmit Link Pulse To Double Link Pulse Spacing 5.0 5.4 µs Full Duplex Mode Signalling t64 Transmit Double Link Pulse Interval Spacing 16 16 Link Pulses Full Duplex Mode Signalling t65 Receive Link Pulse Width Required For Detection 35 200 ns t66 Receive Link Pulse Minimum Period Required For Detection 2 7 ms Link_Test_Min t67 Receive Link Pulse Maximum Period Required For Detection 50 150 ms Link_Loss and Link_Test_Max t68 Receive Link Pulse To Double Link Pulse Spacing Required For Full Duplex Mode Detection 4.8 5.6 µs Full Duplex Mode Detection t69 Receive Double Link Pulse Minimum Period Required For Full Duplex Mode Detection 204 216 ms Full Duplex Mode Detection t70 Receive Double Link Pulse Maximum Period Required for Full Duplex Detection 750 850 ms Full Duplex Detection Mode t71 Receive Link Pulse Assert 2 10 Link Pulses t72 Receive Full Duplex Assert 7 µs 5.2 4 210 3 Refer to Figure 9 for timing diagram. 23 MD400142/D Conditions Full Duplex Mode Detection 80C25 TRANSMIT 16th 1st 2nd 16th TPO± t63 t61 t 62 t62 t 64 RECEIVE TPI± t68 t65 t 66 t66 t67 LNK_LED t 69 t 70 t 72 FDPLX_DET Figure 9. Link Pulse Timing 24 MD400142/D t 71 80C25 Jabber Timing Characteristics Limit Sym. Parameter Min t81 Jabber Activation Time t82 Jabber Deactivation Time Typ Max Unit Conditions 40 60 ms TP and AUI 400 430 ms TP and AUI Refer to Figure 10 for timing diagram SEEQ ALL TIMING TO MIDDLE OF WAVEFORM TxEN t81 TPO± DO± t 82 t81 COLL t81 CSN INTEL SAME AS SEEQ EXCEPT COLL IS INVERTED (ACTIVE LOW), CSN IS INVERTED, AND TxEN IS INVERTED. Figure 10. Jabber Timing 25 MD400142/D 80C25 Loopback/SQE Timing Characteristics Limit Sym. Parameter Min t93 SQE Pulse Delay t94 SQE Pulse Width Typ Max Unit 600 700 ns 750 850 ns Conditions Refer to Figure 11 for timing diagram. b. SQE TEST TIMING TxEN CSN t 93 COLL INTEL SAME AS SEEQ EXCEPT TxEN INVERTED, CSN INVERTED Figure 11. SQE Test Timing 26 MD400142/D t 94 80C25 1.0 0.8 VOLTAGE (V) 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 10 20 30 40 50 60 70 80 90 TIME (ns) Figure 12. Twisted Pair Output Voltage Template with Line Model. 27 MD400142/D 100 110 80C25 0 BT 4.5 BT 3.1 V 0.5 V/ns 0.25 BT 2.25 BT 585 mV 6.0 BT +50 mV –50 mV 45.0 BT 585 mV sin(2 * * (t/1BT)) 0 t 0.25 BT and 2.25 t 2.5 BT –3.1 V 2.5 BT 4.5 BT With and Without Line Model Figure 13. Transmit Start of Idle Pulse Voltage Template 1.3 BT 0 BT 3.1 V 0.5 V/ns 585 mV 0.5 BT 0.6 BT 2.0 BT 300 mV 4.0 BT +50 mV +50 mV –50 mV 200 mV 0.25 BT 585 mV sin(2 * 0.25 BT t –50 mV 4.0 BT * (t/1BT –.25)) 0.5 BT 585 mV sin(2 * 0.6 BT t * (t/1BT –.35)) 0.85 BT –3.1 V 0.85 BT 2.0 BT With and Without Line Model Figure 14. Transmit Link Pulse Voltage Template 28 MD400142/D 42.0 BT 80C25 Ordering Information PART NUMBER N Q 80C25 PRODUCT: 80C25 (SEEQ and INTEL Controller Modes) TEMPERATURE RANGE: = 0° to 70° C PACKAGE TYPE : N = 28 PIN PLCC SEEQ Full Duplex Designation Full Duplex Symbol indentifies product as Full Duplex device. Revision History 5/8/96 - All references to separate ‘digital’ and ‘analog’ power and grounds deleted. - Page 3, Pin Descriptions: Pin 17 (X1) description clarified. - Page 8, Added Power Supply Decoupling Suggestions. - Page 10, Digital I/O Characteristics: - Added VIH and VIL specifications for TP/AUI and FDPLX. - Added VIM (Input Intermediate Voltage) specifications. - VOL (max) changed to 1.2 V. - IIL for CIS pin spec clarified (see note at table bottom). - IIH (min) changed from 30 µA to 15 µA. - IIL (min) changed from –30 µA to –15 µA. - Page 14, AUI Characteristics: - AOCD (max) changed from VCC/2.5 to VCC/2.1. 9/9/96 - Page 30, Dimension diagram has been added to this data sheet. 12/10/96 - Page 16, Transmit Timing Charateristics, TXEN Hold Time (min.) has been changed from 40 to 0. 29 MD400142/D 80C25 Surface Mount Packages 28-Pin Plastic Leaded Chip Carrier Type N .048 (1.22) x 45° .042 (1.07) x 45° PIN NO. 1 IDENTIFIER .300 (7.62) REF PIN NO. 1 .495 (12.57) .485 (12.32) .300 (7.62) REF .456 (11.58) .450 (11.43) .456 (11.58) .450 (11.43) .050 (1.27) BSC .495 (12.57) .485 (12.32) .056 (1.42) .042 (1.07) .0103 (0.261) .0097 (0.246) .180 (4.57) .165 (4.19) .110 (2.79) .099 (2.52) .021 (.53) .013 (.33) R .045 (1.14) R .025 (.64) .430 (10.92) .390 (9.91) Notes 1. All dimensions are in inches and (millimeters). 2. Dimensions do not include mold flash. Maximum allowable flash is .008 (.20). 3. Formed leads shall be planar with respect to one another within 0.004 inches. 30 MD400142/D .020 (.51) Min.