ETC 80C24

80C24
80C24
AutoDUPLEXTM
CMOS Ethernet Interface Adapter
96345
Functional Features
Note: Check for latest Data Sheet revision
before starting any designs.
■ Low Power CMOS Technology Ethernet Serial
Interface Adapter with Integrated Manchester
Code Converter (MCCTM), AUI and 10Base-T
Transceiver with Output Wave Shaping and on
chip filters.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
■ Meets IEEE 802.3 10Base-5, 10Base-2, 10Base-T
Standards
■ Direct Interface to SEEQ, INTEL, AMD &
NATIONAL LAN Controllers
General Description
■ Automatic or Manual Selection of AUI/10Base-T
Interface
MCC and AutoDUPLEX are trademarks of SEEQ Technology, Inc.
1
40 ADPLX/JAB_DIS
41 LONG
UTP/STP
42 APOL
43
VCC1
1
FLTR_DIS
38
SQE_DIS/LPBK/FDPLX
VCC4
9
37
BIAS_RES
GND 4 10
36
TPO–
CI– 11
35
TPO+
34
VCC2
80C24
TOP VIEW
PLCC
RX– 13
25
27
28
RXD
LNK_DIS
23
24
X2
TXD
GND 3
29
21
17
22
TXEN
LNK_LED
VCC3
30
COLL
16
20
TPI–
TX_RX_LED
TXC
31
18
TPI+
AUI_TP_LED 15
19
GND 2
32
CSN
33
RX+ 14
FDPLX_DET
■ Direct AUI interface to the Manchester Code
Converter.
44 GND 1
MODE 2
39
8
CI+ 12
■ Differential Transmit Drivers to support 50 Meters
of AUI Cable Lengths.
MD400119/J
7
TX –
26
■ Low differential and common mode noise on TP
transmit outputs.
TX +
X1
■ Link Integrity Test Disable, Selectable Coded
Link Pulse for AutoDUPLEX Mode
RXC
■ Automatic Polarity Correction
AUI/APT
■ Long Cable Mode Support > 100 Meters
2
■ Selectable Termination Impedance to Support
UTP and STP Cables, (100 ohms, 150 ohms)
3
Interface Features
PDN
■ Separate Analog/Digital Power and Ground Pins
to Minimize Noise
MODE 1
■ Power On Reset with Power Down Mode to
Conserve System Power
4
■ Diagnostic Loopback Support
TP/APT
Pin Configuration
■ Status Indicators: Link, Transmit & Receive,
Port Selection-AUI/TP, TP Cable Polarity
6
■ On Chip Transmit Wave Shaping and Low Pass
Filter Circuits - No External Filters Required
■ Provides AutoDUPLEXTM Detect Function for
SEEQ LAN Controllers and Doubles Bandwidth
to 20 MBits/sec for Switched Networks
5
■ Meets IEEE 10Base-T Standards and IEEE 802.3
standards for AUI.
The SEEQ 80C24 is a CMOS single chip Ethernet serial
interface adapter with a completely integrated Manchester
Code Converter (MCC), AUI & 10Base-T transceiver with
wave shaping & filters eliminating the need for external
filters. The 80C24 is designed to interface directly with
SEEQ's family of Ethernet data link controllers- 8003,
80C03, 8005, 80C04, Intel, AMD & National's controllers.
The chip provides automatic polarity correction, automatic
port selection, support for cables longer than 100m, UTP/
STP cable selection, power down mode, separate analog
& digital ground pins & a link disable feature. It also
provides a selectable coded link pulse to implement AutoDUPLEX function together with SEEQ's 80C03, 80C04
& NCORE controllers allowing seamless full duplex operation in switched network implementations doubling network bandwidth to 20 Mbps in 10Base-T. The 80C24 is
typically suitable for adapter boards, motherboards and
stand-alone TP transceiver designs & switching hubs.
Note: Refer to Appendix B for the
Thin Quad Flat Package (TQFP).
80C24
80C24 Pin Description
Pin
Name
I/O
Description
1
VCC1
—
Power supply pin. +5V ±5%.
2
AUI/APT
Input
Pulldown[1]
AUI Port/autoport select input.
AUI/APT TP/APT
0
0
Automatic port selection enabled when LNK_DIS=1
0
1
TP port selected
1
0
AUI port selected
1
1
Invalid
3,4
MODE2,
MODE1
Inputs
Pulldown
Controller interface mode select input. These pins
select one of four possible controller interfaces.
Controller
SEEQ
NSC
INTEL
AMD
MODE2
0
0
1
1
MODE1
0
1
0
1
5
PDN
Input
Pulldown
Powerdown input. When PDN = 0, all functions are disabled
and power consumption is reduced to a minimum.
6
TP/APT
Input
Pullup[2]
TP Port/autoport select input. See AUI/APT.
7
TX+
Output
AUI transmit output, positive.
8
TX–
Output
AUI transmit output, negative.
9
VCC4
—
Power supply pin. +5V ±5%.
10
GND4
—
Ground pin.
11
CI–
Input
AUI collision input, negative.
12
CI+
Input
AUI collision input, positive.
13
RX–
Input
AUI receive input, negative.
14
RX+
Input
AUI receive input, positive.
15
AUI_TP_LED
Output
Port select indication output. This pin is an open drain output
and is capable of driving an LED from VCC. This pin also
indicates reverse polarity on the twisted pair inputs by blinking
on and off when the polarity is reversed.
AUI_TP_LED = High Z AUI port selected.
=
0 TP port selected.
16
TX_RX_LED
Output
Transmit and receive activity output. This output goes low and stays
low for a minimum of 0.2 sec, when there is packet transmission or
reception on the TP or AUI port. This pin is an open drain output and is
capable of driving an LED from VCC.
[1] Pulldown indicates that the pin is pulled down internally so that the default state is low.
[2] Pullup indicates that the pin is internally pulled up so that the default state is high.
2
MD400119/J
80C24
Pin Description cont’d
Pin
Name
I/O
Description
17
LNK_LED
Output
Link pulse detect output. When LNK_LED = 0, link pulse is
detected on twisted pair receive input. This pin is an open
drain output and is capable of driving an LED from VCC.
18
FDPLX_DET
Output
Full duplex detect output. When FDPLX_DET = 0, the device
has been placed in the full duplex mode by either selection or by
the AutoDUPLEX feature.
19
CSN
Output
Carrier sense output. This controller interface output indicates
valid data and collisions on the receive TP or AUI inputs.
20
TXC
Output
Transmit clock output. This controller interface output provides
a 10MHZ clock to the controller. Transmit data from the controller
on TXD is clocked in on edges of TXC.
21
COLL
Output
Collision output. This controller interface output is asserted
when collision between transmit and receive data is occuring,
and during SQE test.
22
VCC3
—
Power supply pin. +5V ±5%.
23
GND3
—
Ground pin.
24
X2
Output
25
X1
Input
Crystal oscillator input. The master clock for the device is
generated by either placing a crystal between X1 and X2, or by
applying an external clock to X1.
26
RXC
Output
Receive clock output. This controller interface output provides
a 10MHZ clock to the controller. Receive data on RXD is
clocked out on edges of RXC.
27
RXD
Output
Receive data output. This controller interface output contains
receive data decoded from the receive TP/AUI inputs and is
clocked out on edges of RXC.
28
LNK_DIS
Input
Pullup
Link disable input. When LNK_DIS = 0, link pulse functions
are disabled; that is, no link pulses are transmitted on
TP outputs, link pulse detection on receive TP inputs ignored.
29
TXD
Input
Transmit data input. This controller interface input contains
data to be transmitted on either TP or AUI transmit outputs and
is clocked in on edges of TXC.
30
TXEN
Input
Transmit enable input. This controller interface input has to be
asserted when data on TXD is valid.
31
TPI –
Input
Twisted pair receive input, negative.
32
TPI+
Input
Twisted pair receive input, positive.
33
GND2
—
Ground pin.
34
VCC2
—
Power supply pin. +5V ±5%.
Crystal oscillator output. The master clock for the device is
generated by either placing a crystal between X1 and X2, or
by applying an external clock to X1.
3
MD400119/J
80C24
Pin Description cont’d
Pin
Name
I/O
Description
35
TPO+
Output
Twisted pair transmit output, positive.
36
TPO–
Output
Twisted pair transmit output, negative.
37
BIAS_RES
Output
Bias resistor set. A resistor tied between this pin and AGND
sets the twisted pair transmit peak output current level on
TPO±.
38
SQE_DIS/
LPBK/
FDPLX
Input
Pullup
SQE disable/loopback/full duplex enable input. This pin has three
distinct functions. The pin is configured as one of the first two
functions, SQE_DIS and LPBK, depending on whether TP or AUI
port is selected.
IF TP PORT IS SELECTED AND LNK_DIS = 1
SQE_DIS = 1 SQE test enabled
= 0 SQE test disabled
IF AUI PORT IS SELECTED AND LNK_DIS = 0
LPBK
= 1 Loopback disabled
= 0 Loopback enabled
This pin can be configured as the third function, FDPLX, by setting
AUI/APT = 0, TP/APT = 0. LNK_DIS = 0, FDPLX = 1. This pin
combination forces the device into the full duplex mode. It is important
to note that the link pulses will be present even though the LNK_DIS
pin is held low. This happens only in this particular mode.
39
FLTR_DIS
Input
Pulldown
40
ADPLX/
JAB_DIS
Input
Pullup
Filter disable input. When FLTR_DIS=1, the internal transmit
and receive filters are disabled.
Autoduplex enable/jabber disable input. This pin changes
function depending on whether TP or AUI port is selected.
IF TP PORT IS SELECTED AND LNK_DIS = 1
ADPLX
= 1 Half duplex selected
= 0 Autoduplex on
IF AUI PORT IS SELECTED AND LNK_DIS = 0
JAB_DIS = 1 Jabber enabled
= 0 Jabber disabled
41
LONG
Input
Pullup
Long cable mode input. When LONG = 0, the receive input
thresholds are reduced to accomodate cable lengths in
excess of 100 meters.
42
APOL
Input
Pulldown
Autopolarity input. When APOL = 1, this pin enables the
autopolarity function and automatically corrects for reversed
polarity on the twisted pair receive inputs, TPI±.
43
UTP/STP
Input
Pullup
Cable type select input. This pin adjusts the twisted pair
transmit output current level to accomodate either 100 ohm
(UTP) or 150 ohm (STP) cable.
UTP/STP
44
GND1
—
Ground pin.
4
MD400119/J
=1
=0
100 ohm cable (UTP)
150 ohm cable (STP)
80C24
BLOCK DESCRIPTION
Functional Description
The Encoder/Decoder
Manchester encoding is a process of combining the clock
& the data stream together so that they can be transmitted
on the twisted pair interface or AUI at the transceiver side.
Once encoded, the first half contains the complement of
the data and the second half contains the true data, so that
a transition is always guaranteed at the middle of a bit cell.
Data encoding and transmission begins with TXEN going
active, and the subsequent data is clocked on the edges
of TXC and then gets encoded. The end of a transmit
packet occurs at a bit cell center if the last bit is a "ONE" or
at a bit boundary if the last bit is a "ZERO".
The 80C24 is an Ethernet adapter with a completely
integrated Manchester Code Converter, 10Base-T transceiver with on chip filters. The device contains both
10Base-T and AUI interfaces compliant with IEEE 802.3
specifications. The chip is divided into four major blocks,
namely (i) The controller interface (ii) The Encoder /
Decoder (iii) The twisted pair interface and (iv) The AUI.
The input signals are received on the TP or AUI receivers
depending on which is selected. Both the twisted pair and
AUI receivers contain a threshold comparator to validate
the signal and a zero crossing comparator for checking the
transitions. Then the data is sent to the PLL in the decoder
to separate the data from the clock. On the other side,
digital transmit data is clocked into the device via the
controller interface. The data is then sent to the Manchester encoder to be encoded. Encoded data is then transmitted on the twisted pair or AUI based on the selected
port.
The decoding is a process of recovering the encoded data
stream coming from the receiver side and decoding it back
into the clock and data outputs using the phase locked loop
technique. The PLL is designed to lock into the preamble
of the incoming signal at less than 20 bit times with a
maximum jitter of ±13.5 ns at the TPI or AUI inputs and can
also sample the incoming data with this amount of jitter.
The ENDEC asserts the CSN signal to indicate to the
controller that the data and clock received are valid and
available. There is an inhibit period after the end of a frame
after a node has finished transmitting for 4.4 µs during
which CSN is deasserted irregardless of the state of the
receiver and collision status.
The Controller Interface
The 80C24 is designed to interface directly to SEEQ's
80C03, 80C04 & NCORE controllers, INTEL's 82586/596/
592/593 LAN controllers, NSC and AMD's controllers with
the use of MODE1 & MODE2 pins . The controller interface
consists of the Transmit/Receive data (TXD/RXD), transmit/receive Clocks (TXC/RXC), the Transmit Enable
(TXEN) input, the collision output (COLL), the Full Duplex
acknowledgment (FDPLX_DET) and the Carrier Sense
Output (CSN) pins. On the transmit side, data on TXD is
clocked into the device on the edges of TXC clock output
only when the data valid signal (TXEN) is asserted. On the
receive side, data on RXD is clocked out on edges of RXC.
In the SEEQ, NSC and AMD modes, RXC follows TXC for
2.2 µs in the TP mode or 1.8 µs in the AUI mode and then
switches to the recovered clock. In the Intel mode, RXC is
held low for 2.2 µs in the TP mode or 1.8 µs in the AUI mode
while the PLL is acquiring lock and then switches to the
recovered lock. The FDPLX_DET pin signifies to the
controller that full duplex channels have been established.
Twisted Pair Interface
(a) The transmitter function
The transmitter transfers Manchester encoded data from
the ENDEC to the twisted pair cable. The circuit consists
of a set of functional blocks to provide pre-coded waveshaped, pre-equalized and smoothed waveforms so that
the outputs are made to appear as though it had passed
through a 5-7th order external elliptic passive filter, thereby
eliminating the need for an external filter. The waveform
generator consists of a ROM, DAC, PLL, filter and a output
driver to preshape the output waveform transmitted onto
the twisted pair cable to meet the pulse template requirements outlined in IEEE STD 802.3 and illustrated in figure
12. The DAC first converts the data pulse into a stair
stepped representation of the desired output waveform,
which goes through a second order low-pass filter. The
DAC values are determined from the ROM addresses,
which are chosen to have different values for long and
short data bits so as to shape the pulse to meet the
10Base-T waveform template. The line driver takes the
smoothed current waveform and converts it into an high
current output that can drive the TP directly without any
external filters. The current output is also guaranteed to
have a very low common mode and differential noise. The
interface to the twisted pair cable requires a transformer
The following mode table illustrates the selection of the
appropriate inputs to match the controller.
MODE 2
MODE 1
Controller
0
0
SEEQ
0
1
NSC
1
0
INTEL
1
1
AMD
5
MD400119/J
MODE
OUTPUTS
FDPLX_DET
PDN
LNK_DIS
APOL
SQE_DIS/LPBK/FDPLX
UTP/STP
FLTR_DIS
LONG
ADPLX/JAB_DIS
MODE 1
TP/APT
MODE 2
AUI/APT
AUI_TP_LED
TX_RX_LED
MODE
INPUTS
LED
DRIVERS
COLLISION
DETECT
COLL
LNK_LED
MANCH
DECODER
(PLL)
RXC
RXD
CSN
ENDEC
MANCH
ENCODER
CONTROLLER
INTERFACE
TXEN
TXD
TXC
OSC
JABBER
DETECT
TP INTERFACE
PORT
DETECT
AUI
SQUELCH
SOI
GEN
LINK
GEN
CLOCK
GEN
ROM
Figure 1. 80C24 Block Diagram
COLLISION DATA
RCV DATA
XMT DATA
MCLK
AUI INTERFACE
SQUELCH
LINK
PULSE
DETECT
POLARITY
DETECT
PORT
DETECT
AUTO
DUPLEX
DETECT
DAC
–
+
VAUI
VAUI
LP
FILTER
CI+
CI–
RX+
RX–
TX–
TX+
–
6
+
–
+
+
–
+
+
–
MD400119/J
+
–
+
+
X1
X2
V
TP
LP
FILTER
–
+
TPI–
TPI+
TPO–
TPO+
R BIAS_RES
80C24
80C24
simultaneous transmission and reception on the TP port.
The maximum distance between two consecutive pulses
in a double pulse is 5.4 µs.
with a ratio of 2:1 on transmit and a 1:1 on receive, with two
200 ohm resistors connected as shown in figure 2. The
output driver is a current source. The output current level
is set by the values of the resistor tied between the
BIAS_RES ( Pin 37) & GND. The current level is determined by the following equation.
The Forced Full-Duplex mode can be established by the
following pin combinations.
I
= (R BIAS_RES /10K)* 50 mA
OUT
1. AUI/APT (pin 2) = 0, TP/APT (pin 6) = 0;
Though a 10K resistor will meet the template requirements
specified with a no load condition, a capacitive or inductive
loading can influence the level, because the transmitter
has a current source output. So, in a actual application, it
might be necessary to adjust the value to compensate the
loading involved. For example, the bias resistance value
for a loading of 10 pf will be 8K approximately.
2. LNK_DIS (pin 28) = 0.
3. SQE_DIS/LPBK/FDPLX = 1
Disables Link.
Forces the 80C24
into FullDuplex.
In this combination, forced full duplex is effectively established and Collision, SQE & the LoopBack functions are
disabled.
(b) The receiver function
The receiver receives the Manchester-encoded data
from the twisted pair lines( TPI ±) and passes it on to the
ENDEC side, where it gets decoded back into the receive
clock RXC and the receive data RXD. The inputs first goes
through a receive filter, which is a continuous time 3rd
order low pass filter with a typical 3 dB cutoff frequency of
20-25 Mhz. The filter's output then passes through two
different types of comparators, namely threshold and zero
crossing. The threshold comparator compares the TPI ±
inputs with fixed positive and negative thresholds called
the squelch levels. The zero crossing comparator senses
the transition point on the TPI ± inputs without introducing
excess jitter and the outputs goes to the PLL in the
decoder. The receiver is transformer coupled and needs to
be terminated with a 100 Ω resistor or two 50 Ω resistor and
a capacitor as described in figure 2.
(d) Squelch functions
The squelch function is used to discriminate noise from link
test pulses and valid data to prevent the noise from
activating the receiver. It is accomplished by a squelch
comparator which compares the TPI± signals with a fixed
positive and negative squelch value. The output from the
comparator goes to a receive squelch circuit which determines whether the input data is valid or not. If the data is
invalid, the transceiver enters into an squelched state. The
input voltage should exceed ±300mV p-p for five bit times
max. (with alternating polarity) for unsquelching to occur.
In the Unsquelch state, the value of the threshold in the
comparator is reduced to take care of hysteresis effects.
While in the unsquelch state, the receive squelch circuit
looks for the SOI (Start of Idle) signal at the end of the
packet. When the SOI signal is detected, the receive
squelch is turned on again.
(c) Full Duplex Functions
The Full Duplex scheme allows the simultaneous transmission on the TPO ± and simultaneous reception on the
TPI ± without interruption, effectively doubling the bandwidth to 20 MBPS in switched network implementations on
10Base-T. The 80C24 can be made to operate either in the
AutoDUPLEX or in the Forced FullDuplex scheme.
(e) The Link integrity functions
The 80C24 monitors the TPI± pins continuously for valid
data and link pulse activity. If neither data or link test pulse
is detected for a minimum time, the transceiver enters into
a Link Test Fail State and disables the transmitter, receiver, collision presence and the SQE functions. For the
transceiver to exit this state, it should receive three consecutive link pulses or valid data at the TPI ± inputs to
resume normal packet transmission and reception. On the
other hand, the transmitter generates link pulses periodically when it's not transmitting data to indicate to the
network that the link is intact. Please refer to figure 14 for
the diagram illustrating the Transmit Link Pulse Voltage
Template as specified in the IEEE 802.3. The Link function
could be disabled by providing an active low input to pin 28
( LNK_DIS). In this mode, link pulses are neither transmitted nor received. A link pulse detect output capable of
driving a LED is also provided for link indication.
The 80C24 is switched on to the AutoDUPLEX mode when
an active LOW signal is detected on the ADPLX/JAB_DIS
(pin 40) in the TP mode. In this configuration, Full duplex
mode is automatically established by the successful detection of double pulses embedded within the regular link
pulses. The 80C24 sends the double pulses in 16 pulse
intervals constantly on the TPO ± pins and continually
monitors the TPI ± pins for similar type of double pulses
within a time window of 210 ± 6ms. Once the double pulses
are detected, the FDPLX_DET (Pin 18) will go low to
acknowledge to the controller that the network will allow
7
MD400119/J
Sets 80C24
in Autoport.
80C24
(f) The Start of Idle (SOI) pulse
The transmit SOI pulse is a positive pulse inserted at the
end of every transmission to signal the end and the start of
idle period to corresponding receivers. The output pulse is
also shaped by the transmit waveshaper to meet the pulse
requirements specified in IEEE 802.3. Please refer to
figure 13 for the Transmit Start Of Idle Pulse voltage
template diagram. The receiver detects the SOI pulse by
sensing the missing data transitions with the zero crossing
comparator. Once the SOI pulse is detected, another SOI
pulse is generated and sent to the Controller interface
outputs.
(j) Long mode
The 80C24 can be made to support longer cable lengths
(> 100 meters) by applying an active LOW signal to the
LONG (pin 41) pin. When this pin is LOW, the threshold
levels of the internal threshold comparators are lowered to
accommodate the longer cable length. In normal mode, it
supports a cable with 11.5dB of attenuation and in the
LONG mode an additional 4dB of attenuation is supported.
(k) Cable mode
The UTP/STP pin can be used to configure the 80C24 to
be used with a selectable termination impedance of 100
ohms or 150 ohms for use with either UTP or STP cable
types respectively. The STP mode is selected by tying this
pin LOW. When tied LOW, the output current is reduced so
as to keep the amplitude of the transmit signal unchanged
from the template when the STP cable is attached.
(g) Automatic Polarity Correction
The 80C24 provides autopolarity detection and correction
functions for the twisted pair receiver peak detectors to
determine whether normal or inverted data is received
over the TPI ± pins. Automatic polarity is enabled by
making APOL ( Pin 42 ) HIGH. The polarity reversal can be
indicated by connecting a LED to the AUI_TP_LED pin,
which would blink when a reversal is observed. A polarity
reversed condition is sensed when four opposite link
pulses are detected without the expected polarity or if 3-4
frames are received with a reversed start-of-idle.
(l) Signal Quality Error Test
The Signal Quality Error test is used to indicate a successful transmission (i,e A transmission without interruptions
such as Collision, jabber or Link failure) to the DTE.When
the SQE is enabled, a COLL signal is presented to the
controller when the transmitter goes idle after a successful
transmission of a frame on the twisted pair network. The
Signal Quality Error test can be disabled by applying an
active low to SQE_DIS/LPBK/FDPLX (pin 38) since it
becomes necessary to disable SQE tests for applications
such as repeaters. When this pin is tied low, only the SQE
functions are disabled and the normal collision detection
functionality is left unchanged during regular transceiver
operations. The maximum duration of the SQE test is 850
ns and the maximum SQE test wait delay is 700ns.
(h) Jabber functions
The jabber function detects abnormally long streams of
Manchester-encoded data on the TXD input with the help
of a Jabber detect circuit. The jabber circuit uses a Jabber
timer, which monitors the TXEN pin. It starts counting at
the beginning of each transmission. If the timer expires
before TXEN goes inactive, the 80C24 enters a jabber
state disabling the transmit/loopback functions and enabling the collision functions. If TXEN goes inactive before
the timer expires, the timer is reset and becomes ready for
the next transmission. The jabber function can be disabled
in the AUI mode by applying an active low signal to the
ADPLX/JAB_DIS (pin 40). The jabber function can also be
disabled in TP mode for certain pin combinations described in Appendix A.
AUI Interface
The differential transmit output pair TX+/TX- sends the
encoded data on to an external transceiver and is capable
of driving 50 meters of 78ohm shielded AUI cable directly
with a jitter of 0.5 ns max. The receive input differential pair
RX+/RX- goes through the AUI squelch comparator and
the zero crossing comparator. The AUI squelch comparator compares the input signals with fixed minimum and
maximum values of -175mv and -325mv respectively, and
passes it on to the squelch circuit to determine data
validity. The zero crossing comparator senses the transition point of the input pair without introducing excess jitter
and passes the data to the phase locked loop of the
decoder. The CI+/CI- are the collision input pair signals
which would expect a 5 Mhz or a 10 Mhz square wave from
an external transceiver.
(i) Loopback functions
Loopback in the TP mode is internally enabled when
Manchester encoded data is transmitted on TPO ± and no
data is received on the TPI ± in order to simulate Coax
Ethernet behavior. When internal loopback is enabled, the
transmitted data is loopbacked into the RXD and sent to
the controller. The loopback function is disabled during
Link Fail State, Jabber State and during Full-Duplex Operation.
In the AUI mode, internal loopback function can be forcefully enabled by applying an active low to SQE_DIS/LPBK/
FDPLX (pin 38) and the transmit data can be loopbacked
for diagnostic purposes.
8
MD400119/J
80C24
Collisions
Powerdown
Collisions are generated when two stations try to contend
for the network at the same time, which would result in
simultaneous activity detected on the TPO ± and TPI ±.
When this happens, COLL will be asserted to indicate to
the controller the simultaneous transmission of two or
more stations on the network. CSN is also asserted during
collision. For further details, about timing, refer to figures
7 and 8.
The 80C24 can be made to go into a low power mode by
applying an active low signal to PDN (pin 5). In this mode,
all the functions in the device are disabled and the power
consumption is reduced to a bare minimum of 0.5 mA or
less.
Power Supply Decoupling
There are four sets of VCC /GND on the 80C24: (VCC1/GND1 ,
VCC2 /GND2 , VCC3 /GND3 , and VCC4 /GND4 .
Oscillator
The internal clock generator is controlled either by an
external parallel resonant crystal connected across the X1
& X2 or by connecting an clock to the input pin X1. This
external 20 Mhz clock is used by the clock circuitry and the
PLL to generate a 10 Mhz ± 0.01% transmit clock. The
manchester encoding process uses both the 10Mhz and
20Mhz clocks.
All VCC’s should be connected together as close as possible to the device with a large VCC plane. If the VCC’s vary
in potential by even a small amount, noise and latchup can
result.
All GND’s should also be connected together as close as
possible to the device with a large ground plane. If the
GND’s vary in potential by even a small amount, noise and
latchup can result.
Crystal Specification:
1. Parallel resonant mode
2. Frequency ............. 20 MHz ±0.01% @ 0 – 70 °C
3. Equivalent Series Resistance ............ 25 Ω max.
4. Load Capacitance ............................. 20 pf max.
5. Case Capacitance .............................. 7 pf max.
A 0.01-0.1 µF decoupling capacitor should be connected
between each VCC/GND set as close as possible to the
device pins, preferably within 0.5". The value of the
decoupling capacitor should be selected based on
whether the noise on VCC-GND is high or low frequency. A
conservative approach would be to use two decoupling
capacitors on each VCC/GND set, one 0.1µF for low frequency and one 0.001 µF for high frequency noise on the
power supply.
Automatic Port Selection
The automatic port selection feature of the 80C24 can be
enabled by applying active low inputs to the AUI/APT (pin
2) & TP/APT (pin 6) respectively. In this mode, 80C24
automatically selects either the TP or AUI port by detecting
the presence or absence of activity on the TPI ± and RX ±
respectively. In the Autoport mode, the device powers up
with the TP port active. If no activity is detected for a period
of 800 ms on the TP port, the device automatically
switches to AUI mode. The device will stay in AUI mode as
long as no activity is detected on the TP port. Note that
activity is defined as the presence of either link pulses or
packets.
The VCC connection to the transmit transformer center tap
shown in Figure 2 has to be well decoupled in order to
minimize common mode noise injection from VCC onto the
TP wires. It is recommended that a 0.01 µF decoupling
capacitor be placed between the center tap VCC to the
80C24 GND plane. This decoupling capacitor should be
physically placed within 0.5" of the transformer center tap.
The PCB layout and power supply decoupling discussed
above should provide sufficient decoupling to acheive the
following when measured at the device: (1) the resultant
AC noise voltage measured across each VCC/GND set
should be less than 100 mVPP, (2) all VCC’s should be within
50 m VPP of each other, and (3) all GND’s should be within
50m VPP of each other.
9
MD400119/J
Notes:
0.01
µF
TxO
RxI
RX+
RX–
CI+
CI–
TX–
TX+
1K
1K
a. Valor
b. Coilcraft
c. PCA
d. Belfuse
e. FEE Fil_mag
PT4152
Q4430-A
EPE6047S
A553-SEEQ-01
23Z128
4. Transformers are available from
Tel: (619) 537-2500
Tel: (708) 639-6400
Tel: (818) 892-0761
Tel: (201) 432-4463
Tel: (619) 569-6577
3. This resistance value will meet the template requirements
specified on a no load condition. However, a capacitive or
inductive loading can influence the current level. Hence it may be
necessary to adjust the value to compensate the loading involved.
2. The EM2 is an Ethernet transceiver module with on
board isolation transformer and a DC-DC converter.
1. The 80C04 is a low power CMOS Ethernet Data Link
Controller available in a 68 pin surface mount plastic
leaded chip carrier package.
1M
CDS
[2]
EM2
RX+
RX–
CI+
CI–
GND4
VCC4
TX–
TX+
VCC
LNK_LED
TX_RX_LED
AUI_TP_LED
0.1 µF
V
CC
1K
17
16
15
14
13
12
11
10
9
8
7
TP/APT
6
5
PDN
4
3
AUI/APT
2
VCC
1
80C24
80C04
0.1 µF
[1]
44
GND1
0.1 µF
43 42 41 40
APOL
29
30
31
32
33
34
35
36
37
38
39
FLTR_DIS
TxD
TxEN
TPI–
TPI+
GND 2
VCC2
TPO+
TPO–
0.1 µF
VCC
BIAS_RES
10 K
SQE_DIS/LPBK/FDPLX
23 27 28 29
Figure 2. 80C24 in a Typical Application
21 19 22 20
ADUPLX
FDPLX_DET
18
MODE 1
CSN
CSN
19
TxC
TxC
20
MODE 2
21
COLL
COLL
VCC1
22
VCC3
UTP/STP
25
X1
22 pF
23
GND 3
LONG
22 pF
24
X2
ADPLX/JAB_DIS
RxC
RxC
26
RxD
RxD
28
V
CC
27
LNK_DIS
TxD
10
TxEN
[3]
VCC
200Ω
MD400119/J
50Ω
200Ω
OPTIONAL
0.1µF
50Ω
MODE INPUTS
0.1µF
1:1
2CT:1
[4]
RJ-45
6
3
2
1
TRANSFORMER
80C24
80C24
Absolute Maximum Ratings
VCC Supply Voltage .................................... –0.3V to 7V
All Inputs and Outputs ..................... –0.3 to VCC + 0.3 V
Latchup Current ................................................ ±25 mA
Package Power Dissipation .................. 1 Watt @ 25°C
Storage Temperature ............................. –65 to +150°C
Operating Temperature .......................... –65 to +125°C
Lead Temperature (Soldering, 10 sec) ............... 250 °C
*COMMENT: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Power Supply Characteristics
Test conditions are as follows:
1. T = 0 –70°C
2. VCC = 5V ±5%
3. 20 MHZ ±.01%
4. BIAS_RES = 10K, with no load.
Limit
Sym.
Parameter
ICC
VCC Power Supply
Current
Min
Typ
Max
Unit
Conditions
110
85
150
110
0.5
mA
mA
mA
Transmitting, TP selected
Transmitting, AUI selected
Powerdown
Max
Unit
Conditions
0.8
1.5
Volt
Volt
Volt
Volt
All except X1
X1
All except X1
X1
1
µA
VIN= VCC
120
µA
DC Digital I/O Characteristics
Test conditions are as follows:
1. T = 0–70°C
2. VCC = 5V ±5%
3. 20 MHZ ±.01%
4. BIAS_RES = 10K, with no load.
Limit
Sym.
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
IIH
Input High Current
Min
Typ
2
3.5
X1
20
60
VIN= VCC
AUI/APT, MODE1-2, PDN,
FLTR_DIS, APOL
IIL
Input Low Current
–1
µA
VIN= GND
X1
–20
–60
–120
µA
VIN= GND
LNK_DIS, SQE_DIS/LPBK/FDPLX
ADPLX/JAB_DIS, LONG,
UTP/STP, TP/APT
11
MD400119/J
80C24
DC Digital I/O Characteristics cont’d
Limit
Sym.
Parameter
VOL
Output Low Voltage
Min
Typ
Max
Unit
Conditions
0.4
Volt
IOL= 2.1 mA
All except AUI_TP_LED,
TX_RX_LED, LNK_LED
1.2
Volt
IOL= –20mA
AUI_TP_LED, TX_RX_LED,
LNK_LED
VOH
Output High Voltage
4
Volt
IOH= –400µA
All except AUI_TP_LED,
TX_RX_LED, LNK_LED
IOZ
Output Leakage Current
–1
µA
VOH= VCC
AUI_TP_LED, TX_RX_LED,
LNK_LED
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
5
pF
12
MD400119/J
80C24
Twisted Pair Interface Characteristics
Unless otherwise specified, all test conditions are as follows:
1. T = 0–70°C
2. VCC = 5V ±5%
3. 20MHZ ±.01%
4. BIAS_RES = 10K, with no load.
5. TPO± loading as shown in Figure 2 or equivalent.
6. 10Mhz sine wave on TPI±
Sym.
Parameter
Min
Limit
Typ
Max
Unit
TOV
TPO± Differential Output
Voltage
2.2
2.5
2.8
Vpk
TOVT
TPO± Differential Output
Voltage Template
See Figure 12
TSOI
TPO± SOI Output
Voltage Template
See Figure 13
TLPT
TPO± Link Pulse Output
Voltage Template
See Figure 14
TOIV
TPO± Differential Output
Idle Voltage
±50
mV
TOIA
TPO± Output Current
44
50
56
mA pk
UTP cable mode
29
33
37
mA pk
STP cable mode
TOIR
TPO± Output Current
Adjustment Range
0.70
TCMA
TPO± Common Mode
AC Output Voltage
THD
TPO± Harmonic
Distortion
TOR
TPO± Output Resistance
TOC
TPO± Output
Capacitance
RST
TPI± Squelch
Threshold
RUT
TPI± Unsquelch
Threshold
RZT
TPI± Zero Cross
Switching Threshold
ROCV
TPI± Input Open Circuit
Voltage
1.40
10
Measured on Secondary
Side of XFMR in Fig. 2
VCC = 5V Adjustable
with BIAS_RES
50
mV pk
–27
dB
10K
ohms
15
pF
Relative to Value
at BIAS_RES = 10K
310
540
mVpk
LONG = 1
190
330
mVpk
LONG = 0
190
330
mVpk
LONG = 1
115
200
mVpk
LONG = 0
20
mVpk
(VCC/3)+0.25
Volt
(VCC/3)–0.25
VCC/3
13
MD400119/J
Conditions
80C24
Twisted Pair Interface Characteristics cont’d
Limit
Sym.
Parameter
RCMR
TPI± Input Common
Mode Voltage Range
RDR
Min
Typ
VCC/3–1.0
Max
Unit
VCC/3+1.0
Volt
TPI+/– Input Differential
Voltage Range
VCC
Volt
RCRR
TPI+/– Input Common
Mode Rejection Ratio
–20
dB
RIR
TPI+/– Input Resistance
RIC
TPI+/– Input Capacitance
5K
ohm
10
14
MD400119/J
pF
Conditions
0–10Mhz
80C24
AUI Characteristics
Unless otherwise specified, all test conditions are as follows:
1. T = 0–70°C
2. VCC = 5V ±5%
3. 20MHZ ±.01%
4. BIAS_RES = 10K with no load.
5. 78 ohm, 27µH load on TX±
6. 10Mhz sine wave on RX±, CI±
Limit
Sym.
Parameter
Min
AOV
TX±, Differential
Output Voltage
550
AORF
TX±, Output Rise
And Fall Time
AOIV
Max
Unit
1200
mVpk
5
nS
TX±, Differential
Output Idle Voltage
±40
mV
AOVU
TX±, Differential
Output Voltage
Undershoot During Idle
–100
mV
AOCD
TX±, Common
Mode DC Output Voltage
VCC/2.1
Volt
AOCA
TX±, Common
Mode AC Output Voltage
40
mV pk
AOR
TX±, Output
Resistance
75
ohms
AOC
TX±, Output
Capacitance
AIST
RX±, CI± Squelch
Threshold
-175
-325
mV
AIUT
RX±, CI± Unsquelch
Threshold
-100
-225
mV
AIZT
RX±, CI± Zero Cross
Switching Threshold
20
mVpk
AIOC
RX±, CI± Input Open Circuit (VCC/3)–.25
Voltage
(VCC/3)+.25
Volt
AICR
RX±, CI± Input Common
Mode Voltage Range
(VCC/3)–1.0
(VCC/3)+1.0
Volt
AIVR
RX±, CI± Input Differential
Voltage Range
0
VCC
Volt
AIR
RX±, CI± Input Resistance
5K
AIC
RX±, CI± Input Capacitance
VCC/3.5
Typ
VCC/3.0
15
VCC/3
10K
ohm
10
pF
15
MD400119/J
pF
Conditions
tR, tF measured at 10-90%
points
80C24
AC Test Timing Conditions
Unless otherwise specified, all test conditions for timing characteristics are as follows:
1. T = 0 – 70°C
2. VCC = 5v ±5%
3. 20MHZ ±.01%
4. BIAS_RES = 10K, with no load.
5. Input Conditions
All Inputs:
tR, tF< = 10ns from 20-80% points
6. Output Loading
TPO±:
50 ohms to VCC on each output, 10pF
TX±:
78 ohms differentially, 10pF
Open Drain Digital Outputs:
1K pullup, 50pF
All Other Digital Outputs:
50pF
7. Measurement Points
TPO±, TPI±, TX±, RX±, CI±:
Zero crossing during data and ±.3V point at start/end of signal
X1:
VCC/2
All other inputs and outputs:
1.5 Volts
20 MHZ Input Clock Timing Characteristics
Limit
Sym.
Parameter
Min
Typ
Max
Unit
t1
X1 Cycle Time
49.995
50.005
50.005
nS
t2
X1 High Time
15
nS
t3
X1 Low Time
15
nS
Conditions
Refer to Figure 3 for timing diagram.
t2
X1
t1
t3
Figure 3. 20 MHZ Input Clock Timing
16
MD400119/J
80C24
Transmit Timing Characteristics
Parameter
Min
Limit
Typ
Max
Unit
t11
TXC Cycle Time
99.99
100
100.01
nS
t12
TXC High Time
40
60
nS
t13
TXC Low Time
40
60
nS
t14
TXC Rise Time
5
nS
t15
TXC Fall Time
5
nS
t16
TXEN Setup Time
30
nS
t17
TXEN Hold Time
0
nS
t18
TXD Setup Time
30
nS
t19
TXD Hold Time
0
t20
Transmit Bit Loss
2
Bits
TP and AUI
t21
Transmit Propagation
Delay
2
Bits
TP and AUI
t22
Transmit Output Jitter
8
nS
TP
nS
TP
Sym.
Conditions
nS
0.5
t24
Transmit Output Rise
and Fall Time
t25A
Transmit SOI Pulse
Width to 0.3V Point
t25B
See Figure 12
nS
AUI
250
5
nS
TP
Measure TPO± from last
zero cross to 0.3V point.
200
nS
AUI
Measure TX± from last zero
cross to 0.3V point.
4500
nS
TP
Measure TPO± from last
zero cross to 40mV point.
7000
nS
AUI
Measure TX± from last zero
cross to 40 mV point.
150
nS
225
mS
Transmit SOI Pulse
Width to 40 mV Point
t26
TXEN assert to
TX_RX_LED assert
t27
TX_RX_LED
assert time
195
Refer to Figure 4 for timing diagram.
17
MD400119/J
Due To TX Activity
80C24
t 12 t 13
MODE 2, 1 = 00
t14
t15
TxC
t 16
t 11
t 17
TxEN
t19
t 18
TxD
B0
B1
B2
B3
t 21
t25b
t 25a
t 20
TPO±
or
Tx±
B0
B0
B1
B1
B2
B3
B3
t 24
t 22
t 26
B2
t 27
Tx_Rx_LED
MODE 2, 1 = 01
SAME AS MODE [2, 1] = 00 EXCEPT TxC IS INVERTED (RISING EDGE TRIGGERED).
MODE 2, 1 = 10
SAME AS MODE [2, 1] = 00 EXCEPT TxEN IS INVERTED (ACTIVE LOW).
MODE 2, 1 = 11
SAME AS MODE [2, 1] = 00 EXCEPT TxC IS INVERTED (RISING EDGE TRIGGERED).
Figure 4. Transmit Timing
18
MD400119/J
80C24
Receive Timing Characteristics
Limit
Sym.
Parameter
t31
CSN Assert Delay Time
Min
t32
CSN Assert Setup Time
30
t33
CSN Deassert Hold Time
20
Typ
Max
Unit
600
nS
TP
240
nS
AUI
nS
10
t35
RXC to RXD Setup Time
40
t36
RXC to RXD Hold Time
30
t38
RXD Propagation Delay
t39
RXC High Time
t40
RXC Low Time
Conditions
35
nS
Mode [2,1] = 00, 01, 11
nS
Mode [2,1] = 10
nS
nS
200
nS
40
200
nS
Mode [2,1] = 00, 01, 11
40
60
nS
Mode [2,1] = 10
40
60
nS
Mode [2,1] = 00, 01, 11
40
2200
nS
Mode [2,1] = 10 Start of Packet
40
250
nS
Mode [2,1] = 10 End of Packet
CSN Assert To RXC
Switchover From TX Clock
To RX Clock
2200
nS
TP
1800
nS
AUI
t42
CSN Deassert To RXC
Switchover From Rx Clock
To Tx Clock
200
nS
t43
SOI Pulse Width Required
For Idle Detection
125
200
nS
TP
Measure TPI± from last zero
cross to .3v point.
125
160
nS
AUI
Measure RX± from last zero
cross to .45v point.
±13.5
nS
Data
±8.5
nS
Preamble
100
nS
225
mS
10
nS
t41
t44
Receive Input Jitter
t45
CSN Assert To
TX_RX_LED Assert
t46
TX_RX_LED Assert time
t49
RXC, RXD, CSN Output
Rise And Fall Times
195
Due To RX Activity
Refer to Figures 5 and 6 for timing diagram.
NOTES:
1.
2.
3.
4.
CI+ and CI– asserts and deasserts COLL, asynchronously, and asserts and deasserts CSN synchronously with RxC.
If CI+ and CI– arrives within 4.5 µs from the time CSN was deasserted; CSN will not be reasserted (on transmission node only).
When CI+ and CI– terminates, CSN will not be deasserted if Rx+ and Rx– are still active.
When the node finishes transmitting and CSN is deasserted, it cannot be asserted again for 4.5 µs.
19
MD400119/J
80C24
MODE 2, 1 = 00
1
0
1
0
1
0
1
0
1
0
TPI±
or
Rx±
t 31
t 44
CSN
t41
t 39
t 32
RxC
t 38
Tx
Tx
t40
Tx
Rx
Rx
Rx
1
t 45
Rx
t36
t35
RxD
Rx
0
1
0
t 46
Tx_Rx_LED
MODE 2, 1 = 01
SAME AS MODE [2, 1] = 00
MODE 2, 1 = 11
SAME AS MODE [2, 1] = 00 AND RxC IS SHUTOFF DURING IDLE.
Figure 5a. Receive Timing — Start of Packet for SEEQ, NSC and AMD’s Controllers
MODE 2, 1 = 10
1
TPI±
or
Rx±
0
1
0
1
0
1
0
1
0
1
Rx
Rx
t31
t44
CSN
t 41
t 40
t 32
RxC
Tx
Tx
Tx
t38
t39
Rx
Rx
t35
0
RxD
t 45
Rx
Rx
t36
1
0
1
0
t 46
Tx_Rx_LED
NOTE:
SAME AS MODE [2, 1] = 00 EXCEPT CSN IS INVERTED (ACTIVE LOW), RxC IS INVERTED (FALLING EDGE TRIGGERED), RxC
IS SHUTOFF DURING t 41 ACQUISITION TIME, RxD IS HIGH DURING t 41 ACQUISITION TIME AND DURING IDLE TIME.
Figure 5b. Receive Timing — Start of Packet for Intel’s Controllers
20
MD400119/J
1
80C24
MODE 2, 1 = 00
B N–2
TPI±
or
Rx±
BN
B N–1
SOI
t 43
CSN
t 42
t39
t 33
RxC
Rx
Rx
B N–5
RxD
Rx
B N–4
Rx
B N–3
Rx
B N–2
Rx
B N–1
t 40
Rx
Tx
Tx
BN
MODE 2, 1 = 01
SAME AS MODE [2, 1] = 00
MODE 2, 1 = 11
SAME AS MODE [2, 1] = 00 EXCEPT RxC IS SHUTOFF DURING IDLE
Figure 6a. Receive Timing — End of Packet for SEEQ, NSC and AMD’s Controllers.
MODE 2, 1 = 10
B N-2
B N-1
BN
SOI
TPI±
or
Rx±
t 43
t33
CSN
t 42
t
RxC
Rx
Rx
B N-5
RxD
Rx
B N-4
Rx
B N-3
Rx
Rx
B N-2
B N-1
40
t
39
Tx
Tx
Tx
BN
NOTE:
SAME AS MODE [2, 1] = 00 EXCEPT TxEN IS INVERTED (ACTIVE LOW), RxC IS INVERTED RxC IS SHUTOFF DURIN
t 41 ACQUISITION TIME, RxD IS HIGH DURING t 41 ACQUISITION TIME, REFER TO FIGURE 6a.
Figure 6b. Receive Timing — End of Packet for Intel’s Controllers.
21
MD400119/J
80C24
Collision Timing Characteristics
Limit
Sym.
Parameter
t51
COLL Assert Delay Time Rcv After Xmt
t52
t53
t54
Min
Typ
COLL Assert Delay Time Xmt After Rcv
COLL Deassert Delay
Time - Rcv After Xmt
COLL Deassert Delay
Time - Xmt After Rcv
Max
Unit
600
nS
TP
TPI± to COLL
300
nS
AUI
CI± to COLL
600
nS
TP
TPO± to COLL
300
nS
AUI
CI± to COLL
500
nS
TP
TPI± to COLL
500
nS
AUI
CI± to COLL
500
nS
TP
TPO± to COLL
500
nS
AUI
CI± to COLL
10
nS
t55
COLL Rise And Fall Time
t56
CI± Cycle Time
80
117
nS
t57
CI± Low Or High Time
35
70
nS
t58
CI± Rise And Fall Time
10
nS
Refer to Figures 7 and 8 for timing diagram.
22
MD400119/J
Conditions
80C24
MODE 2, 1 = 00, 01, 11
TPO±
or
Tx±
TPI±
(TP Only)
t 57
t 57
CI±
(AUI Only)
t 53
t 51
t 56
t51
t 58
t 58
t 53
COLL
t55
MODE 2, 1 = 10
t55
SAME AS MODE [2, 1] = 00 EXCEPT COLL IS INVERTED (ACTIVE LOW)
Figure 7. Collision Timing — Receive After Transmit
MODE 2, 1 = 00, 01, 11
TPI±
or
Rx±
TPO±
(TP Only)
t 57
t 57
CI±
(AUI Only)
t 54
t 52
t 56
t52
t 58
t58
t 54
COLL
t 55
MODE 2, 1 = 10
t 55
SAME AS MODE 2, 1 = 00 EXCEPT COLL IS INVERTED (ACTIVE LOW)
Figure 8. Collision Timing — Transmit After Receive
23
MD400119/J
80C24
Link Pulse Timing Characteristics
Min
Limit
Typ
Sym.
Parameter
Max
Unit
t61
Transmit Link Pulse Width
75
125
nS
t62
Transmit Link Pulse Period
11
15
mS
t63
Transmit Link Pulse To
Double Link Pulse Spacing
5.0
5.4
µS
Full Duplex Mode Signalling
t64
Transmit Double Link
Pulse Interval Spacing
16
16
Link
Pulses
Full Duplex Mode Signalling
t65
Receive Link Pulse Width
Required For Detection
35
200
nS
t66
Receive Link Pulse
Minimum Period Required
For Detection
2
7
mS
Link_Test_Min
t67
Receive Link Pulse
Maximum Period Required
For Detection
50
150
mS
Link_Loss and
Link_Test_Max
t68
Receive Link Pulse To
Double Link Pulse Spacing
Required For Full Duplex
Mode Detection
4.8
5.6
µS
Full Duplex Mode Detection
t69
Receive Double Link
Pulse Minimum Period
Required For Full Duplex
Mode Detection
204
216
mS
Full Duplex Mode Detection
t70
Receive Double Link Pulse
Maximum Period Required
for Full Duplex Detection
750
850
mS
Full Duplex Detection Mode
t71
Receive Link Pulse Assert
2
10
Link
Pulses
t72
Receive Full Duplex Assert
7
µS
5.2
4
210
3
Refer to Figure 9 for timing diagram.
24
MD400119/J
Conditions
Full Duplex Mode Detection
80C24
TRANSMIT
16th
1st
2nd
16th
TPO±
t
t
63
t
61
t
62
62
t
64
RECEIVE
TPI±
t
t
68
t
66
65
t
66
t67
LNK_LED
t 69
t 70
t 72
FDPLX_DET
Figure 9. Link Pulse Timing
25
MD400119/J
t 71
80C24
Jabber Timing Characteristics
Limit
Sym.
Parameter
Min
t81
Jabber Activation Time
t82
Jabber Deactivation Time
Typ
Max
Unit
Conditions
40
60
mS
TP and AUI
400
430
mS
TP and AUI
Refer to Figure 10 for timing diagram
MODE 2,1 = 00
ALL TIMING TO MIDDLE OF WAVEFORM
TxEN
t81
TPO±
TX±
t 82
t81
COLL
t81
CSN
MODE 2,1 = 01
SAME AS MODE 2, 1 = 00
MODE 2,1 = 10
SAME AS MODE 2, 1 = 00 EXCEPT COLL IS INVERTED (ACTIVE LOW), CSN IS INVERTED, AND TxEN IS INVERTED.
MODE 2,1 = 11
SAME AS MODE 2, 1 = 00
Figure 10. Jabber Timing
26
MD400119/J
80C24
Loopback/SQE Timing Characteristics
Limit
Sym.
Parameter
Min
Typ
Max
Unit
Conditions
t91
LPBK Setup Time
5
µS
AUI Only
t92
LPBK Hold Time
5
µS
AUI Only
t93
SQE Pulse Delay
600
700
nS
t94
SQE Pulse Width
750
850
nS
Refer to Figure 11 for timing diagram.
MODE 2,1 = 00
a. LOOPBACK TIMING
LPBK
t91
t 92
TxEN
b. SQE TEST TIMING
TxEN
CSN
t 93
t 94
COLL
MODE 2,1 = 01
SAME AS MODE [2, 1] = 00 EXCEPT LPBK INVERTED (ACTIVE HIGH)
MODE 2,1 = 10
SAME AS MODE [2, 1] = 00 EXCEPT TxEN INVERTED, CSN INVERTED
MODE 2,1 = 11
SAME AS MODE [2, 1] = 00 EXCEPT LPBK INVERTED (ACTIVE HIGH)
Figure 11. Loopback/SQE Test Timing
27
MD400119/J
80C24
1.0
0.8
VOLTAGE (V)
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
10
20
30
40
50
60
70
80
90
TIME (ns)
Figure 12. Twisted Pair Output Voltage Template with Line Model.
28
MD400119/J
100
110
80C24
0 BT
4.5 BT
3.1 V
0.5 V/ns
0.25 BT
2.25 BT
585 mV
6.0 BT
+50 mV
–50 mV
45.0 BT
585 mV sin(2 * * (t/1BT))
0 t 0.25 BT and
2.25 t 2.5 BT
–3.1 V
2.5 BT
4.5 BT
With and Without Line Model
Figure 13. Transmit Start of Idle Pulse Voltage Template
1.3 BT
0 BT
3.1 V
0.5 V/ns
585 mV
0.5 BT
0.6 BT
2.0 BT
300 mV
4.0 BT
+50 mV
+50 mV
–50 mV
200 mV
0.25 BT
585 mV sin(2 *
0.25 BT
t
–50 mV
4.0 BT
* (t/1BT –.25))
0.5 BT
585 mV sin(2 *
0.6 BT
t
* (t/1BT –.35))
0.85 BT
–3.1 V
0.85 BT
2.0 BT
With and Without Line Model
Figure 14. Transmit Link Pulse Voltage Template
29
MD400119/J
42.0 BT
80C24
Ordering Information
PART NUMBER
N
Q
80C24
PRODUCT:80C24 AutoDuplex CMOS ETHERNET INTERFACE ADAPTER
TEMPERATURE RANGE: = 0° to 70° C
PACKAGE TYPE : N = 44 PIN PLCC
F = 44 PIN TQFP
Revision History
4/15/96
- All references to separate ‘digital’ and ‘analog’ power and grounds deleted.
- There are four sets of VCC/GND on the 80C24: VCC1/GND1, VCC2/GND2,VCC3/GND3, and VCC4/GND4.
- Page 9, Power Supply Decoupling suggestions added to page.
- Page 12, DC Digital I/O Characteristics: VOL (max) changed from 0.8 to 1.2 V.
- Page 15, AUI Characteristics: AOCD (max) changed from Vcc/2.5 to Vcc/2.1.
- Page 31, Table replaced with addendum dated April 1995.
9/9/96
- Pages 33, 34, PLCC and TQFP dimension diagrams have been added to this data sheet.
12/10/96
- Pages 17, Transmit Timing Characteristics, TXEN Hold Time (min.) has been changed from 40 to 0.
30
MD400119/J
80C24
Appendix A
Mode Port Select Table
This Mode/Port Select Table lists out all the possible pin combinations and describes the
corresponding features that are enabled in those combinations.
Apt 3
L
L
Pins 40 & 38 Can Be
Varied to Have
Features as Desired.
H
L
L
H
H
L
✔
✔
✔
AUI
✔
✔
TP
✔
✔
AUI
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
TP FDX
NFDX
AUI
TP FDX
Apt 4
L
L
H
L
L
NFDX
AUI
Auto Port
[1]
Forced Full Duplex Mode
Apt 5
L
H
L
H
L
Apt 6
L
L
L
H
L
TP ONLY
TP 1
L
H
H
H
H
TP 2
L
H
H
L
H
TP 3
L
L
H
H
H
TP Only Mode
Pin 2 -- L & Pin 6 -- H
Pins 40, 28 & 38 Can
Be Varied to Have
Features as Desired.
Forced Full Duplex
AUI ONLY
AUI Only Mode Pin 2 -- H
Pins 40 Can Be Varied.
Pin 38 -- H[3]
LOOPBACK
Loopback Mode
Pin 2 -- H,
Pin 38 -- L
Pin 40 Can
Be Varied.
Intel &
SEEQ
Mode
AMD &
National
TP 4
L
L
H
TP 5
L
H
L
TP 6
L
H
TP 7
L
L
TP 8
L
L
TP 9
L
H
TP 10
L
L
AUI 1
H
H
H
L
H
✔
✔
✔
FDX
✔
✔
NFDX
✔
✔
FDX
✔
✔
NFDX
✔
✔
H
H
✔
L
L
H
✔
L
H
H
L
L
H
L
L
L
L
L
L
H [3]
X
X
AUI 2
H
L
H
H [3]
AUI 3
H
H
L
H [3]
X
AUI 4
H
L
L
H [3]
X
LPBK 1
H
H
X
L
X
LPBK 2
H
L
X
L
X
LPBK 3
H
H
X
H
X
LPBK 4
H
L
X
H
X
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
MD400119/J
[2]
✔
✔
✔
✔
✔
✔
[2]
✔
✔
[2]
Notes:
[1]. Note that the link presence is indicated even though the LNK_DIS is Low.
[2]. Internal.
[3]. Values shown for pin (38) are for Intel & SEEQ mode. Reverse the polarity for the AMD & National Mode.
31
LOOPBACK
H
TP
FDX
L
L
AUTO FDX
Apt 2
H
SQET
To Enable Autoport
Pins 2, 6 -- L & Pin 28 -- H
H
LINK TEST
H
PORT
JABBER
L
TP/APT (6)
Apt 1
SQE_DIS/LPBK/FDPLX (38)
ADPLX/JAB_DIS (40)
AUTOPORT
PORT GROUP
FEATURES
LNK_DIS (28)
SYMBOL
AUI/APT (2)
INPUTS
[2]
Appendix B
80C24
PDN
MODE 1
MODE 2
AUI/APT
AV
A GND
UTP/STP
APOL
LONG
ADPLX/JAB_DIS
10
9
8
7
6
5
4
3
2
1
CC
TP/APT
11
Pin Configuration
TX + 12
44
FLTR_DIS
TX – 13
43
SQE_DIS/LPBK/FDPLX
AVCC 14
42
BIAS_RES
A GND 15
41
TPO–
40
TPO+
39
AVCC
38
A GND
CI– 16
CI+
80C24
TOP VIEW
TQFP
17
RX– 18
32
MD400119/J
LNK_DIS 33
TXD
RXD 32
34
RXC 31
22
X1 30
LNK_LED
X2 29
TXEN
D GND 28
35
27
21
DVCC
TX_RX_LED
26
TPI–
COLL
36
25
20
TXC
AUI_TP_LED
24
TPI+
CSN
37
23
19
FDPLX_DET
RX+
80C24
Surface Mount Packages
44 Pin Plastic Leaded Chip Carrier Type N
.048 (1.22) x 45°
.042 (1.07) x 45°
PIN NO. 1 IDENTIFIER
.500 (12.70)
REF.
PIN NO. 1
.695 (17.65)
.685 (17.40)
.500 (12.70)
REF.
.656 (16.66)
.650 (16.51)
.656 (16.66)
.650 (16.51)
.050 (1.27)
BSC
.695 (17.65)
.685 (17.40)
.0103 (.261)
.0097 (.246)
.056 (1.42)
.042 (1.07)
R .045 (1.14)
R .025 (.64)
.021 (0.53)
.013 (0.33)
.630 (16.00)
.590 (14.99)
.112 (2.84)
.100 (2.54)
.020 (0.51) min.
Notes
1. All dimensions are in inches and (millimeters).
2. Dimensions do not include mold flash. Maximum allowable flash is .008 (.20).
3. Formed leads shall be planar with respect to one another within 0.004inches.
33
MD400119/J
.180 (4.57)
.165 (4.19)
80C24
44-Pin TQFP
12.00 (0.472)
10.00 (0.394)
10.00 (0.394)
12.00 (0.472)
#1
1.0 Ref.
0.37 ± 0.07
(0.015 ± 0.003)
0.80 BSC
1.40 ± 0.05
(0.055 ± 0.002)
0° Min.
0° - 7°
0.10 ± 0.05
(0.004 ± 0.002)
0.15 ± 0.05
(0.006 ± 0.002)
0.60 ± 0.15
(0.024 ± 0.006) Min.
1.0 Ref.
Notes
1. All dimensions are in inches and (millimeters).
2. Dimensions do not include mold flash. Maximum allowable flash is .01 (.254).
34
MD400119/J