19-1789; Rev 2; 1/12 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable Features o 1.2ns Propagation Delay The MAX9691/MAX9692/MAX9693 are ultra-fast ECL comparators capable of very short propagation delays. Their design maintains the excellent DC matching characteristics normally found only in slower comparators. The MAX9691/MAX9692/MAX9693 have differential inputs and complementary outputs that are fully compatible with ECL-logic levels. Output current levels are capable of driving 50Ω terminated transmission lines. The ultra-fast operation makes signal processing possible at frequencies in excess of 600MHz. o 100ps Propagation Delay Skew o 150ps Dispersion o 0.5ns Latch Setup Time o 0.5ns Latch-Enable Pulse Width o Available in µMAX and QSOP Packages o +5V, -5.2V Power Supplies Ordering Information The MAX9692/MAX9693 feature a latch-enable (LE) function that allows the comparator to be used in a sample-hold mode. When LE is ECL high, the comparator functions normally. When LE is driven ECL low, the outputs are forced to an unambiguous ECL-logic state, dependent on the input conditions at the time of the latch input transition. If the latch-enable function is not used on either of the two comparators, the appropriate LE input must be connected to ground; the companion LE input must be connected to a high ECL logic level. These devices are available in SO, QSOP, and tiny µMAX® packages for added space savings. TEMP RANGE PART PIN-PACKAGE -40°C to +85°C -40°C to +85°C MAX9691EUA MAX9691ESA 8 µMAX 8 SO MAX9691EPA -40°C to +85°C 8 PDIP Note: Devices are also available in lead(Pb)-free/RoHS-compliant packages. Specify lead-free by adding a “+” after the part number. Ordering Information continued at the end of data sheet. Selector Guide ________________________Applications PART COMPARATORS PER PACKAGE LATCH ENABLE PINPACKAGE MAX9691 1 No 8 µMAX, 8 SO, 8 PDIP MAX9692 1 Yes 10 µMAX, 16 SO, 16 PDIP MAX9693 2 Yes High-Speed Line Receivers Peak Detectors Threshold Detectors High-Speed Triggers µMAX is a registered trademark of Maxim Integrated Products, Inc. 16 QSOP, 16 SO, 16 PDIP Pin Configurations appear at end of data sheet. _________________________________________________________Functional Diagrams IN+ Q OUT Q OUT INRL NONINVERTING INPUT Q OUT INVERTING INPUT RL MAX9693 RL RL LATCH ENABLE RL MAX9693 LE LE LE LE VT INVERTING INPUT Q OUT RL MAX9691 NONINVERTING INPUT VT LATCH ENABLE THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULLDOWN RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50Ω TO 200Ω CONNECTED TO -2.0V, OR 240Ω TO 2000Ω CONNECTED TO -5.2V. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9691/MAX9692/MAX9693 General Description MAX9691/MAX9692/MAX9693 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable ABSOLUTE MAXIMUM RATINGS 8-Pin PDIP (derate 9.1mW/°C above +70°C) ...........727.3mW 10-Pin µMAX (derate 8.8mW/°C above +70°C) ...........707.3mW 16-Pin QSOP (derate 9.6mW/°C above +70°C) .........771.5mW 16-Pin SO (derate 13.3mW/°C above +70°C) ..........1066.7mW 16-Pin PDIP (derate 10.5mW/°C above +70°C) .......842.1mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Supply Voltage (VCC) ...............................................-0.3V to +6V Supply Voltage (VEE)................................................-6V to +0.3V Input Voltage....................................(VCC + 0.3V) to (VEE - 0.3V) Output Short-Circuit Duration ....................................Continuous Differential Input Voltage ......................................................±5V Latch Enable ...............................................(VEE - 0.3V) to +0.3V Output Current ....................................................................50mA Input Current ....................................................................±25mA Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 4.8mW/°C above 70°C)...............387.8mW 8-Pin SO (derate 7.4mW/°C above +70°C)..................588.2mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V, VEE = -5.2V, RL = 50Ω to VT, VT = -2V, LE = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current Input Voltage Range SYMBOL VOS CONDITIONS MIN IB VCM -6.5 6.5 TA = TMIN to TMAX -11.5 +11.5 10 TA = +25°C 0.2 TA = TMIN to TMAX 6 TA = TMIN to TMAX Note 1 CMRR -2.5V ≤ VCM ≤ +3.0V (Note 1) Positive Power-Supply Rejection Ratio +PSRR Negative Power-Supply Rejection Ratio -PSRR 20 30 -2.5 mV +3.0 µA µA V 80 dB 4.5V ≤ VCC ≤ 5.5V 60 dB -5.7V ≤ VEE ≤ -4.7V 60 dB 70 dB 60 kΩ Open-Loop Gain AOL VCM = 0V Differential Input Resistance RIN -10mV < VIN < 10mV 60 UNITS µV/°C 5 8 TA = +25°C Common-Mode Rejection Ratio Differential Input Clamp Voltage Input Capacitance MAX TA = +25°C ∆VOS/∆T IOS TYP CIN 1.7 V 3 pF Latch Enable Input Current High IIH(LE) VIH(LE) = 1.1V 60 120 µA Latch Enable Input Current Low IIL(LE) VIL(LE) = 1.5V 0.2 10 µA Latch Enable Logic High Voltage VIH(LE) Latch Enable Logic Low Voltage VIL(LE) Logic Output High Voltage Logic Output Low Voltage 2 VOH VOL -1.1 V -1.5 TA = TMIN -1.2 -0.87 TA = TMAX -0.99 -0.70 TA = +25°C -1.06 -0.76 TA = TMIN -1.93 -1.57 TA = TMAX -1.89 -1.51 TA = +25°C -1.89 -1.55 _______________________________________________________________________________________ V V V Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable (VCC = +5V, VEE = -5.2V, RL = 50Ω to VT, VT = -2V, LE = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MAX9693 Supply Current ICC MIN TA = +25°C TYP MAX 34 46 18 26 TA = TMIN to TMAX 50 TA = +25°C MAX9691/ MAX9692 TA = TMIN to TMAX UNITS mA 36 AC ELECTRICAL CHARACTERISTICS (VCC = 5V, VEE = -5.2V, RL = 50Ω to VT, VT = -2V, LE = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9691/MAX9692/MAX9693 Propagation Delay (Notes 1, 2) Rise/Fall Time tpd+, tpdtr, tf Propagation Delay Skew ∆PD Dispersion PDSP TA = +25°C 1.2 TA = TMIN to TMAX 10% to 90% 1.8 2.0 ns 500 ps 100 ps VOD from 10mV to 100mV 150 ps TA = +25°C 1.0 MAX9692/MAX9693 Latch-Enable Time (Note 1) Latch-Enable Pulse Width (Note 1) TLE(±) TA = TMIN to TMAX 1.8 2.0 ns tpw(LE) 0.5 1.0 ns Setup Time (Note 1) ts 0.5 1.0 ns Hold Time (Note 1) th 0.5 1.0 ns Channel-to-Channel Propagation Match tPDM Note 2 (MAX9693 only) 100 ps Note 1: Guaranteed by design. Note 2: VIN = 100mV, VOD = 10mV. _______________________________________________________________________________________ 3 MAX9691/MAX9692/MAX9693 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +5V, VEE = -5.2V, RL = 50Ω to VT, VT = -2V, VOD = 10mV, TA = +25°C, unless otherwise noted.) WORST-CASE PROPAGATION DELAY vs. INPUT OVERDRIVE 600 3000 2000 10 20 30 40 50 60 70 80 90 100 0 INPUT OVERDRIVE (mV) WORST-CASE PROPAGATION DELAY vs. TEMPERATURE 1000 -1.64 RPULLDOWN = 200Ω 60 -1.78 85 -1.80 -40 -15 10 35 60 -40 85 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) INPUT OFFSET VOLTAGE vs. TEMPERATURE INPUT BIAS CURRENT vs. TEMPERATURE INPUT BIAS CURRENT vs. DIFFERENTIAL INPUT VOLTAGE 500 0 -500 -1000 7.0 6.5 6.0 5.5 5.0 -1500 4.5 -2000 4.0 -15 10 35 TEMPERATURE (°C) 60 85 MAX9691/3-10 4000 INPUT BIAS CURRENT (µA) 7.5 INPUT BIAS CURRENT (µA) 1000 5000 MAX9691/3-09 8.0 MAX9691/3-08 1500 4 RPULLDOWN = 50Ω TEMPERATURE (°C) 2000 -40 -1.70 -1.76 -1.1 35 -1.68 -1.74 VOD = 100mV 600 10 RPULLDOWN = 200Ω -1.72 700 -15 RPULLDOWN = 100Ω -1.66 -1.0 -40 25 -1.62 RPULLDOWN = 50Ω 800 20 -1.60 -0.9 900 15 OUTPUT LOW VOLTAGE vs. TEMPERATURE RPULLDOWN = 100Ω -0.8 10 OUTPUT HIGH VOLTAGE vs. TEMPERATURE VOL (V) VOH (V) 1100 5 CLOAD (pF) -0.7 1200 0 SOURCE IMPEDANCE (Ω) MAX9691/3-05 1300 1000 50 100 150 200 250 300 350 400 450 500 -0.6 MAX9691/3-04 1400 1200 600 0 0 1400 800 1000 400 PROPAGATION DELAY (ps) 1600 MAX9691/3-06 800 4000 MAX9691/3-03 5000 PROPAGATION DELAY (ps) 1000 1800 MAX9691/3-02 6000 MAX9691/3-01 1200 WORST-CASE PROPAGATION DELAY vs. CLOAD WORST-CASE PROPAGATION DELAY vs. SOURCE IMPEDANCE PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 1400 INPUT OFFSET VOLTAGE (µV) MAX9691/MAX9692/MAX9693 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable 3000 2000 1000 0 -1000 -2000 -3000 -4000 -5000 -40 -15 10 35 TEMPERATURE (°C) 60 85 -5 -4 -3 -2 -1 0 1 2 3 DIFFERENTIAL INPUT VOLTAGE (V) _______________________________________________________________________________________ 4 5 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable 100MHz OUTPUT RESPONSE PROPAGATION DELAY MAX9691/3-12 MAX9691/3-11 VIN = 100mV VOD = 10mV -1.0V VIN 200mV/div Q OUT 200mV/div -1.8V -1.0V Q OUT 200mV/div Q OUT - Q OUT 200mV/div -1.8V 1ns/div 1ns/div Pin Description PIN NAME FUNCTION MAX9691 MAX9692 µMAX MAX9692 PDIP/SO MAX9693 1 1 2 11 VCC Positive Supply. Bypass to GND with a 0.1µF capacitor. 2 2 3 — IN+ Positive Input 3 3 4 — IN- Negative Input 4 6 8 6 VEE Negative Supply. Bypass to GND with a 0.1µF capacitor. 5 7 11 — Q OUT Output 6 8 12 — Q OUT Complimentary Output 7 9 16 — GND2 Device Ground 8 10 1 — GND1 Device Ground — 4 5, 7, 9, 10, 13, 14, 15 — N.C. — 5 6 — LE Latch Enable Input — — — 1 Q OUTA Channel A Output — — — 2 Q OUTA — — — 3, 14 GND — — — 4 LEA Channel A Latch Enable Input — — — 5 LEA Channel A Latch Enable Complementary Input — — — 7 INA- Channel A Negative Input — — — 8 INA+ Channel A Positive Input — — — 9 INB+ Channel B Positive Input — — — 10 INB- Channel B Negative Input — — — 12 LEB Channel B Latch Enable Complementary Input — — — 13 LEB Channel B Latch Enable Input — — — 15 Q OUTB Channel B Complementary Output — — — 16 Q OUTB Channel B Output No Connection. Not internally connected. Channel A Complementary Output Device Ground _______________________________________________________________________________________ 5 MAX9691/MAX9692/MAX9693 Typical Operating Characteristics (continued) (VCC = +5V, VEE = -5.2V, RL = 50Ω to VT, VT = -2V, VOD = 10mV, TA = +25°C, unless otherwise noted.) MAX9691/MAX9692/MAX9693 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable __________ Applications Information Layout Because of the MAX9691/MAX9692/MAX9693s’ large gain-bandwidth characteristic, special precautions must be taken to use them. A PC board with a ground plane is mandatory. Mount 0.01µF ceramic decoupling capacitors as close to the power-supply pins as possible, and process the ECL outputs in microstrip fashion, consistent with the load termination of 50Ω to 200Ω (for VT = -2V). For low-impedance applications, microstrip layout and terminations at the input may also be helpful. Pay close attention to the bandwidth of the decoupling and terminating components. Chip components can be used to minimize lead inductance. Connect GND1 and GND2 together to a solid copper ground plane for the MAX9691/MAX9692. GND1 biases the input gain stages, while GND2 biases the ECL output stage. If the LE function is not used, connect the LE pin to GND (MAX9692/MAX9693) and the complementary LE to ECL logic high level (MAX9693 only). Do not leave the inputs of an unused comparator floating for the MAX9693. Input Slew-Rate Requirements As with all high-speed comparators, the high gainbandwidth product of these devices creates oscillation VIN problems when the input goes through the linear region. For clean switching without oscillation or steps in the output waveform, the input must meet certain minimum slew-rate requirements. The tendency of the part to oscillate is a function of the layout and source impedance of the circuit employed. Poor layout and larger source impedance will increase the minimum slew-rate requirement. Figure 1 shows a high-speed receiver application with 50Ω input and output termination. With this configuration, in which a ground plane and microstrip PC board are used, the minimum slew rate for clean output switching is 1V/µs. In many applications, adding regenerative feedback will assist the input signal through the linear region, which will lower the minimum slew-rate requirement considerably. For example, with the addition of positive feedback components, Rf = 1kΩ and Cf = 10pF, the minimum slew-rate requirement can be reduced by a factor of four. As high-speed receivers, the MAX9691/MAX9692/ MAX9693 are capable of processing signals in excess of 600MHz. Figure 2 is a 100MHz example with an input signal level of 14mVRMS. Q 50Ω Q LE INPUT 20mV/div 50Ω -2V Rf Cf 50Ω 0V OUTPUT 500mV/div -0.9V -1.7V 50Ω 2ns/div Figure 1. Regenerative Feedback—High-Speed Receiver with 50Ω Input and Output Termination 6 Figure 2. Signal Processed at 100MHz with Input Signal Level of 14mVRMS _______________________________________________________________________________________ Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable sistors are similar in timing. The input signal must occur at time ts before the latch falling edge, and must be maintained for time th after the edge to be acquired. After th, the output is no longer affected by the input status until the latch is again strobed. A minimum latch pulse width of tpw(LE) is needed for the strobe operation, and the output transitions occur after a time tLE(±). The MAX9691/MAX9692/MAX9693 will not false trip (i.e., output invert) if one of the inputs is in the valid common-mode range while the other input is outside the common-mode range. COMPARE LATCH ENABLE 50% LATCH ts t pw(LE) th DIFFERENTIAL INPUT VOLTAGE VIN VOS VOD t pd t LE(+) Q 50% Q 50% Figure 3. Timing Diagram _______________________________________________________________________________________ 7 MAX9691/MAX9692/MAX9693 The timing diagram (Figure 3) illustrates the series of events that complete the compare function, under worst-case conditions. The top line of the diagram illustrates two latch-enable pulses. Each pulse is high for the compare function and low for the latch function. The first pulse demonstrates the compare function; part of the input action takes place during the compare mode. The second pulse demonstrates a compare function interval during which there is no change in the input. The leading edge of the input signal (illustrated as a large-amplitude, small-overdrive pulse) switches the comparator after time interval tpd. Output Q and Q tran- MAX9691/MAX9692/MAX9693 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable Definition of Terms VOS VIN VOD tpd+ tpd- tLE(+) tLE(-) Input Offset Voltage. The voltage required between the input terminals to obtain 0V differential at the output. Input Voltage Pulse Amplitude Input Voltage Overdrive Input to Output High Delay. The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output low-to-high transition. Input to Output Low Delay. The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output high-to-low transition. Latch-Enable to Output High Delay. The propagation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output low-to-high transition. Latch-Enable to Output Low Delay. The propagation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output high-to-low transition. Chip Information tpw(LE) ts th ∆pd PDSP tpdm Latch-Enable Pulse Width. The minimum time the latch-enable signal must be high to acquire and hold an input signal. Setup Time. The minimum time before the negative transition of the latch-enable pulse that an input signal must be present to be acquired and held at the outputs. Hold Time. The minimum time after the negative transition of the latch-enable signal that an input signal must remain unchanged to be acquired and held at the output. Propagation Delay Skew. The difference in propagation delay between the Q and Q outputs crossing each other in both directions. Propagation Delay Dispersion. The change in propagation delay as a result of the overdrive of the input signal varying. Propagation Delay Match (MAX9693 only). The difference in propagation delay between two separate channels. Ordering Information (continued) PROCESS: BiCMOS MAX9692EUB TEMP RANGE -40°C to +85°C 10 µMAX MAX9692ESE -40°C to +85°C 16 Narrow SO PART PIN-PACKAGE MAX9692EPE -40°C to +85°C 16 PDIP MAX9693ESE -40°C to +85°C 16 Narrow SO MAX9693EEE -40°C to +85°C 16 QSOP MAX9693EPE -40°C to +85°C 16 PDIP Note: Devices are also available in lead(Pb)-free/RoHS-compliant packages. Specify lead-free by adding a “+” after the part number. 8 _______________________________________________________________________________________ Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable TOP VIEW MAX9691 MAX9692 VCC 1 10 GND1 IN+ 2 9 GND2 IN- 3 8 Q OUT N.C. 4 7 Q OUT LE 5 6 VEE VCC 1 8 GND1 IN+ 2 7 GND2 IN- 3 6 Q OUT VEE 4 5 Q OUT µMAX DIP/SO/µMAX MAX9692 MAX9693 GND1 1 16 GND2 Q OUTA 1 16 Q OUTB VCC 2 15 N.C. Q OUTA 2 15 Q OUTB IN+ 3 14 N.C. GND 3 14 GND IN- 4 13 N.C. LEA 4 13 LEB N.C. 5 12 Q OUT LEA 5 12 LEB LE 6 11 Q OUT VEE 6 11 VCC 10 N.C. INA- 7 10 INB- 9 INA+ 8 9 N.C. 7 VEE 8 N.C. INB+ DIP/SO/QSOP PDIP/SO Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 µMAX U8+1 21-0036 90-0092 8 SO S8+2 21-0041 90-0096 PACKAGE TYPE 8 PDIP P8+5 21-0043 — 10 µMAX U10+2 21-0061 90-0330 16 QSOP E16+1 21-0055 90-0167 16 SO S16+3 21-0041 90-0097 16 PDIP P16+1 21-0043 — _______________________________________________________________________________________ 9 MAX9691/MAX9692/MAX9693 Pin Configurations MAX9691/MAX9692/MAX9693 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable Package Information (continued) For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. D D α α 10 ______________________________________________________________________________________ Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ______________________________________________________________________________________ 11 MAX9691/MAX9692/MAX9693 Package Information (continued) MAX9691/MAX9692/MAX9693 Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable Revision History REVISION NUMBER REVISION DATE DESCRIPTION 0 8/00 Initial release 1 10/02 Updated Ordering Information. 2 1/12 Revised Ordering Information, Absolute Maximum Ratings, and Pin Description. PAGES CHANGED — 7 1, 2, 5, 7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.