19-2400; Rev 1; 7/93 Dual, Ultra-Fast ECL-Output Comparator ________________________Applications ____________________________Features ♦ 1.4ns Propagation Delay ♦ 0.5ns Latch Setup Time ♦ 2.0ns Latch-Enable Pulse Width ♦ +5V, -5.2V Power Supplies ♦ Pin-Compatible with AD9687, Am6687, SP9687 ♦ Available in Commercial, Extended-Industrial, and Military Temperature Ranges ♦ Available in Narrow SO Package ______________Ordering Information PART TEMP. RANGE PIN-PACKAGE* MAX9687CPE 0°C to +70°C 16 Plastic DIP MAX9687CSE MAX9687CJE MAX9687C/D MAX9687EPE MAX9687ESE MAX9687MJE 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 16 Narrow SO 16 CERDIP Dice** 16 Plastic DIP 16 Narrow SO 16 CERDIP * Contact factory for availability of 20-pin PLCC. ** Contact factory for dice specifications. High-Speed A/D Converters High-Speed Line Receivers Peak Detectors Threshold Detectors High-Speed Triggers ________________Functional Diagram ___________________Pin Configuration TOP VIEW NONINVERTING INPUT Q OUT NONINVERTING INPUT Q OUT INVERTING INPUT INVERTING INPUT Q OUT 1 16 Q OUT Q OUT 2 15 Q OUT GND 3 LEA 4 RL LE RL RL LE LE LATCH ENABLE RL VT LE LATCH ENABLE THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULL-DOWN RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50Ω – 200Ω CONNECTED TO -2.0V, OR 240Ω – 2000Ω CONNECTED TO -5.2V. 14 GND A B 13 LEB LEA 5 12 LEB V- 6 11 V+ INA- 7 10 INB- INA+ 8 9 INB+ DIP/SO ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX9687 _______________General Description The MAX9687 is a dual, ultra-fast ECL comparator manufactured with a high-frequency bipolar process (fT = 6GHz) capable of very short propagation delays. This design maintains the excellent DC matching characteristics normally found only in slower comparators. The MAX9687 is pin-compatible with the AD9687 and Am6687, but exceeds their AC characteristics. The MAX9687 has differential inputs and complementary outputs that are fully compatible with ECL-logic levels. Output current levels are capable of driving 50Ω terminated transmission lines. The ultra-fast operation makes signal processing possible at frequencies in excess of 600MHz. A latch-enable (LE) function is provided to allow the comparator to be used in a sample/hold or track/hold mode. The latch-enable inputs are designed to be driven from the complementary outputs of a standard ECL –—– gate. When LE is high and LE is low, the comparator –—– functions normally. When LE is forced low and LE is high, the comparator outputs are locked in the logical states determined by the input conditions at the time of the latch transition. If the latch-enable function is not used on either of the two comparators, the appropriate LE –—– input must be connected to ground; the companion LE input can be left open. MAX9687 Dual, Ultra-Fast ECL-Output Comparator ABSOLUTE MAXIMUM RATINGS Supply Voltages.....................................................................±6V Operating Temperature Ranges Output Short-Circuit Duration (Note 1) ..........................Indefinite MAX9687C_ E .....................................................0°C to +70°C Input Voltages........................................................................±5V MAX9687E_ E ..................................................-40°C to +85°C Differential Input Voltages .....................................................3.5V MAX9687MJE ................................................-55°C to +125°C Output Current ....................................................................30mA Storage Temperature Range .............................-55°C to +150°C Continuous Power Dissipation (TA = +70°C) Lead Temperature (soldering, 10sec) .............................+300°C Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW Narrow SO (derate 8.70mW/°C above +70°C) .............696mW CERDIP (derate 10.00mW/°C above +70°C) ................800mW Note 1: Continuous short-circuit protection is allowed on one comparator at a time up to case temperatures of +85°C and ambient temperatures of +30°C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VS = ±15V, VCM = 0V, TA= +25°C, unless otherwise noted.) PARAMETER Input Offset Voltage (Note 2) Temperature Coefficient Input Offset Current Input Bias Current Input Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Input Resistance Input Capacitance SYMBOL VOS CONDITIONS RS = 100Ω TA = +25°C TA = TMIN to TMAX ∆VOS/∆T IOS IB VCM CMRR TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX (Note 2) RIN (Note 2) VOL MAX9687E Negative Supply Current IEE 5 8 20 30 +2.5 12 20 40 +2.5 10 -2.5 80 60 TA = +25°C TA = TMIN to TMAX mV µV/°C µA µA V dB 60 kΩ 3 pF TA = TMIN -1.05 -0.87 -1.16 -0.89 TA = TMAX -0.89 -0.70 -0.88 -0.69 TA = +25°C -0.96 -0.81 -0.96 -0.81 TA = TMIN -1.14 -0.88 TA = TMAX -0.88 -0.70 TA = +25°C -0.96 -0.81 TA = TMIN -1.89 -1.65 -1.90 -1.65 TA = TMAX -1.83 -1.57 -1.82 -1.55 TA = +25°C -1.85 -1.65 -1.85 -1.65 TA = TMIN -1.90 -1.65 TA = TMAX -1.83 -1.57 TA = +25°C -1.85 V V -1.65 30 TA = TMIN to TMAX TA = +25°C UNITS dB 60 3 VOH ICC 5 80 CIN Positive Supply Current MAX9687M MIN TYP MAX -5 5 -8 8 15 60 MAX9687C, MAX9687M 2 -2.5 PSRR MAX9687E Logic Output Low Voltage 10 (Note 2) MAX9687C, MAX9687M Logic Output High Voltage MAX9687C/E MIN TYP MAX -5 5 -7 7 10 46 30 50 54 68 46 52 54 72 _______________________________________________________________________________________ 68 74 mA mA Dual, Ultra-Fast ECL-Output Comparator MAX9687 SWITCHING CHARACTERISTICS (VS = ±5V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Input to Output High (Notes 2, 3) tpd+ Input to Output Low (Notes 2, 3) tpd- Latch-Enable to Output High (Notes 2, 3) tpd+(E) Latch-Enable to Output Low (Notes 2, 3) tpd-(E) Latch-Enable Pulse Width (Note 2) tpw(E) Minimum Setup Time Minimum Hold Time Note 2: Note 3: CONDITIONS MAX9687C/E MIN TYP MAX MAX9687M MIN TYP MAX 1.4 1.6 1.4 1.9 1.7 1.4 2.6 1.9 1.9 1.3 2.6 1.8 1.5 1.3 2.0 1.8 1.7 2.6 TA = +25°C TA = 0°C to +70°C TA = -55°C to +125°C TA = +25°C TA = 0°C to +70°C TA = -55°C to +125°C TA = +25°C TA = 0°C to +70°C TA = -55°C to +125°C TA = +25°C TA = 0°C to +70°C TA = -55°C to +125°C 1.4 1.6 1.3 1.4 1.4 1.6 3.0 ts th 1.9 2.2 0.5 0.5 ns 1.9 2.2 ns 1.8 2.0 ns 1.8 1.9 2.0 UNITS ns 3.0 1.0 1.0 2.0 0.5 0.5 ns 1.0 1.0 Not tested, guaranteed by design. VIN = 100mV, VOD = 10mV. INPUT 20mV/div VIN OUTPUT 500mV/div 2ns/div 50Ω LE 50Ω INPUT 0V -2V 50Ω Rf Cf 50Ω OUTPUT -0.9V -1.7V Figure 1. High-speed receiver application with 50Ω input and output termination. With this configuration, in which a ground plane and microstrip PC board was used, the minimum slew rate for clean output switching is 1.6V/µs. For sine-wave inputs, this implies a minimum signal size of 360mVRMS at 500MHz and 90mV at 2MHz. E RMS = Slew Rate Figure 2. As a high-speed receiver, the MAX9687 is capable of processing signals in excess of 600MHz. Figure 2 is a 100MHz example with an input signal level of 14mVRMS. 2 2 πf __________Applications Information Layout Because of the MAX9687’s large gain-bandwidth characteristic, special precautions need to be taken if its highspeed capabilities are to be used. A PC board with a ground plane is mandatory. Mount all decoupling capacitors as close to the power-supply pins as possible, and process the ECL outputs in microstrip fashion, consistent with the load termination of 50Ω to 120Ω. For low-imped- ance applications, microstrip layout at the input may also be helpful. Pay close attention to the bandwidth of the decoupling and terminating components. Chip components can be used to minimize lead inductance. Input Slew-Rate Requirement As with all high-speed comparators, the high gainbandwidth product of these devices creates oscillation problems when the input traverses through the linear region. For clean switching without oscillation or steps in the output waveform, the input must meet certain _______________________________________________________________________________________ 3 MAX9687 Dual, Ultra-Fast ECL-Output Comparator minimum slew-rate requirements. The tendency of the part to oscillate is a function of the layout and source impedance of the circuit employed. Both poor layout and larger source impedance will increase the minimum slew-rate specification. In many applications, the addition of regenerative feedback will assist the input signal through the linear region, which will lower the minimum slew-rate requirement considerably. For example, with the addition of positive feedback components Rf = 1kΩ and Cf = 10pF, the minimum slew-rate requirement can be reduced by a factor of four. ____________________Timing Diagram The timing diagram (Figure 3) illustrates the series of events that complete the compare function, under worst-case conditions. The top line of the diagram illustrates two latch-enable (LE) pulses; each pulse is high for the compare function and low for the latch function. The first pulse demonstrates the compare function in which part of the input action takes place during the compare mode. The second pulse demonstrates a compare-function interval during which there is no change in the input. The leading edge of the input signal (illustrated as a large-amplitude, small-overdrive pulse) switches the –– comparator after time interval tpd. Outputs Q and Q are similar in timing. The input signal must occur at time ts before the latch falling edge and, to be acquired, must be maintained for time th after the edge. After th, the output is no longer affected by the input status until the latch is again strobed. A minimum latch pulse width of tpw(E) is needed for the strobe operation, and the output transitions occur after a time tpd(E). Definition of Terms VOS Input Offset Voltage—The voltage required between the input terminals to obtain 0V differential at the output. VIN Input Voltage Pulse Amplitude VOD Input Voltage Overdrive tpd+ Input to Output High Delay—The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output low-to-high transition. tpdInput to Output Low Delay—The propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output high-to-low transition. tpd+(E) Latch-Enable to Output High Delay—The propagation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output low-to-high transition. tpd-(E) Latch-Enable to Output Low Delay—The propagation delay measured from the 50% point of the latch-enable signal low-to-high transition to the 50% point of an output high-to-low transition. tpw(E) Minimum Latch-Enable Pulse Width—The minimum time the latch-enable signal must be high to acquire and hold an input signal. ts Minimum Setup Time—The minimum time before the negative transition of the latch-enable pulse that an input signal must be present to be acquired and held at the outputs. th Minimum Hold Time—The minimum time after the negative transition of the latch-enable signal that an input signal must remain unchanged to be acquired and held at the outputs. COMPARE LATCH ENABLE 50% LATCH t pw (E) ts th DIFFERENTIAL INPUT VOLTAGE VIN VOS VOD t pd t pd (E) Q 50% Q 50% Figure 3. Timing Diagram Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 4 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.