LINER LT685CJ

LT685
High Speed Comparator
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FEATURES
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DESCRIPTIO
The LT®685 is an ultrafast comparator with differential
inputs and complementary outputs fully compatible with
ECL logic levels. The output current capability is adequate
for driving transmission lines terminated in 50Ω. The low
input offset and high resolution make this comparator
ideally suited for analog-to-digital signal processing
applications.
Ultrafast (5.5ns typ)
Complementary ECL Output
50Ω Line Driving Capability
Low Offset Voltage
Output Latch Capability
External Hysteresis Control
Pin Compatible with Am685
A latch function is provided to allow the comparator to be
used in a sample-hold mode. When the latch enable input
is ECL high, the comparator functions normally. When the
latch enable is driven low, the comparator outputs are
locked in their existing logical states. If the latch function
is not used, the latch enable must be connected to ground
or ECL high.
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APPLICATIO S
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High Speed A-to-D Converters
High Speed Sampling Circuits
Oscillators
The device is pin-compatible with the Am685. Hysteresis
has been added to improve switching time with slow input
signals as well as to minimize oscillation. A single resistor
between the hysteresis pin and V – adds input hysteresis
voltage as more current is drawn. If hysteresis is not
required, the pin can be left unconnected.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
Comparator with Hysteresis
Hysteresis
100
HYSTERESIS IS ZERO
IF PIN LEFT OPEN
6V
GND2
+
VIN
Q
LT685
–
Q
V–
HYSTERESIS
R
RL
HYSTERESIS (mV)
GND1
V+
10
RL
LATCH
ENABLE
1
100
–5.2V
VT
200
1k
2k
500
RESISTANCE (Ω)
5k
10k
LT685 • TA02
LT685 • TA01
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LT685
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AXI U
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ABSOLUTE
RATI GS
(Note 1)
Positive Supply Voltage ............................................. 7V
Negative Supply Voltage .......................................... –7V
Input Voltage ........................................................... ±4V
Differential Input Voltage ......................................... ±6V
Latch Pin Voltage .............................................. 2V to V –
Hysteresis Pin Voltage ...................................... 0V to V –
Output Current ...................................................... 30mA
Power Dissipation (Note 2) ................................ 500mW
Operating Temperature
LT685C ......................................... –30°C ≤ TA ≤ 85°C
LT685M (OBSOLETE) ................. –55°C ≤ TA ≤ 125°C
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U
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
GND #1
+
GND #2
V
10
1
9
NONINVERTING 2
INPUT
INVERTING 3
INPUT
4
LATCH
ENABLE
+
–
5
V–
LT685CH
LT685MH
TOP VIEW
GND #1 1
16 GND #2
V+ 2
15 NC
NON-INVERTING INPUT 3
14 NC
INVERTING INPUT 4
13 NC
NC 5
12 Q OUTPUT
8 Q OUTPUT
LATCH ENABLE 6
11 Q OUTPUT
7 Q OUTPUT
NC 7
10 NC
V– 8
9 HYSTERESIS
6
ORDER PART
NUMBER
LT685CN
HYSTERESIS
H PACKAGE
TO-5 METAL CAN
N16 PACKAGE
16-LEAD CERDIP
J16 PACKAGE (HERMETIC)
16-LEAD PDIP
OBSOLETE PACKAGE
OBSOLETE PACKAGE
Consider the N16 Package as an Alternate Source
Consider the N16 Package as an Alternate Source
ORDER PART
NUMBER
LT685CJ
LT685MJ
LT685 • POI01
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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LT685
ELECTRICAL CHARACTERISTICS
erature ranges, unless otherwise noted.
V+ = 6.0V, V– = –5.2V, VT = –2V, RL = 50Ω, R = ∞ over the operating temp-
MIN
LT685C
TYP
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
TA = 25°C
dVOS/dT
Input Offset Voltage Drift
(Note 3)
lOS
Input Offset Current
TA = 25°C
0.3
±1.0
±1.3
IB
Input Bias Current
TA= 25°C
5
10
13
RIN
Input Resistance
TA = 25°C (Note 3)
CIN
Input Capacitance
TA = 25°C (Note 3)
VCM
lnput Voltage Range
CMRR
Common Mode Rejection
80
80
dB
SVRR
Supply Voltage Rejection
70
70
dB
VOH
Output High Voltage
TA = 25°C
TA = TMIN
TA = TMAX
– 0.960
–1.060
– 0.890
–0.810
–0.890
–0.700
–0.960
–1.100
–0.850
–0.810
–0.920
–0.620
V
V
V
VOL
Output Low Voltage
TA = 25°C
TA = TMIN
TA = TMAX
–1.850
–1.890
–1.825
–1.650
–1.675
–1.625
–1.850
–1.910
–1.810
–1.650
–1.690
–1.575
V
V
V
I+
Positive Supply Current
22
22
mA
I–
Negative Supply Current
26
26
mA
PDISS
Power Dissipation
300
300
mW
1.0
MAX
MIN
LT685M
TYP
SYMBOL
MAX
UNITS
±2.0
±3.0
mV
mV
±10
µV/°C
0.3
±1.0
±1.6
µA
µA
5
10
16
µA
µA
1.0
±2.0
±2.5
±10
6.0
6.0
kΩ
3.0
3.0
pF
±3.3
±3.3
V
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LT685
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SWITCHI G CHARACTERISTICS
(VIN = 100mV step, 5mV overdrive)
SYMBOL
PARAMETER
CONDITIONS
MIN
tPD
Propagation Delay
(Note 4)
TA = 25°C
TA = TMAX
TA = TMIN
4.5
5.0
4.0
tPD(E)
Latch Enable to
Output Delay
(Note 3)
TA = 25°C
TA = TMAX
TA = TMIN
4.5
5.0
4.0
tS
Minimum Set-Up Time
(Note 3)
TMIN ≤ TA ≤ 25°C
TA = TMAX
tH
Minimum Hold Time
(Note 3)
tPW(E)
Minimum Latch Enable
Pulse Width (Note 3)
LT685C
TYP
LT685M
TYP
MAX
MIN
5.5
6.5
9.5
6.5
4.5
5.5
3.5
5.5
6.5
12
6.5
ns
ns
ns
5.5
6.5
9.5
6.5
4.5
5.5
3.5
5.5
6.5
12
6.5
ns
ns
ns
3.0
4.0
3.0
6.0
ns
ns
TMIN ≤ TA ≤ TMAX
1.0
1.0
ns
TMIN ≤ TA ≤ 25°C
TA = TMAX
3.0
4.0
3.0
5.0
ns
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: For the metal can package, derate at 6.8mW/°C for operation at
ambient temperatures above 100°C; for the hermetic dual-in-line package,
derate at 9mW/°C for operation at ambient temperatures above 105°C.
Note 3: Guaranteed by design, but not tested.
Note 4: Sample tested at 25°C only.
MAX
UNITS
Definitions:
tPD: The propagation delay measured from the time the input signal
crosses the input offset voltage to the 50% point of the output transition.
tPD(E): The propagation delay measured from the 50% point of the latch
enable signal positive transition to the 50% point of the output transition.
tS: The minimum time before the negative transition of the latch enable
signal that an input signal change must be present in order to be acquired
and held at the outputs.
tH: The minimum time after the negative transition of the latch enable
signal that the input signal must remain unchanged in order to be acquired
and held at the outputs.
tPW (E): The minimum time that the latch enable signal must be HIGH in
order to acquire and hold an input signal change.
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LT685
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W
SCHE ATIC DIAGRA
V+
R2
300Ω
R1
300Ω
R23
1.7k
Q14
D2
Q13
Q33
D1
R22
2.9k
R5
525Ω
D4
Q19
D3
Q3
Q4
R6
525Ω
Q32
Q20
Q31
Q18
GND #2
Q17
GND #1
Q30
NONINVERTING
INPUT
Q7
Q8
Q6
Q1
D5
D7
D8
Q5
INVERTING
INPUT
Q2
R3
1.4k
R4
2.4k
R7
275Ω
R8
275Ω
D6
Q23
R21
846Ω
Q21
Q24
Q29
LATCH
ENABLE
Q9
R20
3.8k
Q10
Q16
Q22
Q15
Q28
Q12
Q11
R11
430Ω
Q26
Q27
R12
200Ω
R19
2.4k
R10
880Ω
R14
3k
R18
150Ω
Q25
R13
3.0k
R15
2.1k
R16
2.1k
Q
Q
OUTPUT OUTPUT
R17
150Ω
V–
HYSTERESIS
LT685 • S01
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LT685
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TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delays as a Function
of Temperature
Hysteresis as a Function of
Temperature
12
100
90
80
HYSTERESIS (mV)
PROPAGATION (ns)
10
8
VOD = 5mV
6 VOD = 2.5mV
4 V = 20mV
OD
VOD = 10mV
70
R = 200Ω
60
50
40
30
R = 500Ω
20
R = 1000Ω
10
2
–50 –25
50
25
0
75
TEMPERATURE (°C)
0
–50 –25
125
100
50
25
0
75
TEMPERATURE (°C)
LTC685 • TPC01
100
125
LTC685 • TPC02
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PACKAGE DESCRIPTIO
H Package
10-Lead TO-5 Metal Can
(Reference LTC DWG # 05-08-1322)
0.335 – 0.370
(8.509 – 9.398)
DIA
0.305 – 0.335
(7.747 – 8.509)
0.040
(1.016)
MAX
0.050
(1.270)
MAX
SEATING
PLANE
0.165 – 0.185
(4.191 – 4.699)
GAUGE
PLANE
0.010 – 0.045*
(0.254 – 1.143)
REFERENCE
PLANE
0.500 – 0.750
(12.700 – 19.050)
0.016 – 0.021**
(0.406 – 0.533)
0.027 – 0.045
(0.686 – 1.143)
PIN 1
36°BSC
0.028 – 0.034
(0.711 – 0.864)
0.230
( 5.842)
TYP
0.110 – 0.160
(2.794 – 4.064)
INSULATING
STANDOFF
*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045" BELOW THE REFERENCE PLANE
0.016 – 0.024
**FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS
(0.406 – 0.610)
H10(TO-5) 1197
OBSOLETE PACKAGE
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LT685
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PACKAGE DESCRIPTIO
J Package
16-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)
0.005
(0.127)
MIN
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0.840
(21.336)
MAX
16
15
14
13
12
11
10
9
0.220 – 0.310
(5.588 – 7.874)
0.025
(0.635)
RAD TYP
1
2
3
4
5
6
7
8
0.200
(5.080)
MAX
0.300 BSC
(0.762 BSC)
0.015 – 0.060
(0.380 – 1.520)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0.125
(3.175)
MIN
0.045 – 0.065
(1.143 – 1.651)
0.014 – 0.026
(0.360 – 0.660)
0.100
(2.54)
BSC
J16 1298
OBSOLETE PACKAGE
685fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT685
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PACKAGE DESCRIPTIO
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325 –0.015
(
8.255
+0.889
–0.381
0.045 – 0.065
(1.143 – 1.651)
0.065
(1.651)
TYP
0.125
(3.175)
MIN
)
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.018 ± 0.003
(0.457 ± 0.076)
N16 1098
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Linear Technology Corporation
LW/TP 0902 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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 LINEAR TECHNOLOGY CORPORATION 1988