PI6C2402 Phase-Locked Loop Clock Driver Features Description • Clock doubler The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop (PLL) clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. The PI6C2402 provides 2X CLK_IN on CLK_OUT output. • High-Performance Phase-Locked-Loop Clock Distribution for Networking, ATM, 100 MHz and 134 MHz Registered DIMM Synchronous DRAM modules for server, workstation, and PC applications • Zero Input-to-Output delay Applications • Cycle-to-Cycle jitter ≤ ±150ps max. If the system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as the PI6C2509, and the PI6C2510, are likely to be impractical. The device-to-device skew introduced can significantly reduce the performance. Pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. For example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. • On-chip series damping resistor at clock output drivers for low noise and EMI reduction • Operates at 3.3V VCC • Packaging (Pb-free & Green available): — 8-pin SOIC Package (W) Pin Configuration Block Diagram CLK_IN ÷2 FB_IN CLK_IN 1 8 FB_IN AVCC 2 7 VCC AGND 3 6 GND CLK_OUT 4 5 CLK_OUT PLL S S Control Input Feedback Reference Clock Signal CLK_OUT Outputs Source PLL Shutdown HIGH PLL Disabled LOW CLK_IN Enabled V Zero Delay Buffer PI6C2402 18 Output Non-Zero Delay Buffer S 17 Figure 1. Zero-Delay Buffering Diagram 08-0298 1 PS8418I 11/13/08 PI6C2402 Phase-Locked Loop Clock Driver Pin Functions Name Number Type Description CLK_IN 1 I AVCC 2 Power Analog Power AGND 3 Ground Analog Ground CLK_OUT 4 O Clock Output. The output provides low-skew copies of CLK_IN and has an embedded series-damping resistor. S 5 I Control Input S. S is used to bypass the PLL for test purposes. When S is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs GND 6 Ground Ground VCC 7 Power Power Supply FB_IN 8 I Reference Clock inptu, CLK_IN allows spread spectrum clock input Feedback input. FB_IN provides the feedback signal to the internal PLL. Absolute Maximum Ratings(1) (Over operating free-air temperature range) Symbol Test Conditions Min. Max. Units VI Input voltage range -0.5 VCC + 0.5 VO Output voltage range -0.5 VCC + 0.5 VI_DC DC input voltage -0.5 5.0 IO_DC DC output current 100 mA Power Maximum power dissipation at TA = 55ºC in still air 1.0 W TSTG Storage temperature 150 ºC Min. Max. Units 3.0 3.6 3.135 3.465 -65 V Note: 1. Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Recommended Operating Conditions Symbol Test Conditions VCC Supply Voltage VIH High Level input voltage VIL Low Level input voltage VI Input voltage TA Operating free-air temperature 08-0298 Temperature Commercial Industrial 2.0 V 0.8 Commercial Industrial 2 0 VCC 0 70 -40 85 ºC PS8418I 11/13/08 PI6C2402 Phase-Locked Loop Clock Driver Electrical Characteristics (Over recommended operating free-air temperature range) Symbol Temperature Condition Commercial Min. Typ. 10 3.465V 10 VI = GND; IO = 0(1) CI VI = VCC or GND 3.3V 4 CO Vo = VCC or GND 3.3V 6 IOL Industrial Max. 3.6V ICC IOH 1. Test Conditions -12 VOUT = 2.0V -18 18 VOUT = 0.55V 12 μA pF VOUT = 2.4V VOUT = 0.8V Units mA Note: Continuous Output Current AC Specifications Timing Requirements (Over recommended ranges of supply voltage and operating free-air temperature, CL = 25pF) Symbol Parameters FOUT Clock Frequency DCYI Input clock duty cycle Test Conditions Min. Typ. tp Phase error without tj Units Commercial 25 134 Industrial 25 100 40 60 % 1 ms Stabilization time after power up jitter(1) Max. CLK_IN↑ at 100 MHz and 66 MHz -150 150 Jitter, cycle-to-cycle At 100 MHz -150 150 Duty Cycle At ≤ 100 MHz 45 55 At > 100 MHz 35 65 tr Rise-time 0.4V to 2.0V 1.0 tf Fall-time 2.0V to 0.4V 1.1 MHz ps % ns Note: 1. This switching parameter is guaranteed by design. 08-0298 3 PS8418I 11/13/08 PI6C2402 Phase-Locked Loop Clock Driver Packaging Mechanical: 8-pin Plastic SOIC (W) 8 .149 .157 3.78 3.99 .0099 .0196 1 0.25 x 45° 0.50 .0075 .0098 0-8° .189 .196 4.80 5.00 .016 .026 0.406 0.660 0.19 0.25 0.40 .016 1.27 .050 .053 .068 .2284 .2440 5.80 6.20 1.35 1.75 SEATING PLANE REF .050 BSC 1.27 .0040 0.10 .0098 0.25 .013 0.330 .020 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information(1,2,3) Ordering Code Package Code PI6C2402WE W Package Description Pb-free & Green, 8-pin, 150-mil SOIC Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free & Green 3. X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 08-0298 4 PS8418I 11/13/08