19-2201; Rev 0; 8/01 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features ♦ Improved Second Source of the MC10LVEP11 (MAX9320) ♦ +2.25V to +3.8V Differential HSTL/LVPECL Operation ♦ -2.25V to -3.8V LVECL Operation ♦ Low 22mA (typ) Supply Current ♦ 20ps (typ) Part-to-Part Skew ♦ 6ps (typ) Output-to-Output Skew ♦ 208ps (typ) Propagation Delay ♦ Minimum 300mV Output at 3GHz ♦ Outputs Low for Open Input ♦ ESD Protection >2kV (Human Body Model) ♦ Available in Thermally Enhanced Exposed-Pad SO Package These devices are offered in space-saving 8-pin SOT23* and industry-standard TSSOP* and SO packages. Applications Ordering Information Precision Clock Distribution PART Low-Jitter Data Repeater MAX9320EKA-T* Protection Switching TEMP. RANGE PINPACKAGE -40°C to +85°C TOP MARK 8 SOT23 — — MAX9320ESA -40°C to +85°C 8 SO-EP** MAX9320EUA* -40°C to +85°C 8 TSSOP — MAX9320AEKA* -40°C to +85°C 8 SOT23 AAIW *Future product—contact factory for availability. **EP-Exposed pad. Pin Configurations Q0 1 8 VCC MAX9320 VCC 1 60kΩ Q0 2 MAX9320A 8 Q0 VCC 1 MAX9320 VCC 7 D VEE 2 6 D D 3 5 VEE D 4 8 Q0 VCC 60kΩ 7 Q0 VEE 2 6 Q1 D 3 5 Q1 D 4 7 Q0 60kΩ 100kΩ Q1 3 100kΩ 100kΩ Q1 4 6 Q1 100kΩ 100kΩ VEE TSSOP*/SO 100kΩ 5 Q1 VEE SOT23* SOT23* ________________________________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9320/MAX9320A General Description The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. The MAX9320/MAX9320A feature ultra-low propagation delay (208ps), part-to-part skew (20ps), and output-tooutput skew (6ps) with 30mA maximum supply current, making these devices ideal for clock distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The pinout is the only difference between the MAX9320 and MAX9320A. Multiple pinouts are provided to simplify routing across a backplane to either side of a doublesided board. MAX9320/MAX9320A 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers ABSOLUTE MAXIMUM RATINGS VCC to VEE ..........................................................................+4.1V D or D .................................................. VEE - 0.3V to VCC + 0.3V D to D .................................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin SOT23.............................................................+112°C/W 8-Pin TSSOP ............................................................+221°C/W 8-Pin SO...................................................................+170°C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin SOT23...............................................................+78°C/W 8-Pin TSSOP ............................................................+155°C/W 8-Pin SO.....................................................................+99°C/W Junction-to-Case Thermal Resistance 8-Pin SOT23...............................................................+80°C/W 8-Pin TSSOP ..............................................................+39°C/W 8-Pin SO.....................................................................+40°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (D, D, Q_, Q_) .................................>2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = +3.3V, VIHD = VCC 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS DIFFERENTIAL INPUT (D, D) High Voltage of Differential Input VIHD VEE + 1.2 V VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD VEE VCC - 0.1 VEE VCC - 0.1 VEE VCC - 0.1 V For VCC - VEE < +3.0V 0.1 VCC - VEE 0.1 VCC - VEE 0.1 VCC - VEE For VCC - VEE ≥ +3.0V 0.1 3.0 0.1 3.0 0.1 3.0 Differential Input Voltage VIHD - VILD Input High Current IIH D Input Low Current IILD -10 D Input Low Current IILD -150 150 100 150 -10 100 -150 -10 V 150 µA 100 µA -150 µA DIFFERENTIAL OUTPUTS (Q_, Q__) Single-Ended Output High Voltage 2 VOH Figure 1 VCC - 1.135 VCC - 0.885 VCC - 1.07 VCC - 0.82 VCC - 1.01 _______________________________________________________________________________________ VCC - 0.76 V 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = +3.3V, VIHD = VCC 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN Single-Ended Output Low Voltage VOL Figure 1 VCC - 1.935 Differential Output Voltage VOH - VOL Figure 1 550 +25°C TYP MAX MIN TYP VCC VCC - 1.685 - 1.87 +85°C MAX MIN VCC - 1.62 VCC - 1.81 550 TYP MAX VCC - 1.56 550 UNITS V mV POWER SUPPLY Supply Current (Note 4) 20 IEE 28 22 28 23 30 mA AC ELECTRICAL CHARACTERISTICS (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Differential Input-toOutput Delay tPLHD, tPHLD Output-toOutput Skew (Note 6) Part-to-Part Skew (Note 7) CONDITIONS -40°C +25°C +85°C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX 145 220 265 155 208 265 160 203 270 ps tSKOO 6 30 6 30 6 30 ps tSKPP 20 120 20 110 20 110 ps fIN = 1.5GHz, Clock pattern 1.7 2.8 1.7 2.8 1.7 2.8 fIN = 3.0GHz, Clock pattern 0.6 1.5 0.6 1.5 0.6 1.5 3.0Gbps 223-1 PRBS pattern 57 80 57 80 57 80 Added Random Jitter (Note 8) tRJ Added Deterministic Jitter (Note 8) tDJ Figure 1 ps (RMS) ps (p-p) _______________________________________________________________________________________ 3 MAX9320/MAX9320A DC ELECTRICAL CHARACTERISTICS (continued) MAX9320/MAX9320A 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers AC ELECTRICAL CHARACTERISTICS (continued) (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5) PARAMETER Switching Frequency Output Rise/Fall Time (20% to 80%) SYMBOL CONDITIONS VOH - VOL ≥ 300mV, Clock pattern, Figure 1 fMAX tR, tF -40°C MIN TYP +25°C MAX 3.0 MIN TYP +85°C MAX 3.0 MIN TYP MAX UNITS 3.0 GHz VOH - VOL ≥ 550mV, Clock pattern, Figure 1 2.0 Figure 1 50 2.0 88 120 50 2.0 89 120 50 90 120 ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25°C. Guaranteed by design and characterization over the full operating temperature range. Note 4: All pins open except VCC and VEE. Note 5: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 8: Device jitter added to the input signal. 4 _______________________________________________________________________________________ 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY 21 20 19 18 0.7 0.6 0.5 0.4 0.3 17 0.2 16 0.1 90 TRANSITION TIME (ps) OUTPUT AMPLITUDE (V) 0.8 22 89 tF 88 tR 87 86 15 85 0 10 35 60 85 0 500 TEMPERATURE (°C) -15 225 VIHD - VILD = 0.5V tPLHD 210 205 tPHLD 200 35 60 85 PROPAGATION DELAY vs. TEMPERATURE 240 230 PROPAGATION DELAY (ps) 220 10 TEMPERATURE (°C) FREQUENCY (MHz) PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD 215 -40 1000 1500 2000 2500 3000 3500 MAX9320 toc05 -15 MAX9320 toc04 -40 PROPAGATION DELAY (ps) SUPPLY CURRENT (mA) 23 91 MAX9320 toc02 24 TRANSITION TIME vs. TEMPERATURE 0.9 MAX9320 toc01 25 MAX9320 toc03 SUPPLY CURRENT, IEE vs. TEMPERATURE tPLHD 220 210 200 190 tPHLD 180 170 160 195 1.0 1.4 1.8 2.2 2.6 VIHD (V) 3.0 3.4 3.8 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9320/MAX9320A Typical Operating Characteristics (VCC = +3.3V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.) 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9320/MAX9320A Pin Description (MAX9320) PIN NAME FUNCTION TSSOP/SO SOT23 1 8 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 2 7 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 3 6 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 4 5 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 5 2 VEE 6 4 D Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE. 7 3 D Noninverting Differential Input. 100kΩ pulldown to VEE. 8 1 VCC Negative Supply Voltage Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Pin Description (MAX9320A) PIN SOT23 6 NAME FUNCTION 1 VCC Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 VEE Negative Supply Voltage 3 D Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE. 4 D Noninverting Differential Input. 100kΩ pulldown to VEE. 5 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 6 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 7 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 8 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. _______________________________________________________________________________________ 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers VIHD VIHD -VILD VILD D tPLHD Applications Information tPHLD Q_ VOH VOH -VOL VOL Q 80% 80% 0 (DIFFERENTIAL) (Q_) - (Q_) 0 (DIFFERENTIAL) 20% Supply Bypassing Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel vias for low inductance. Traces 20% tR tF Figure 1. Differential Transition Time and Propagation Delay Timing Diagram Detailed Description The MAX9320/MAX9320A low-skew, 1-to-2 differential drivers are designed for clock and data distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock and data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. Inputs The maximum magnitude of the differential input from D to D is VCC - VEE or 3.0V, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting input, D, is biased with a 60kΩ pullup to VCC and a 100kΩ pulldown to VEE. The noninverting input, D, is biased with a 100kΩ pulldown to VEE. Specifications for the high and low voltages of the differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). Input and output trace characteristics affect the performance of the MAX9320/MAX9320A. Connect each signal of a differential input or output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. The exposed-pad (EP) SO package can be soldered to the PC board for enhanced thermal performance. If the EP is not soldered to the PC board, the thermal resistance is the same as the regular SO package. The EP is connected to the chip VEE supply. Be sure that the pad does not touch signal lines or other supplies. Contact the Maxim Packaging department for guidelines on the use of EP packages. Output Termination Terminate outputs through 50Ω to VCC - 2V or use an equivalent Thevenin termination. Terminate both outputs and use the same termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0. Chip Information TRANSISTOR COUNT: 182 Outputs Output levels are referenced to VCC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are LVPECL. The outputs are LVECL when VCC is connected to GND and VEE is connected to a negative supply. _______________________________________________________________________________________ 7 MAX9320/MAX9320A D A single-ended input of ±100mV around a reference voltage or a differential input of at least ±100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers 8L, SOIC EXP. PAD.EPS SOT23, 8L.EPS MAX9320/MAX9320A Package Information 8 _______________________________________________________________________________________ 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers 8LUMAXD.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9320/MAX9320A Package Information (continued)