19-2544; Rev 1; 12/02 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0GHz. The 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function. The MAX9322 operates in LVPECL systems with a +2.375V to +3.8V supply or in LVECL systems with a -2.375V to -3.8V supply. A VBB reference output provides compatibility with single-ended clock input signals and a master reset input provides a simultaneous reset on all outputs. The MAX9322 is available in 52-pin TQFP and 68-pin QFN packages and is specified for operation over -40°C to +85°C. For 1:10 clock drivers, refer to the MAX9311/MAX9313 data sheet. For 1:5 clock drivers, refer to the MAX9316 data sheet. Applications Features ♦ 1.2ps (RMS) Maximum Random Jitter ♦ 300mV Differential Output at 1.0GHz ♦ 900ps Propagation Delay ♦ Selectable Divide-by-1 or Divide-by-2 Frequency Outputs ♦ Multiplexed 2:1 Input Function ♦ LVECL Operation from VEE = -2.375V to -3.8V ♦ LVPECL Operation from VCC = +2.375V to +3.8V ♦ ESD Protection: > 2kV Human Body Model Ordering Information PART PINPACKAGE TEMP RANGE MAX9322ECY -40°C to +85°C 52 TQFP MAX9322ETK* -40°C to +85°C 68 QFN *Future product—contact factory for availability. Precision Clock Distribution Low-Jitter Data Repeaters Pin Configurations Central-Office Backplane Clock Distribution DSLAM Backplane VCC 1 MR 2 FSELA 3 FSELB 4 CLK0 5 CLK0 6 CLK_SEL 7 CLK1 8 CLK1 9 QA0 QA0 QA1 QA1 VCCO QB0 QB0 QB1 QB1 QB2 QB2 VCCO ATE VCCO TOP VIEW Base Stations 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VCCO 38 QC0 37 QC0 Typical Operating Circuit 36 QC1 35 QC1 34 QC2 MAX9322 33 QC2 RECEIVER MAX9322 32 QC3 31 QC3 VBB 10 ZO = 50Ω Q_ 30 VCCO FSELC 11 29 N.C. FSELD 12 28 N.C. VEE 13 ZO = 50Ω 27 VCCO 21 22 23 24 25 26 QD0 QD0 QD4 20 QD1 QD4 19 QD1 18 QD2 17 QD2 16 QD3 15 QD3 14 QD5 50Ω QD5 50Ω VCCO Q_ TQFP VTT = VCC - 2.0V Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9322 General Description MAX9322 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver ABSOLUTE MAXIMUM RATINGS VCC to VEE .............................................................................4.1V Inputs and Outputs to VEE..........................-0.3V to (VCC + 0.3V) Differential Input Magnitude............Lower of (VCC - VEE) and 3V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................±0.65mA Continuous Power Dissipation (TA = +70°C) Single-Layer PC Board 52-Pin TQFP (derate 15.4mW/°C above +70°C).....1230.8mW 68-Lead QFN (derate 27.8mW/°C above +70°C) ...2222.2mW Multilayer PC Board 52-Pin TQFP (derate 19.1mW/°C above +70°C).....1529.6mW 68-Lead QFN (derate 38.5mW/°C above +70°C) ...3076.9mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 52-Pin TQFP...............................................................+65°C/W 68-Lead QFN .............................................................+36°C/W Multilayer PC Board 52-Pin TQFP............................................................+52.3°C/W 68-Lead QFN .............................................................+26°C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow Single-Layer PC Board 52-Pin TQFP...............................................................+50°C/W 68-Lead QFN .............................................................+27°C/W Multilayer PC Board 52-Pin TQFP...............................................................+40°C/W 68-Lead QFN .............................................................+20°C/W Junction-to-Case Thermal Resistance 52-Pin TQFP............................................................+12.9°C/W 68-Lead QFN ...............................................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (Q_ _, Q_ _, CLK_SEL, FSEL_, CLK_, CLK_, MR, VBB) ............................................±2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS ((VCC - VEE) = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V; CLK_SEL, FSEL_ = high or low; MR = low; |VID| = 0.095V to the lower of (VCC - VEE ) and 3V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1–4) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS SINGLE-ENDED INPUT (MR, FSEL_, CLK_SEL) Input High Voltage VIH1 Figure 1 VCC 1.155 VCC 0.88 VCC 1.155 VCC - VCC 0.88 1.155 VCC 0.88 V Input Low Voltage VIL1 Figure 1 VCC 1.81 VCC - VCC 1.505 1.81 VCC - VCC 1.505 1.81 VCC 1.505 V +150 +150 +150 µA MR, FSEL_, CLK_SEL = VIL or VIH DIFFERENTIAL INPUT (CLK_, CLK_) Input Current IIN1 Single-Ended Input High Voltage VIH2 Figure 1 VCC 1.155 VCC - VCC 0.88 1.155 VCC - VCC 0.88 1.155 VCC 0.88 V Single-Ended Input Low Voltage VIL2 Figure 1 VCC 1.81 VCC - VCC 1.505 1.81 VCC - VCC 1.505 1.81 VCC 1.505 V High Voltage of Differential Input VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD VEE VCC 0.095 VEE VCC 0.095 VEE VCC 0.095 V 2 -15 -15 -15 _______________________________________________________________________________________ LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver ((VCC - VEE) = 2.375V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V; CLK_SEL, FSEL_ = high or low; MR = low; |VID| = 0.095V to the lower of (VCC - VEE ) and 3V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1–4) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP VCC 0.095 VEE +85°C MAX MIN TYP VCC 0.095 VEE MAX UNITS VCC VEE For VCC - VEE < 3.0V 0.095 For VCC - VEE ≥ 3.0V 0.095 3.0 0.095 3.0 0.095 3.0 IIN2 CLK_, CLK_ = VIHD or VILD -150 +150 -150 +150 -150 +150 µA Single-Ended Output High Voltage VOH Figure 1 VCC 1.085 VCC - VCC 0.880 1.025 VCC - VCC 0.880 1.025 VCC 0.880 V Single-Ended Output Low Voltage VOL Figure 1 VCC 1.810 VCC - VCC 1.52 1.810 VCC - VCC 1.620 1.810 VCC 1.620 V VOH VOL Figure 1 500 Differential Input Voltage Input Current VIHD VILD V OUTPUTS (Q_, Q_) Differential Output Voltage 600 600 mV REFERENCE Reference Voltage Output VBB IBB = ±0.5mA (Note 5) IEE (Note 6) VCC 1.41 VCC - VCC 1.25 1.41 VCC - VCC 1.25 1.41 VCC 1.25 V 130 mA SUPPLY Supply Current 50 85 66 115 80 _______________________________________________________________________________________ 3 MAX9322 DC ELECTRICAL CHARACTERISTICS (continued) MAX9322 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver AC ELECTRICAL CHARACTERISTICS ((VCC - VEE) = 2.375V to 3.8V; outputs loaded with 50Ω ±1% to VCC - 2V; input frequency ≤ 1000MHz; input transition time = 125ps (20% to 80%); CLK_SEL, FSEL_ = high or low, MR = low; VIHD = VEE + 1.2V to VCC; VILD = VEE to VCC - 0.4V; VIHD - VILD = 0.4V to 1V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Note 7) PARAMETER SYMBOL -40°C CONDITION +25°C +85°C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Differential Input-toOutput Delay tPLHD, tPHLD Figure 2 700 900 1150 725 900 1180 750 950 1225 ps Single-Ended CLK_/CLK_ to Output Delay tPHLS, tPLHS Figure 1 700 900 1170 700 900 1175 725 950 1250 ps MR to Output Delay tPD Figure 3 450 930 450 930 450 930 ps Output-to-Output Skew tSKOO (Note 8) 85 56 50 ps Added Random Jitter tRJ fIN = 1.0GHz clock pattern (Note 9) 1.2 1.2 1.2 ps (RMS) Added Deterministic Jitter tDJ 1Gbps 223 - 1 PRBS pattern (Note 9) 61 61 61 psP-P Switching Frequency fMAX VOD > 300mV 1.0 Differential Output Rise and Fall Time (20% to 80%) tR , t F Figure 2 200 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 4 1.0 260 400 200 1.0 260 400 200 GHz 240 400 ps Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. Single-ended CLK_, CLK_ input operation is limited to VCC - VEE = 3.0V to 3.8V. DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range. Use VBB as a reference for inputs of the same device only. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at ±6 sigma. Measured between outputs of the same parts at the signal crossing points under identical conditions for a same-edge transition. Device jitter added to a jitter-free input signal. _______________________________________________________________________________________ LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY 55 45 260 600 TRANSITION TIME (ps) 65 TRANSITION TIME vs. TEMPERATURE 270 MAX9322 toc02 700 OUTPUT AMPLITUDE (V) 75 500 400 300 200 0 -40 -15 10 35 60 tR 240 230 220 200 200 400 600 800 1000 1200 1400 1600 0 -40 -15 10 35 60 TEMPERATURE (°C) FREQUENCY (MHz) TEMPERATURE (°C) PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD PROPAGATION DELAY vs. TEMPERATURE PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE 900 895 890 885 VIH2 = VCC = 1.15V VIL2 = VCC = 1.48V 980 960 940 920 SINGLE-ENDED CLOCK 900 1.5 1.8 2.1 2.4 VIHD - VEE (V) 2.7 3.0 3.3 870 830 DIFFERENTIAL CLOCK 860 1.2 910 790 880 880 85 950 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 905 1000 MAX9322 toc05 1020 MAX9322 toc04 910 PROPAGATION DELAY (ps) 85 250 210 100 35 tF MAX9322 toc06 SUPPLY CURRENT (mA) 800 MAX9322 toc01 85 MAX9322 toc03 SUPPLY CURRENT, IEE vs. TEMPERATURE 750 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT VOLTAGE (VIHD - VILD) (V) _______________________________________________________________________________________ 5 MAX9322 Typical Operating Characteristics (VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, VID = 500mV, CLK_SEL = 0, FSEL_ = 0, fIN = 600MHz, TA = +25°C, unless otherwise noted.) LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322 Pin Description PIN 6 NAME FUNCTION TQFP QFN 1 2, 3 VCC Positive Power Supply. Powers input circuitry. Bypass each VCC to VEE with a 0.01µF and 0.1µF capacitor. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 4 MR Single-Ended Master Reset. A high on MR sets all outputs to differential zero. A low on MR enables all outputs. MR is pulled to VEE through a 75kΩ resistor. 3 5 FSELA Single-Ended Frequency Select A. Selects the output frequency for bank A. Bank A consists of two differential outputs. A low on FSELA selects divide-by-1. A high on FSELA selects divide-by-2. FSELA is pulled to VEE through a 75kΩ resistor. 4 6 FSELB Single-Ended Frequency Select B. Selects the output frequency for bank B. Bank B consists of three differential outputs. A low on FSELB selects divide-by-1. A high on FSELB selects divide-by-2. FSELB is pulled to VEE through a 75kΩ resistor. Noninverting Clock 0 Input. CLK0 is pulled to VEE through 75kΩ resistors. Inverting Clock 0 Input. CLK0 is pulled to VCC and to VEE through a 75kΩ resistor. 5 7 CLK0 6 8 CLK0 7 9 CLK_SEL 8 10 CLK1 9 11 CLK1 Inverting Clock 1 Input. CLK1 is pulled to VCC and to VEE through 75kΩ resistors. Reference Voltage Output. Connect VBB to CLK_ or CLK_ to provide a reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise leave open. Single-Ended Clock Selector Input. A low on CLK_SEL selects CLK0. A high on CLK_SEL selects CLK1. CLK_SEL is pulled to VEE through a 75kΩ resistor. Noninverting Clock 1 Input. CLK1 is pulled to VEE through a 75kΩ resistor. 10 12 VBB 11 13 FSELC Single-Ended Frequency Select C. Selects the output frequency for bank C. Bank C consists of four differential outputs. A low on FSELC selects divide-by-1. A high on FSELC selects divide-by-2. FSELC is pulled to VEE through a 75kΩ resistor. 12 14 FSELD Single-Ended Frequency Select D. Selects the output frequency for bank D. Bank D consists of six differential outputs. A low on FSELD selects divide-by-1. A high on FSELD selects divide-by-2. FSELD is pulled to VEE through a 75kΩ resistor. 13 15, 16 VEE 14, 27, 30, 39, 40, 47, 52 19, 20, 33, 36, 37, 40, 49, 50, 53, 54, 61, 66, 67 VCCO Output Driver Positive Power Supply. Powers device output drivers. Bypass each VCCO to VEE with a 0.01µF and 0.1µF capacitor. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Negative Power-Supply Input 15 21 QD5 Inverting QD5 Output. Typically terminate with 50Ω resistor to VCC - 2V. 16 22 QD5 Noninverting QD5 Output. Typically terminate with 50Ω resistor to VCC - 2V. 17 23 QD4 Inverting QD4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 18 24 QD4 Noninverting QD4 Output. Typically terminate with 50Ω resistor to VCC - 2V. _______________________________________________________________________________________ LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver PIN TQFP QFN NAME FUNCTION 19 25 QD3 20 26 QD3 Noninverting QD3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 21 27 QD2 Inverting QD2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 22 28 QD2 Noninverting QD2 Output. Typically terminate with 50Ω resistor to VCC - 2V. Inverting QD1 Output. Typically terminate with 50Ω resistor to VCC - 2V. Inverting QD3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 23 29 QD1 24 30 QD1 Noninverting QD1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 25 31 QD0 Inverting QD0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 26 32 QD0 Noninverting QD0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 28, 29 1, 17, 18, 34, 35, 38, 39, 51, 52, 68 N.C. No Connection. Not internally connected. 31 41 QC3 Inverting QC3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 32 42 QC3 Noninverting QC3 Output. Typically terminate with 50Ω resistor to VCC - 2V. Inverting QC2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 33 43 QC2 34 44 QC2 Noninverting QC2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 35 45 QC1 Inverting QC1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 36 46 QC1 Noninverting QC1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 37 47 QC0 Inverting QC0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 38 48 QC0 Noninverting QC0 Output. Typically terminate with 50Ω resistor to VCC - 2V. Inverting QB2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 41 55 QB2 42 56 QB2 Noninverting QB2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 43 57 QB1 Inverting QB1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 44 58 QB1 Noninverting QB1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 45 59 QB0 Inverting QB0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 46 60 QB0 Noninverting QB0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 48 62 QA1 Inverting QA1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 49 63 QA1 Noninverting QA1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 50 64 QA0 Inverting QA0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 51 65 QA0 Noninverting QA0 Output. Typically terminate with 50Ω resistor to VCC - 2V. — EP VEE The exposed pad of the QFN package is internally connected to VEE. Refer to Application Note HFAN-08.1. _______________________________________________________________________________________ 7 MAX9322 Pin Description (continued) MAX9322 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MR, FSEL_, CLK_SEL VIH1 VBB VIL1 CLK_ VIH2 CLK_ VBB VIL2 (CLK_ IS CONNECTED TO VBB) tPHLS tPLHS Q_ VOH VOH - VOL VOL Q_ Figure 1. Timing Diagram for Single-Ended Inputs CLK_ VIHD VIHD - VILD VILD CLK_ tPLHD tPHLD VOH Q_ VOH - VOL VOL Q_ 80% 80% 0V (DIFFERENTIAL) 0V (DIFFERENTIAL) 20% 20% Q_ - Q_ tR VOH - VOL tF Figure 2. Timing Diagram for Differential Inputs 8 _______________________________________________________________________________________ LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322 VIH VBB MR VIL tPD Q_ VOH Q_ VOL Figure 3. Timing Diagram for MR Detailed Description The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input frequency operation in excess of 1.0GHz. The 15 outputs are arranged into four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function. all outputs for normal operation. A high on MR resets all outputs to differential low condition. See Table 1. Input Termination Resistors Differential inputs CLK_ and CLK_ are biased to guarantee a known state (differential low) if the inputs are left open. CLK_ is internally pulled to VEE through a 75kΩ resistor. CLK_ is internally pulled to VCC and to VEE through 75kΩ resistors. Single-ended inputs FSEL_, MR, and CLK_SEL are internally pulled to VEE through a 75kΩ resistor. LVECL/LVPECL Operation Output levels are referenced to VCC and are LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to ground, the outputs are LVPECL. The outputs are LVECL when VCC is connected to ground and VEE is connected to a negative supply. When interfacing to differential LVPECL signals, the VCC range is 2.375V to 3.8V (VEE = 0), allowing high-performance clock distribution in systems with nominal 2.5V and 3.3V supplies. When interfacing to differential LVECL, the VEE range is -2.375V to -3.8V (VCC = 0). Control Inputs (FSEL_, CLK_SEL, MR) The MAX9322 provides four output banks: A, B, C, and D. Bank A consists of two differential output pairs. Bank B consists of three differential output pairs. Bank C consists of four differential output pairs. Bank D consists of six differential output pairs. FSEL_ selects the output clock frequency for a bank. A low on FSEL_ selects divide-by-1 frequency operation while a high on FSEL_ selects divide-by-2 operation. CLK_SEL selects CLK0 or CLK1 as the input signal. A low on CLK_SEL selects CLK0 while a high selects CLK1. Master reset (MR) enables all outputs. CLK_SEL and FSEL_ are asynchronous. Changes to the control inputs (CLK_SEL, FSEL_) or on power-up cause indeterminate output states requiring a MR assertion to resynchronize any divide-by-2 outputs (Figure 4). A low on MR activates Differential Clock Input The MAX9322 accepts two differential or single-ended clock inputs, CLK0/CLK0 and CLK1/CLK1. CLK_SEL selects between CLK0/CLK0 and CLK1/CLK1. A low on CLK_SEL selects CLK0/CLK0. A high on CLK_SEL selects CLK1/CLK1. See Table 1. Differential CLK_ inputs must be at least VBB ±95mV to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. The maximum magnitude of the differential signal applied to the differential clock input is the lower of (VCC - VEE) and 3.0V. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. Table 1. Function Table PIN FUNCTION LOW OR OPEN HIGH Divide-by-2 FSEL_ Divide-by-1 CLK_SEL CLK0 CLK1 MR* Active Reset *A master reset is required following power-up or changes to input functions to prevent indeterminant output states. _______________________________________________________________________________________ 9 MAX9322 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver Single-Ended Inputs and VBB The differential clock input can be configured to accept a single-ended input when operating at VCC - VEE = 3.0V to 3.8V. Connect VBB to the inverting or noninverting input of the differential input as a reference for single-ended operation. The differential CLK_ input is converted to a noninverting, single-ended input by connecting VBB to CLK_ and connecting the single-ended input signal to CLK. Similarly, an inverting configuration is obtained by connecting VBB to CLK_ and connecting the single-ended input to CLK_. The single-ended inputs FSEL_, CLK_SEL, and MR are internally referenced to VBB. All single-ended inputs (FSEL_, CLK_SEL, MR, and any CLK_ in single-ended mode) can be driven to VCC and VEE or with a singleended LVPECL/LVECL signal. The single-ended input must be at least VBB ±95mV to switch the outputs to the V OH and V OL levels specified in the DC Electrical Characteristics table. When using the VBB reference output, bypass VBB with a 0.01µF ceramic capacitor to VCC. Leave VBB open when not used. The VBB reference can source or sink 0.5mA. Use VBB as a reference for the same device only. Applications Information Supply Bypassing Bypass each VCC and VCCO to VEE with high-frequency surface-mount ceramic 0.01µF and 0.1µF capacitors in parallel as close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass VBB to VCC with a 0.01µF ceramic capacitor. Controlled-Impedance Traces Input and output trace characteristics affect the performance of the MAX9322. Connect input and output signals with 50Ω characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs with 50Ω to V CC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if QA0 is used as a single-ended output, terminate both QA0 and QA0. CLK_ MR Q_(÷1) Q_(÷2) Figure 4. Timing Diagram for MR Resynchronization 10 ______________________________________________________________________________________ LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver FSELA 75kΩ MAX9322 VEE CLK0 VCC 75kΩ 75kΩ BANK A VEE CLK0 ÷1 0 QA0 QA0 ÷2 1 QA1 QA1 75kΩ VEE CLK1 VCC 75kΩ 75kΩ VEE BANK B CLK1 0 QB0 QB0 QB1 QB1 75kΩ 1 VEE QB2 QB2 CLK_SEL 75kΩ VEE MR 75kΩ VEE FSELB BANK C 75kΩ 0 QC0 QC0 QC1 QC1 VEE 1 QC2 QC2 FSELC 75kΩ QC3 QC3 VEE QD0 QD0 BANK D 0 QD1 QD1 QD2 QD2 1 QD3 QD3 FSELD 75kΩ QD4 QD4 VEE VBB QD5 QD5 ______________________________________________________________________________________ 11 MAX9322 Functional Diagram LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver VCCO N.C. VCCO QB2 QB2 QB1 QB1 QB0 QB0 VCCO QA1 QA1 67 66 65 64 QA0 68 QA0 VCCO VCCO TOP VIEW N.C. MAX9322 Pin Configurations (continued) 63 62 61 60 59 58 57 56 55 54 53 52 N.C. 1 51 N.C. VCC 2 50 VCCO VCC 3 49 VCCO MR 4 48 QC0 FSELA 5 47 QC0 FSELB 6 46 QC1 CLK0 7 45 QC1 CLK0 8 CLK_SEL 9 44 QC2 MAX9322 43 QC2 CLK1 10 42 QC3 CLK1 11 41 QC3 VBB 12 40 VCCO FSELC 13 39 N.C. FSELD 14 38 N.C. VEE 15 37 VCCO VEE 16 36 VCCO N.C. 17 35 N.C. N.C. VCCO QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3 QD4 QD4 QD5 QD5 VCCO N.C. VCCO 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 QFN* THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO VEE FOR PROPER THERMAL AND ELECTRICAL OPERATION OF THE MAX9322. Chip Information TRANSISTOR COUNT: 2063 PROCESS: Bipolar 12 ______________________________________________________________________________________ LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver DIM A A1 A2 b c D D1 E E1 e L e D1 4 E1 52 SEE NOTE 2 E b E1 4 MIN 0.05 0.95 0.22 0.09 11.80 NOM 0.10 1.00 0.32 12.00 10.00 BSC 12.00 11.80 10.00 BSC 0.65 BSC 0.60 0.45 52L TQFP.EPS D D1 MAX 1.20 0.15 1.05 0.38 0.20 12.20 12.20 0.75 1 TOP VIEW 0 MIN. 0.25 A2 SEE DETAIL "A" GAGE PLANE A SEATING PLANE L A1 0-7 1.00 REF c DETAIL A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 52L TQFP, 10x10x1.0 MM APPROVAL DOCUMENT CONTROL NO. 21-0146 REV. A 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9322 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)