19-2223; Rev 1; 1/02 Quad Differential LVECL/LVPECL Buffer/Receivers These devices operate with a supply voltage of (VCC VEE) = 2.375V to 5.5V, and are specified for operation from -40°C to +85°C. These devices are offered in space-saving 32-pin 5mm ✕ 5mm TQFP and 32-lead 5mm ✕ 5mm QFN packages. Applications Features ♦ 400mV Differential Output at 3.0GHz Data Rate ♦ 335ps Propagation Delay in Asynchronous Mode ♦ 8ps Channel-to-Channel Skew in Synchronous Mode ♦ Integrated 50Ω Outputs (MAX9402/MAX9405) ♦ Integrated 100Ω Inputs (MAX9403/MAX9405) ♦ Synchronous/Asynchronous Operation Ordering Information TEMP RANGE PART PINDATA OUTPUT PACKAGE INPUT MAX9400EHJ -40°C to +85°C 32 TQFP Open Open MAX9400EGJ* -40°C to +85°C 32 QFN Open Open MAX9402EHJ -40°C to +85°C 32 TQFP Open 50Ω MAX9402EGJ* -40°C to +85°C 32 QFN Open 50Ω MAX9403EHJ -40°C to +85°C 32 TQFP 100Ω Open MAX9403EGJ* -40°C to +85°C 32 QFN 100Ω Open MAX9405EHJ -40°C to +85°C 32 TQFP 100Ω 50Ω MAX9405EGJ* -40°C to +85°C 32 QFN 100Ω 50Ω *Future product—contact factory for availability. Data and Clock Driver and Buffer Pin Configurations VCC OUT0 OUT0 VEE IN1 IN1 TOP VIEW Base Station IN0 DSLAM Backplane IN0 Central Office Backplane Clock Distribution 32 31 30 29 28 27 26 25 ATE 1 24 VCC SEL 2 23 OUT1 SEL 3 22 OUT1 CLK 4 21 VEE MAX9400 MAX9402 MAX9403 MAX9405 20 VEE CLK 5 EN 6 EN 7 18 OUT2 VCC 8 17 VCC 10 11 12 13 14 15 16 IN3 OUT3 OUT3 VEE IN2 IN2 IN3 9 19 OUT2 VCC Functional Diagram appears at end of data sheet. VCC TQFP (5mm x 5mm) Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9400/MAX9402/MAX9403/MAX9405 General Description The MAX9400/MAX9402/MAX9403/MAX9405 are extremely fast, low-skew quad LVECL/ECL or LVPECL/ PECL buffer/receivers designed for high-speed data and clock driver applications. These devices feature an ultra-low propagation delay of 335ps and channel-tochannel skew of 16ps in asynchronous mode with 86mA supply current. The four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. A variety of input and output terminations are offered for maximum design flexibility. The MAX9400 has open inputs and open emitter outputs. The MAX9402 has open inputs and 50Ω series outputs. The MAX9403 has 100Ω differential input impedance and open emitter outputs. The MAX9405 has 100Ω differential input impedance and 50Ω series outputs. MAX9400/MAX9402/MAX9403/MAX9405 Quad Differential LVECL/LVPECL Buffer/Receivers ABSOLUTE MAXIMUM RATINGS VCC to VEE ................................................................-0.3V to +6V Inputs to VEE...............................................-0.3V to (VCC + 0.3V) Differential Input Voltage .......................................................±3V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Power Dissipation (TA = +70°C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/°C above +70°C) .................................761mW 32-Lead 5mm x 5mm QFN (derate 21.3mW/°C above +70°C) ...................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin 5mm x 5mm TQFP ........................................+105°C/W 32-Lead 5mm x 5mm QFN ........................................+47°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 32-Pin 5mm x 5mm TQFP .........................................+73°C/W Junction-to-Case Thermal Resistance 32-Pin 5mm x 5mm TQFP .........................................+25°C/W 32-Lead 5mm x 5mm QFN .........................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (Inputs and Outputs) ........................2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 2.375V to 5.5V, MAX9400/MAX9403 outputs terminated with 50Ω ±1% to VCC - 2.0V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage VIHD Figure 1 VEE + 1.4 VCC V Differential Input Low Voltage VILD Figure 1 VEE VCC 0.2 V Differential Input Voltage VID Figure 1 VCC - VEE < +3.0V 0.2 VCC VEE Input Current Differential Input Resistance IIH, IIL RIN VCC - VEE ≥ +3.0V 0.2 3.0 MAX9400/ MAX9402 EN, EN, SEL, SEL , IN_, IN_, CLK, or CLK = VIHD or VILD -10 25 MAX9403/ MAX9405 EN, EN, SEL, SEL, CLK, or CLK = VIHD or VILD -10 25 MAX9403/MAX9405 86 114 V µA Ω OUTPUTS (OUT_, OUT_) Differential Output Voltage VOH VOL Figure 1 600 660 Output Common-Mode Voltage VOCM Figure 1 VCC 1.5 VCC 1.25 VCC 1.1 V Internal Current Source ISINK MAX9402/MAX9405, Figure 2 6.5 8.3 10 mA Output Impedance ROUT MAX9402/MAX9405, Figure 2 40 50 60 Ω MAX9402/MAX9405 150 180 MAX9400/MAX9403 86 118 mV POWER SUPPLY Supply Current 2 IEE _______________________________________________________________________________________ mA Quad Differential LVECL/LVPECL Buffer/Receivers (VCC - VEE = 2.375V to 5.5V, outputs terminated with 50Ω ±1% to VCC - 2.0V, enabled, CLK = 3.2GHz, fIN = 1.6GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.2V, VIHD - VILD = 0.2V to smaller of |VCC - VEE| or 3V, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 0.9V, VILD = VCC 1.7V, TA = +25°C, unless otherwise noted.) (Notes 1, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 237 335 437 237 335 437 397 475 597 397 475 597 UNITS IN-to-OUT Differential Propagation Delay tPLH1 tPHL1 MAX9400/MAX9403 CLK-to-OUT Differential Propagation Delay tPLH2 tPHL2 MAX9400/MAX9403 IN-to-OUT Channel-to-Channel Skew (Note 5) tSKD1 SEL = high 16 80 ps CLK-to-OUT Channel-toChannel Skew (Note 5) tSKD2 SEL = low 8 55 ps MAX9402/MAX9405 MAX9402/MAX9405 SEL = high, Figure 3 SEL = low, Figure 4 ps ps Maximum Clock Frequency fCLK(MAX) VOH - VOL ≥ 500mV, SEL = low 3.0 GHz Maximum Data Frequency fIN(MAX) VOH - VOL ≥ 400mV, SEL = high 2 GHZ Added Random Jitter (Note 6) Added Deterministic Jitter (Note 6) tRJ tDJ SEL = low, fCLK = 3.0GHz clock, fIN = 1.5GHz 0.64 1.3 SEL = high, fIN = 2GHz 0.74 1.5 SEL = low, fCLK = 3.0GHz, IN_ = 3.0Gbps 223 - 1 PRBS pattern 17 30 SEL = high, IN = 2.0Gbps 223 - 1 PRBS pattern 40 55 ps(RMS) ps(P-P) IN-to-CLK Setup Time tS Figure 4 80 CLK-to-IN Hold Time tH Figure 4 80 Output Rise Time tR Figure 3 80 120 ps Output Fall Time tF Figure 3 80 120 ps 0.2 1 ps/°C Propagation Delay Temperature Coefficient ∆tPD/ ∆T ps ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 6: Device jitter added to the input signal. _______________________________________________________________________________________ 3 MAX9400/MAX9402/MAX9403/MAX9405 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC - VEE = 3.3V, MAX9400, outputs terminated with 50Ω ±1% to VCC - 2.0V, enabled, SEL = high, CLK = 2.0GHz, fIN = 1.0GHz, input transition time = 125ps (20% to 80%), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, TA = +25°C, unless otherwise noted.) OUTPUT AMPLITUDE (VOH - VOL) vs. IN_ FREQUENCY 85 80 75 800 OUTPUT RISE/FALL TIME (ps) OUTPUT AMPLITUDE (mV) 90 100 MAX9400 toc02 1000 MAX9400 toc01 95 OUTPUT RISE/FALL vs. TEMPERATURE 600 400 200 70 0 -40 -15 10 35 60 85 90 tR 80 tF 70 60 0 500 TEMPERATURE (°C) 1000 1500 2000 2500 3000 3500 -40 -15 IN_ FREQUENCY (MHz) PROPAGATION DELAY (ps) 350 345 340 tPLH 335 tPHL MAX9400 toc05 520 MAX9400 toc04 355 10 500 tPLH2 480 tPHL2 460 330 325 440 -40 -15 10 35 TEMPERATURE (°C) 4 60 85 -40 35 TEMPERATURE (°C) CLK-TO-OUT PROPAGATION DELAY vs. TEMPERATURE IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE PROPAGATION DELAY (ps) MAX9400 toc03 SUPPLY CURRENT (IEE) vs. TEMPERATURE SUPPLY CURRENT (mA) MAX9400/MAX9402/MAX9403/MAX9405 Quad Differential LVECL/LVPECL Buffer/Receivers -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Quad Differential LVECL/LVPECL Buffer/Receivers PIN NAME FUNCTION 1, 8,11, 17, 24, 30 VCC Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 SEL Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronous mode. 3 SEL Inverting Differential Select Input 4 CLK Noninverting Differential Clock Input 5 CLK Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = low. 6 EN Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the outputs. Setting EN = low and EN = high (differential low) drives outputs low. 7 EN Inverting Differential Output Enable Input 9 IN3 Noninverting Differential Input 3 10 IN3 Inverting Differential Input 3 12 OUT3 Inverting Differential Output 3 13 OUT3 Noninverting Differential Output 3 14, 20, 21, 27 VEE Negative Supply Voltage 15 IN2 Noninverting Differential Input 2 16 IN2 Inverting Differential Input 2 18 OUT2 Inverting Differential Output 2 19 OUT2 Noninverting Differential Output 2 22 OUT1 Noninverting Differential Output 1 23 OUT1 Inverting Differential Output 1 25 IN1 Inverting Differential Input 1 26 IN1 Noninverting Differential Input 1 28 OUT0 Noninverting Differential Output 0 29 OUT0 Inverting Differential Output 0 31 IN0 Inverting Differential Input 0 32 IN0 Noninverting Differential Input 0 — EP Exposed Paddle (MAX940_EGJ only). Connected to VEE internally. See package dimensions. _______________________________________________________________________________________ 5 MAX9400/MAX9402/MAX9403/MAX9405 Pin Description MAX9400/MAX9402/MAX9403/MAX9405 Quad Differential LVECL/LVPECL Buffer/Receivers Detailed Description The MAX9400/MAX9402/MAX9403/MAX9405 are extremely fast, low-skew quad LVECL/ECL or LVPECL/ PECL buffer/receivers designed for high-speed data and clock driver applications. The devices feature an ultra-low propagation delay of 335ps and channel-tochannel skew of 16ps in asynchronous mode with an 86mA supply current. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. A variety of input and output terminations are offered for maximum design flexibility. The MAX9400 has open inputs and open-emitter outputs. The MAX9402 has open inputs and 50Ω series outputs. The MAX9403 has 100Ω differential input impedance and open-emitter outputs. The MAX9405 has 100Ω differential input impedance and 50Ω series outputs. Supply Voltage The MAX9400/MAX9402/MAX9403/MAX9405 are designed for operation with a single supply. Using a single negative supply of VEE = -2.375V to -5.5V (VCC = ground) yields LVECL/ECL-compatible input and output levels. Using a single positive supply of VCC = 2.375V to 5.5V (VEE = ground) yields LVPECL/PECL input and output levels. Data Inputs The MAX9400/MAX9402 have open inputs and require external termination. The MAX9403/MAX9405 have integrated 100Ω differential input termination resistors from IN_ to IN_, reducing external component count. Outputs The MAX9402/MAX9405 have internal 50Ω series output termination resistors and 8mA internal pulldown current sources. Using integrated resistors reduces external component count. The MAX9400/MAX9403 have open-emitter outputs. An external termination is required. See the Output Termination section. Enable Setting EN = high and EN = low enables the device. Setting EN = low and EN = high forces the outputs to a differential low, and all changes on CLK, SEL, and IN_ are ignored. Asynchronous Operation Setting SEL = high and SEL = low enables the four channels to operate independently as buffer/receivers. 6 The CLK signal is ignored in this mode. In asynchronous mode, the CLK signal should be set to either a logic low or high state to minimize noise coupling. Synchronous Operation Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode. In this mode, buffered inputs are clocked into flip-flops simultaneously on the rising edge of the differential clock input (CLK and CLK). Differential Signal Input Limit The maximum signal magnitude of the differential inputs is VCC - VEE or 3V, whichever is less. Applications Information Input Bias Unused inputs should be biased or driven as shown in Figure 5. This avoids noise coupling that might cause toggling at the unused outputs. Output Termination Terminate open-emitter outputs (MAX9400/MAX9403) through 50Ω to VCC - 2V or use an equivalent Thevenin termination. Terminate both outputs and use identical termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_. Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device’s total thermal limits should be observed. Power-Supply Bypassing Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors as close to the device as possible with the 0.01µF capacitor closest to the device pins. Use multiple bypass vias for connection to minimize inductance. Circuit Board Traces Input and output trace characteristics affect the performance of the MAX9400/MAX9402/MAX9403/MAX9405. Connect each of the inputs and outputs to a 50Ω characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω char- _______________________________________________________________________________________ Quad Differential LVECL/LVPECL Buffer/Receivers VCC Chip Information TRANSISTOR COUNT: 713 PROCESS: Bipolar VIHD (MAX) VID VCC VID = 0V VOH VILD (MAX) VOH - VOL VOCM VIHD (MIN) VID VOL VID = 0V VEE VEE VILD (MIN) INPUT VOLTAGE DEFINITION OUTPUT VOLTAGE DEFINITION Figure 1. Input and Output Voltage Definitions IN_ IN_ 100kΩ IN_ IN_ MAX9420/MAX9421 MAX9422/MAX9423 VCC VCC 50Ω OUT_ 50Ω OUT_ OUT_ OUT_ 8mA 8mA VEE MAX9420/MAX9422 MAX9421/MAX9423 Figure 2. Input and Output Configurations _______________________________________________________________________________________ 7 MAX9400/MAX9402/MAX9403/MAX9405 acteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. MAX9400/MAX9402/MAX9403/MAX9405 Quad Differential LVECL/LVPECL Buffer/Receivers IN_ VIHD - VILD IN_ tPLH1 tPHL1 OUT_ VOH - VOL OUT_ VOH - VOL 80% OUT_ - OUT_ VOH - VOL 20% DIFFERENTIAL OUTPUT WAVEFORM 80% 20% tR tF SEL = HIGH EN = HIGH Figure 3. IN-to-OUT Propagation Delay and Transition Timing Diagram CLK VIHD - VILD CLK tH tS tH IN_ VIHD - VILD IN_ tPLH2 tPHL2 OUT_ VIHD - VILD OUT_ SEL = LOW EN = HIGH Figure 4. CLK-to-OUT Propagation Delay Timing Diagram 8 _______________________________________________________________________________________ Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405 VCC VCC IN_ IN_ OUT_ OUT_ 100Ω 100Ω OUT_ IN_ OUT_ IN_ 1/4 MAX9400/MAX9402 1kΩ 1kΩ VEE 1/4 MAX9403/MAX9405 VEE Figure 5. Input Bias Circuits for Unused Inputs Pin Configurations (continued) IN0 IN0 VCC OUT0 OUT0 VEE IN1 IN1 32 31 30 29 28 27 26 25 TOP VIEW * * VCC 1 24 VCC SEL 2 23 OUT1 SEL 3 22 OUT1 21 VEE 20 VEE MAX9400 MAX9402 MAX9403 MAX9405 CLK 4 CLK 5 EN 6 19 OUT2 EN 7 18 OUT2 VCC 8 17 VCC 12 13 14 15 16 OUT3 VEE IN2 IN2 11 VCC OUT3 9 10 IN3 * IN3 *EXPOSED PADDLE * QFN-EP* *EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE. _______________________________________________________________________________________ 9 Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405 Functional Diagram IN0 IN0 1 D Q D Q 0 OUT0 OUT0 CK CK IN1 IN1 1 D Q D Q 0 OUT1 OUT1 CK CK IN2 IN2 1 D Q D Q 0 OUT2 OUT2 CK CK IN3 IN3 1 D Q D Q 0 CK CK CLK CLK SEL SEL EN EN 10 ______________________________________________________________________________________ OUT3 OUT3 Quad Differential LVECL/LVPECL Buffer/Receivers 32L TQFP, 5x5x01.0.EPS ______________________________________________________________________________________ 11 MAX9400/MAX9402/MAX9403/MAX9405 Package Information Quad Differential LVECL/LVPECL Buffer/Receivers MAX9400/MAX9402/MAX9403/MAX9405 Package Information (continued) 12 ______________________________________________________________________________________ Quad Differential LVECL/LVPECL Buffer/Receivers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9400/MAX9402/MAX9403/MAX9405 Package Information (continued) This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.