PI74LVTCH16374 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs Product Features Product Description · Advanced low power CMOS design for 2.7V to 3.6V Vcc operation Pericom Semiconductor’s PI74LVTC series of logic circuits are produced using Pericom’s advanced CMOS technology, achieving industry leading speed. · Supports 5V input/output tolerance in mixed signal mode operation The PI74LVTCH16374 is a 16-bit edge-triggered D-type Flip-Flop designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. This D-type Flip-Flop is particularly suitable for implementing buffers registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the Clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data D inputs. · Function compatible with LVT family of products · Balanced ±24mA output drive · Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25°C · Ioff and Power Up/Down 3-State support live insertion · Bus Hold on data inputs eliminates the need for external pull-up/down resistors A buffered output enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high impedance state. · Latch-up performance exceeds 200mA Per JESD78 · ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) · Packages(Pb-free available): - 48-pin 240-mil wide plastic TSSOP (A48) - 48-pin 300-mil wide plastic SSOP (V48) · Industrial Temperature: -40°C to +85°C The PI74LVTCH16374 has "Bus Hold" which retains the data input's last valid logic state whenever the data input goes to highimpedance, preventing "floating" inputs and eliminating the need for pull-up/down resistors. Logic Block Diagram 1OE 1CLK 1 48 When Vcc is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above 1.5V, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. C1 2 1D1 47 1Q1 1D The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the highimpedance state during power up or power down, preventing driver conflict. To Seven Other Channels 2OE 2CLK 24 25 C1 13 2D1 36 2Q1 1D To Seven Other Channels 1 PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings Product Pin Description (Above which the useful life may be impaired. For user guidelines, not tested.) Pin Name Supply voltage range, VCC .............................. –0.5V to +6.5V Input voltage range, VI(1) ................................. –0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ –0.5V to +6.5V Voltage range applied to any output in the active state, VO(1) ,(2) .................................. –0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ..................................... –50mA Output clamp current, IOK (VO <0) ............................... –50mA Continous Output Current IO ....................................... ±50mA Continous Current through each VCC or GND pin .............. ±100mA Package thermal impedance, θJA(3): package A ......... 104°C/W package V ........... 94°C/W Storage Temperature range, Tstg ..................... –65°C to 150°C 1. Input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. Truth Table(4) Outputs xOE xCLK xDx xQx L ↑ H H L ↑ L L L H or L X Q0 H X X Z xOE Output Enable Input (Active LOW) xCLK Clock Input (Active HIGH) xDx Data Inputs xQx 3- State Outputs GND Ground VC C Power Product Pin Configuration Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Inputs De s cription Notes: 4. H = High Signal Level L = Low Signal Level Q 0 = Previous xQx After the last LOW-to-HIGH Transition of CLK Input. X = Don’t Care or Irrelevant Z = High Impedance 2 1OE 1 48 1CLK 1Q1 2 47 1D1 1Q2 3 46 1D2 GND 4 45 GND 1Q3 5 44 1D3 1Q4 VCC 6 43 7 42 1D4 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 1Q7 11 48-Pin A, V 39 GND 38 1D7 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 VCC 2Q5 18 31 19 30 VCC 2D5 2Q6 20 29 2D6 GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 2OE 24 25 2CLK PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions(5) VCC Supply Voltage M in. M a x. Units Operating 2.7 3.6 V 2.0 VIH High- level Input Voltage VCC = 2.7V to 3.6V VIL Low- level Input Voltage VCC = 2.7V to 3.6V VI Input Voltage VO Output Voltage IOH High- level output current IOL Low- level output current 0.8 0 5.5 High or Low State 0 VCC 3- State 0 5.5 VCC = 2.7V –12 VCC = 3.0V to 3.6V – 24 VCC = 2.7V 12 VCC = 3.0V to 3.6V 24 ∆t/∆v Input transition rise or fall rate mA 10 ∆t/∆VCC Power- up ramp rate 150 TA – 40 Operating free- air temperature ns/V µs/V 85 °C Notes: 5.All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C) Parame te rs VIK VO H De s cription Clamp Diode Voltage Output High Voltage Te s t Conditions VC C = 2.7V II = –18mA VC C = 2.7V to 3.6V IO H = –100µA VC C –0.2V VC C = 2.7V IO H = –12mA 2.2 IO H = –12mA 2.4 IO H = –24mA 2.2 VC C = 3V VO L Output Low Voltage Units –1.2V V IO L = 100µA 0 .2 VC C = 2.7V IO L = 12mA 0.4 IO L = 12mA 0.4 IO L = 24mA 0.55 VI = 0V to5.5V ±5 Control Inputs VC C = 0V to 3.6V Input Leakage Current M a x. VC C = 2.7V to 3.6V VC C = 3V II M in. VI = 5.5V Data Inputs VC C = 3.6V VI = VC C ±5 VI = GND II(HO LD) Data Input Hold Current VC C = 3V VI = 0.8V 75 VI = 2V –75 VC C = 3.6V(6) VI = 0 to 3.6V ± 500 IO FF Power Off Output Leakage Current VC C = 0V VI or VO = 0V to 5.5V ±5 IO Z 3- State Output Leakage Current VC C = 2.7V to 3.6V VO = 0V to 5.5V ±5 IO ZPU Power- Up 3- State Current VC C = 0V to 1.5V VO = 0.5V to 5.5V, OE = don't care ±5 IO ZPD Power- Down 3- State Current VC C = 1.5V to 0V VO = 0.5V to 5.5V, OE = don't care ±5 IC C Quiescent Power Supply Current VC C = 2.7V to 3.6V ∆IC C Increase in IC C VC C = 3V to 3.6V VI = VC C or GND 3.6V ≤ VI ≤ 5.5V IO = 0 One input at VC C - 0.6V(7) Other inputs at VC C or GND µA 100 200 Notes: 6. This is the maximum bus-hold dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 7. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Capacitance Parame te rs De s cription Typ.(8) Te s t Conditions CI Input Capacitance VCC = 3.3V, VI = VCC or GND 3.7 CO Output Capacitance VCC = 3.3V, VO = VCC or GND 7 C PD Power Dissipation Capacitance (9) VCC = 3.3V, VI = 0 or VCC, f =10 MHz Units pF 14 Notes: 8. All typical values are measured at VCC = 3.3V, TA = 25°C. 9. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current con sumption (ICCD) at no output loading and operating at 50% duty cycle, CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN)+(ICCstatic). Timing Requirements Over Operating Range Parame te rs VCC = 3.3V ±0.3V De s cription M in. fmax VCC = 2.7V M a x. M in. 150 150 tw Pulse Duration, CLK HIGH or LOW 3 3 tsu Setup Time, Data before CLK↑ 1.8 2 th Hold Time, Data after CLK↑ 0.8 0.6 Units M a x. MHz ns Switching Characteristics Over Operating Range Parame te rs tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) D e s cription From (Input) To (Output) Propagation Delay CLK Q O utput Enable Time OE Q O utput Disable Time OE Q VCC = 3.3V ±0.3V VCC = 2.7V CL = 50pF, RL = 500Ohm CL = 50pF, RL = 500Ohm M in. Typ. (10) M ax. 1.0 3.0 4.2 4.7 1.0 2.9 4.2 4.7 1.0 3.0 4.5 5.0 1.0 3.1 4.7 5.2 1. 0 2.6 4.2 4.7 1.0 2.5 4.4 4.9 O utput to O utput Skew(11) M in. Units M a x. ns 0.5 Notes: 10. All typical values are measured at VCC = 3.3V, TA = 25°C 11. Skew between any two outputs, switching in the same direction. 5 PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.7V and 3.3V ±0.3V 500Ω From Output Under Test CL = 50pF S1 2xVCC Open GND 500Ω (See Note A) Te s t S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Load Circuit 2.7V Timing Input 1.5V 0V tsu tW th VCC 2.7V Data Input VCC/2 Input 1.5V 1.5V VCC/2 0V 0V Voltage Waveforms Setup and Hold Times Voltage Waveforms Pulse Duration Output Control (Low Level Enabling) 2.7V Input 1.5V Output Waveform 1 S1 at 6V (see Note B) 1.5V 0V tPHL tPLH 1.5V tPZL 1.5V Output Waveform 2 S1 at GND (see Note B) VOL Voltage Waveforms Propagation Delay Times 1.5V 0V tPLZ 3V 1.5V tPZH VOH Output 2.7V 1.5V VOL+0.3V tPHZ 1.5V VOH -0.3V VOL VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. D. The outputs are measured one at a time with one transition per measurement. 6 PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-pin TSSOP (A) Package 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .0197 BSC 0.50 .002 .006 0.05 0.15 .007 .010 0.17 0.27 0.45 .018 0.75 .030 .319 BSC 8.1 48-pin SSOP (V) Package 48 .291 .299 7.39 7.59 .395 .420 10.03 10.67 Gauge Plane .010 0.25 .02 0.51 .04 1.01 1 .620 .630 15.75 16.00 .015 0.381 x 45˚ .025 0.635 .008 0.20 Nom. .110 2.79 Max .025 BSC 0.635 .008 0.20 .0135 0.34 0-8˚ .008 0.20 .016 0.40 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 7 PS 8654A 05/19/03 PI74LVTCH16374 3.3V 16-Bit Edge Triggered D-Type Flip-Flop with 3-State Output 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Orde ring Code Package Code Package De s cription PI74LVTCH16374A A 48- pin, 240- mil wide plastic TSSOP PI74LVTCH16374AE A 48- pin, 240- mil wide plastic TSSOP PI74LVTCH16374V V 48- pin, 300- mil wide plastic SSOP PI74LVTCH16374VE V 48- pin, 300- mil wide plastic SSOP Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php 2. X = Tape/Reel Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS 8654A 05/19/03