ETC PI74ALVCH16820V

PI74ALVCH16820
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3.3V 10-Bit Flip-Flop with Dual Outputs
and 3-State Outputs
Product Features
Product Description
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•
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Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
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PI74ALVCH16820 is designed for low-voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce) < 0.8V
at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot) < 2.0V
at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-state
eliminating the need for external pullup resistors
Industrial operation: –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
The PI74ALVCH16820, a 10-bit flip-flop designed for 2.3V to 3.3V
VCC operation, features edge-triggered D-type flip-flops. On the
positive transition of clock (CLK) input, the device provides true
data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a highimpedance state. In high-impedance state, outputs neither load nor
drive the bus lines significantly. The high-impedance state and
increased drive are able to drive bus lines without interface or pullup
components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor whose
minimum value is determined by the current sinking capability of the
driver.
To prevent “floating” inputs and to eliminate the need for pullup/
down resistors, the PI74ALVCH16820 has “Bus Hold” which retains
the data input’s last state whenever the data input goes to highimpedance .
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1OE
2OE
CLK
D1
1
28
2
56
55
C1
1D
3
1Q1
1Q2
TO 9 OTHER CHANNELS
1
PS8126A
05/07/01
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with
Dual and 3-State Outputs
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Maximum Ratings
Product Pin Description
Pin Name
(Above which the useful life may be impaired.
For user guidelines, not tested.)
D e s cription
OE
O utput Enable Input (Active LO W)
CLK
Clock Input (Active HIGH)
Dx
Data Inputs
Qx
3- State O utputs
GND
Ground
VCC
Power
Storage Temperature .................................... –65°C to +150°C
Ambient Temperature with Power Applied ... –40°C to +85°C
Input Voltage Range, VIN .................................. –0.5V to VCC+0.5V
Output Voltage Range, VOUT .......................... –0.5V to VCC+0.5V
DC Input Voltage ............................................. –0.5V to +5.0V
DC Output Current ...................................................... 100mA
Power Dissipation ........................................................... 1.0W
Truth Table(1)
Inputs
OEn
CLK
D
Qn
L
—
H
H
L
—
L
L
L
L
X
Q0
H
X
X
Z
Note:
1. H
L
X
Z
↑
n
=
=
=
=
=
=
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Outputs
Product Pin Configuration
High Signal Level
Low Signal Level
Irrelevant
High Impedance
LOW-to-HIGH Transition
1,2
1OE
1Q1
1Q2
GND
2Q1
2Q2
VCC
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
VCC
9Q1
9Q2
GND
10Q1
10Q2
2OE
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin
A, V
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
D1
NC
GND
D2
NC
VCC
D3
NC
D4
GND
NC
D5
NC
D6
NC
D7
GND
NC
D8
NC
VCC
D9
NC
GND
D10
NC
NC
PS8126A
05/07/01
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with
Dual and 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs De s cription
VCC
Supply Voltage
VIH(3)
Input HIGH Voltage
VIL(3)
VIN
(3)
VOUT(3)
Input LOW Voltage
Te s t Conditions (1)
M in.
2.3
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
VOL
IOH(3)
IOL(3)
IIN
IIN (HOLD)
M ax.
0.7
VCC = 2.7V to 3.6V
0.8
Input Voltage
0
VCC
Output Voltage
0
VCC
Output
HIGH
Voltage
Output
LOW
Voltage
VCC - 0.2
VIH = 1.7V, IOH = –6mA, VCC = 2.3V
2.0
VIH = 1.7V, IOH = –12mA, VCC = 2.3V
1.7
VIH = 2.0V, IOH = –12mA, VCC = 2.7V
2.2
VIH = 2.0V, IOH = –12mA, VCC = 3.0V
2.4
VIH = 2.0V, IOH = –24mA, VCC = 3.0V
2.0
V
IOL = 100µA, VIL = Min. to Max.
0.2
VIL = 0.7V, IOL = 6mA, VCC = 2.3V
0.4
VIL = 0.7V, IOL = 12mA, VCC = 2.3V
0.7
VIL = 0.8V, IOL = 12mA, VCC = 2.7V
0.4
VIL = 0.8V, IOL = 24mA, VCC = 3.0V
0.55
Output
HIGH
Current
VCC = 2.3V
–12
VCC = 2.7V
–12
VCC = 3.0V
–24
Output
LOW
Current
VCC = 2.3V
12
VCC = 2.7V
24
VCC = 3.0V
24
Input Current
VIN = VCC or GND, VCC = 3.6V
±5
Input
Hold
Current
VIN = 0.7V, VCC = 2.3V
45
VIN = 1.7V, VCC = 2.3V
–45
VIN = 0.8V, VCC = 3.0V
75
VIN = 2.0V, VCC = 3.0V
–75
VIN = 0 to 3.6V, VCC = 3.6V
±500
IOZ
Output Current
(3- State Outputs)
VOUT = VCC or GND, VCC = 3.6V
±10
ICC
Supply Current
VCC = 3.6V, IOUT = 0µA,
VIN = GND or VCC
40
∆ICC
Supply Current per VCC = 3.0V to 3.6V
Input @ TTL HIGH One Input at VCC - 0.6V
Other Inputs at VCC or GND
CI
CO
Control Inputs
Data Inputs
Outputs
Units
3.6
VCC = 2.3V to 2.7V
IOH = –100µA, VCC = Min. to Max.
VOH
Typ.(2)
mA
µA
750
VIN = VCC or GND, VCC = 3.3V
3.5
6
pF
7
VO = VCC or GND, VCC = 3.3V
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
3
PS8126A
05/07/01
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with
Dual and 3-State Outputs
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Timing Requirements over Operating Range
PI74ALVCH16820
Parame te rs
fCLOCK
De s cription
VCC = 2.5 V ±0.2 V
VCC = 2.7 V
VCC = 3.3 V ±0.3 V
M in.
M ax.
M in.
M ax.
M in.
M ax.
0
150
0
150
0
150
Clock Frequency
tW
Pulse duration CLK high or low
3.3
3.3
3.3
tSU
Setup time data before CLK↑
1.7
1.8
1.4
tH
Hold time data after CLK↑
1.1
1.1
1.0
∆t/∆v(3)
Input Transition Rise or Fall
Units
MHz
ns
0
10
ns/V
Switching Characteristics over Operating Range(1)
Parame te rs
From
(Input)
To
(Output)
fMAX
VCC = 2.5V ± 0.2V
M in.(2)
M ax.
150
VCC = 2.7V
M in.(2)
M ax.
150
VCC = 3.3V ± 0.3V
M in.(2)
M ax.
Units
150
MHz
tPD
CLK
Q
1.0
6.5
5.5
1.0
4.8
ns
tEN
OE
Q
1.0
6.9
6.1
1.0
5.0
ns
tDIS
OE
Q
1.3
5.9
5.0
1.0
4.5
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Recommended operating condition.
Operating Characteristics, TA = 25°C
Parame te rs
CPD Power Dissipation
Capacitance
Te s t Conditions
O utputs Enabled
O utputs Disabled
CL = 50pF, f = 10 MHz
VCC = 2.5V ±0.2V
VCC = 3.3V ±0.3V
Typical
Typical
60
63
38
46
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
4
PS8126A
05/07/01