ETC ALP-PXB4350

ICs for Communications
ATM Layer Processor
ALP
PXB 4350 E Version 1.1
Data Sheet 08.2000
DS 1
3;%(
5HYLVLRQ+LVWRU\&XUUHQW9HUVLRQ
Previous Version: Preliminary Data Sheet 09.98 (DS 2)
Page
Page
Subjects (major changes since last revision)
(in previous (in current
Version)
Version)
The Data Sheet has been reorganized.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.Infineon.com.
IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI®, ARCOFI® , ARCOFI®-BA,
ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, ISAC®-P, ISAC®-P TE, IDEC®,
SICAT®, OCTAT®-P, QUAT®-S are registered trademarks of Infineon Technologies AG.
MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, DigiTape™ are trademarks of Infineon Technologies AG.
All other brand or product names, Hardware or Software names are trademarks or registered trademarks of their
respective companies or organizations.
(GLWLRQ
This edition was realized using the software system FrameMaker.
3XEOLVKHGE\ ,QILQHRQ7HFKQRORJLHV$*
6&
%DODQVWUD‰H
0QFKHQ
© Infineon Technologies AG 2000.
All Rights Reserved.
$WWHQWLRQSOHDVH
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
3DFNLQJ
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
&RPSRQHQWVXVHGLQOLIHVXSSRUWGHYLFHVRUV\VWHPVPXVWEHH[SUHVVO\DXWKRUL]HGIRUVXFKSXUSRVH
Critical components1 of Infineon Technologies AG, may only be used in life-support devices or systems2 with the
express written approval of Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device
or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
3;%(
7DEOHRI&RQWHQWV
3DJH
1.1
1.2
1.3
1.4
2YHUYLHZ Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.3.1
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.3
2.4.4
2.5
2.5.1
2.6
2.7
2.8
2.9
)XQFWLRQDO'HVFULSWLRQ Core Functions and Interfaces of the ALP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Functional Description of user data flow in up- and downstream direction . . . . 28
Address Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Internal Address Reduction Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
External Address Reduction Circuit (CAME device) . . . . . . . . . . . . . . . . . . . . . 33
Processing of the Header Structure by the ALP . . . . . . . . . . . . . . . . . . . . . . . . . 36
House Keeping (HK) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Policing in Upstream Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
The Leaky Bucket (LB) Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General Configuration of the POLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Operation Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operation Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operation Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operation Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Calculation of POLU Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Example for POLU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Traffic Measurement Unit for up- and downstream direction . . . . . . . . . . . . . . . 46
Traffic Measurement data transfer via DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
UTOPIA Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
OAM Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Programmable Cell Filter Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Configuration of ALP via Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.1.7
3.3.1.8
3.3.1.9
3.3.1.10
3.3.1.11
5HJLVWHU'HVFULSWLRQ Overview of the ALP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Transfer Register General Mapping to Dwords . . . . . . . . . . . . . . . . . . . . . . . . . 69
Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Write Transfer Registers (WDR0L/WDR0H..WDRAL/WDRAH) . . . . . . . . . . . . . 69
Read Transfer Registers (RDR0L/RDR0H..RDRAL/RDRAH) . . . . . . . . . . . . . . 70
Mapping of Transfer Register to Internal / External RAMs . . . . . . . . . . . . . . . . . 71
Policing RAM (POLURAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Policing RAM : Dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Policing RAM : Dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Policing RAM : Dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Policing RAM : Dword3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Policing RAM : Dword4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Policing RAM : Dword5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Policing RAM : Dword6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Policing RAM : Dword7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Policing RAM : Dword8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Policing RAM : Dword9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Policing RAM: Dword10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Sheet
3
08.2000
3;%(
7DEOHRI&RQWHQWV
3.3.2
3.3.2.1
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.4
3.3.4.1
3.3.4.2
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.1.3
3.4.1.4
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3.4.4
3.4.4.1
3.4.4.2
3.4.4.3
3.4.4.4
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.8
3.8.1
3.8.2
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
Data Sheet
3DJH
Connection RAM Upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Connection RAM Upstream: Dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Connection RAM downstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Connection RAM downstream : Dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Connection RAM downstream : Dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Connection RAM downstream : Dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Traffic Measurement RAM (Port Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port Table Upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port Table Downstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Cell Type Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Register for Programmable Cell Type Filter 1 in Upstream . . . . . . . . . . . . . . . . 85
Byte 1 and 2 of Cell Type Filter 1 : Dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Byte 3 and 4 of Cell Type Filter 1 : Dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Byte 5 and 6 of Cell Type Filter 1 : Dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Byte 7 of Cell Type Filter 1 : Dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Register for Programmable Cell Type Filter 2 in Upstream . . . . . . . . . . . . . . . . 86
Byte 1 and 2 of Cell Type Filter 2 : Dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Byte 3 and 4 of Cell Type Filter 2 : Dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Byte 5 and 6 of Cell Type Filter 2 : Dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Byte 7 of Cell Type Filter 2 : Dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Register for Programmable Cell Type Filter 1 in Downstream . . . . . . . . . . . . . . 87
Byte 1 and 2 of Cell Type Filter 1 : Dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Byte 3 and 4 of Cell Type Filter 1 : Dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Byte 5 and 6 of Cell Type Filter 1 : Dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Byte 7 of Cell Type Filter 1 : Dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Register for Programmable Cell Type Filter 2 in Downstream . . . . . . . . . . . . . . 88
Byte 1 and 2 of Cell Type Filter 2 : Dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Byte 3 and 4 of Cell Type Filter 2 : Dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Byte 5 and 6 of Cell Type Filter 2 : Dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Byte 7 of Cell Type Filter 2 : Dword 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Port Configuration UNI (UNIPORTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Port Configuration UNI (UNIPORTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CAME Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CAMADRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CAMADRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
POLU Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
POLU Configuration Register (P_CONRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
POLU Configuration Register (P_CONRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VERL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VERH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Transmit Cell Registers 0..26 (TXR0..26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Transmit Cell Register 0 (TXR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Transmit Cell Register 1 (TXR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Transmit Cell Register 2 (TXR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transmit Cell Registers 3..26 (TXR3..TXR26) . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Configuration of Transmit Cell Buffer (TXR_CONFIG) . . . . . . . . . . . . . . . . . . . . 97
4
08.2000
3;%(
7DEOHRI&RQWHQWV
3.10
3.11
3.11.1
3.11.2
3.11.3
3.12
3.12.1
3.12.2
3.12.3
3.13
3.14
3.14.1
3.14.2
3.15
3.15.1
3.15.2
3.16
3.16.1
3.16.2
3.16.3
3.16.4
3.16.5
3.17
3.17.1
3.17.2
3.18
3.18.1
3.18.2
3.19
3.20
3.20.1
3.20.2
3.21
3.21.1
3.21.2
3.21.3
3.21.4
3.22
3.23
3.24
3.24.1
3.24.2
3.25
3.26
3.27
3.27.1
3.27.2
3.28
Data Sheet
3DJH
Receive Register/Receive Cell Buffer (RXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Header Capture/Protocol Monitoring Register Set 0 ... 3 Upstream . . . . . . . . . . 99
Protocol Monitoring Buffer 0...3 Upstream (PRMONR0A_U..3A_U) . . . . . . . . . 99
Protocol Monitoring Buffer 0...3 Upstream (PRMONR0B_U..3B_U) . . . . . . . . . 99
Protocol Monitoring Buffer 0...3 Upstream (PRMONR0C_U..3C_U) . . . . . . . . 100
Header Capture/Protocol Monitoring Register Set Downstream . . . . . . . . . . . 100
Protocol Monitoring Buffer 0 Downstream (PRMONRA_D) . . . . . . . . . . . . . . . 100
Protocol Monitoring Buffer Downstream (PRMONRB_D) . . . . . . . . . . . . . . . . 101
Protocol Monitoring Buffer Downstream (PRMONRC_D) . . . . . . . . . . . . . . . . 101
Protocol Monitoring Configuration Register (HEADCAPEN) . . . . . . . . . . . . . . 101
Configuration of Portspecific Counters Upstream . . . . . . . . . . . . . . . . . . . . . . 102
Port Specific Counter Configuration Upstream (PORTCONF0_U..7_U) . . . . . 102
ENPOTIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Configuration of Portspecific Counters Downstream . . . . . . . . . . . . . . . . . . . . 104
PORTCONF0_D ... 7_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ENPOTOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UTOPIA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UTOPIA Configuration (CONUT1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UTOPIA Configuration (CONUT1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UTOPIA Configuration (CONUT1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UTOPIA Configuration (CONUT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UTOPIA Configuration (CONUT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UTOPIA Downstream Queue Overflow Indication Registers . . . . . . . . . . . . . . 109
UT_QOV1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UT_QOV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Configuration of Header Translation/Special Enable Bits . . . . . . . . . . . . . . . . . 110
ADRED_VPIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Command Register (CMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Status Registers for Header Capture/CAME . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Status Register for Header Capture (STATR) . . . . . . . . . . . . . . . . . . . . . . . . . 113
Status Register for CAME (CSTATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Interrupt Status Registers/Interrupt Mask Registers . . . . . . . . . . . . . . . . . . . . . 115
Interrupt Status Register (ISR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Interrupt Status Register (ISR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Interrupt Mask Register (IMR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Interrupt Mask Register (IMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
CAME Interrupt Status Register (CSIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
RWR Mask Register (RMW_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Cell Type Recognition Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 123
UCT_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DCT_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Reset Configuration Register (RMW_CONF) . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Address Register for CMR Commands (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . 128
Scan Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SC_CONR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SC_CONR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
DMA Configuration/Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5
08.2000
3;%(
7DEOHRI&RQWHQWV
3DJH
3.28.1
3.28.2
3.29
3.30
3.30.1
3.30.2
3.30.3
3.31
3.32
3.32.1
3.32.2
3.33
3.33.1
3.33.2
3.33.3
3.33.4
DCONR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
DMAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Test Register/Special Modes (TESTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
POLU Status Registers (P_STATR0..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
P_STATR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
P_STATR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
P_STATR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
CAME Valid Intermediate LCI (CAMVILCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DMA Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DMA_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DMA_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
BIST Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
BIST Mode Register 1 (BISTMODE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
BIST Mode Register 2 (BISTMODE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
BIST Active Register (BISTDONE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
BIST Result Register (BISTERROR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
2SHUDWLRQ Multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
UTOPIA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
RAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CAME Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Policing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Connection Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Cell Insertion and Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
DMA Configuration and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.7
,QWHUIDFH'HVFULSWLRQ UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
External RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Microprocessor and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
JTAG/Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Clock And Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
CAME Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Data Structure at CAME Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
(OHFWULFDO&KDUDFWHULVWLFV Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DC Characteristics for all Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Data Sheet
6
08.2000
3;%(
7DEOHRI&RQWHQWV
3DJH
6.5.5
6.5.5.1
6.5.5.2
6.5.6
6.5.7
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Boundary-Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
AC Characteristics of CAME Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
3DFNDJH2XWOLQHV 8.1
5HIHUHQFHV Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Data Sheet
7
08.2000
3;%(
/LVWRI)LJXUHV
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Data Sheet
3DJH
Chipset configuration for main ATM layer functionality . . . . . . . . . . . . . . . . . . . 11
Chipset configuration for main ATM layer functionality plus full OAM . . . . . . . . 12
Chipset configuration for main ATM layer functionality plus full OAM
and arbitrary header translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Miniswitch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Line card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ALP Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ALP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ALP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cell Header Structure used by the ATM Chip Set . . . . . . . . . . . . . . . . . . . . . . . 29
Mapping Rule for Transparent VPCs (VPI ≥ VPIMIN) . . . . . . . . . . . . . . . . . . . . 31
Mapping Rule for Terminated VPCs (VPI < VPIMIN) . . . . . . . . . . . . . . . . . . . . . 31
LCI Structure for 4 Ports with a VCI- and VPI Bundle Size of 128 . . . . . . . . . . . 32
VPI/VCI Range needed for Usage of Internal ARC . . . . . . . . . . . . . . . . . . . . . . 33
Address Reduction with CAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Cell Header Format at the PHY-ALP UTOPIA Interface . . . . . . . . . . . . . . . . . . 37
Cell Header Format at the ATM-ALP UTOPIA Interface . . . . . . . . . . . . . . . . . . 37
Leaky Bucket Algorithm (according to ITU-T I.371) . . . . . . . . . . . . . . . . . . . . . . 39
POLU Operation Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
POLU Operation Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
POLU Operation Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
POLU Operation Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Structure in the External CONNRAMUP and CONNRAMDO RAM
for each LCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Traffic Measurement at the Port, VPC and VCC Level . . . . . . . . . . . . . . . . . . . 48
DMA for Fast Traffic Measurement Data Transfer . . . . . . . . . . . . . . . . . . . . . . . 49
Relationship between Link Rate, Switch Port Rate and ATM User Cell Rate . . 50
UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UTOPIA Interface Configuration for 4*6 PHYs at the PHY Side . . . . . . . . . . . . 52
Possible Address Group Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Example of an Address Group Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Types of Connection Points for F4 and F5 OAM Flow . . . . . . . . . . . . . . . . . . . . 56
Consequent Actions on OAM Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Configuration of the Connection Points for Nodes with Switching Fabric . . . . . . 57
Configuration of the Connection Points for Nodes without Switching Fabric . . . 58
Processing for AIS, RDI, CC and CCA OAM Cells . . . . . . . . . . . . . . . . . . . . . . . 58
Processing for LB OAM Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Cell Format extracted from ALP to Microprocessor . . . . . . . . . . . . . . . . . . . . . . 59
Cell Format inserted from Microprocessor into the ALP Upstream Direction
without Header Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Cell Format checked for Programmable Cell Filter . . . . . . . . . . . . . . . . . . . . . . . 62
Access to the Internal and External RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example for Spatial Multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
UTOPIA Interface Configuration with Slave Mode at the ATM Side . . . . . . . . . 146
UTOPIA Interface Configuration with Master Mode at the ATM Side . . . . . . . . 147
UTOPIA Interface Configuration with Master Mode for Tx and Slave Mode
for Rx Direction at the ATM Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Connection RAM Upstream Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . 150
8
08.2000
3;%(
/LVWRI)LJXUHV
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Data Sheet
3DJH
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
JTAG/Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
CAME Interface for 16k Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
CAME Interface for 8k Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . . . . . . . . 172
Clock and Reset Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DMA Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SRAM Interface Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Microprocessor Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Microprocessor Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 178
Example of Execution Timing for Write Command (Request #4) . . . . . . . . . . . 179
CAME Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
CAME Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Sorts of Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
9
08.2000
3;%(
/LVWRI7DEOHV
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Data Sheet
3DJH
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Relationship between Network Requirements and Configuration Parameters . . 30
Policing Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Definition of Services (ITU-T and ATM-Forum) . . . . . . . . . . . . . . . . . . . . . . . . . 40
Example for Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Traffic Measurement at VCC Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Traffic Measurement at VPC Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Traffic Measurement Counters at Port Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Polling Order of Port Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Example for Port Number 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Recommended F4 and F5 Configuration and Consequent Action on OAM
and RM cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Truth Table for Cell Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ALP Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
UTOPIA Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Possible RAM Configurations of the ALP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Microprocessor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
ALP Boundary Scan Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Clock and Reset Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . 173
Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Clock and Reset Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . 174
SRAM Interface AC Timing Characteristics for 80pF Load . . . . . . . . . . . . . . . 175
Microprocessor Write Cycle AC Timing Characteristics . . . . . . . . . . . . . . . . . . 176
Microprocessor Read Cycle AC Timing Characteristics . . . . . . . . . . . . . . . . . . 177
Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . . . . . . . . . 178
Duration of Command Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Parameters for Read/Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10
08.2000
3;%(
2YHUYLHZ
2YHUYLHZ
The PXB 4350 E ATM Layer Processor ALP is a member of the Infineon ATM622 chip set. The
whole chip set consists of:
• PXB 4330 E ATM Buffer Manager ABM
• PXB 4340 E ATM OAM Processor AOP
• PXB 4350 E ATM Layer Processor ALP
• PXB 4360 F Content Addressable Memory Element CAME
Main ATM Layer functionality is achieved with only two chips, ALP and ABM. The combination
of these two devices provides elementary ATM functionality like header translation, policing,
OAM support, multicast and traffic management (Fig.1). The functionality is upgradeable to full
OAM support by the AOP (Fig.2) and to arbitrary header translation by CAME (Fig.3).
Pol.
RAM
UTOPIA
P H Ys
UTOPIA
UTOPIA
PXB 4350 E
PXB 4330 E
ALP
ABM
Cell
RAM
Conn.
RAM
)LJXUH
Data Sheet
Cell
RAM
Pointer
RAM
Switch (Loop)
Conn.
RAM
&KLSVHWFRQILJXUDWLRQIRUPDLQ$70OD\HUIXQFWLRQDOLW\
1-11
08.2000
3;%(
2YHUYLHZ
Pol.
RAM
UTOPIA
UTOPIA
PHYs
PXB 4340 E
PXB 4330 E
ALP
AOP
ABM
CAME
Pointer
RAM
Conn.
RAM
UTOPIA
Cell
RAM
UTOPIA
PXB 4350 E
PXB 4340 E
PXB 4330 E
ALP
AOP
ABM
Conn.
RAM
Data Sheet
S
wit
ch
Cell
RAM
Conn.
RAM
Conn.
RAM
Switch (Loop)
Pol.
RAM
UTOPIA
)LJXUH
UTOPIA
&KLSVHWFRQILJXUDWLRQIRUPDLQ$70OD\HUIXQFWLRQDOLW\SOXVIXOO2$0
Conn.
RAM
PHYs
Cell
RAM
PXB 4350 E
Conn.
RAM
)LJXUH
Pointer
RAM
Conn.
RAM
Switch (Loop)
Conn.
RAM
S
wit
ch
Cell
RAM
&KLSVHWFRQILJXUDWLRQIRUPDLQ$70OD\HUIXQFWLRQDOLW\SOXVIXOO2$0DQGDU
ELWUDU\KHDGHUWUDQVODWLRQ
1-12
08.2000
3;%(
2YHUYLHZ
The ATM 622 Layer devices can be used as ....
...a full switch in:
ADSL Concentrators / Multiplexers (DSLAM)
Access Multiplexers
Access Concentrators
Multiservice switches
...Line card in:
Workgroup Switches
Edge Switches
Core Switches
UTOPIA
UTOPIA
$/3
)LJXUH
Data Sheet
$23
UTOPIA
$%0
0LQLVZLWFKFRQILJXUDWLRQ
1-13
08.2000
3;%(
2YHUYLHZ
UTOPIA
$/3
)LJXUH
UTOPIA
UTOPIA
$23
$%0
6ZLWFK
/LQHFDUGFRQILJXUDWLRQ
Due to their most flexible scaling facilities, feature set and throughput the Infineon ATM622 layer
chips are the ideal devices for almost any ATM system.
Data Sheet
1-14
08.2000
3;%(
$70/D\HU3URFHVVRU
$/3
9HUVLRQ
&026
)HDWXUHV
3HUIRUPDQFH
• Performance up to STM-4/OC-12 equivalent ATM layer
processing
• Throughput up to 687 Mbit/s bi-directional
• Up to 16384 connections in both directions (VPC/ VCC)
P-BGA-456
+HDGHU7UDQVODWLRQ
• Header Verification and discarding of unallocated PN/
VPI/VCIs
• Address Reduction in upstream direction (PN/VPI/VCIs -> LCI); two modes
–Built-in, programmable, versatile address reduction
–Optional external address reduction
• Header translation in downstream direction (LCI -> PN/VPI/VCIs)
3ROLFLQJIRU8SVWUHDP'LUHFWLRQ
• Policing according to ITU-T I.371 and ATM Forum UNI Specification
• UPC/NPC function capability on a per connection basis for up to 16384 connections
• Modification of adjusted UPC/NPC parameters on a per established connection basis without
additional cell losses
• Up to 3 Leaky Buckets (LB) per connection with 2 parallel branches: branch 1 containing LB1
and optionally LB2; branch 2 containing LB3
• 4 Leaky Bucket configurations selectable per connection
• Flexible Policing of each port specific cell flow (user data, F4 RM, F5 RM, F4 segment OAM,
F5 segment OAM, F4 end-to-end OAM, F5 end-to-end OAM) with SW programmable control
flags indicating whether the flow is policed in branch 1, branch 2 or is not policed at all
• CDV tolerance (i.e. size of PCR Leaky Bucket) up to 4s
• Maximum Burst Size (MBS) given by the size of SCR Leaky Bucket of up to 210 s
• 232 PCR values ranging between 1 cell/s and 1,620,000 cells/s. PCR and SCR can be adjusted
with a granularity of at least 2 -10 cells/s
0XOWLFDVWLQGRZQVWUHDPGLUHFWLRQ
• Spatial (different ports) and logical (different VPI/VCI for one port) Multicast light
7\SH
PXB 4350 E
Data Sheet
3DFNDJH
BGA-456
1-15
08.2000
3;%(
2YHUYLHZ
2$00DQDJHPHQWIRUXSDQGGRZQVWUHDP
• OAM Levels and Flows (F4/F5) according to ITU-T/I.610 and Bellcore GR-1248-core
• Extraction and insertion of OAM, RM and 2 programmable cell types for both up- and
downstream direction via a 12 cell extraction and 1 cell insertion buffer to the microprocessor
• Supported OAM cells are AIS, RDI, Continuity Check and Loopback cells
• Check and Generation of CRC-10 for incoming and outgoing cells
• Extraction point can be configured as originating, intermediate or terminating point for F4 and
F5 Flow (segment and end-to-end)
• Cell processing options as forwarding, dropping, copying and discarding of cells at the
extraction and insertion point
7UDIILF0HDVXUHPHQWIRUXSDQGGRZQVWUHDP
• Traffic Measurement (can be dis/enabled) according to Bellcore GR-1248
• Traffic Measurement intervals of at least 44 minutes
• At VCC level
–Total Incoming and Outgoing Cells
–Total Incoming and Outgoing Cells with CLP=0
–Total Discarded Cells due to UPC/NPC with CLP=1 and CLP=0 for incoming
cells respectively
–Total Tagged Cells due to UPC/NPC for incoming cells
• At VPC level
–VPC specific Total Incoming and Outgoing Cells
–VPC specific Total Incoming and Outgoing Cells with CLP=0
• At Port level
–Total Discarded Cells due to unallocated PN/VPI/VCI
–Total Incoming Cells with non-zero GFC field
–Total Incoming and Outgoing Cells
–Total Incoming and Outgoing OAM/RM Cells enabled per connection
8723,$,QWHUIDFH
• Multiport UTOPIA [ ] Level 1 and Level 2 interface in up- and downstream direction
according to ATM forum, UTOPIA level 2 specification for up to 24 ports
• PHY side is Master, ATM side is Master/Slave configurable for both TX and RX direction
• UTOPIA frequency up to 51.84 MHz
• Statistical Demultiplexing with 64 cell shared buffer for up to 24 queues with flexible queue size
at UTOPIA downstream transmit interface
• Support of up to 24 PHYs with one queue respectively
• In addition to the UTOPIA-PN a second PN in UDF1 is supported for enhanced PHY
addressing
([WHUQDO665$0
•
•
•
•
Policing Data SSRAM; can be omitted if policing is not needed.
Connection Data upstream SSRAM; can be omitted if traffic statistic and OAM is not needed.
Connection Data downstream SSRAM; mandatory for header translation and multicast
All SSRAMs scale with the number of connections; usable Pipelined Burst SSRAM Types:
–e.g. Toshiba TC55V1325FF-7 1MSSRAM(32k*32) or TC55V2325FF-7 2M(64k*32).
Data Sheet
1-16
08.2000
3;%(
2YHUYLHZ
0LFURFRPSXWHU,QWHUIDFH
• Intel 386 EX microprocessor interface
• Support of DMA for fast data transfer between external RAM and microprocessor
%RXQGDU\6FDQ
• Boundary scan support according to JTAG
,QWHUQDO/RRSV
• Internal hardwired loop: upstream to downstream and downstream to upstream
7HFKQRORJ\
•
•
•
•
BGA-456 package
0,35 µm CMOS
typ. power dissipation 1.7 W
Extended temperature range -40°C to 85°C
Data Sheet
1-17
08.2000
3;%(
2YHUYLHZ
/RJLF6\PERO
(optional)
policing data
Content Adressable
Memory Element
(CAME)
1M .. 6M SSRAM
connection data
1M .. 4M SSRAM
UTOPIA
transmit
interface
PXB 4350 E
slave/master
UTOPIA
receive
interface
master
upstream
connection
RAM Interface
UTOPIA
receive
interface
UTOPIA
transmit
interface
ALP
Test / JTAG
Interface
Clock and
Reset
interface
Microprocessor
Interface, 16bit
downstream
connection
RAM Interface
Address control
1M .. 4M SSRAM
)LJXUH $/3/RJLF6\PERO
Data Sheet
1-18
08.2000
3;%(
2YHUYLHZ
3LQ&RQILJXUDWLRQ
(Bottom view)
)LJXUH $/33LQ&RQILJXUDWLRQ
Data Sheet
1-19
08.2000
3;%(
2YHUYLHZ
3LQ'HILQLWLRQVDQG)XQFWLRQV
The following explanations applies for all pins of a field in the table respectively:
• Pins with a 1) attached are connected with an internal pull up resistor.
• Pins with a 2) attached are connected with an internal pull down resistor.
• Pins with a 3) attached are 5V compatible.
• Pins with a 4) attached are tristate when not active.
• Pins with a 5) attached are open drain output.
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
AD17
RESET
I
Chip reset
AC16
SYSCLK
I
Core operating clock
A11
UTPHYCLK
I
UTOPIA clock at PHY side.
UTATMCLK
I
UTOPIA clock at ATM side.
RAMVERS
I
Selection of 1M (low) or 2M (high) SSRAMtype.
*HQHUDOSLQV
R26
AD25
2)
8723,$5HFHLYH,QWHUIDFHXSVWUHDPSLQV
C15, D14, B15,
A16, C16, B16,
D15, A17, C17,
B17, D16, A18,
C18, B18, D17,
A19 2) 3)
RXDATU
(15:0)
I
Receive data from PHY side.
C15 corresponds to RXDATU(15) ... A19
corresponds to RXDATU(0).
C14, A14, B14,
A15 3)
RXADRU
(3:0)
O
Address to PHY side.
C14 corresponds to RXADRU(3) ... A15
corresponds to RXADRU(0).
C13 2) 3)
RXPRTYU
I
Odd parity of RXDATU(15:0) from PHY side.
C12, D13, A13,
B13 3)
RXENBU
(3:0)
O
Enable signal to PHY side.
C12 corresponds to RXENBU(3) ... B13
corresponds to RXENBU(0).
C11, D12, A12,
B12 2) 3)
RXCLAVU
(3:0)
I
Cell available signal from PHY side.
C11 corresponds to RXCLAVU(3) ... B12
corresponds to RXCLAVU(0).
B11 2) 3)
RXSOCU
I
Start of cell signal from PHY side.
Data Sheet
1-20
08.2000
3;%(
2YHUYLHZ
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
8723,$7UDQVPLW,QWHUIDFHGRZQVWUHDPSLQV
D8, C7, A7, B7,
D9, A8, C8, B8,
A9, C9, D10, B9,
A10, C10, D11,
B10 3)
TXDATD
(15:0)
O
Transmit data to PHY side.
D8 corresponds to TXDATD(15) ... B10
corresponds to TXDATD(0).
B5, C6, A6, B6 3)
TXADRD
(3:0)
O
Address to PHY side.
B5 corresponds to TXADRD(3) ... B6
corresponds to TXADRD(0).
D7 3)
TXPRTYD
O
Odd parity to PHY side.
TXENBD
(3:0)
O
Enable signal to PHY side.
D6 corresponds to TXENBD(3) ... C5
corresponds to TXENBD(0).
TXCLAVD
(3:0)
I
2) 3)
Cell available signal from PHY side.
D5 corresponds to TXCLAVD(3) ... C4
corresponds to TXCLAVD(0).
A3 3)
TXSOCD
O
Start of cell signal to PHY side.
D6, B4, A5, C5
D5, B3, A4, C4
3)
8723,$5HFHLYH,QWHUIDFHGRZQVWUHDPSLQV
V24, V25, U23,
RXDATD
W26, W24, W25, (15:0)
V23, Y26, Y24,
Y25, W23, AA26,
AA24, AA25, Y23,
AB26 2) 3)
I
Receive data from ATM side.
V24 corresponds to RXDATD(15) ... AB26
corresponds to RXDATD(0).
U26, U24, U25,
T23 3)
RXADRD
(3:0)
I/O
Address from ATM side.
U26 corresponds to RXADRD(3) ... T23
corresponds to RXADRD(0).
V26 1) 3)
RXPRTYD
I
Odd parity of RXDATD(15:0) from ATM side.
T26, T24, T25,
R23 3)
RXENBD
(3:0)
I/O
Enable signals from ATM side.
T26 corresponds to RXENBD(3) ... R23
corresponds to RXENBD(0).
AB24, AB25,
AA23, AC26
RXCLAVD
(3:0)
I/O
Cell available signal to ATM side.
AB24 corresponds to RXCLAVD(3) ... AC26
corresponds to RXCLAVD(0).
RXSOCD
I
Start of cell signal from ATM side.
3) 4)
R25 2) 3)
Data Sheet
1-21
08.2000
3;%(
2YHUYLHZ
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
R24
RXMS
I
Selects Master (high) or Slave (low) mode for
UTOPIA Rx downstream.
8723,$7UDQVPLW,QWHUIDFHXSVWUHDPSLQV
K24, L23, K25,
L26, L25, L24,
M23, M26, M25,
M24, N23, N26,
N25, N24, P24,
P26 3) 4)
TXDATU
(15:0)
O
Transmit data to ATM side.
K24 corresponds to TXDATU(15) ... P26
corresponds to TXDATU(0).
G25, J23, H26,
H24 3)
TXADRU
(3:0)
I/O
Address from ATM side.
G25 corresponds to TXADRU(3) ... H24
corresponds to TXADRU(0).
K26 3) 4)
TXPRTYU
O
Odd parity of TXDATU(15:0) to ATM side.
F25, H23, G24,
G26 3)
TXENBU
(3:0)
I/O
Enable signal from ATM side.
F25 corresponds to TXENBU(3) ... G26
corresponds to TXENBU(0).
J26, J24, K23,
J25 3) 4)
TXCLAVU
(3:0)
I/O
Cell available signal to ATM side.
J26 corresponds to TXCLAVU(3) ... J25
corresponds to TXCLAVU(0).
H25 3) 4)
TXSOCU
O
Start of cell signal from ATM side.
P23
TXMS
I
Selects Master (high) or Slave (low) mode for
UTOPIA Tx upstream.
0LFURSURFHVVRU,QWHUIDFHSLQV
C19, B19, D18,
A20, C20, B20,
D19, A21, C21,
B21, D20, A22,
C22, B22, D21,
A23 3) 4)
MPDAT
(15:0)
I/O
Data to/ from microprocessor.
C19 corresponds to MPDAT(15) ... A23
corresponds to MPDAT(0).
F23, D25, E26,
E24, G23, E25,
F24, F26 3)
MPADR
(7:0)
I
Address to microprocessor.
F23 corresponds to MPADR(7) ... F26
corresponds to MPADR(0).
D24 3)
MPWR
I
Write enable from microprocessor.
D26
3)
MPRD
I
Read enable from microprocessor.
B24
3)
MPCS
I
Chip select from microprocessor.
MPINT
O
Interrupt request to microprocessor.
A24 3) 5)
Data Sheet
1-22
08.2000
3;%(
2YHUYLHZ
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
B23 3) 4)
MPDREQ
O
DMA request to microprocessor.
C23 3) 4)
MPRDY
O
Ready output signal for MPDAT write/ read to
microprocessor.
D22 3)
MPDACK
I
µP DMA acknowledge
5$0,QWHUIDFH665$0SLQV
AF6, AD6, AE6,
AC7, AF5, AD5,
AE5, AC6, AF4,
AD4, AE4, AC5,
AF3, AE3, AF2,
AD1, AB4, AD2
RAMADR
(17:0)
O
Common address to all external RAMs.
AF6 corresponds to RAMADR(17) ... AD2
corresponds to RAMADR(0).
8SVWUHDP&RQQHFWLRQ5$0,QWHUIDFHSLQV
AB2, AA3, AA1, RDATU
AA2, W4, Y3, Y1, (31:0)
Y2, V4, W1, W3,
W2, V1, V3, U4,
V2, U1, U3, T4,
U2, T1, T2, T3,
R4, R1, R2, R3,
P4, P1, P2, P3,
N3
I/O
Data to/ from connection RAM upstream incl.
parity bit.
AB2 corresponds to RDATU(31) ... N3
corresponds to RDATU(0).
AB3, Y4
RSCU
(1:0)
O
Upstream RAM address status control.
AB3 corresponds to RSCU(1) and Y4
corresponds to RSCU(0).
AB1
RADVU
O
Upstream RAM advance input.
AA4, AC2
RCEU
(1:0)
O
Upstream RAM chip enable.
AA4 corresponds to RCEU(1) and AC2
corresponds to RCEU(0).
AC3
RGWU
O
Upstream RAM global write.
AC1
ROEU
O
Upstream RAM output enable.
Data Sheet
1-23
08.2000
3;%(
2YHUYLHZ
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
3ROLFLQJ5$0,QWHUIDFHSLQV
M4, K1, K3,
K2, L4, J1,
J3, J2, K4,
H1, H3, H2,
J4, G1, G3,
G2, H4, F1,
F3, F2, G4,
E1, E3, E2,
F4, D1, D3,
D2, E4, C1,
C2, B1
POLDAT
(31:0)
I/O
Multiplexed data to/ from Policing-RAM/
testbus incl. parity bit.
M4 corresponds to POLDAT(31) ... B1
corresponds to POLDAT(0).
L1, L3, L2
POLADSC
(2:0)
O
Address status control to Policing RAM.
L1 corresponds to POLADSC(2) ... L2
corresponds to POLADSC(0).
M2
POLADV
O
Advance input to Policing RAM.
M1, M3, N4
POLCE
(2:0)
O
Chip enable to Policing RAM.
M1 corresponds to POLCE(2) ... N4
corresponds to POLCE(0).
N2
POLGW
O
Global write to Policing RAM.
N1
POLOE
O
Output enable to Policing RAM.
'RZQVWUHDP&RQQHFWLRQ5$0,QWHUIDFHSLQV
AD15, AC14,
RDATD
AF14, AE14,
(31:0)
AD14, AD13,
AF13, AE13,
AF12, AD12,
AC13, AE12,
AF11, AD11,
AE11, AC12,
AF10, AD10,
AE10, AC11,
AF9, AD9, AE9,
AC10, AF8, AD8,
AE8, AC9, AF7,
AD7, AE7, AC8
Data Sheet
I/O
Data to/ from connection RAM downstream
incl. parity bit.
AD15 corresponds to RDATD(31) ... AC8
corresponds to RDATD(0).
1-24
08.2000
3;%(
2YHUYLHZ
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
AF15, AE15
RSCD
(1:0)
O
Downstream RAM address status control.
AF15 corresponds to RSCD(1) and AE15
corresponds to RSCD(0).
AC15
RADVD
O
Downstream RAM advance input.
AE16, AD16
RCED
(1:0)
O
Downstream RAM chip enable.
AE16 corresponds to RCED(1) and AD16
corresponds to RCED(0).
AF16
RGWD
O
Downstream RAM global write.
AE17
ROED
O
Downstream RAM output enable.
$GGUHVV5HGXFWLRQ&LUFXLW,QWHUIDFH&$0(SLQV
AE22, AD21,
AF21, AE21,
AC19, AD20,
AF20, AE20,
AC18, AF19,
AD19, AE19,
AF18, AD18,
AC17, AE18,
AF17 2) 4)
ARCDAT
(16:0)
I/O
Data from/to CAME incl. parity bit.
AE22 corresponds to ARCDAT(16) ... AF17
corresponds to ARCDAT(0).
AE23, AF22,
AD22, AC20
ARCADR
(3:0)
O
Address to CAME.
AE23 corresponds to ARCADR(3) ... AC20
corresponds to ARCADR(0).
AC21
ARCRES
O
Reset to CAME.
AD23
ARCCS
O
Chip select to CAME.
AF23
ARCWE
O
Write enable to CAME.
AE24
ARCOE
O
Output enable to CAME.
AC22
ARCCLK
O
Clock to CAME is half of the ALP core
frequency given by SYSCLK.
-7$*,QWHUIDFHSLQV
C25 1)
TRST
I
Boundary scan reset
C26 1)
TDI
I
Test data input
P25
1)
TCK
I
Test clock
E23
1)
TMS
I
Test mode select
A25 4)
TDO
O
Test data output
Data Sheet
1-25
08.2000
3;%(
2YHUYLHZ
7DEOH 3LQ'HILQLWLRQVDQG)XQFWLRQV
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
7HVW,QWHUIDFHSLQV
AC25 1)
OUTTRI
I
Puts all outputs except TDO into tristate
mode.
AC24
UTTRI
I
Puts all UTOPIA outputs into tristate mode.
AF24 2)
SMODE
I
Has to be connected to ground.
AE26 2)
SENAB
I
Has to be connected to ground.
AD26
ALPIIDD
I
Has to be connected to ground.
AB23
NDTRO
O
3LQ1R
)XQFWLRQ
6XSSO\SLQV
E7, E9, E11, E13, E14, E16, E18, E20, G5,
VDD
G22, J5, J22, L5, L22, N5, N22, P5, P22, T5,
T22, V5, V22, Y5, Y22, AB7, AB9, AB11, AB13,
AB14, AB16, AB18, AB20
A1, A2, A26, B2, B25, B26, C3, C24, D4, D23, VSS
E5, E6, E8, E10, E12, E15, E17, E19, E21, E22,
F5, F22, H5, H22, K5, K22, L11, L12, L13, L14,
L15, L16, M5, M11, M12, M13, M14, M15, M16,
M22, N11, N12, N13, N14, N15, N16, P11, P12,
P13, P14, P15, P16, R5, R11, R12, R13, R14,
R15, R16, R22, T11, T12, T13, T14, T15, T16,
U5, U22, W5, W22, AA5, AA22, AB5, AB6, AB8,
AB10, AB12, AB15, AB17, AB19, AB21, AB22,
AC4, AC23, AD3, AD24, AE1, AE2, AE25, AF1,
AF25, AF26
8QFRQQHFWHGSLQVSLQV
-
Data Sheet
unconnected pins
1-26
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
)XQFWLRQDO'HVFULSWLRQ
&RUH)XQFWLRQVDQG,QWHUIDFHVRIWKH$/3
The ATM Layer Processor (ALP) is a device which has a bidirectional data transfer throughput
of 687 Mbit/s for up to 16384 connections. The ALP performs Header Translation, Traffic
Measurement and a simple OAM Fault Management Function in both directions. Additionally a
Policing unit is implemented in upstream and a logical Multicast and Buffer Management Unit is
implemented in downstream direction. The UTOPIA Interface at the ingress and engress side
transfers the standardized ATM cell format.
The connection specific data for Policing, Traffic Measurement and OAM can be stored in
external RAMs. If these functions are not needed the related RAMs can be omitted. For Header
Translation in downstream direction an external RAM is mandatory. In upstream direction either
an external Address Reduction Circuit like the Infineon Technologies Chip CAME PXB 4360 E
or an internal Address Reduction Circuit (ARC) can be used for the conversion of the PN/PI/VCI
into a Local Connection Identifier (LCI). The internal ARC is limited in the arbitrary usage of the
VPI and VCI range.
CAME
access
block
upstream
connection RAM
access block
policing RAM
access block
cell
policing
type
traffic
recog- measurement
nition
upstream
address
reduction
UTOPIA
upstream
receive
header
translation
UTOPIA
upstream
transmit
cell filter
upstream
µC
access
block
add/
drop
register
cell filter
downstream
header
translation
UTOPIA
multiplex
downstream
buffer
transmit
multicast light
UTOPIA
downstream
receive
cell type
recognition
traffic
measurement
downstream
downstream
connection RAM
access block
data busses
cell streams
)LJXUH
Data Sheet
$/3%ORFN'LDJUDP
2-27
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
)XQFWLRQDO'HVFULSWLRQRIXVHUGDWDIORZLQXSDQGGRZQVWUHDPGLUHFWLRQ
Throughout this specification the term ‘port’ is used in the meaning given by the UTOPIA
specification [1]. ‘Upstream’ means the direction towards the switching network, ‘Downstream’
towards the physical layer device (PHY).
Upstream:
In the upstream direction the cells are taken from the PHY-devices into the input UTOPIA buffer,
which performs the speed adaptation between the UTOPIA clock and the internal ALP clock.
Subsequently the header of the cell is extracted and used for address reduction together with
the port number. The resulting reduced address is called Local Connection Identifier (LCI). It
uniquely identifies the connection during processing in the ATM Layer. In order to make the LCI
accessible to the following ATM Layer devices (e.g. AOP, ABM) it is mapped into the header of
the cell. Additionally the so-called housekeeping (HK) bits are mapped into the cell header
(UDF1 byte), which carry Infineon Technologies proprietary cell identification (e.g.: Cross Office
Check) evaluated by the ATM Layer devices within the system. The mapping of new contents
into the header is called Header Translation (HT). In the ALP the LCI is used as address for
accessing the external RAMs containing the connection specific data.
Two other functions performed upon the upstream cell flow are traffic measurement and
policing. In case of traffic measurement the various traffic counters are read from the external
connection RAM (CONNRAMUP), updated and stored back. The policing unit (POLU) reads the
variables, constants and flags needed by the UPC/NPC algorithm, performs it and stores the
updated state variables back into the policing RAM (POLURAM). If an overflow of the contracted
bit rate happens, cells will be discarded or tagged depending on the chosen configuration. Both,
policing and traffic measurement, require a preliminary cell type recognition, which uses the cell
header and the connection configuration flags read from CONNRAMUP. If not discarded, the
cell with the new header (including LCI and HK) exits ALP through the output UTOPIA interface.
Downstream:
After the cell has passed the input UTOPIA buffer the LCI is extracted from the header and used
to address the external connection RAM (CONNRAMDO), which contains the new VPI,VCI and
PN as well as the traffic counters for downstream direction. In case of the header translation the
restored VPI, VCI and PN are mapped into the header as defined by the external ATM UTOPIA
cell format. For special ‘low end’ applications there is a possibility to perform a so-called
‘Multicast-light’ function, which means broadcasting the incoming cell to different ports and/or
connections, in exchange for lower performance. The traffic measurements downstream are
performed in a similar way as in upstream direction. The outgoing cell is intermediately stored
in the UTOPIA output buffer until the addressed PHY device is able to receive it.´
$GGUHVV5HGXFWLRQ
The ALP and the other members of the Infineon Technologies 622MBit ATM chip set use an
internal address identifier beside the switching element for all ATM related functions. The
internal address identifier is named LCI and has an address width of 14 bits which supports up
to 16k connections for the STM-4 link. Two modes are supported by the ALP to reduce the
address range. The first mode needs an external Address Reduction Circuit (CAME device PXB
4360 E) which translates any arbitrary address, inside the address range from 0 to 232-1, into
another arbitrary address inside the address range from 0 to 214-1. The configuration of the
external ARC (CAME device) has to be done for each established connection separately.
Data Sheet
2-28
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
Herewith the PN, VPI and VCI of an incoming cell are converted into an LCI. This mode is the
most flexible translation mechanism which is not always needed if the VPI and VCI is in a
predefined address range as used e.g. in the Access Network area or in a LAN environment. For
such applications an internal Address Reduction Circuit was built in which can be used in a
second mode. The internal ARC can be configured with only three parameters for all
connections which determine the range of the PN, VPI and VCI for the calculation of the LCI.
The cell header structure used by the Infineon Technologies ATM chip set is shown in ILJXUH .
7
0
15
VPI
VPI
VCI
VCI
VCI
PT
UDF/PN
0
VCI(15:12)
PTI
C
VPI(11:0)
VCI(11:0)
PN(5:0)
15
LCI
LCI(11:0)
VCI(11:0)
HK(2:0) PN(2:0)
0
VCI(15:12)
PTI
C
C
LCI generation
13
0
PN, VPI and VCI reduction
B
LCI
13
0
shown mapping according to
an external ARC
UTOPIA Level 2 16-bit
UTOPIA Level 2 16-bit
A
LCI
HK: House Keeping bits, proprietary use,
should be ’111’
PN: Only used by IWE8 device
A
or
an internal ARC
PHY
)LJXUH
B
ALP
ABM
AOP
ALP
&HOO+HDGHU6WUXFWXUHXVHGE\WKH$70&KLS6HW
The LCI is used by the ALP to address the connection specific entries stored in the external
CONNRAMUP and POLURAM in upstream direction and CONNRAMDO in downstream
direction. CONNRAMUP stores information for OAM, Traffic Measurement and Header
Translation for each connection. It is also SW configurable (see VHFWLRQ page 75)
whether the connection is valid (see VCON_UP) or not which is a useful feature for both set up
and release procedure. Herewith an established connection can be configured and tested before
it is valid for the user. The release of a connection can be done immediately and afterwards all
connection specific data can be read out for billing purposes. The cell arrival of an invalid
connection can cause two actions. Either an interrupt is generated (see VLD_ERR_U/D,
VHFWLRQ page 117) and the cell is discarded or the cell is transmitted
(see VLDERREN_U/D, VHFWLRQpage 133) without interrupt generation.
Data Sheet
2-29
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
,QWHUQDO$GGUHVV5HGXFWLRQ&LUFXLW
The usage and configuration of the internal ARC is SW-controlled via the MODE and
ADRED_VPIM register (see VHFWLRQpage 110). The CAM Flag in register MODE selects
the usage of the internal or external ARC (CAME device). For the internal ARC the range of the
PN, VPI and VCI for the calculation of the LCI is determined by the three parameters P_NUMB,
M_NUMB and VPIMIN. The source of the PN, which can be derived either from the UTOPIA
Address or the PN inside the UDF1 of a cell, is selected by the flag PN_SOURCE_U. Using
internal ARC requires an assignement of VPI and VCI to a logical connection in an order which
accommodates the mapping scheme of the ALP (see ILJXUH ). The mapping rule has the
following concept.
The VPCs are divided into two groups. The first group contains the terminated VPCs and the
second group the transparent VPCs. The VPI values of the terminated VPCs are lower than the
value of the parameter VPIMIN. The VPI values of the transparent VPCs are greater than or
equal to the value of the parameter VPIMIN. The number of VCCs from each terminated VPC is
determined by the ratio of the Blocksize (BLS) to maximum PNmax. The number of transparent
VPCs is equal to the number of VCCs of each terminated VPC minus VPIMIN. The SW is
responsible for the correct selection of the parameters P_NUMB, M_NUMB and VPIMIN. The
meaning of parameters is the following:
• The Blocksize BLS = number of ports * number of VCCs within a terminated VPC = 2M_NUMB.
• The maximum number of ports PNmax = 2P_NUMB.
• The maximum of VCCs in a terminated VPC = VCCmax = 2(M_NUMB - P_NUMB) = BLS/PNmax
Please note that,
• since a VPC block size is equal to a VCC block size, VPCmax = VCCmax.
• the terminated VPIs < VPIMIN, the transparent VPIs >= VPIMIN.
The principle of the internal ARC is explained on an example where 4 ports are supported by the
ALP. Each port transports 128 VPCs and 128 VCCs per VPC. 20 VPCs are terminated at the
ATM switch. The calculation of the three parameters and the mapping rules for the calculation
of the LCI is shown in WDEOH , ILJXUH and .
7DEOH
5HODWLRQVKLSEHWZHHQ1HWZRUN5HTXLUHPHQWVDQG&RQILJXUDWLRQ3DUDPHWHUV
1HWZRUN5HTXLUHPHQWV
4 Ports
128 VCCs per terminated VPC
128 VPCs split into
20 terminated and 108 transparent VPCs
&RQILJXUDWLRQ3DUDPHWHU
P_NUMB = 2
BLS = 4ports * 128 VCCs = 512 ->
M_NUMB = 9
VPIMIN = 21
According to the requirement of 20 terminated VPCs the value of VPIMIN is 21. The external
RAM can store 32 blocks of the given block size (16k / BLS). These blocks should be divided in
up to 31 blocks with terminated VPCs (0..30) and one block with transparent VPCs. However for
the most efficient usage of the external RAM the value of VPIMIN should be 31. The example is
continued with these new parameters. Two mapping rules exist for the mapping of transparent
and terminated VPCs.
Data Sheet
2-30
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
M_NUMB - P_NUMB = 7
11
M_NUMB - P_NUMB = 7
0
15
93,
P_NUMB =2
0
9&,
13
/&,
)LJXUH
5
0
31
M
P
0
1 1 1 1 1
0DSSLQJ5XOHIRU7UDQVSDUHQW93&V93,≥93,0,1
)LJXUH 10 shows that the LCI value of the transparent VPCs is gathered only from the VPI and
the PN range. The LCI range is in the interval between LCImax and LCImax-2M_NUMB (maximum
number of transparent VPC over all ports). Inside the LCI range only the LCIs from the VPCs
with a VPI value greater than or equal to VPIMIN are generated. The LCI value from the
transparent VPCs with a VPI value between 0 and VPMIN-1 is not generated because the
internal ACR mechanism switches to the other mapping rule depicted in ILJXUH . In this case
the LCI value of the terminated VPCs is gathered from the PN, VPI and VCI range.
V_MIN = Min(12,14-M)
11
M_NUMB - P_NUMB = 7
0
15
93,
0
9&,
13
5
0
31
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
P_NUMB =2
M
P
0 0 0 0
0
/&,
)LJXUH
0DSSLQJ5XOHIRU7HUPLQDWHG93&V93,93,0,1
The bit field of the PN and VPI not mapped into the LCI must be zero in the header of the
incoming cell. Otherwise the cell will be discarded. The same is true for the not mapped bit fields
of the VCI of the cell with VPI < VPIMIN.
The mapping rule gives the following LCI structure. The LCI address range is divided into two
sections. The upper section contains the LCI which corresponds to the VPI of the transparent
Virtual Path Connections. In this section the LCIs for the VPI interval between 0 and 30 are not
generated (VPIs ≥VPIMIN).
Data Sheet
2-31
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
16383
16383
16382
16381
16380
PN=3
PN=2
PN=1
PN=0
15875
15874
15873
15873
PN=3
PN=2
PN=1
PN=0
VPI=127
:
VPI=1
VPI=0
VPC block
for VPI*=0-127
512 entries
VCC block
for VPI=30
512 entries
LCI values
0
515
514
513
512
PN=3
PN=2
PN=1
PN=0
3
2
1
0
PN=3
PN=2
PN=1
PN=0
4 Ports each
with
128 not
terminated VPCs
VCI=127
:
VCI=1
VCI=0
VCI=127
:
VCI=1
VCI=0
VCC block
for VPI=1
512 entries
4 Ports each
with
31 terminated
VPC
each
containing
128 VCCs
VCC block
for VPI=0
512 entries
* VPI entries 0..30 contain VP-specific data for terminated VPs
)LJXUH
/&,6WUXFWXUHIRU3RUWVZLWKD9&,DQG93,%XQGOH6L]HRI
This LCI range can be used to store the connection specific traffic measurement data for the
terminated VPCs which are addressed by the LCI2_UP pointer. For detailed explanation see
VHFWLRQpage 46. The lower section contains the LCI corresponding to the VPI and VCI
values of the terminated Virtual Path Connections. The LSBs of the LCI contain the PHY
numbers PN so the ascending LCI-values are cyclically associated with the PHYs. Details of
the LCI structure are depicted in ILJXUH .
In the following a second example is shown to explain the difference between the usage of the
external ARC (CAME device) and the internal ARC. It is shown that it only depends on the VPI
and VCI range whether the internal or external ARC (CAME device) is selected. The scenario is
that 2 physical lines are connected to the ALP via the UTOPIA interface at port 1 and 2.
a) At port 1: There are transmitted 10 terminated and 205 not terminated VPCs.
VPI = 0 contains 73 VCCs (VCI = 0...72),.... and VPI = 9 contains 40 VCCs
(VCI = 0...39).
b) At port 2: There are transmitted 1 terminated and 180 not terminated VPCs.
VPI = 0 contains 86 VCCs (VCI = 0...85).
For the selected VPI and VCI values the external ARC (CAME device) has to be used. The
internal ARC can be used if different VPI/VCI values are chosen for the same number of
transmitted VPCs and VCCs. The steps for the selection of the right VPI and VCI values are
depicted in ILJXUH . In this example the VPI values for the first not terminated VPC have to be
shifted to VPIMIN = 16. Additionally the number of all VCCs of each terminated VPC has to be
the same as the number of all transmitted VPCs.
Data Sheet
2-32
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
$
6HDUFKWKHELJJHVW93DQG9&%XQGOH
%LJJHVW93%XQGOHFRQWDLQV93V
%LJJHVW9&%XQGOHFRQWDLQV9&V
1
%XQGOHVL]HZLOOEHURXQGHGWR %
3RUW
'HWHUPLQHWKHKLJKHVWQXPEHURIWKHWHUPLQDWHG93
3RUW
+LJKHVW93QXPEHULV
1
5DQJHRI QRW
1XPEHURIWHUPLQDWHG93VLVURXQGHGWR WHUQLPDWHG93V
3RUW
3RUW
QRWXVHG
5DQJHRI
QRWXVHG
WHUQLPDWHG93V
93,
)LJXUH
9&,
93,
93,
9&,
9&,
93,
9&,
93,9&,5DQJHQHHGHGIRU8VDJHRI,QWHUQDO$5&
The number of VPCs being equal to the number of VCCs is 256. Using such VPI/VCI values we
can serve up to 4 ports each transmitting 4096 connections. The difference between the two
scenarios is that the internal ARC has predefined ranges of VPI and VCI which are not
completely used.
([WHUQDO$GGUHVV5HGXFWLRQ&LUFXLW&$0(GHYLFH
The Address Reduction Circuit can be a Content Addressable Memory or a Pointer Look-up
Circuit which reads the PN, VPI and VCI and delivers the corresponding LCI as a search result.
Infineon Technologies provides a Content Addressable Memory Element CAME PXB 4360 E.
The ALP supports the configuration, test and search in the external ARC operation mode (CAME
device, see ILJXUH ).
The configuration of the external ARC (CAME device) is SW controlled. The CAM Flag of the
MODE register (see VHFWLRQpage 110) selects the usage of the external ARC (CAME
device). For the setup of each connection the corresponding LCI, PN, VPI and VCI are written
from the microprocessor into the ADR (see VHFWLRQ page 128), CAMADRL register
(see VHFWLRQ page 90) and CAMADRH register (see VHFWLRQ page 90).
Furthermore it can be defined whether this entry belongs to a connection of a terminated VPC
and whether the entry is valid which is indicated by the P_IP and VCON bits respectively in the
ADR register. Subsequently the CAME-Write command of the CMR (see VHFWLRQpage
111) register invokes the writing of the ADR, CAMADRL and CAMADRH register successively
to the external ARC (CAME device). After a number of cycles needed for the command
execution of the CAME the ALP reads the status information from the CAME and writes it into
the CSTATR register (see VHFWLRQ page 114). An indication for the execution of the
CAME-Write command is delivered to the CMR register. In the CSTATR register two alarm
Data Sheet
2-33
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
indications are foreseen for the CAME-Write mode. First alarm is generated by the CAME if a
PN, VPI, VCI and LCI iswritten into the CAME which already exists. Such an entry is refused by
the CAME. The second alarm is generated by the CAME if a valid connection (VCON in the
CAME) is overwritten. This means the PN, VPI and VCI for an active LCI is changed without
switching down the VCON of the LCI in the previous step. This has to be prevented because the
connection has to be released before an new connection with the same LCI is set up. In this case
the CAME has to refuse the entry.
P_IP
32
0
16
0
match bit 0..31 0
valid
valid
match bit 16..31 1
or
LCI (VCC)
valid
don’t care
LCI (VPC)
8191
PN (3:0)
PN
VPI
VCI
VPI (11:0)
VCI (15:0)
)LJXUH
$GGUHVV5HGXFWLRQZLWK&$0(
The ALP supports a CAME-Read mode into the CMR register to verify the values of the PN, VPI,
VCI, P_IP and VCON for each LCI defined in the ADR register, which are written into the
CAMADRL and CAMADRH registers.
To test the external ARC (CAME device) a test mode is supported by the ALP. In this mode the
test commands are written into the ADR register and transferred to the CAME with the test
command in the CMR register. After test command execution the ALP reads the status
information and writes it into the CSTATR register. Two test cases are foreseen to identify
failures in the internal memory of the CAME. After the configuration of the memory banks with a
predefined value the contents of the memory banks are read and compared. In case of a
difference an alarm indication TEST READ FAULT is activated in the CSTATR register. The
same can be done using a search command which detects memory locations with different
contents. For this case the alarm indication TEST SEARCH FAULT is activated in the CSTATR
register.
Upon cell arrival the ALP invokes the CAME search command either for the user cells or for the
OAM F4 Flow cells of a terminated VPC. The PN, VPI and VCI are written to the external ARC
Data Sheet
2-34
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
(CAME device). After the execution of the search command which needs a number of cycles the
ALP reads the LCI, VCON, P_IP and status information. The status information is written into
the CSIR register and the LCI is written into the cell header. The source of the PN which can be
either the UTOPIA Address or the PN in the UDF1 of the cell is determined by the
PN_SOURCE_U in the MODE register. The number of PN(5:0) bits used for the CAME is
defined by P_NUMB in the MODE register and has to be in the interval between 4 and 6. For
P_NUMB equal to 4 the contents of CAMADRH(16:0) are gathered from PN (3:0) and VPI (11:0)
which is used for NNI application. If the number of PN bits is increased then
(16 - (number of PN bits))
least significant VPI bits are mapped into the CAMADRH register. In case of a failure all internal
errors in the CAME during the address reduction are signalled by the CAM_ERR interrupt in the
ISR1 register (see VHFWLRQpage 117). The status information is written into the CSIR
register (see VHFWLRQ page 121). Information on parity errors at the CAME interface,
mismatch or multimatch as a response of the CAME search command and other failure cases
are given. The VCON bit in the CAME defines whether the connection is valid or not. For not
valid LCIs the ALP will discard or forward the cell depending on the NODIS_CAM flag in the
TESTR (see VHFWLRQpage 133) register. For OAM F4 cells the CAME delivers an LCI of
any of the VCC’s contained in the VPC.
A short summary of all SW related control, interrupt and status registers is given below for
orientation. The detailed description can be founded in VHFWLRQpage 64.
Control bits of the internal register 02'(:
• The usage of the internal or external Address reduction circuit is determined by the &$0 bit.
• The 3B180% bits define how many bits of the port number are used to derive the LCI. The
port number is used by both the internal and external ACR.
• The 0B180% bits define the block size used by the internal ACR to derive the LCI. The
31B6285&(B8 bit selects whether the UTOPIA address or the PN in the UDF1 of the cell
header is used as the source of the port number.
Control bits of the internal register $'5('B93,0:
• 93,0,1 bits define the lowest VPI value of all transparent VPCs. This parameter is only used
by the internal ARC. The value of VPIs above the value of the lowest VPI belong to the group
of transparent VPCs (not terminated VPC).
Control bits of the register $'5:
• $'5 bits correspond to the value of the LCI for the operation of the external ARC (CAME
device).
• 3B,3 bit indicates whether the connection point is a path intermediate point of a transparent
VPC or an termination point of the VPC.
• 9&21 bit indicates whether the connection is valid or not.
Control bits of the registers &$0$'5/ and &$0$'5+:
• 9&, bits correspond to the value of the VCI for the operation of the external ARC (CAME
device).
• 31 bits correspond to the value of the PN for the operation of the external ARC (CAME
device).
• 93, bits correspond to the value of the VPI for the operation of the external ARC (CAME
device).
Data Sheet
2-35
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
Control bits of the internal register &05:
• 035(4'() bits control both the reading from and the writing to the external ARC (CAME
device) and CONNRAMUP. The data transfer to the external ARC (CAME device) occurs via
the internal registers ADR, CAMADRL and CAMADRH. The data transfer to the external
CONNRAMUP occurs via the internal registers ADR, WDRxL/H and RDRxL/H. Besides the
separate transfer to the ADR and CONNRAMUP it is also possible to write the data to both
units simultaneously. The addressing of the WDRxL/H occurs via the LCI in the internal ADR
register which is also used for programming, testing and operation of the external ADR.
• 675(4 bit invokes the command and indicates the finishing of the command which is defined
by the 035(4'() bits.
Status bits of the internal register &67$75:
• 67$786 bits give a detailed status report of the external ARC (CAME device) after the
microprocessor request.
Alarm Indication bits of the internal register ,65:
• &$0B(55 bit gives an interrupt if errors occur during the address reduction in the external
ARC (CAME device).
Status bits of the internal register &6,5:
• 67$786 bits give a detailed failure report of the external ARC (CAME device) whenever the
interrupt CAM_ERR is generated.
Configuration bit of the Test register 7(675:
• The bit 12',6B&$0 determines whether a cell is discarded or not if the connection is not
configured in the external ARC (CAME device) for this cell.
Test bits of the Test register &$09,/&,:
• The bits /&, are the response to the LCI value from the external ARC (CAME device) in the
test mode.
• The bit 3B,3 is the response to the P-IP value from the external ARC (CAME device) in the
test mode.
• The bit 9&21 is the response to the VCON value from the external ARC (CAME device) in the
test mode.
3URFHVVLQJRIWKH+HDGHU6WUXFWXUHE\WKH$/3
The header format of the ATM cells which are received and transmitted at the 16 bit UTOPIA
Interface at the PHY side is depicted in ILJXUH . According to the standardized cell format [1],
the ALP optionally supports a second proprietary port number information in the UDF1
(word2(8:15)). In upstream direction the ALP can extract the port number either from the
UTOPIA Address or from the UDF1 in the cell header. In downstream direction the ALP can
provide two port numbers simultaneously. The first port number is transmitted via the UTOPIA
Address and the second via the PN in the UDF1. This is a useful feature especially for low bit
rate lines were up to 64 ports can be supported with one queue and a single UTOPIA address.
However it is necessary that the PHY device translates the second PN in the UDF1 into the
corresponding PN of the physical line. The Infineon Technologies chip IWE8 (PXB4220)
supports this feature. The contents of the new generated cell in downstream direction come from
the external RAM (CONNRAMDOWN).
Data Sheet
2-36
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
bit: 15
0
1
2
word
14
13
12 11 10
9
8
7
6
VPI(11:0) or GFC(3:0) and VPI(7:0)
VCI(11:0)
PN(5:0)
5
4
)LJXUH
&HOO+HDGHU)RUPDWDWWKH3+<$/38723,$,QWHUIDFH
3
2
1
0
VCI(15:12)
PT(2:0)
CLP
UDF2
The header format of the ATM cells which are received and transmitted at the 16 bit UTOPIA
Interface at the ATM side is depicted in ILJXUH . The contents of the new generated cell in
upstream direction come from the internal or external Address Reduction Circuit (LCI), the
external RAM CONNRAMUP (HK) and the policing unit (CLP) depending on the
nonconformance test.
bit: 15 14 13 12 11 10
9
8
0
LCI(11:0)
1
VCI(11:0)
2 LCI(13:12)
HK(2:0)
PN(2:0)
word
)LJXUH
7
6
5
4
3
2
1
0
VCI(15:12)
PT(2:0)
CLP
UDF2
&HOO+HDGHU)RUPDWDWWKH$70$/38723,$,QWHUIDFH
+RXVH.HHSLQJ+.%LWV
Within the Infineon ATM Chip Set the use of House Keeping (HK) bits is possible. These three
bits are included in the cell header in upstream direction and evaluated only in downstream
direction. These bits are used to perform a kind of node internal OAM processing which is
Infineon proprietary. The ALP only supports three combinations. With HK = "111" the incoming
cell is a user cell, i.e. all cells without special HK functions. When a user cells arrives at the ALP,
it is forwarded to the UTOPIA interface. Cells with HK = "010" are Dynamic Bandwith Allocation
(DBA) cells, which are needed for traffic management. These cells are dropped to the
microprocessor. The last supported HK = "100" defines Cross Office Check (COC) cells. These
cells are used to verify the functionality of the network node. They are dropped to the
microprocessor when arriving at the ALP. Because the HK is only defined in the Infineon ATM
Chip Set, all cells with HKs should not leave the network node. Therefore all cells with not
supported HKs are discarded. The HK function can be disabled using bit HK_DIS in register
DCT_CONFIG (see VHFWLRQpage 125).
Data Sheet
2-37
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
3ROLFLQJLQ8SVWUHDP'LUHFWLRQ
At the announcement of a connection request, an acceptance algorithm checks in ATM
networks if enough capacity is available on the transmission line in order to transmit the user
data at the desired bit rate assuring quality of services objectives. The connection acceptance
algorithm usually requires separate policing of Sustainable Cell Rate (SCR, ATM-Forum) and
Peak Cell Rate (PCR, ITU). The policing function checks if the cells of the incoming cell stream
are conforming to the negotiated connection parameters in order to guarantee the transmission
quality for each network user. If the contracted cell rate is exceeded the cell is either discarded
or tagged (changing the CLP bit from 0 for high priority cells to 1 for low priority cells, i.e.
increasing the cell loss probability.). Policing at the entrance of the public network is called
Usage Parameter Control (UPC); policing between two networks is called Network Parameter
Control (NPC).
The UPC/NPC algorithm implemented in the ALP is functionally equivalent to the Generic Cell
Rate Algorithm (i.e. Leaky Bucket or Virtual Scheduling Algorithm, abbreviated GCRA, LB or
VSA) as defined in the ATM Forum, UNI specification and the ITU-T recommendation I.371.
The Policing Unit of the ALP has a UPC/NPC function capability on a per connection basis for
up to 16384 connections. The general configuration and the alarm indication of the policing unit
is determined by the internal registers of the ALP (P_CONRL [VHFWLRQ page 91],
P_CONRH [VHFWLRQ page 92], SC_CONR1 [VHFWLRQ page 129], SC_CONR2
[VHFWLRQ page 129],
ISR1
[VHFWLRQ page 117]
and
TESTR
[VHFWLRQ page 133]). The connection specific configuration of the Leacky Bucket (LB) units
and the corresponding policing parameters are stored in the external POLURAM (Dword 0-10
[VHFWLRQ 3.3.1.1 - 3.3.1.11, page 71 - page 73]). The counter values of the nonconforming cells
are stored in the external SSRAM (CONNRAMUP) [VHFWLRQ page 75] for traffic
measurement.
7KH/HDN\%XFNHW/%$OJRULWKP
The principle of the Leaky Bucket can be viewed as a finite capacity bucket whose real-valued
content drains out at a continuous rate of one unit of content per time unit and whose content is
increased by the increment T for each conforming cell. Equivalently, it can be viewed as the work
load in a finite capacity queue or as a real-valued counter. If at a cell arrival the counter of the
bucket is less than or equal to the limit value τ, then the cell is conforming; otherwise, the cell is
non-conforming. The capacity of the bucket (the upper bound of the counter) is (T+τ).
Tracing the steps of the continuous-state leaky bucket algorithm (see ILJXUH ), at the arrival
time of the first cell ta(1), the content of the bucket is set to zero and the last conformance time
LCT is set to ta(1). At the next arrival time of the kth cell ta(k), first the content of the bucket is
provisionally updated to the value X’, which equals the content of the bucket after the arrival of
the last conforming cell X minus the amount the bucket has drained since the arrival, [t a(k)-LCT].
If X’ is less than or equal to the limit value τ, then the cell is conforming and the bucket content
X is set to X’ (or to 0 if X’ is negative) plus the increment T, and the last conformance time LCT
is set to the current time ta(k). If X’ is greater than the limit value τ, then the cell is non-conforming
and the values of X and LCT are unchanged.
Data Sheet
2-38
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
Arrival of a cell at time ta
next cell
X’ = X - (ta -LCT)
&RQWLQXRXVVWDWHOHDN\
EXFNHWDOJRULWKP
X
X’
LCT
Non-conforming
cell
Yes
X’ > τ ?
Value of the Leaky
Bucket counter
Auxiliary variable
Last Conformance
Time
At the time of arrival ta of the
first cell of the connection to
cross the given interface,
X = 0 and LCT = ta.
No
X = max(0,X’) + T
LCT = ta
Conforming cell
)LJXUH
/HDN\%XFNHW$OJRULWKPDFFRUGLQJWR,787,
To realize a number of different sevices defined by ATM-Forum and ITU, the ALP provides a set
of three Leaky Buckets, organized in two parallel branches. The first upper branch contains an
LB1 and optionally an LB2 in serial. Herewith the parameters of the services can be realized.
The second down branch contains the LB3. The lower branch is not necessary for the realisation
of ATM-Forum and ITU-T services. Therefore LB3 can be disabled and is provide for additional
parameters. For each connection the Leaky Bucket configuration and the policing parameters,
containing the three parameters Wmin, Delta and Y (see VHFWLRQpage 43), are stored in
the external policing RAM (POLURAM, see VHFWLRQpage 71). The POLURAM entry for a
connection contains 11 Dwords. The Dwords 0 to 9 contain the policing parameters, Dword10
the configuration parameters. Up to four different modes are selectable per connection via the
MODE bits. The policing configuration modes are summarized in WDEOH , page 40 and are
depicted in the VHFWLRQpage 41 (mode 0), VHFWLRQpage 42 (mode 1), VHFWLRQ
page 42 (mode 2) and VHFWLRQpage 43 (mode 3). The context between policing
modes and the services of ATM-Forum and ITU is shown in WDEOH .
Data Sheet
2-39
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
7DEOH
0RGH
0
1
2
3
3ROLFLQJ2SHUDWLRQ0RGHV
7DJJLQJ
/%
Yes
SCR (0)
No
SCR (0)
No
SCR (0+1)
No
PCR (0+1)
7DEOH
,787
Service
DBR
'HILQLWLRQRI6HUYLFHV,787DQG$70)RUXP
$70)RUXP
Parameters
Service
Parameters
PCR (0+1)
CBR
PCR (0+1)
PCR (OAM)
PCR (OAM)
PCR (0+1)
VBR1
PCR (0+1)
SCR (0+1)
SCR (0+1)
PCR (0+1)
VBR2
PCR (0+1)
SCR (0)
SCR (0)
PCR (0+1)
VBR3
PCR (0+1)
SCR (0)
SCR (0)
tagging optional
tagging optional
PCR (0+1)
SCR (0+1)
PCR (RM)
PCR (OAM)
UBR1
PCR (0+1)
UBR2
PCR (0+1)
tagging optional
PCR (0+1)
ABR
PCR (0)
MCR (0+1)
MCR (0)
ICR (0)
ACR (0)
SBR1
SBR2
SBR3
ABT/DT
ABT/IT
ABR
/%
PCR (0+1)
PCR (0+1)
PCR (0+1)
disabled
/%
PCR (0+1)
PCR (0+1)
PCR (0+1)
PCR (0+1)
0RGH
3
2
1
0
2
3
not supported
for ITU : 3
for ATM : not
supported
For each connection the microprocessor can configure which cells should be policed. Therefore
register MODE consists a set of 2-bit flags for seven different cell types. Using these flags it is
choosen, if the according cell type is policed (and in which branch) or not. If all cell types in a
connection are not policed by setting the flag bits to ’00’, the connection is defined as not
configured. In this case an interrupt is generated if a cell for this connection is detected by the
POLU. Using bits DIS_U/D the microprocessor is able to select, which branch for the Leaky
Bucket is used.
*HQHUDO&RQILJXUDWLRQRIWKH32/8
The operation of the POLU is controlled by the microprocessor via the P_CONRL and
P_CONRH registers. The VALID_CONF bit is used to indicate that the data has been changed
Data Sheet
2-40
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
by the microprocessor and that the POLU has accepted and executed the command. Two
operation modes, namely Test Operation Mode (TOM) and Normal Operation Mode, are
implemented. A reset of the ALP puts the POLU in TOM with no policing is enabled. After
initializing the POLURAM (all ’0’) and the establishment of a connection the POLU can be
operated in the Normal Operation Mode by setting the TOM bit in register P_CONRL. For all
connections the tagging and discarding of cells can be suppressed resprectively via the bits
TAGINH and DISINH.
Using the scan registers SC_CONR1 and SC_CONR2 the range of policed LCIs is defined. The
POLU can only be operated after the activation of the POLU refresh mechanism which is
activated with the POLU_REFR_EN bit.
The TESTR register provides two bits for the handling of incorrect cells. The selection whether
a cell is discarded or not if the cell generates a parity error at the POLURAM interface is done
using bit PARERREN_POLU. Such an error is indicated via the interrupt status register bit
POLU_PARERR_U. It doesn’t matter if discarded or not, for these cells no policing occurs. The
second bit, POVLDERREN, determines whether a cell is discarded or not if the connection is not
configured for this cell. This error generates an interrupt which is indicated by the interrupt status
register bit POLVLD_ERR. A connection is not configured if all values of the cell policing option
flags are ’00’. A connection is defined as configured if all values of the cell policing option flags
are ’11’. For both cases the policing is not active.
2SHUDWLRQ0RGH
mode = 00
CLP=1
Tag non-conforming
CLP 0 cells as CLP 1
CLP=0
)LJXUH
Leaky Bucket 1
Conforming
(CLP0+1)
Σ
Leaky Bucket 2
Discard nonconforming
cells (CLP0+1)
32/82SHUDWLRQ0RGH
This mode is the only one in which the priority of non-conforming cells is changed to lower
priority (cell is tagged). When this mode is configured, e.g. for SBR.3 (ITU) or VBR.3 (ATMForum) services, the values for the LB1 are calculated with the SCR(0)-parameter and the
values for LB2 with the PCR(0+1)-parameter. Cells with CLP=1 bypass the LB1. Only cells with
CLP=0 are policed by the LB1. The resulting cell stream, consists of the conforming CLP(0) cells
and the not policed cells with CLP(1), run through the policing with LB2.
Data Sheet
2-41
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
2SHUDWLRQ0RGH
mode = 01
CLP=1
Conforming
(CLP0+1)
Σ
CLP=0
Leaky Bucket 1
Leaky Bucket 2
Discard nonconforming
cells (CLP0+1)
Discard nonconforming
cells (CLP0)
)LJXUH
32/82SHUDWLRQ0RGH
This mode is configured for e.g. SBR.2 (ITU) or VBR.2 (ATM-Forum) services. The values for
the LB1 are calculated with the SCR(0)-parameter and the values for LB2 with the PCR(0+1)parameter. Cells with CLP=1 bypass the LB1. Only cells with CLP=0 are policed by the LB1. In
this mode, no tagging is available. So the non-conforming cells are discarded. The resulting cell
stream, consists of the conforming CLP(0) cells and the not policed cells with CLP(1), run
through the policing with LB2.
2SHUDWLRQ0RGH
mode = 10
CLP0+1
Leaky Bucket 2
Leaky Bucket 1
Discard nonconforming
cells (CLP0+1)
)LJXUH
Conforming
(CLP0+1)
Conforming
(CLP0+1)
Discard nonconforming
cells (CLP0+1)
32/82SHUDWLRQ0RGH
In mode 2 the values for the LB1 are calculated with the SCR(0+1)-parameter and the values
for LB2 with the PCR(0+1)-parameter. This mode is selected e.g. for SBR.1 (ITU) or VBR.1
(ATM-Forum) service. The complete cell stream (cells with CLP=0 and CLP=1) is policed by the
Data Sheet
2-42
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
LB1. The resulting cell stream is conforming to the SCR(0+1) and is afterwards policed by LB2.
Now, the resulting cell stream is conforming to the PCR(0+1). Additionally the LB3 can be
declared for PCR(OAM) policing (for ABT services by ITU).
2SHUDWLRQ0RGH
mode = 11
CLP0+1
Conforming
(CLP0+1)
Leaky Bucket 1
disabled
Conforming
(CLP0+1)
Leaky Bucket 2
Discard nonconforming
cells (CLP0+1)
)LJXUH
32/82SHUDWLRQ0RGH
This mode is used e.g. for DBR (ITU), CBR or UBR1 (ATM-Forum) services. The values for the
LB1 are calculated with the PCR(0+1)-parameter. The LB2 is disabled in this mode, the cell
stream passes it without policing actions. The complete cell stream is policed by the LB1. The
non-conforming cells are discarded. For DBR and CBR the LB3 can be configured for policing
the PCR (OAM).
&DOFXODWLRQRI32/83DUDPHWHUV
The policing parameters for the leaky bucket are derived from the PCR, SCR, MBS and tagging
indication provided from the signalling message. The CDVT is provided by the network operator
via mutual agreements between network operator and user or via signalling message. The Λx
and Tx parameters for SCR and PCR are calculated with the same formula. Therefore the index
in the formula is named xCR, where x stands for Peak (P) or Sustainable (S).
According to ITU up to 16384 xCR values ΛxCR are defined which range from 1cell/s to
4.29077Gcell/s. The relative difference between any pair of successive ΛxCR value is smaller than
2-9.
m xCR =
k xCR =
xCR sig
+9
log 2  ----------------- 1023 
xCR sig
-------------------– 512
2 mxCR – 9
Note :x stands for rounding up to the nearest integer value.
Data Sheet
2-43
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
ΛxCR = 2mxCR(1+kxCR/512) [cells/second]
0 ≤ mxCR ≤ 31
0 ≤ kxCR ≤ 511
The reciprocal value of ΛxCR gives the corresponding peak emission interval value TxCR. Due to
the non-linearity an extra bit is needed for the exponent. TxCR is calculated as:
T xCR = 2
–( m xCR + 1 ) 
1023 – k’xCR
⋅  1 + -------------------------------------- sec onds
1024


2047 ⋅ k x CR – 512
k’PCR = --------------------------------------------- + 1
k x CR + 512
0 ≤ m x CR ≤ 31
0 ≤ k x CR ≤ 511
This gives 16384 peak emission interval values TxCR ranging between 0.9995 and 2.33*10-10
seconds. The relative difference between any pair of ΛxCR and TxCR is smaller than 0.0997%. For
the non-conformance test of a connection two policing parameters are needed by the POLU for
configuration of the Leaky Buckets. These are the value of 'HOWD, the decrement parameter, and
: , comparable to the limit value of the Leaky Bucket. The two parameters are stored between
Word3 [VHFWLRQ page 72] and Word10 [VHFWLRQ page 73] in the external RAM
(POLURAM) and are calculated as:
Delta = T/Tz = xCRZ /xCR
Wmin = τ/Tz
Tz is the peak emission interval for the cell processing of the ALP. For a SYSCLK with 51.84MHz
and 32 cycles for one cell, the peak emission interval Tz for one cell is 617.28ns. The
corresponding xCR is 1,620,000 cells per second. Delta is the cell emission interval normalized
to the cell processing period. It has 232 values and a granularity of 2-11. As a result a granularity
of 2-10 cells/s of the PCR or SCR can be adjusted.
Wmin is the ratio between the CDV parameter τ and the emission interval for one cell Tz. τ can
also be derived from the signalling parameters MBS, TSCR and TPCR as:
τ IBT = [ ( MBS – 1 ) ( T SCR – T PCR ) ] sec onds
PLQ
Data Sheet
2-44
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
([DPSOHIRU32/8FRQILJXUDWLRQ
This example is according to to the specification for Unstructured Circuit Emulation Service of
the ATM Forum and ITU. This service e.g. handles CBR traffic using AAL1 with 47 bytes per cell
at a data rate of 2.048Mbit/s for E1, which results in a peak cell rate of 5446.8cell/s (= PCRsig).
According to I.371 the m and k parameters are calculated according:
PCRsig
m PCR = log  -------------------- + 9
2 1023 
PCR sig
- – 512
k PCR = --------------------m PCR – 9
2
The value of both parameters has to be round up. As a result mPCR=12 and kPCR=169. With the
formula given in VHFWLRQ the parameters are: k’PCR=508 (rounding down),
TPCR = 183.463µs and ΛPCR =5448cells/s. Be aware that the inverse value of TPCR (which is
5450.68cells/s) is higher than the value of ΛPCR.
The POLU parameter Delta (TPCR/TZ) is 297.21006. The cell cycle time Tz is 617.28ns.
The value of the LSB of Delta is 2-11. Herewith Delta is encoded as 949AEH (= Delta*211, round
down). The POLU parameter Wmin (τPCR/Tz) is 1215 if the CDVT is 750µs at the UNI. The
encoding of the Wmin is 25F800H (= Wmin*211). The Configuration and parameter values for POLU
are as follow:
7DEOH
([DPSOHIRU&RQILJXUDWLRQ
6HUYLFH3DUDPHWHUV
32/8&RQILJXUDWLRQ3DUDPHWHUV
IRU(&LUFXLW(PXODWLRQ
ZLWKµV&'97DWWKH
81,
DBR
PCR(0+1)
MODE = 3
Delta1 = 949AEH Delta2 = 0
Delta3 = 0
τPCR(0+1)
Wmin1 = 25F800H
Wmin2 = 0
Wmin3 = 0
USER_U/D = 10
F4RM_U/D = 00
F5RM_U/D = 00
F4SEG_U/D = 00
F4E2E_U/D = 00
F5SEG_U/D = 00
F5E2E_U/D = 00
DIS_U/D
= 01
The user cells are policed in the upper branch at LB1. Discarding is enabled. The LB2 is
disabled. The OAM and RM cell types are not policed (transparent bypass). The LB3 can be
optionally used for a separate OAM policing. Delta3 and Wmin3 is derived from the PCR(OAM) and
τPCR(OAM) values as shown above. The FxSEG_U/D and/or FxE2E_U/D has to be set to 01 and
the DIS_U/D to 00.
Data Sheet
2-45
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
7UDIILF0HDVXUHPHQW8QLWIRUXSDQGGRZQVWUHDPGLUHFWLRQ
The ALP provides several traffic counters which can be used for accounting management (i.e.
billing), for observation of the ATM cell traffic behavior as well as for protocol monitoring
measurement. Traffic measurement is implemented at VCC, VPC and port level and fulfills the
Bellcore requirements GR-1248-core. The ALP supports a minimum measurement interval of at
least 44 minutes.
The connection specific data as well as the traffic measurement data of the VCCs, transparent
and terminated VPCs are stored in the external CONNRAMUP and CONNRAMDO RAMs. The
port specific traffic measurement data are stored in the internal Port table of the ALP. After the
address reduction the connection specific data and traffic measurement counter values are read
from the external connection RAM which is addressed via the LCI value of the cell. For the
upstream direction 8 dwords and for the downstream direction 7 dwords are read. The data
structure is depicted in ILJXUH .
LCI_n
HT_CD_UP
TIC
TIC0
TDC1
TDC0
TTC
VP_TIC
VP_TIC0
CONNRAMUP
LCI_m
HT_CD_DO_L
HT_CD_DO_H
MC_PTR
TOC
TOC0
VP_TOC
VP_TOC0
CONNRAMDO
These are the connection specific data
These counter values are updated with the LCI addressing and
correspond to the VCC and transparent VPC
These policing counter values are updated with the LCI addressing
and correspond to the VCC and transparent VPC.
These counter values are updated with the LCI2 addressing and
correspond to the terminated VPC.
)LJXUH
'DWD6WUXFWXUHLQWKH([WHUQDO&2115$083DQG&2115$0'25$0IRUHDFK
/&,9DOXH
Subsequently both the Traffic Measurement (TIC, TIC0 in upstream and TOC, TOC0 in
downstream) and Policing (TDC0, TDC1 and TTC) counter values are updated with respect to
the identified cell type for VCC and transparent VPC. Additionally the ALP reads from a second
LCI2 address the Traffic Measurement (VP_TIC, VP_TIC0 in upstream and VP_TOC,
VP_TOC0 in downstream) counter values for the terminated VPCs. The LCI2 is stored in the
connection specific data addressed by the LCI. The value of the LCI2 is identical for all VCCs
which are transported in a common terminated VPC. After counter update all counter values are
stored back in the external CONNRAMUP and CONNRAMDO. For transparent VPCs it is
possible to set LCI2 to the value of LCI. Herewith the counter values TI/OCs and VP_TI/OC are
Data Sheet
2-46
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
identical and the memory usage is reduced. The cell types and the corresponding name of
counters are given in WDEOH for the VCC level and in WDEOH for the VPC level.
7DEOH
7UDIILF0HDVXUHPHQWDW9&&/HYHO
&HOO7\SH
&RXQWHUDQG5$0
Total incoming cells
TIC in CONNRAMUP
Total outgoing cells
TOC in CONNRAMDO
Total incoming cells with CLP=0
TIC0 in CONNRAMUP
Total outgoing cells with CLP=0
TOC0 in CONNRAMDO
Total discarded incoming cells due to UPC/
TDC1 in CONNRAMUP
NPC with CLP=1
Total discarded incoming cells due to UPC/
TDC0 in CONNRAMUP
NPC with CLP=0
Total tagged incoming cells due to UPC/NPC TTC in CONNRAMUP
7DEOH
7UDIILF0HDVXUHPHQWDW93&/HYHO
&HOO7\SH
&RXQWHUDQG5$0
Total incoming cells
VP_TIC in CONNRAMUP
Total outgoing cells
VP_TOC in CONNRAMDO
Total incoming cells with CLP=0
VP_TIC0 in CONNRAMUP
Total outgoing cells with CLP=0
VP_TOC0 in CONNRAMDO
Two kind of traffic measurement counters are implemented for the port level. The first group of
counters is fixedly allocated to the UTOPIA ports 0..15 and counts the total number of incoming
cells in upstream direction (POTIC, see VHFWLRQ page 79) and the total number of
outgoing cells in downstream direction (POTOC, see VHFWLRQ page 82). The fixed
counters can be enabled or disabled via register ENDPOTC (see VHFWLRQpage 103) for
upstream direction and register ENPOTOC (see VHFWLRQ page 105) for downstream
direction. The second group consists of eight countersets for each direction, which can be
flexibly allocated to the ports 0..23. In upstream direction the countersets contain four counters,
named POTI_Ci, PDC_Ci, POTICN_Ci and POTICOR_Ci. POTIC_Ci counts the total number
of incoming cells at port i. PDC_Ci summarizes the total number of discarded cells due to
unallocated PN/VPI/VCI at port i. The total number of incoming cells with a non-zero GFC field
at port i is counted by POTICN_Ci. And POTICOR_Ci shows the number of total incoming OAM/
RM cells at port i. These counters are stored in the traffic measurement RAM, which is also
called port table. The structure of the port table is shown in VHFWLRQpage 79. The PN
allocation to the counterset and their configuration is controlled by registers PORTCONFn_U
(VHFWLRQ page 102) for upstream direction. In downstream direction, the countersets
include two counters, which are POTOC_Ci and POTOCOR_Ci. Using POTOC_Ci the total
number of outgoing cells at port i is available and POTOCOR_Ci counts the total number of
outgoing OAM/RM cells at port i. The PN allocation in downstream direction and the
configuration of the countersets is done via registers PORTCONFn_D (VHFWLRQpage
104). It is selectable for each counterset, which counter should be enabled or disabled. If two or
more countersets are allocated to one port, only the counterset with the lowest number is active.
This case is given after reset, because at this event all eight countersets are assigned to port
Data Sheet
2-47
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
number 0. The cell types and the corresponding name of counters are given in WDEOH for the
Port level. An overview of the traffic measurement capability is depicted in ILJXUH .
7DEOH
7UDIILF0HDVXUHPHQW&RXQWHUVDW3RUW/HYHO
&HOO7\SH
Q>@IRUHDFKFRXQWHUVHW
Total incoming cells due to unallocated PN/VPI/VCI at port number
defined in CNT_PORTn_U
Total incoming cells with non-zero GFC-field at port number defined in
CNT_PORTn_U
Total incoming cells at port number defined in CNT_PORTn_U
Total incoming OAM or RM cells enabled per connection at port number
defined in CNT_PORTn_U
Total outgoing cells at port number defined in CNT_PORTn_U
Total outgoing OAM, RM or discarded F5RM cells enabled per
connection at port number defined in CNT_PORTn_U
7UDIILF0HDVXUHPHQW3URFHVVRU
Enable / disable Traffic Measurement
according to Bellcore GR-1248-core
1
24
Port Mux
)LJXUH
M
VCC Mux
N
VPC Mux
1
1
&RXQWHURIWKH3RUW
WDEOH
PDC_Cn
POTICN_Cn
POTIC_Cn
POTICOR_Cn
POTOC_Cn
POTOCOR_Cn
Virtual connection specific counting of
Total incoming and outgoing cells
Total incoming cells with CLP = 0
Total discarded incoming cells due to
UPC/NPC with CLP = 0 and CLP = 1
Total tagged incoming cells due to
UPC/NPC
Virtual path specific counting of
Total incoming and outgoing cells
Total incoming and outgoing cells
with CLP = 0
Port specific counting of
Total incoming and outgoing cells
Total incoming cells with non-zero GFC field*
Total discarded incoming cells due to
unallocated PN/VPI/VCI*
Total incoming and outgoing OAM/RM cells*
* only for 8 ports
7UDIILF0HDVXUHPHQWDWWKH3RUW93&DQG9&&/HYHO
The Traffic Measurement can be activated by a SW flag EN_TRAF_MEAS_UP/DO in the
external CONNRAMUP/DO for each connection at the VCC and VPC level.
At the port level it is configurable with the SW flag OAM_CNT_U (VHFWLRQpage 102) in
the ALP register whether the TM counter POTICOR counts the OAM or RM cells in upstream
direction. Furthermore the SW flag INC_TIMC_SSD (VHFWLRQ page 75) in the
CONNRAMUP define per connection whether this specific connection is counted. For the
downstream direction the SW flag OAM_CNT_D (VHFWLRQpage 104) in the ALP register
selects whether the TM counter POTOCOR_Ci counts the OAM, RM or both discarded F5RM
and PTI (111) cells. The SW flags INC_TOMC_SSD and INC_TOF5RMC_SSD (VHFWLRQ
Data Sheet
2-48
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
page 77) in the CONNRAMDO define per connection whether this specific connection
is counted in the POTOC_Ci and POTOCOR_Ci. Herewith it is possible that one, some or all
connections running on this port are counted.
7UDIILF0HDVXUHPHQWGDWDWUDQVIHUYLD'0$
The ALP supports a DMA mechanism for fast data transfer of the connection specific counters
at VCC and VPC level from CONNRAMUP and CONNRAMDO to the microprocessor RAM. The
ALP internal condition for a DMA access is the occurence of an empty cycle that means no cell
is available at the UTOPIA receive interface. This has to be considered for system design
(amount of user cells, UTOPIA frequency, core frequency of ALP). In downstream direction it is
possible to force empty cycles by setting bit FORCE_EC_D in register CONUT3 to generate
backpressure to the preceding ASIC that stores the cells in its buffer queues (see VHFWLRQ
page 108).
LCI = 16383
HT_CD_UP
TIC
TIC0
TDC1
TDC0
TTC
VP_TIC
VP_TIC0
LCI_MAX
LCI_N
RAM
LCI_MIN
LCI = 0
These 7 counters
are read with 1
DMA access
15
ALP
DMAR
DMA UP
DMA DO
0
Microprocessor
CONNRAMUP
CONNRAMDO
LCI = 16383
LCI_MAX
LCI_M
LCI_MIN
LCI = 0 0
)LJXUH
HT_CD_DO_L
HT_CD_DO_H
MC_PTR
TOC
TOC0
VP_TOC
VP_TOC0
These 4 counters
are read with 1
DMA access
31
'0$IRU)DVW7UDIILF0HDVXUHPHQW'DWD7UDQVIHU
In upstream direction it has to be considered in the system design (UTOPIA frequency, ALP
frequency and ATM user cell rate) that there is a trade off between switch port usage and
microprocessor access time to CONNRAMUP and CONNRAMDO. For PHY devices up to STM4 equivalent there is no restriction for the ALP as each 10th cell will be an empty cell. For the
ALP this means no cell at the UTOPIA interface. Due to the fact that idle cells can also be
transmitted in the STM-4 signal but not via the UTOPIA interface the number of empty cells will
be higher. The empty cell will be used for configuration and DMA access. Problems will occur
only if the UTOPIA Interface is overbooken. The relationship between link rate, switch port rate
and user cell rate is shown in ILJXUH .
Data Sheet
2-49
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
Physical Implementation:
STM-4 Link rate is 622.08MBit/s
Utopia Level 2
Interface 16Bit
STM-4
PHY-Device
Physical Link Bitrates:
Switch Port Bitrate:
STM-4 = 622.08MBit/s
Payload = 599.04 MBit/s
Utopia = 686.88MBit/s
STM-4 = Utopia load of 0.872 =>
each 10th cell is an emty cell or
even better as no idle cell
is transmitted via Utopia
Signal Structure::
POH
Payload is ATM cells
SOH
User cells
)LJXUH
Utopia Level 2
Interface 16Bit
STM-4
ATM-Layer-Device
Only User cell transfer
Only User cell transfer
Idle cells
5HODWLRQVKLSEHWZHHQ/LQN5DWH6ZLWFK3RUW5DWHDQG$708VHU&HOO5DWH
The DMA is controlled by three registers called DMA_MIN (VHFWLRQ page 136),
DMA_MAX (VHFWLRQpage 136) and DCONR (VHFWLRQpage 130) . DMAMIN and
DMAMAX determine the range of LCIs which counters are read to the microprocessor RAM via
DMA. The DMA is performed LCI-wise with one DMA access transferring all counters of one LCI.
The order of the DMA accesses is from LCI_MIN to LCI_MAX. Using bit DMA_UD in register
DCONR the direction (up- or downstream) can be selected. By setting bit DMA_START in the
same register the mircoprocessor can start the DMA. This bit is reset by the ALP when the DMA
process has finished, therefore the microprocessor has to poll this bit until it is reset. After the
DMA access is done the microprocessor can get the counter values by reading the DMAR
register (VHFWLRQpage 132). After the bit DMA_START of the DCONR register is set, the
write access to DMAMIN, DMAMAX and DCONR except the DMA_START bit is blocked. This
guarantees that the configuration of DMA cannot be changed during the complete DMA cycle.
The microprocessor can stop the DMA by clearing DMA_START. As a result the DMA is
finished and the DMA processor of the ALP is reset. The DMA for a single LCI_n occures during
an empty cell cycle. The transfer between ALP and microprocessor is controlled by the HW pins
MPDREQ and MPDACK. MPDREQ is active after all connection specific traffic measurement
counters are written into the DMA buffer of the ALP and becomes inactive after the contents of
the DMA buffer are read out by the microprocessor via the DMAR register. The next DMA cycle
for LCI_n+1 is initiated either by the MPDACK signal from the microprocessor or by the ALP.
The delay time between two consecutive DMA depends on the occurrence of the next suitable
empty cell cycle. This can lead to a large load on the microprocessor bus if enough empty cycles
are available so that the processes with lower priority than the DMA are blocked. Therefore the
minimum delay between two DMA accesses can be configured by the DMA_WAIT bit in register
TESTR (VHFWLRQ page 133) and by the DMA_DELAY variable in the DCONR register.
Using the reset bits CTRn_RES in the CONR register the microprocessor can reset each
counter value separately for the specified LCIs. When the values are read to the DMA buffer, the
counters are reset. A guide line for DMA is given in chapter 4.
Data Sheet
2-50
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
8723,$)XQFWLRQDOLW\
The ALP provides an UTOPIA Level 2 interface with multiplexed status polling according to [2]
at the PHY and the ATM side. At the PHY side the receive and transmit UTOPIA Interface has
master capability. At the ATM side the hardware pins RXMS and TXMS select for the receive
and transmit direction of the UTOPIA interface whether it acts as an UTOPIA master or slave
(see ILJXUH ).
3+<
$70
6LGH
6LGH
8SVWUHDP&HOO)ORZ
PHY
(P)
PHY
(P)
ATM
(A)
TXDATU(15:0)
Transmit Upstream Master/Slave
RXDATU(15:0)
RXCLAVU(3:0)
RXENBU(3:0)
RXADRU(3:0)
Receive Upstream Master
RXSOCU
RXPRTYU
UTPHYCLK
TXENBD(3:0)
TXADRD(3:0)
Receive Downstream Master/Slave
TXCLAVD(3:0)
TXPRTYU
TXCLAVU(3:0)
TXENBU(3:0)
TXADRU(3:0)
TXMS
RXDATD(15:0)
Transmit Downstream Master
TXPRTYD
TXSOCU
UTATMCLK
$/3
TXDATD(15:0)
TXSOCD
ATM
(A)
RXSOCD
RXPRTYD
RXCLAVD(3:0)
RXENBD(3:0)
RXADRD(3:0)
RXMS
'RZQVWUHDP&HOO)ORZ
)LJXUH
8723,$,QWHUIDFH
The multiplexed status polling of the ALP supports up to 4 independent Clav/Enable line pairs.
This has the advantage that all PHYs can be polled during one cell cycle. Additionally 4 UTOPIA
Level 1 devices with a tristate Rx-Data bus can be supported by the ALP. During one cell cycle
up to 12 UTOPIA Addresses are scanned which gives a maximum capacitance of 48 ports with
the 4 Clav/Enable line pairs. The ALP supports 24 ports. An example for the ALP configuration
Data Sheet
2-51
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
with 4 PHY-devices connected with the 4 Clav/Enable line pairs is given in ILJXUH . In this
example 24 lines, each with a data transfer rate of 25.6 MBit/s result in a total throughput of
614.4 MBit/s, are supported by the ALP.
25Mbit/s 6
25Mbit/s 7
3+<
Enb. 1
CLAV 1
25Mbit/s 12
25Mbit/s 13
3+<
Enb. 2
CLAV 2
25Mbit/s 18
25Mbit/s 19
3+<
25Mbit/s 24
)LJXUH
Enb. 3
CLAV 3
State of Queues 1-24
Enb. 0
CLAV 0
Address Matching and
Serving Unit
3+<
Clav 1-24
Address 0:3
Enb 1-24
25Mbit/s 1
Address, Clav and Enb Conversion unit
Address 1-24
Operation Mode
A 2 Groups a 12 Addresses
B 3 Groups a 8 Addresses
C 4 Groups a 6 Addresses
D 4 Groups without Address
8723,$,QWHUIDFH&RQILJXUDWLRQIRU3+<VDWWKH3+<6LGH
For both PHY and ATM sides the parity protection and the data bus width of 8 or 16 bit is
selectable via the configuration bits UTP_PAR, UTA_PAR, UTP_16BIT and UTA_16BIT in the
CONUT2 register (see SDJH ). The ALP supports cell level handshake without paused
transfer. The frequencies of the UTOPIA clocks UTPHYCLK and UTATMCLK at the PHY and
ATM side are independent from each other and should be lower than or equal to the SYSCLK
of the ALP. The bidirectional data throughput of the UTOPIA interface is up to 686.88MBit/s for
a 16 bit data bus and an UTOPIA clock of 51.84MHz. According to [2] the UTOPIA interface
supports a minimum of up to 8 PHY-devices for an STM-1 throughput and up to 4 PHY-devices
for an STM-4 throughput at the PHY and the ATM side.
For up- and downstream each of the 24 ports can be enabled via SW configuration bits
UT_PORT_U and UT_PORT_D in registers CONUT1A-C (see SDJH ). In upstream direction
the cells in the UTOPIA transmit interface buffer are discarded in the ALP and the cells at the
UTOPIA receive interface are not accepted by the ALP if the port is disabled during the
operation. In downstream direction the acceptance and transmission of cells is locked but the
cells in the port specific queue are not discarded. As the cells remain in the port specific queue
of the ALP the port disabling should be done at the switch element which locks the acceptance
but transmit the rest of cells in the port specific queue.
The ALP converts the 24 ports into an UTOPIA Address and 4 Clav/Enable line pairs. Four
Address Group configurations are selectable for the PHY and ATM side via the SW configuration
bits UTP_CONFIG and UTA_CONFIG in the register CONUT2. The possible configurations are
shown in ILJXUH .
Data Sheet
2-52
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
Configuration for
4 PHY-Devices
with Utopia Level 1
Configuration for
4 PHY-Devices
with 6 Multiports
Configuration for
3 PHY-Devices
with 8 Multiports
Configuration for
2 PHY-Devices
with 12 Multiports
Address -, Clav 0
Address -, Clav 1
Address -, Clav 2
Address -, Clav 3
Address 0, Clav 0
Address 1, Clav 0
Address 2, Clav 0
Address 3, Clav 0
Address 4, Clav 0
Address 5, Clav 0
Address 0, Clav 0
Address 1, Clav 0
Address 2, Clav 0
Address 3, Clav 0
Address 4, Clav 0
Address 5, Clav 0
Address 6, Clav 0
Address 7, Clav 0
Address 0, Clav 1
Address 1, Clav 1
Address 2, Clav 1
Address 3, Clav 1
Address 4, Clav 1
Address 5, Clav 1
Address 6, Clav 1
Address 7, Clav 1
Address 0, Clav 0
Address 1, Clav 0
Address 2, Clav 0
Address 3, Clav 0
Address 4, Clav 0
Address 5, Clav 0
Address 6, Clav 0
Address 7, Clav 0
Address 8, Clav 0
Address 9, Clav 0
Address 10, Clav 0
Address 11, Clav 0
Address 0, Clav 1
Address 1, Clav 1
Address 2, Clav 1
Address 3, Clav 1
Address 0, Clav 2
Address 1, Clav 2
Address 2, Clav 2
Address 3, Clav 2
Address 4, Clav 2
Address 5, Clav 2
Address 6, Clav 2
Address 7, Clav 2
Address 4, Clav 1
Address 5, Clav 1
Address 6, Clav 1
Address 7, Clav 1
Address 8, Clav 1
Address 9, Clav 1
Address 10, Clav 1
Address 11, Clav 1
Address 0, Clav 1
Address 1, Clav 1
Address 2, Clav 1
Address 3, Clav 1
Address 4, Clav 1
Address 5, Clav 1
Address 0, Clav 2
Address 1, Clav 2
Address 2, Clav 2
Address 3, Clav 2
Address 4, Clav 2
Address 5, Clav 2
Address 0, Clav 3
Address 1, Clav 3
Address 2, Clav 3
Address 3, Clav 3
Address 4, Clav 3
Address 5, Clav 3
)LJXUH
Support for up to
24 Ports scanned
round robin
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
3RVVLEOH$GGUHVV*URXS&RQILJXUDWLRQV
Herewith the ALP supports:
• 4 PHY devices without UTOPIA Address (UTOPIA level 1) or with up to 6 Port Addresses
• 3 PHY devices with up to 8 Port Addresses
• 2 PHY devices with up to 12 Port Addresses
The poll cycle is identical in all modes, i.e. the address lines output all addresses from 0 to 11 in
ascending order during one cell cycle. For each address output at the address lines all PHYs
are polled. The polling order is shown in WDEOH. If the address is greater than the number of
Multiports at the device, the associated CLAVx is set to 0. The real Multiport number depends
on the selected mode. The polling sequence of the next polling cycle depends on the current
transmitting PHY, e.g. if port 5 is the current transmitter the next polling sequence starts in 4x6
mode with port 11.
7DEOH
3ROOLQJ2UGHURI3RUW1XPEHUV
0RGH 3ROOLQJ2UGHURI3RUWQXPEHUV
0 6 12 18 1 7 13 19 2 8 14 20
4x6
3x8
0
2x12
1x4
1
9 17
2 10 18
0 12
1 13
2 14
3 15
0
2
4
Data Sheet
8 16
1
3
3 11 19
4 16
5 17
2-53
3
9 15 21
4 12 20
6 18
4 10 16 22
5 13 21
7 19
8 20
5 11 17 23
6 14 22
7 15 23
9 21 10 22 11 23
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
Depending on the selected mode different Clav/Enable lines and addresses are associated to a
special port. As an example for port number 9, the following table shows that 3 different
addresses and Clav/Enable lines are activated for 4 different address group configurations. The
configuration of 4 UTOPIA level 1 interfaces is not possible as the port number 9 is not in the
port address range 0 to 3.:
7DEOH
([DPSOHIRU3RUW1XPEHU
&RQILJXUDWLRQRIWKH8723,$,QWHUIDFH
UTOPIA Address
Clav/Enable line
3
1
1
1
9
0
-
)LJXUH depicts the address group configuration at the PHY and ATM side of two ALPs
connected to one AOP. This is a possible scenario for Access Network System architecture. As
it can be seen it is not necessary that the Address Group Configuration is identical at the PHY
and the ATM side of the ALP, AOP or ABM. However it is required that the port number range
from 0 to 23 is shared by the number of ALPs and each port number is used only once. The SW
is responsible that the used port number range is covered by the Address group configuration.
Clav 0
Clav 1
Clav 2
ALP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Clav 0
Clav 0
Clav 0
Clav 1
Clav 0
Clav 1
Clav 2
Clav 3
)LJXUH
Clav 1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Clav 2
Clav 0
Clav 1
Clav 1
Clav 2
Clav 2
Clav 3
Clav 3
Clav 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Clav 0
Clav 1
AOP
ALP
([DPSOHRIDQ$GGUHVV*URXS&RQILJXUDWLRQ
The ALP has a shared memory buffer of 64 cells for the downstream direction. Up to 24 queues
share the memory buffer. The queue number range of 0 to 23 corresponds to the port number
range. The addressing of the ports or queues occurs via the UTOPIA address and the Clav/
Enable pairs which are converted into the port number depending on the address group
configuration. One threshold which is identical for all queues can be adjusted via the SW
configuration bits UT_THRESH in register CONUT3. Herewith a port specific backpressure
signal can be given to the UTOPIA receive interface in downstream direction if the filling level of
the queue is greater than or equal to the queue threshold. The error indication which is related
to the UTOPIA interface is given in register ISR0. An interrupt indication BOV is generated if the
63rd cell is stored in the shared buffer and an interrupt indication QOV is generated if one or
more queues have an overflow status. A detailed queue overflow indication is provided in the
Data Sheet
2-54
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
register UT_QO1/2 (see SDJH ) by the indication bits QOV_i. Parity errors at the PHY side
of the receive and transmit UTOPIA interface generate an interrupt UT_PARERR_U/D. The
occurrence of a start of cell error or cell length error at the receive UTOPIA interface in up- and
downstream direction generates an interrupt UT_CELLERR_U/D. An overflow at the UTOPIA
receive FIFO in upstream direction is detected via the interrupt flag UTRXFIFO_OV_U.
For diagnosis the ALP has 4 protocol monitoring register sets PRMONR0..3x_U for upstream
direction and one protocol monitoring register set PRMONRx_D for downstream direction to
buffer the last discarded cell due to ATM cell header error. An ATM cell header error occurs if
either an error in the external address reduction circuit CAME is indicated or if a parity error
appears at the CONNRAMDO interface. For both cases an interrupt CAM_ERR and
RAM_PARERR_D indication is given in register ISR1. Each register set can be enabled by SW
flags EN0_U, EN1_U, EN2_U, EN3_U and EN_D in the register HEADCAPEN (see SDJH ).
The 4 registers for upstream direction are related to the 4 CLAV Groups. In downstream
direction only one register set is related to all CLAV groups. An indication is given by the interrupt
bit PMO_HLOG in register ISR0 if one or more cells are stored in the PRMONR registers. A
detailed status indication for each PRMONR register is given by the SW flags PMO_HLOH0_U,
PMO_HLOH1_U, PMO_HLOH2_U, PMO_HLOH3_U and PMO_HLOH_D in register STATR
(see SDJH ). The indication bit is reset after the complete read out of the cell header by the
microprocessor.
Data Sheet
2-55
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
2$0)XQFWLRQDOLW\
The ALP supports together with the external microprocessor an OAM light function for low cost
applications where no AOP is used. The OAM light function covers the AIS, RDI, CC, CCA and
LB handling for F4 and F5 flow according ITU [7] and Bellcore [8]. Not supported are the OAM
functions for Connections Quality Measurement (PM). The OAM light function can be disabled
by the SW flag OAM_EN in the register DCT/UCT_CONFIG (see page 123) for up- and
downstream direction if the AOP is used. In this mode all OAM cells are forwarded to the AOP
without CRC-10 checking. In the OAM light mode the type of the connection point and the
consequent OAM cell processing can be defined and the CRC-10 checking and generation is
performed for the extracted and inserted OAM cells. For the F4 and F5 OAM flow the connection
point can be configurated via SW Bits F4/F5PT_CFG in the CONNRAMUP/DO RAM as
intermediate point IP, originating segment point OSP, originating end-to-end point OEP,
terminating segment point TSP and terminating end-to-end point TEP for each connection.
Additionally a connection point can be also defined as not existing. The following )LJXUH depicts the different types of connection points and the corresponding possible segment and
end-to-end flows for F4 and F5 OAM flow.
End-to-End
TEP
OEP
IP
IP
1
2
3
4
Segment 1
OSP
5
6
Segment 2
TSP
)LJXUH
IP
7
8
Segment 3
OSP
TSP
OSP
TSP
7\SHVRI&RQQHFWLRQ3RLQWVIRU)DQG)2$0)ORZ
The consequent actions for the OAM cells at the connection points can be configurated via SW.
At the termination points it is configurable for each defined and undefined OAM cell type whether
it is discarded or dropped. The corresponding SW flags AR/CC/LB_DISC in the ALP register
DCT/UCT_CONFIG has an influence on all connections.
Utopia
Utopia
Utopia
Utopia
Utopia
)LJXUH
ALP
ALP
µ3,QWHUIDFH
Copy
µ3,QWHUIDFH
ALP
µ3,QWHUIDFH
Utopia
ALP
Drop
Utopia
Discard
Utopia
Forward
µ3,QWHUIDFH
&RQVHTXHQW$FWLRQVRQ2$0&HOOV
At the intermediate points it is configurable whether the AIS, RDI, CC and CCA cells are copied
or forwarded and whether the LB cells are dropped or forwarded. The corresponding SW flags
AR/CC_IP_COPY and LB_IP_DROP in the CONNRAMUP/DO are connection specific.
Data Sheet
2-56
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
For each connection point only one F4 and one F5 connection point can be defined by the
F4PT_CFG and F5PT_CFG Bits. This has an influence to the ALP configuration if two adjacent
segment boarders are located at the same Network Node. This case is illustrated in the following
)LJXUH and where in network Node 3 a segment is terminated and the next is originated.
For a transparent and terminated VP the termination point VP-TSP/EP is configured at the
ingress and the originating point VP-OSP/EP is configured at the engress side of the Node. A
configuration of a termination and origination for the same F4 or F5 flow at one node side is not
possible. )LJXUH shows a Network Node with a Switching fabric and several ALPs at the
ingress and engress side of the Network node. )LJXUH shows a low cost Network Node with
a single ALP and no additional Switching fabric which is used as an ATM-Multiplexors for up to
622MBit/s Throughput in Access Networks.
TSP
1
Segment 1
OSP
3
Segment 2
5
VP-OSP
VC-IP
Subscriber lines
ALP
ALP
VC-OSP
ALP
VP-TEP
VC-TSP
Switching Fabric
)LJXUH
Data Sheet
VP-OEP
Service node line
VP-TSP
Service node line
ASM
&RQILJXUDWLRQRIWKH&RQQHFWLRQ3RLQWVIRU1RGHVZLWK6ZLWFKLQJ)DEULF
2-57
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
TSP
1
OSP
Segment 1
3
Segment 2
5
Service node line
VP-TSP
VP-TEP
Subscriber lines
ALP
VC-TSP
VP-OEP
VC-OSP
VP-OEP
VP-OSP
)LJXUH
&RQILJXUDWLRQRIWKH&RQQHFWLRQ3RLQWVIRU1RGHVZLWKRXW6ZLWFKLQJ)DEULF
The normal OAM processing of the ALP is the insertion of OAM cells via the insertion buffer by
the microprocessor at the OEP and OSP. At the IP the OAM cell is forwarded without any
processing and is automatically dropped via the extraction buffer to the microprocessor at the
TEP and TSP. With the connection specific flags AR_IP_COPY and CC_IP_COPY the AIS, RDI,
CC and CCA cells are copied to the microprocessor for monitoring purpose at the IP. The OAM
flow is depicted in )LJXUH . With the connection specific flags LB_IP_DROP the LB cells are
dropped to the microprocessor. After the LB processing the LB cell is reinserted. The dropping
is necessary as the microprocessor has to check the LB-Identification number which is located
at the payload of the LB cell.
AIS/RDI/CC Copy =1
ins.
ins.
extr.
ins.
extr.
Utopia
ALP
Utopia
Utopia
Utopia
Utopia
Utopia
extr.
ALP
ALP
Utopia
ALP
Utopia
AIS/RDI/CC Copy =0
extr.
ins.
µ3,QWHUIDFH
µ3,QWHUIDFH
µ3,QWHUIDFH
µ3,QWHUIDFH
OEP or OSP
IP
IP
TEP or TSP
)LJXUH
Data Sheet
3URFHVVLQJIRU$,65',&&DQG&&$2$0&HOOV
2-58
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
The )LJXUH depicts the OAM flow processing for LB cells. With the cell type specific flags
AR_DISC, CC_DISC, LB_DISC and UNDEF_DISC in the register DCT/UCT_CONFIG the AIS,
RDI, CC, CCA, LB and undefined OAM cells can be discarded at the TEP and TSP in order to
minimize the processor load in failure case.
LB Drop = 1
ins.
ins.
extr.
ins.
extr.
Utopia
ALP
Utopia
Utopia
Utopia
Utopia
Utopia
extr.
ALP
ALP
Utopia
ALP
Utopia
LB Drop = 0
extr.
ins.
µ3,QWHUIDFH
µ3,QWHUIDFH
µ3,QWHUIDFH
µ3,QWHUIDFH
OEP or OSP
IP
IP
TEP or TSP
)LJXUH
3URFHVVLQJIRU/%2$0&HOOV
A check of error detection code (CRC-10) is performed by the UTOPIA receive interface in upand downstream direction for every OAM cell and an EDC error is indicated by the
EDC_ERR_U/D bits in the ISR1 register. The false OAM cells are discarded or forwarded
according to the configuration by the CRC_NODISC bit in the DCT/UCT_CONFIG register. The
OAM cells and the information on the identified cell type is extracted via the receive cell buffer
register RXR (see page 97) to the microprocessor. The OAM cell has a 56Byte format which
includes the cell type information in word 27 Bit(15:10) as depicted in )LJXUH . The receive
cell buffer stores up to 12 cells and an indication bit RXR_USTR in ISR1 register is set until all
cells are read out by the microprocessor and is afterwards reset automatically by the ALP.
bit:
0
1
2
3
4
:
26
27
15
14
13
12 11 10
Header_1
Header_3
UDF1
Payload_1
Payload_3
:
Payload_47
Celltype(5:0)
9
8
7
6
5
4
3
2
Header_2
Header_4
UDF2
Payload_2
Payload_4
:
Payload_48
unused
1
0
word
)LJXUH
&HOO)RUPDWH[WUDFWHGIURP$/3WR0LFURSURFHVVRU
The insertion of OAM cells is performed via the Transmit cell registers 0 to 26 (see page 94) by
the microprocessor. The cell format is 56 Bytes as in receive direction however the cell type field
in word 28 is not used. An E Bit in UDF2 (5) controls the generation of the CRC-10 for outgoing
OAM cells at the UTOPIA transmit interface. For inserted Non-OAM cells the CRC-10
generation can be disabled. For OAM/RM cells passing the ALP no further CRC-10 is
generated. The cell structure is depicted in )LJXUH for the ALP upstream direction without
Header translation. The other scenario are described in the TXR2 register description
(see page 95). The insertion of the cell from the transmit cell buffer into the cell stream is initiated
Data Sheet
2-59
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
by the START_TR bit in TXR_CONFIG register (see page 97).
bit:
0
1
2
3
4
:
26
27
15
14
LCI
13
12 11 10
Header_1
Header_3
HK
Payload_1
Payload_3
:
Payload_47
unused
9
8
unused
7
6
5
E
4
3
Header_2
Header_4
2
1
0
PNUT
Payload_2
Payload_4
:
Payload_48
unused
word
)LJXUH
&HOO)RUPDWLQVHUWHGIURP0LFURSURFHVVRULQWRWKH$/38SVWUHDP'LUHFWLRQ
ZLWKRXW+HDGHU7UDQVODWLRQ
The following table gives an overview of the consequent actions on the OAM and RM cells in
dependence on the configuration of the connection points at the F4 and F5 flow. If no connection
point is defined (F4-no and F5-no) no useful action is guaranteed. In this case the F4
configuration has a higher priority than the F5 configuration.
.
7DEOH
5HFRPPHQGHG)DQG)&RQILJXUDWLRQDQG&RQVHTXHQW$FWLRQRQ2$0DQG
50FHOOV
&RQQHFWLRQ3RLQW
&RQVHTXHQW$FWLRQV
F4
F5
OAM
RM, F5RES
F4-no
F5-no
no action
no action
F4-no
F5-OEP
dis-F4 & dis-F5
no action
F4-no
F5-OSP
dis-F4 & dis-F5S
no action
F4-no
F5-IP
dis-F4
no action
F4-no
F5-TSP
dis-F4 & dro-F5S
no action
F4-no
F5-TEP
dis-F4 & dro-F5
no action
F4-OEP
no
dis-F5
no action
F4-OEP
F5-OEP
dis-F4 & dis-F5
no action
F4-OEP
F5-OSP
dis-F4 & dis-F5S
no action
F4-OEP
F5-IP
dis-F4
no action
F4-OEP
F5-TSP
dis-F4 & dro-F5
no action
F4-OSP
don’t care
dis-F4S & F5=User
F5=User
F4-IP
don’t care
F5=User
F5=User
F4-TSP
don’t care
dro-F4S & F5=User
F5=User
F4-TEP
F5-no
dro-F4 & dis-F5
no action
F4-TEP
F5-OSP
dro-F4 & dis-F5S
no action
F4-TEP
F5-IP
dro-F4
no action
F4-TEP
F5-TSP
dro-F4 & dro-F5S
no action
F4-TEP
F5-TEP
dro-F4 & dro-F5
no action
dro: dropping; dis: discarding; F4/F5: F4/F5 End-to-End cell; F4S/F5S: F4/F5 Segment cell;
Data Sheet
2-60
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
In downstream direction the discarding of the House Keeping cells for proprietary OAM functions
and of both the F5RM and F5RES (PTI=111) at TEP can be enabled or disabled by the HK_DIS
and F5RM_DISC flags in the DCT/UCT_CONFIG register. The F5RM and F5RES discard
function is needed if the PHY device cannot handle these cell types.
3URJUDPPDEOH&HOO)LOWHU)XQFWLRQDOLW\
The ALP has two fully programmable and maskable cell type filters for up- and downstream
direction that can be configurated to forward, discard, drop or copy the filtered cell. Each
programmable cell filter can be enabled or disabled via the SW flag PCF1/2_EN and the
corresponding actions on the filtered cell are configurated via SW bits PCF1/2_ACT in the DCT/
UCT_CONFIG register respectively. The data format of the cell filter and the cell mask structure
is written from the microprocessor via the WDR0-3 (see page 69) write registers to the cell filter.
The cell filter compares bit by bit the first seven Bytes of each cell with the seven Bytes of the
unmasked cell filter. Masked bits of the cell filter are not compared. The following 7DEOH shows the matching conditions for the cell filter.
7DEOH
7UXWK7DEOHIRU&HOO)LOWHU
&RPSDULVRQRI&HOO+HDGHU%LW[\ZLWK
3URJUDPPDEOH&HOO)LOWHU%LW[\
don’t care
cell header bit(x,y) = cell filter bit(x,y)
cell header bit(x,y) ≠ cell filter bit(x,y)
3URJUDPPDEOH&HOO
0DVN%LW[\
0
1
1
0DWFKIRU%LW[\
yes
yes
no
The Cell filter match if the comparison of all bits of the extended cell header matches. After the
matching the corresponding action on the filtered cell (forward, discard, drop or copy) depends
on the status of the CRC-10 check and the SW flag CRC_1/2_NODISC in register DCT/
UCT_CONFIG. The action on the filtered cell is performed if no CRC-10 failure occur or if the
discarding of cells with CRC-10 failure is disabled by the SW flag CRC_1/2_NODISC which is
recommended for all user cells extracted by the cell filter. The reason is that user cells have
normally no CRC-10.
The programmable cell filter 1 and 2 as well as the cell type filter for OAM light has different
priorities which influence the cell processing if all three cell filters match for the same incoming
cell. The priority is as follow:
• Programmable and maskable cell filter 1 has highest priority if matching (Prio 1)
• Programmable and maskable cell filter 2 has medium priority if matching (Prio 2)
• Cell filter for other cells as OAM cell has lowest priority if matching (Prio 3)
The filter with the highest priority determines the cell processing. The SW is responsible for the
reasonable programming of the cell filters because the priority mechanism can lead to
misinserted cells in case of OAM light.
&DXWLRQ:
At a F4 TEP the OAM filter will drop the F4 End-to-End OAM cell if OAM light is enabled. A
programmable cell filter configurated for the same F4 End-to-End OAM cell with the cell action
„forward“ has a higher priority than the OAM cell filter so that this cell is forwarded. This leads to
a misinserted OAM cell.
Data Sheet
2-61
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
The extended cell header format checked by the programmable cell filter is depicted in
)LJXUH . The Payload_1 contains informations on the OAM type (AIS, RDI, CC, CCA, LB or
undefined).
bit:
7
6
5
4
3
2
1
1
Up: GFC/VPI; Down: LCI
Up: VPI; Down: LCI
2
Up: VPI; Down: LCI
VCI
3
VCI
4
VCI
PTI
5
UDF1
6
UDF2
7
Payload_1
)LJXUH &HOO)RUPDWFKHFNHGIRU3URJUDPPDEOH&HOO)LOWHU
Data Sheet
2-62
0
CLP
08.2000
3;%(
)XQFWLRQDO'HVFULSWLRQ
&RQILJXUDWLRQRI$/3YLD0LFURSURFHVVRU
The ALP is configurated via the write and read registers WDR and RDR (see page 69) by the
microprocessor. The WDR and RDR registers consist of 11 dwords (32Bit) which are connected
with the 16 Bit Data bus of the microprocessor interface. The CMR register (see page 111)
controls the access of the microprocessor to the external RAMs (POLURAM, CONNRAMUP
and CONNRAMDO), the external Address Reduction Circuit CAME, the internal Port Tables for
Traffic Measurement and the internal programmable Cell Filters 1 and 2. The address of the
RAMs, CAME and Port Table is transferred via the ADR register (see page 128). For the
programming of the POLURAM all 11 dwords of the WDR and RDR registers are used. For the
CONNRAMUP only 8 dwords, for the CONNRAMDO only 7 dwords, for the Port Tables only 8
dwords and for the programmable Cell Filter only 4 dwords are used. The LCI address of all
RAMs and the Port Table Address is written into the ADR register. The addressing of the
programmable Cell Filters is controlled directly by the CMR. The CAME contents is transferred
via the CAMADR register and the LCI address via the ADR register. Additionally a read modify
write mask register RMW (see page 122) is implemented for the case that only parts of the
dwords shall be changed. The start of the specific request is initiated by the SW flag STREQ
which is reset by the ALP when the command is finished. The ALP registers are programmed
as usual. The structure of register and the address and data flow for the access to the internal
and external RAMs is depicted in )LJXUH .
Data
ADR
Address Register
CMR
Control Register
WDR/RDR and CAMADR
for Write/Read Transfer
RMW
Mask Register
CAME
Mask Filter
(external ARC)
POLURAM
Selection
7
6
5
4
3
2
1
0
Programmable
Programmable
Cell Type Filter
1
Cell Type Filter 1
downstream
upstream
7
6
5
Data Sheet
CONNRAMUP
4
3
2
1
0
Port Table
up- and downstream
)LJXUH
µP
Address
CONNRAMDO
Programmable
Programmable
Cell Type Filter
1
Cell Type Filter 2
downstream
upstream
$/3
$FFHVVWRWKH,QWHUQDODQG([WHUQDO5$0V
2-63
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
5HJLVWHU'HVFULSWLRQ
2YHUYLHZRIWKH$/35HJLVWHU
7DEOH
DGGU
KH[
$/35HJLVWHUV2YHUYLHZ
UHJLVWHU
GHVFULSWLRQ
UHVHW
YDOXH
µ3
VHH
SDJH
5HDG:ULWH5HJLVWHUV
00
WDR0L
write register 0
undef.
r/w
69
01
WDR0H
write register 0
undef.
r/w
69
...
...
...
14
WDRAL
write register A
undef.
r/w
69
15
WDRAH
write register A
undef.
r/w
69
16
RDR0L
read register 0
undef.
r/w
70
17
RDR0H
read register 0
undef.
r/w
70
...
...
...
2A
RDRAL
read register A
undef.
r/w
70
2B
RDRAH
read register A
undef.
r/w
70
3RUW&RQILJXUDWLRQ5HJLVWHUV
2E
UNIPORTL
port configuration (UNI)
0000
r/w
89
2F
UNIPORTH
port configuration (UNI)
0000
r/w
89
&$0('DWD5HJLVWHUV
32
CAMADRL
data which is to store into the CAME
0000
r/w
90
33
CAMADRH
data which is to store into the CAME
0000
r/w
90
32/8&RQILJXUDWLRQ5HJLVWHU
36
P_CONRL
POLU configuration register
00FF
r/w
91
37
P_CONRH
POLU configuration register
0000
r/w
92
9HUVLRQ5HJLVWHU
40
VERL
Low/High Word of Version numberv
9063
r
93
41
VERH
Low/High Word of Version numberv
523B
r
93
Data Sheet
3-64
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7DEOH
DGGU
KH[
$/35HJLVWHUV2YHUYLHZ
UHJLVWHU
GHVFULSWLRQ
UHVHW
YDOXH
µ3
VHH
SDJH
7UDQVPLW5HJLVWHUV&HOO,QVHUWLRQ%XIIHU7;5&RQILJXUDWLRQ5HJLVWHU
50
TXR0
transmit cell register 0
0000
r/w
94
51
TXR1
transmit cell register 1
0000
r/w
94
52
TXR2
transmit cell register 2
0000
r/w
95
53
TXR3
transmit cell register 3:
payload 0/ payload 1
0000
r/w
96
...
...
...
6A
TXR26
transmit cell register 26:
payload 46/ payload 47
0000
r/w
96
6B
TXR_CONFIG
configuration of transmit cell buffer
0000
r/w
97
undef.
r
97
...
5HFHLYH5HJLVWHU5HFHLYH&HOO%XIIHU
70
RXR
receive cell buffer access
+HDGHU&DSWXUH3URWRFRO0RQLWRULQJ5HJLVWHU6HW8SVWUHDP
72
PRMONR0A_U
protocol monitoring buffer 0 upstream
0000
r
99
73
PRMONR0B_U
protocol monitoring buffer 0 upstream
0000
r
99
74
PRMONR0C_U
protocol monitoring buffer 0 upstream
0000
r
100
...
...
...
7B
PRMONR3A_U
protocol monitoring buffer 3 upstream
0000
r
99
7C
PRMONR3B_U
protocol monitoring buffer 3 upstream
0000
r
99
7D
PRMONR3C_U
protocol monitoring buffer 3 upstream
0000
r
100
+HDGHU&DSWXUH3URWRFRO0RQLWRULQJ5HJLVWHU6HW'RZQVWUHDP
7E
PRMONRA_D
protocol monitoring buffer downstream
0000
r
100
7F
PRMONRB_D
protocol monitoring buffer downstream
0000
r
101
80
PRMONRC_D
protocol monitoring buffer downstream
0000
r
101
0000
r/w
101
3URWRFRO0RQLWRULQJ&RQILJXUDWLRQ5HJLVWHU
81
Data Sheet
HEADCAPEN
enables header capturing
3-65
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7DEOH
DGGU
KH[
$/35HJLVWHUV2YHUYLHZ
UHJLVWHU
GHVFULSWLRQ
UHVHW
YDOXH
µ3
VHH
SDJH
PORTCONF0_U port specific counter configuration upstream 0000
r/w
102
r/w
102
0000
r/w
103
0000
r/w
104
&RQILJXUDWLRQRI3RUWVSHFLILF&RXQWHUV8SVWUHDP
84
...
8B
8C
...
...
PORTCONF7_U port specific counter configuration upstream 0000
ENPOTIC
enables port specific counter POTIC
&RQILJXUDWLRQRI3RUWVSHFLILF&RXQWHUV'RZQVWUHDP
8D
PORTCONF0_D
port specific counter configuration downstream
...
...
...
94
PORTCONF7_D
port specific counter configuration
downstream
0000
r/w
104
95
ENPOTOC
enables port specific counter POTOC
0000
r/w
105
8723,$&RQILJXUDWLRQ5HJLVWHUV
96
CONUT1A
UTOPIA configuration
0000
r/w
105
97
CONUT1B
UTOPIA configuration
0000
r/w
106
98
CONUT1C
UTOPIA configuration
0000
r/w
106
99
CONUT2
UTOPIA configuration
0000
r/w
106
9A
CONUT3
UTOPIA configuration
003F
r/w
108
8723,$'RZQVWUHDP4XHXH2YHUIORZ,QGLFDWLRQ5HJLVWHUV
9B
UT_QOV1
UTOPIA queue overflow (downstream)
0000
r*)
109
9C
UT_QOV2
UTOPIA queue overflow; buffer overflow
(downstream)
0000
r*)
109
&RQILJXUDWLRQ2I+HDGHU7UDQVODWLRQ6SHFLDO(QDEOH%LWV
9E
ADRED_VPIM
minimal VPI used in ARC without CAME
0000
r/w
110
9F
MODE
configuration of address reduction, header
translation and traffic measurement; enable
writing of TESTR and BISTMODE
0000
r/w
110
Data Sheet
3-66
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7DEOH
DGGU
KH[
$/35HJLVWHUV2YHUYLHZ
UHJLVWHU
GHVFULSWLRQ
UHVHW
YDOXH
µ3
VHH
SDJH
µP-request definition
0000
r/w
111
&RPPDQG5HJLVWHU
A0
CMR
6WDWXV5HJLVWHUV)RU+HDGHU&DSWXUH&$0(
A1
STATR
status of protocol monitoring
0000
r
113
A2
CSTATR
status of CAME after µP request
0000
r
114
,QWHUUXSW6WDWXV5HJLVWHUV,QWHUUXSW0DVN5HJLVWHUV
A3
ISR0
interrupt status register
0000
r*)
115
A4
ISR1
interrupt status register
0000
r*)
117
A5
IMR0
interrupt mask register
0000
r/w
118
A6
IMR1
interrupt mask register
0000
r/w
120
status of CAME after interrupt;
port number after interrupts
0000
r*)
121
mask of single words at read/write
accesses
0000
r/w
122
&$0(,QWHUUXSW6WDWXV5HJLVWHU
A7
CSIR
5:50$6.5(*,67(5
A9
RMW_MASK
&HOO7\SH5HFRJQLWLRQ&RQILJXUDWLRQ5HJLVWHUV
AA
UCT_CONFIG
action on receiving OAM-cells upstream
0000
r/w
123
AB
DCT_CONFIG
action on receiving OAM-cells downstream
0000
r/w
125
0000
r/w
127
0000
r/w
128
50:5HVHW&RQILJXUDWLRQ5HJLVWHU
AC
RMW_CONF
reset of single words in the read/modify/
write block
$GGUHVV5HJLVWHU)RU&05&RPPDQGV
AD
Data Sheet
ADR
address of a µP request
3-67
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7DEOH
DGGU
KH[
$/35HJLVWHUV2YHUYLHZ
UHJLVWHU
GHVFULSWLRQ
UHVHW
YDOXH
µ3
VHH
SDJH
6FDQ&RQILJXUDWLRQ5HJLVWHUV
AE
SC_CONR1
configuration of POLU refresh
0000
r/w
129
AF
SC_CONR2
configuration of POLU refresh
0000
r/w
129
'0$&RQILJXUDWLRQ5HDG5HJLVWHU
B0
DCONR
configuration of DMA
0000
r/w
130
B1
DMAR
DMA FIFO access
undef.
r
132
test configuration
0000
r/w
133
7HVW5HJLVWHU6SHFLDO0RGHV
B2
TESTR
32/86WDWXV5HJLVWHUV
B3
P_STATR0
POLU status register 0
0000
r
135
B4
P_STATR1
POLU status register 1
0000
r
135
B5
P_STATR2
POLU status register 2
0000
r
135
response from address reduction test
0000
r
136
&$0(9DOLG,QWHUPHGLDWH/&,
B6
CAMVILCI
'0$5DQJH5HJLVWHUV
B8
DMA_MIN
lower LCI of DMA
0000
r/w
136
B9
DMA_MAX
upper LCI of DMA
0000
r/w
136
%,675HJLVWHUV
BA
BISTMODE1
BIST mode register 1
0000
r/w
137
BB
BISTMODE2
BIST mode register 2
0000
r/w
138
BC
BISTDONE
BIST active register
0000
r
139
BD
BISTERROR
BIST result register
01FF r/w**) 140
1RWH
6LQJOHELWVRIWKLVUHJLVWHUDUHUHVHWWDEOHE\ZULWLQJDµ¶WRWKHP
5HJLVWHULVUHVHWDWHDFKZULWHDFFHVV
Data Sheet
3-68
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7UDQVIHU5HJLVWHU*HQHUDO0DSSLQJWR'ZRUGV
5HDG:ULWH5HJLVWHUV
Register set used for all read/write µP-requests (see CMR-register 6HFWLRQpage 111).
They are used as an shadow image of the specified data block.
WDR (Write Data Register): contents of WDR registers are transferred to the destination
selected in register CMR.
RDR (Read Data Register): contents of the source selected in register CMR are transferred to
RDR registers.
1RWH
$WZULWHDFFHVVHVWRDQH[WHUQDO5$0ELWRIWKHFRUUHVSRQGLQJ:'5UHJLVWHULVXVHGWRFRQWUROWKHSDULW\
JHQHUDWLRQDVIROORZV
ELW JHQHUDWHULJKWSDULW\IRUWKLVZRUG
ELW JHQHUDWHZURQJSDULW\IRUWKLVZRUG
$W UHDG DFFHVVHV IURP DQ H[WHUQDO 5$0 WKH UHVXOW RI WKH SDULW\ FKHFN LV ZULWWHQ LQWR ELW RI WKH
FRUUHVSRQGLQJ5'5UHJLVWHU7KHFRGLQJLVDVIROORZV
ELW SDULW\FKHFNLVRND\IRUWKLVZRUG
ELW SDULW\FKHFNIDLOHGIRUWKLVZRUG
'ZRUG
:ULWH7UDQVIHU5HJLVWHUV:'5/:'5+:'5$/:'5$+
Read/write Address 00H..15H
Value after reset undefined
10
Register WDRAH / Address 15H
Register WDRAL / Address 14H
9
Register WDR9H / Address 13H
Register WDR9L / Address 12H
8
Register WDR8H / Address 11H
Register WDR8L / Address 10H
7
Register WDR7H / Address 0FH
Register WDR7L / Address 0EH
6
Register WDR6H / Address 0DH
Register WDR6L / Address 0CH
5
Register WDR5H / Address 0BH
Register WDR5L / Address 0AH
4
Register WDR4H / Address 09H
Register WDR4L / Address 08H
3
Register WDR3H / Address 07H
Register WDR3L / Address 06H
2
Register WDR2H / Address 05H
Register WDR2L / Address 04H
1
Register WDR1H / Address 03H
Register WDR1L / Address 02H
0
Register WDR0H / Address 01H
Register WDR0L / Address 00H
Data Sheet
3-69
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
5HDG7UDQVIHU5HJLVWHUV5'5/5'5+5'5$/5'5$+
Read/write Address 16H..2BH
Value after reset undefined
10
Register RDRAH / Address 2BH
Register RDRAL / Address 2AH
9
Register RDR9H / Address 29H
Register RDR9L / Address 28H
8
Register RDR8H / Address 27H
Register RDR8L / Address 26H
7
Register RDR7H / Address 25H
Register RDR7L / Address 24H
6
Register RDR6H / Address 23H
Register RDR6L / Address 22H
5
Register RDR5H / Address 21H
Register RDR5L / Address 20H
4
Register RDR4H / Address 1FH
Register RDR4L / Address 1EH
3
Register RDR3H / Address 1DH
Register RDR3L / Address 1CH
2
Register RDR2H / Address 1BH
Register RDR2L / Address 1AH
1
Register RDR1H / Address 19H
Register RDR1L / Address 18H
0
Register RDR0H / Address 17H
Register RDR0L / Address 16H
Data Sheet
3-70
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
0DSSLQJRI7UDQVIHU5HJLVWHUWR,QWHUQDO([WHUQDO5$0V
3ROLFLQJ5$032/85$0
'ZRUG
1RWH
7KHVWELWLVDOZD\VDSDULW\RYHUDGGUHVVDQGGDWD
F5E2 F4E2 F5SE F4SE F5R F4R USE
DIS_
MOD
27 E_U/ E_U/ G_U/ G_U/ M_U/ M_U/ R_U/
U/
E(1:0)
D(1:0)D(1:0)D(1:0)D(1:0)D(1:0)D(1:0)D(1:0)
D(1:0)
10 31
9 31
DELTA3(22:0)
8 31
DELTA3(31:23)
DELTA2(31:24)
DELTA2(23:0)
7 31
DELTA1(31:25)
DELTA1(24:0)
6 31
WMIN3(33:28)
WMIN2
(33:31)
WMIN3(27:0)
5 31
WMIN2(30:0)
4 31
WMIN1(41:11)
3 31
WMIN1(10:0)
2 31
Y3(34:15)
Y3(14:0)
1 31
Y2(34:19)
Y2(18:0)
0 31
CMR(4:0) = 00000
Y1(42:31)
Y1(30:0)
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword0
Odd Parity over address and data.
Y1(30:0)
Policing variable of LB1.
1RWH
,QLWLDOL]HGZLWKDOO¶¶DWWKHHVWDEOLVKPHQWRIDFRQQHFWLRQ'RQ¶WFKDQJHWKHYDOXHGXULQJQRUPDOSROLFLQJ
RSHUDWLRQ
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword1
Odd Parity over address and data.
Y2(18:0)
Policing variable of LB2.
1RWH
,QLWLDOL]HGZLWKDOO¶¶DWWKHHVWDEOLVKPHQWRIDFRQQHFWLRQ'RQ¶WFKDQJHWKHYDOXHGXULQJQRUPDOSROLFLQJ
RSHUDWLRQ
Y1(42:31)
1RWH
Policing variable of LB1.
,QLWLDOL]HGZLWKDOO¶¶DWWKHHVWDEOLVKPHQWRIDFRQQHFWLRQ'RQ¶WFKDQJHWKHYDOXHGXULQJQRUPDOSROLFLQJ
RSHUDWLRQ
Data Sheet
3-71
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword2
Odd Parity over address and data.
Y3(14:0)
Policing variable of LB3.
1RWH
,QLWLDOL]HGZLWKDOO¶¶DWWKHHVWDEOLVKPHQWRIDFRQQHFWLRQ'RQ¶WFKDQJHWKHYDOXHGXULQJQRUPDOSROLFLQJ
RSHUDWLRQ
Y2(34:19)
1RWH
Policing variable of LB2.
,QLWLDOL]HGZLWKDOO¶¶DWWKHHVWDEOLVKPHQWRIDFRQQHFWLRQ'RQ¶WFKDQJHWKHYDOXHGXULQJQRUPDOSROLFLQJ
RSHUDWLRQ
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword3
Odd Parity over address and data.
WMIN1(10:0)
Policing parameter wmin1 of LB1
WMIN1(10:0) is fractional value of wmin1. LSB of wmin1 (WMIN1(0)) is 2-11.
Y3(34:15)
Policing variable of LB3.
1RWH
,QLWLDOL]HGZLWKDOO¶¶DWWKHHVWDEOLVKPHQWRIDFRQQHFWLRQ'RQ¶WFKDQJHWKHYDOXHGXULQJQRUPDOSROLFLQJ
RSHUDWLRQ
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword4
Odd Parity over address and data.
WMIN1(41:11)
Policing parameter wmin1 of LB1
WMIN1(41:11) is integer value of wmin1. MSB of wmin1 (WMIN1(41)) is 231.
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword5
Odd Parity over address and data.
WMIN2(30:0)
Policing parameter wmin2 of LB2
WMIN2(10:0) is fractional value of wmin2. LSB of wmin2 (WMIN2(0)) is 2-11.
WMIN2(30:11) is integer value of wmin2.
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword6
Odd Parity over address and data.
WMIN3(27:0)
Policing parameter wmin3 of LB3
WNIM3(10:0) is fractional value of wmin3. LSB of wmin3 (WMIN3(0)) is 2-11.
WMIN3(27:11) is integer value of wmin3.
WMIN2(33:31)
MSB of wmin2 (WMIN2(33)) is 223.
Data Sheet
3-72
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword7
Odd Parity over address and data.
DELTA1(24:0)
Policing parameter Delta1 of LB1
DELTA1(10:0) is fractional value of Delta1. LSB of Delta1 (DELTA1(0)) is 2-11.
DELTA1(24:11) is integer value of Delta1.
WMIN3(33:28)
MSB of wmin3 (WMIN3(33)) is 223.
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword8
Odd Parity over address and data.
DELTA2(23:0)
Policing parameter Delta2 of LB2
DELTA2(10:0) is fractional value of Delta2. LSB of Delta2 (DELTA2(0)) is 2-11.
DELTA2(23:11) is integer value of Delta2.
DELTA1(31:25) Policing parameter Delta1 of LB1
MSB of Delta1 (DELTA1(31)) is 221.
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword9
Odd Parity over address and data.
DELTA3(22:0)
Policing parameter Delta3 of LB3
DELTA3(10:0) is fractional value of Delta3. LSB of Delta3 (DELTA3(0)) is 2-11.
DELTA3(22:11) is integer value of Delta3.
DELTA2(31:24) Policing parameter Delta2 of LB2
MSB of Delta2 (DELTA2(31)) is 221.
3ROLFLQJ5$0'ZRUG
Bit 31
Parity Bit of Dword10
Odd Parity over address and data.
Bit 30:28
Not used.
Bit 27
SHOW_PARAM used only for testing. Don’t change the contents.
F5E2E_U/D(1:0) Coding of F5 end to end cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
F4E2E_U/D(1:0) Coding of F4 end to end cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
Data Sheet
3-73
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
F5SEG_U/D(1:0) Coding of F5 segment cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
F4SEG_U/D(1:0) Coding of F4 segment cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
F5RM_U/D(1:0)
Coding of F5RM cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
F4RM_U/D(1:0)
Coding of F4RM cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
USER_U/D(1:0) Coding of User cell policing option flags:
00
No policing.
01
Down path (LB3).
10
Upper path (LB1 and LB2)
11
No policing.
MODE(1:0)
Data Sheet
POLU operating mode.
00
Tagging option is on
Parameters of LB1 are:
Parameter of LB2 is:
Parameter of LB3 is:
01
Tagging option is off
Parameters of LB1 are:
Parameter of LB2 is:
Parameter of LB3 is:
10
Tagging option is off
Parameters of LB1 are:
Parameter of LB2 is:
Parameter of LB3 is:
11
Tagging option is off
Parameters of LB1 are:
Parameter of LB2 is:
Parameter of LB3 is:
3-74
SCR0 and MBS0
PCR0+1
PCR0+1
SCR0 and MBS0
PCR0+1
PCR0+1
SCR0+1 and MBS0+1
PCR0+1
PCR0+1
PCR0+1
disabled
PCR0+1
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
DIS_U/D(1:0)
1RWH
'LVDEOLQJPHDQV7KHVWDWHYDULDEOHVDQGWKHFRXQWHUVRIWKHQRQFRQIRUPLQJFHOOVDUHXSGDWHGEXWWKH
FHOOVDUHQHLWKHUGLVFDUGHGRUWDJJHG
DELTA3(31:23)
'ZRUG
Disable connection flag for upper/down path.
00
normal policing
01
down path disabled
10
upper path disabled
11
down and upper path disabled
Policing parameter Delta3 of LB3
MSB of Delta3 (DELTA3(31)) is 221.
&RQQHFWLRQ5$08SVWUHDP
7
VPC specific total incoming cells with CLP=0 (= P_TIC0)
6
VPC specific total incoming cells (= P_TIC)
5
Counter (Total tagged cells) (= TTC)
4
Counter (Total discarded cells with CLP=0) (= TDC0)
3
Counter (Total discarded cells with CLP=1) (= TDC1)
2
Total incoming cells with CLP=0 (= TIC0)
1
Total incoming cells (= TIC)
F5PT_ F4PT_
21 20 19 HK(2:0) 15 14
CFG(2:0) CFG(2:0)
CMR(4:0) = 00001
0 31 30
28
LCI2_UP(13:0)
&RQQHFWLRQ5$08SVWUHDP'ZRUG
Header translation connection data up.
Bit 31
Parity
Odd Parity over address and data (look at remarks for Read/Write registers
in ALP Registers Detailed Description).
Bit 30
P_IP
Reserved for future functions.
Bit 29
Not used.
Bit 28
CC_IP_COPY
0
Forward cells
1
Continuity Check (CC) OAM cells are copied at intermediate points
(IP) (used for OAM Light).
Data Sheet
3-75
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
F5PT_CFG(2:0) F5 (channel specific) point configuration (used for OAM Light). The
subsequent layer point codings are possible :
000 No F5 layer point
010 F5 OEP (originating end point)
011 F5 OSP (originating segment point)
100 F5 IP (intermediate point)
110 F5 TSP (terminating segment point)
111 F5 TEP (terminating end point)
F4PT_CFG(2:0) F4 (path specific) point configuration (used for OAM Light). The subsequent
layer point codings are possible :
000 No F4 layer point
010 F4 OEP (originating end point)
011 F4 OSP (originating segment point)
100 F4 IP (intermediate point)
110 F4 TSP (terminating segment point)
111 F4 TEP (terminating end point)
Bit 21
LB_IP_DROP
Default LB action on IP points (used by cell type recognition) :
0
Forward cells.
1
Drop OAM cells of type LB at intermediate points.
Bit 20
AR_IP_COPY
Default OAM action on IP points (used by cell type recognition) :
0
Forward cells.
1
Copy OAM cells of type AIS/RDI at intermediate points.
Bit 19
VCON_UP
0
Invalid connection.
1
Valid connection indicated.
HK(2:0)
Bit 15
House Keeping bits.
INC_TIMC_SSD
1
Increment the Total Incoming Management Cells special studies
counter upstream at cell emission on this VC.
Bit 14
EN_TRAF_MEAS_UP
1
Enable traffic measurements (independently of VCON).
LCI2_UP(13:0)
F4 data pointer.
Data Sheet
3-76
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
&RQQHFWLRQ5$0GRZQVWUHDP
6
VP specific total outgoing cells with CLP=0 (= P_TOC0)
5
VPC specific total outgoing cells (= P_TOC)
4
Total outgoing cells with CLP=0 (= TOC0)
3
Total outgoing cells (= TOC)
PN_UT_DO
(4:0)
2 31
1 31 30 29 28
VPI_DO(11:0)
F5CFG F4CFG
23 22
(2:0)
(2:0)
CMR(4:0) = 00010
0 31 30
14
NEXT_LCI(13:0)
VCI_DO(15:0)
PNUDF(5:0)
15 14
LCI2_DO(13:0)
&RQQHFWLRQ5$0GRZQVWUHDP'ZRUG
Header translation connection data down (Flags, LCI2, PN).
Bit 31
Parity
Odd Parity over address and data (look at remarks for Read/Write registers
in ALP Registers Detailed Description).
Bit 30
P_IP
0
Path End Point.
1
Path Intermediate Point. At Path Intermediate Points only a VPI
header translation takes place.
F5CFG(2:0)
F5 (channel specific) point configuration (used for OAM Light). The
subsequent layer point codings are possible :
000 No F5 layer point
010 F5 OEP (originating end point)
011 F5 OSP (originating segment point)
100 F5 IP (intermediate point)
110 F5 TSP (terminating segment point)
111 F5 TEP (terminating end point)
F4CFG(2:0)
F4 (path specific) point configuration (used for OAM Light). The subsequent
layer point codings are possible :
000 No F4 layer point
010 F4 OEP (originating end point)
011 F4 OSP (originating segment point)
100 F4 IP (intermediate point)
110 F4 TSP (terminating segment point)
111 F4 TEP (terminating end point)
Data Sheet
3-77
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
Bit 23
EN_TRAF_MEAS_DO
1
Enable traffic measurements of all connection specific counters of this
specific connection (independently of VCON-bit).
Bit 22
VCON_DO
1
Indicates that this connection is valid.
PNUDF(5:0)
New portnumber (PN) that is mapped into the UDF1 field of the outgoing cell
header (mapping will be always done independently of selected portnumber
mode).
INC_TOF5RMC_SSD
Increment the Total Outgoing Resource Management Cells special studies
counter downstream (counter POTOCOR) at F5 RM cell emission on this VC.
INC_TOMC_SSD
Increment the Total Outgoing Cells special studies counter downstream
(counter POTOCOR) at cell emission on this VC.
The LCI2 is a F4 data pointer which addresses the path specific counters.
Bit 15
Bit 14
LCI2_DO(13:0)
&RQQHFWLRQ5$0GRZQVWUHDP'ZRUG
Header translation connection data down (VPI,VCI).
Bit 31
Parity
Odd Parity over address and data.
Bit 30
CC_IP_COPY
0
Forward cells.
1
Copy OAM cells of type CCA/CC at intermediate points.
Bit 29
LB_IP_DROP
Default LB action on IP points (used by cell type recognition) :
0
Forward cells.
1
Drop OAM cells of type LB at intermediate points.
Bit 28
AR_IP_COPY
Default OAM action on IP points (used by cell type recognition) :
0
Forward cells.
1
Copy OAM cells of type AIS/RDI at intermediate points.
VPI_DO(11:0)
VCI_DO(15:0)
New VPI for Header Translation.
New VCI for Header Translation.
&RQQHFWLRQ5$0GRZQVWUHDP'ZRUG
LCI of the following connection in the multicast chain.
Bit 31
Parity
Odd Parity over address and data.
Bit 30:21
Not used.
PN_UT_DO(4:0) UT-PN, used if MODE(11) = ’0’.
Bit 15
Not used.
Data Sheet
3-78
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
Bit 14
MC_ANCHOR
0
Indicates the end of the linked list in MC.
1
The NEXT_LCI pointer (b.13..0) is valid.
NEXT_LCI(13:0) LCI of the following connection in the multicast chain.
7UDIILF0HDVXUHPHQW5$03RUW7DEOH
'ZRUG
3RUW7DEOH8SVWUHDP
Counter POTIC_F for :
47 Total incoming cells at port number 15
...
...
Counter POTIC_0 for :
32 Total incoming cells at port number 0
Counter POTICOR_C7 for :
31 Total incoming OAM or RM cells enabled per connection at port number CNTPORT7_U
Counter POTIC_C7 for :
30 Total incoming cells at port number CNTPORT7_U
Counter POTICN_C7 for :
29 Total incoming cells with non-zero GFC-field at port number CNTPORT7_U
Counter PDC_C7 for :
28 Total discarded cells due to unallocated PN/VPI/VCI at port number CNTPORT7_U
...
...
Counter POTICOR_C0 for :
3 Total incoming OAM or RM cells enabled per connection at port number CNTPORT0_U
Counter POTIC_C0 for :
2 Total incoming cells at port number CNTPORT0_U
Counter POTICN_C0 for :
1 Total incoming cells with non-zero GFC-field at port number CNTPORT0_U
Counter PDC_C0 for :
0 Total discarded cells due to unallocated PN/VPI/VCI at port number CNTPORT0_U
CMR(4:0) = 00011;
Data Sheet
3-79
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
$GGUHVVLQJYLD/&,RI$'5UHJLVWHU
$GGUHVV
'ZRUG
0H
0-7
1H
8 - 15
2H
16 - 23
3H
24 - 31
4H
32 - 39
5H
40 - 47
6H - 3FFFH
no action
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
0
PDC_C0
0
PDC_C2
1
POTICN_C0
1
POTICN_C2
2
POTIC_C0
2
POTIC_C2
3
POTICOR_C0
3
POTICOR_C2
4
PDC_C1
4
PDC_C3
5
POTICN_C1
5
POTICN_C3
6
POTIC_C1
6
POTIC_C3
7
POTICOR_C1
7
POTICOR_C3
8-A
not used
8-A
not used
Data Sheet
3-80
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
0
PDC_C4
0
PDC_C6
1
POTICN_C4
1
POTICN_C6
2
POTIC_C4
2
POTIC_C6
3
POTICOR_C4
3
POTICOR_C6
4
PDC_C5
4
PDC_C7
5
POTICN_C5
5
POTICN_C7
6
POTIC_C5
6
POTIC_C7
7
POTICOR_C5
7
POTICOR_C7
8-A
not used
8-A
not used
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
0
POTIC_0
0
POTIC_8
1
POTIC_1
1
POTIC_9
2
POTIC_2
2
POTIC_A
3
POTIC_3
3
POTIC_B
4
POTIC_4
4
POTIC_C
5
POTIC_5
5
POTIC_D
6
POTIC_6
6
POTIC_E
7
POTIC_7
7
POTIC_F
8-A
not used
8-A
not used
Data Sheet
3-81
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
3RUW7DEOH'RZQVWUHDP
Counter POTOC_F for :
31 Total outgoing cells at port number 15
...
...
Counter POTOC_0 for :
16 Total outgoing cells at port number 0
Counter POTOCOR_C7 for :
15 Total outgoing OAM or RM cells or discarded F5RM cells enabled per connection at port
number CNTPORT7_D
Counter POTOC_C7 for :
14 Total outgoing cells at port number CNTPORT7_D
...
...
Counter POTOCOR_C0 for :
1 Total outgoing OAM or RM cells or discarded F5RM cells enabled per connection at port
number CNTPORT0_D
Counter POTOC_C0 for :
0 Total outgoing cells at port number CNTPORT0_D
CMR(4:0) = 00100;
$GGUHVVLQJYLD/&,RI$'5UHJLVWHU
$GGUHVV
'ZRUG
0H
0-7
1H
8 - 15
2H
16 - 23
3H
24 - 31
4H - 3FFFH
no action
Read out with CMR register. TM counters addressed by LCI value of ADR register.
Data Sheet
3-82
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
0
POTOC_C0
0
POTOC_C4
1
POTOCOR_C0
1
POTOCOR_C4
2
POTOC_C1
2
POTOC_C5
3
POTOCOR_C1
3
POTOCOR_C5
4
POTOC_C2
4
POTOC_C6
5
POTOCOR_C2
5
POTOCOR_C6
6
POTOC_C3
6
POTOC_C7
7
POTOCOR_C3
7
POTOCOR_C7
8-A
not used
8-A
not used
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
'DWDWRIURP5'5:'5UHJLVWHUDW
DGGUHVV+LQ$'5UHJLVWHU
'ZRUG
&RXQWHU
0
POTOC_0
0
POTOC_8
1
POTOC_1
1
POTOC_9
2
POTOC_2
2
POTOC_A
3
POTOC_3
3
POTOC_B
4
POTOC_4
4
POTOC_C
5
POTOC_5
5
POTOC_D
6
POTOC_6
6
POTOC_E
7
POTOC_7
7
POTOC_F
8-A
not used
8-A
not used
Data Sheet
3-83
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&HOO7\SH)LOWHU5HJLVWHUV
up/down
celltype
Read/write Address controlled by CMR command
Value after reset occur via µP initialization
Data structure of extended cell header...
11
01 5
02 0 7
VPI
VCI
PT C
...is compared with data structure of masked cell filter :
07
UDF1
07
UDF2
0
1st payload
U 1 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTU1 CT_FILTU2 CT_FILTP1
_U1(7:0)
_U1(7:0)
_U1(7:0)
_U1(7:0)
_U1(7:0)
_U1(7:0)
_U1(7:0)
U 1 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTU1 CT_FILTU2 CT_FILTP1
_U1(15:8) _U1(15:8) _U1(15:8) _U1(15:8) _U1(15:8) _U1(15:8) _U1(15:8)
U 2 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTU2 CT_FILTU2 CT_FILTP1
_U2(7:0)
_U2(7:0)
_U2(7:0)
_U2(7:0)
_U2(7:0)
_U2(7:0)
_U2(7:0)
U 2 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTU2 CT_FILTU2 CT_FILTP1
_U2(15:8) _U2(15:8) _U2(15:8) _U2(15:8) _U2(15:8) _U2(15:8) _U2(15:8)
D 1 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTD1 CT_FILTU2 CT_FILTP1
_D1(7:0)
_D1(7:0)
_D1(7:0)
_D1(7:0)
_D1(7:0)
_D1(7:0)
_D1(7:0)
D 1 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTD1 CT_FILTU2 CT_FILTP1
_D1(15:8) _D1(15:8) _D1(15:8) _D1(15:8) _D1(15:8) _D1(15:8) _D1(15:8)
D 2 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTD2 CT_FILTU2 CT_FILTP1
_D2(7:0)
_D2(7:0)
_D2(7:0)
_D2(7:0)
_D2(7:0)
_D2(7:0)
_D2(7:0)
D 2 CT_FILTH1 CT_FILTH2 CT_FILTH3 CT_FILTH4 CT_FILTD2 CT_FILTU2 CT_FILTP1
_D2(15:8) _D2(15:8) _D2(15:8) _D2(15:8) _D2(15:8) _D2(15:8) _D2(15:8)
7
Data Sheet
07
07
07
07
3-84
07
07
0
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
5HJLVWHUIRU3URJUDPPDEOH&HOO7\SH)LOWHULQ8SVWUHDP
3
CT_FILTP1_U1(15:0)
2
CT_FILTU1_U1(15:0)
CT_FILTU2_U1(15:0)
1
CT_FILTH3_U1(15:0)
CT_FILTH4_U1(15:0)
0
CT_FILTH1_U1(15:0)
C T_FILTH2_U1(15:0)
CMR(4:0) = 00101; write/read depicted data format to/from WDR0..3/RDR0..3 registers.
1RWH
0DVNELW
¶¶LVGRQ¶WFDUH
¶¶XVH)LOWHUELWIRUFRPSDULVRQ
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH2_U1(15:8)
Filter1 for header byte 2.
CT_FILTH2_U1(7:0)
Mask for filter 1 for header byte 2.
CT_FILTH1_U1(15:8)
Filter1 for header byte 1.
CT_FILTH1_U1(7:0)
Mask for filter 1 for header byte 1.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH4_U1(15:8)
Filter1 for header byte 4.
CT_FILTH4_U1(7:0)
Mask for filter 1 for header byte 4.
CT_FILTH3_U1(15:8)
Filter1 for header byte 3.
CT_FILTH3_U1(7:0)
Mask for filter 1 for header byte 3.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTU2_U1(15:8)
Filter1 for UDF2.
CT_FILTU2_U1(7:0)
Mask for filter UDF2.
CT_FILTU1_U1(15:8)
Filter1 for UDF1.
CT_FILTU1_U1(7:0)
Mask for filter 1 UDF1.
%\WHRI&HOO7\SH)LOWHU'ZRUG
Bit (31:16)
Not used.
CT_FILTP1_U1(15:8)
Filter1 for payload byte 1.
CT_FILTP1_U1(7:0)
Mask for filter 1 for payload byte 1.
Data Sheet
3-85
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
5HJLVWHUIRU3URJUDPPDEOH&HOO7\SH)LOWHULQ8SVWUHDP
3
CT_FILTP1_U2(15:0)
2
CT_FILTU1_U2(15:0)
CT_FILTU2_U2(15:0)
1
CT_FILTH3_U2(15:0)
CT_FILTH4_U2(15:0)
0
CT_FILTH1_U2(15:0)
C T_FILTH2_U2(15:0)
CMR(4:0) = 00110; write/read depicted data format to/from WDR0..3/RDR0..3 registers.
1RWH
0DVNELW
¶¶LVGRQ¶WFDUH
¶¶XVH)LOWHUELWIRUFRPSDULVRQ
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH2_U2(15:8)
Filter2 for header byte 2.
CT_FILTH2_U2(7:0)
Mask for filter 2 for header byte 2.
CT_FILTH1_U2(15:8)
Filter2 for header byte 1.
CT_FILTH1_U2(7:0)
Mask for filter 2 for header byte 1.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH4_U2(15:8)
Filter2 for header byte 4.
CT_FILTH4_U2(7:0)
Mask for filter 2 for header byte 4.
CT_FILTH3_U2(15:8)
Filter2 for header byte 3.
CT_FILTH3_U2(7:0)
Mask for filter 2 for header byte 3.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTU2_U2(15:8)
Filter2 for UDF2.
CT_FILTU2_U2(7:0)
Mask for filter UDF2.
CT_FILTU1_U2(15:8)
Filter2 for UDF1.
CT_FILTU1_U2(7:0)
Mask for filter 2 UDF1.
%\WHRI&HOO7\SH)LOWHU'ZRUG
Bit (31:16)
Not used.
CT_FILTP1_U2(15:8)
Filter2 for payload byte 1.
CT_FILTP1_U2(7:0)
Mask for filter 2 for payload byte 1.
Data Sheet
3-86
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
5HJLVWHUIRU3URJUDPPDEOH&HOO7\SH)LOWHULQ'RZQVWUHDP
3
CT_FILTP1_D1(15:0)
2
CT_FILTU1_D1(15:0)
CT_FILTU2_D1(15:0)
1
CT_FILTH3_D1(15:0)
CT_FILTH4_D1(15:0)
0
CT_FILTH1_D1(15:0)
C T_FILTH2_D1(15:0)
CMR(4:0) = 01110; write/read depicted data format to/from WDR0..3/RDR0..3 registers.
1RWH
0DVNELW
¶¶LVGRQ¶WFDUH
¶¶XVH)LOWHUELWIRUFRPSDULVRQ
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH2_D1(15:8)
Filter1 for header byte 2.
CT_FILTH2_D1(7:0)
Mask for filter 1 for header byte 2.
CT_FILTH1_D1(15:8)
Filter1 for header byte 1.
CT_FILTH1_D1(7:0)
Mask for filter 1 for header byte 1.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH4_D1(15:8)
Filter1 for header byte 4.
CT_FILTH4_D1(7:0)
Mask for filter 1 for header byte 4.
CT_FILTH3_D1(15:8)
Filter1 for header byte 3.
CT_FILTH3_D1(7:0)
Mask for filter 1 for header byte 3.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTU2_D1(15:8)
Filter1 for UDF2.
CT_FILTU2_D1(7:0)
Mask for filter UDF2.
CT_FILTU1_D1(15:8)
Filter1 for UDF1.
CT_FILTU1_D1(7:0)
Mask for filter 1 UDF1.
%\WHRI&HOO7\SH)LOWHU'ZRUG
Bit (31:16)
Not used.
CT_FILTP1_D1(15:8)
Filter1 for payload byte 1.
CT_FILTP1_D1(7:0)
Mask for filter 1 for payload byte 1.
Data Sheet
3-87
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'ZRUG
5HJLVWHUIRU3URJUDPPDEOH&HOO7\SH)LOWHULQ'RZQVWUHDP
3
CT_FILTP1_D2(15:0)
2
CT_FILTU1_D2(15:0)
CT_FILTU2_D2(15:0)
1
CT_FILTH3_D2(15:0)
CT_FILTH4_D2(15:0)
0
CT_FILTH1_D2(15:0)
C T_FILTH2_D2(15:0)
CMR(4:0) = 01111; write/read depicted data format to/from WDR0..3/RDR0..3 registers.
1RWH
0DVNELW
¶¶LVGRQ¶WFDUH
¶¶XVH)LOWHUELWIRUFRPSDULVRQ
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH2_D2(15:8)
Filter2 for header byte 2.
CT_FILTH2_D2(7:0)
Mask for filter 2 for header byte 2.
CT_FILTH1_D2(15:8)
Filter2 for header byte 1.
CT_FILTH1_D2(7:0)
Mask for filter 2 for header byte 1.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTH4_D2(15:8)
Filter2 for header byte 4.
CT_FILTH4_D2(7:0)
Mask for filter 2 for header byte 4.
CT_FILTH3_D2(15:8)
Filter2 for header byte 3.
CT_FILTH3_D2(7:0)
Mask for filter 2 for header byte 3.
%\WHDQGRI&HOO7\SH)LOWHU'ZRUG
CT_FILTU2_D2(15:8)
Filter2 for UDF2.
CT_FILTU2_D2(7:0)
Mask for filter UDF2.
CT_FILTU1_D2(15:8)
Filter2 for UDF1.
CT_FILTU1_D2(7:0)
Mask for filter 2 UDF1.
%\WHRI&HOO7\SH)LOWHU'ZRUG
Bit (31:16)
Not used.
CT_FILTP1_D2(15:8)
Filter2 for payload byte 1.
CT_FILTP1_D2(7:0)
Mask for filter 2 for payload byte 1.
Data Sheet
3-88
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
3RUW&RQILJXUDWLRQ5HJLVWHUV
With these registers every port can be configured individually as UNI (User to Network Interface)
with reduced 8 bit address range or NNI (Network to Network Interface) with full address range
of up to 12 bit.
3RUW&RQILJXUDWLRQ81,81,3257/
Read/write Address 2EH
Value after reset 0000H
UNI(15:8)
UNI(7:0)
UNI(15:0)
0
1
NNI-Port (i.e. up to 12 bits of VPI will be used for address reduction
depending on the number of port number bits ⇒ see MODE register
6HFWLRQpage 110)
UNI-port (i.e. only 8 bit of VPI will be used for address reduction)
3RUW&RQILJXUDWLRQ81,81,3257+
Read/write Address 2FH
Value after reset 0000H
unused
UNI(23:16)
unused(15:8)
UNI(23:16)
Fixed to zero.
0
1
Data Sheet
NNI-Port (i.e. up to 12 bits of VPI will be used for dress reduction
depending on the number of port number bits ⇒ see MODE register
6HFWLRQpage 110)
UNI-port (i.e. only 8 bit of VPI will be used at address reduction)
3-89
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&$0('DWD5HJLVWHUV
These registers are programmed with the full-length input address (PN / VPI / VCI) of 32 bit
length which shall be assigned to the reduced LCI (Local Connection Identifier) of 14 bit length
in the CAME.
&$0$'5/
Read/write Address 32H
Value after reset 0000H
CAMADRL(15:8)
CAMADRL(7:0)
CAMADRL(15:0) Data (i.e. VCI) which is stored in the CAME under the address LCI specified
in the ADR register. Responds of the CAME for the following CAME
commands defined in CMR register (see SDJH ) :
00111 ’read a line from the CAME ...’
01000 ’write a line into the CAME ...’
01001 ’write a line into the CAME and one entry to Connection ...’
01011 ’CAME test ...’
&$0$'5+
Read/write Address 33H
Value after reset 0000H
CAMADRH(15:8)
CAMADRH(7:0)
CAMADRH(15:0) Data (i.e. PN / VPI) which is stored in the CAME under the address LCI
specified in the ADR register. Responds of the CAME for the following CAME
commands defined in CMR register (see SDJH ) :
00111 ’read a line from the CAME ...’
01000 ’write a line into the CAME ...’
01001 ’write a line into the CAME and one entry to Connection ...’
Data Sheet
3-90
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
32/8&RQILJXUDWLRQ5HJLVWHU
With P_CONR_L and P_CONR_H the POLU (Policing Unit) is configured for normal mode as
well as for test modes. In the test mode ’Show selected policing values ...’ the results are loaded
in the registers P_STATR0 ... P_STATR2.
32/8&RQILJXUDWLRQ5HJLVWHU3B&215/
Read/write Address 36H
Value after reset 00FFH
COM(9:2)
COM(1:0)
1RWH
TOM
INC COUNT INH(2:0)
DISC INH TAG INH
7KH FRQWHQWV RI 3B&215/ DQG 3B&215+ ZLOO EH WUDQVIHUUHG WRJHWKHU WR WKH 32/8 RQO\ LI ELW
9$/,'B&21)LQ3B&215+LVVHWWR
COM(9:0)
TOM
Only for Test. Don’t change the contents for normal policing operation.
0
1
INC COUNT INH(2:0)
0
Normal Operation Mode.
Test Operation Mode (only for Testing).
1
The corresponding PH_INCR_COUNTER-pulse is suppressed for all
connections.
The pulse is transmitted.
0
1
’Cell discard’ indication is suppressed for all connections.
Cell discard enabled.
0
1
’Tag cell’ indication is suppressed for all connections.
Tagging is enabled.
DISC INH
TAG INH
Data Sheet
3-91
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
32/8&RQILJXUDWLRQ5HJLVWHU3B&215+
Read/write Address 37H
Value after reset 0000H
VALID_
CONF
COM(24:18)
COM(17:10)
1RWH
7KH FRQWHQWV RI 3B&215/ DQG 3B&215+ ZLOO EH WUDQVIHUUHG WRJHWKHU WR WKH 32/8 RQO\ LI ELW
9$/,'B&21)LQ3B&215+LVVHWWR
VALID_CONF
0
1
COM(24:10)
Data Sheet
The content of the register has already been transferred to the POLU.
The register has been written into by the µP, but it has QRWbeen
synchronized by the POLU yet.
Only for Test. Don’t change the contents for normal policing operation.
3-92
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
9HUVLRQ5HJLVWHU
The Version register provides a Version number for system management purposes. The Version
number is identical with the boundary scan ID code.
9(5/
Read Address 40H
Value after reset 9069H
VERL(15:8)
VERL(7:0)
VERL(15:0)
Version of the ALP (low part): 1001 0000 0110 1001
9(5+
Read Address 41H
Value after reset 523BH
VERH(15:8)
VERH(7:0)
VERH(15:0)
Data Sheet
Version of the ALP (high part): 0101 0010 0011 1011
3-93
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7UDQVPLW&HOO5HJLVWHUV7;5
These are registers used by µP to insert a cell into the cell flow upstream or downstream.
7UDQVPLW&HOO5HJLVWHU7;5
Read/write Address 50H
Value after reset 0000H
word0(15:8)
word0(7:0)
word0(15:0)
Upstream with header translation:
UNI: GFC[3:0] / VPI[7:0] / VCI[15:12]
NNI: VPI[11:0] / VCI[15:12]
Upstream without header translation:
LCI[11:0] / VCI[15:12]
Downstream with header translation:
LCI[11:0] / VCI[15:12]
Downstream without header translation:
UNI: GFC[3:0] / VPI[7:0] / VCI[15:12]
NNI: VPI[11:0] / VCI[15:12]
7UDQVPLW&HOO5HJLVWHU7;5
Read/write Address 51H
Value after reset 0000H
word1(15:8)
word1(7:0)
word1(15:0)
Data Sheet
VCI[11:0] / PTI[2:0] / CLP
3-94
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7UDQVPLW&HOO5HJLVWHU7;5
Read/write Address 52H
Value after reset 0000H
word2(15:8)
word2(7:0)
word2(15:0)
Upstream without header translation:
LCI[13:12] / HK[2:0] / unused[4:0] / E / PNUT[4:0]
Upstream with header translation:
unused[1:0] / PNPHY[5:0](*) / unused[1:0] / E / PNUT[4:0](*)
Downstream without header translation:
unused[1:0] / PNPHY[5:0] / unused[1:0] / E / PNUT[4:0]
Downstream with header translation:
LCI[13:12] / unused[7:0] / E / PNUT[4:0] :
E
Error Detection Code (CRC10):
0
No action.
1
Perform EDC.
PNUT[4:0]
Absolute port number UTOPIA.
PNPHY[5:0]
Port number of PHY-device:
0..63
For AN applications.
0..7
For PADACK applications.
1RWH
31VRXUFHDVSURJUDPPHGLQ02'(UHJLVWHU
Data Sheet
3-95
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7UDQVPLW&HOO5HJLVWHUV7;57;5
Read/write Address 53H...6AH
Value after reset 0000H (for all)
$GGU
1DPH
Payload byte 0
Payload byte 1
Payload byte 2
Payload byte 3
53
TXR3
54
TXR4
55
TXR5
Payload byte 4
Payload byte 5
56
TXR6
Payload byte 6
Payload byte 7
57
TXR7
Payload byte 8
Payload byte 9
55
TXR8
Payload byte 10
Payload byte 11
59
TXR9
Payload byte 12
Payload byte 13
5A
TXR10
Payload byte 14
Payload byte 15
5B
TXR11
Payload byte 16
Payload byte 17
5C
TXR12
Payload byte 18
Payload byte 19
5D
TXR13
Payload byte 20
Payload byte 21
5E
TXR14
Payload byte 22
Payload byte 23
5F
TXR15
Payload byte 24
Payload byte 25
60
TXR16
Payload byte 26
Payload byte 27
61
TXR17
Payload byte 28
Payload byte 29
62
TXR18
Payload byte 30
Payload byte 31
63
TXR19
Payload byte 32
Payload byte 33
64
TXR20
Payload byte 34
Payload byte 35
65
TXR21
Payload byte 36
Payload byte 37
66
TXR22
Payload byte 38
Payload byte 39
67
TXR23
Payload byte 40
Payload byte 41
68
TXR24
Payload byte 42
Payload byte 43
66
TXR25
Payload byte 44
Payload byte 45
6A
TXR26
Payload byte 46
Payload byte 47
Data Sheet
3-96
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&RQILJXUDWLRQRI7UDQVPLW&HOO%XIIHU7;5B&21),*
Read/write Address 6BH
Value after reset 0000H
unused
TRANSM_
DIR
unused
unused(15:3)
TRANSM_DIR
HTON
START
_TR
Fixed to zero.
0
1
Transmit a cell upstream.
Transmit a cell downstream.
0
1
Without header translation.
Header translation on.
0
1
No action.
Start transmission from transmit cell buffer TXR (this bit is reset by the
ASIC after transmission).
HTON
START_TR
1RWH
,WLVVWURQJO\UHFRPPHQGHGQRWWRVWDUWWKHWUDQVPLVVLRQXSVWUHDPZKLOHWKH875;),)2B29B8ELWLVVHW
WRLQSXWTXHXHRYHUIORZRI8723,$UHFHLYHXSVWUHDPLQWHUIDFH
,WLVVWURQJO\UHFRPPHQGHGQRWWRVWDUWWKHWUDQVPLVVLRQGRZQVWUHDPZKLOHWKH%29ELWRI,65RUWKH
87B429ELWRIWKHFRUUHVSRQGLQJSRUWLVVHWWREXIIHUTXHXHRYHUIORZRIVWDWLVWLFDOGHPXOWLSOH[LQJEXIIHU
LQ8723,$WUDQVPLWGRZQVWUHDPLQWHUIDFH
5HFHLYH5HJLVWHU5HFHLYH&HOO%XIIHU5;5
Read Address 70H
Value after reset undefined
word n(15:8)
word n(7:0)
This 16 bit read-only register is used for access to the Receive Cell Buffer. There is one common
Receive Cell Buffer for up- and downstream direction that can store 12 cells at maximum. With
RXR the Receive Cell Buffer is read in the order octet number 0 to octet number 55.
1RWH
&HOOV ZLWK KHDGHU WUDQVODWLRQ LQVHUWHG E\ WKH µ3 YLD 7UDQVPLW &HOO %XIIHU FDQ GLUHFWO\ EH GURSSHG WR
5HFHLYH&HOO%XIIHU
&HOOVZLWKRXWKHDGHUWUDQVODWLRQLQVHUWHGE\WKHµ3YLD7UDQVPLW&HOO%XIIHUFDQQRWEHGURSSHGWR5HFHLYH
&HOO%XIIHU+RZHYHUIRUWHVWSXUSRVHVWKLVFDQEHDFKLHYHGE\GLUHFWO\IRUZDUGLQJDFHOOIURP7;5WR5;5
XVLQJELWRIUHJLVWHU7(675/223B7;5;
Data Sheet
3-97
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
word 0(15:8)
word 0(7:0)
word 1(15:8)
word 1(7:0)
word 2(15:8)
1RWH
Upstream:
UNI: GFC[3:0] / VPI[7:4]
NNI: VPI[11:4]
Downstream:
LCI[11:4]
Upstream:
VPI[3:0] / VCI[15:12]
Downstream:
LCI[3:0] / VCI[15:12]
VCI[11:4]
VCI[3:0] / PTI[2:0] / CLP
Upstream:
Unused[1:0] / PNPHY[5:0].
Downstream:
LCI[13:12] / HK[2:0] / unused[2:0].
PNPHY[5:0]
Port number of PHY-device:
0..63
For AN applications.
313+<>@UHSUHVHQWVWKHSRUWQXPEHURI,:(LQXSVWUHDPGLUHFWLRQ
word 2(7:0)
Unused[1:0] / D / PNUT[4:0]
D
Direction:
0
Downstream
1
Upstream
PNUT[4:0]
Absolute port number UTOPIA.
word 3(15:8)
word 3(7:0)
...
word 26(15:8)
word 26(7:0)
word 27(15:8)
Payload byte 0.
Payload byte 1.
...
Payload byte 46.
Payload byte 47.
CELLTYPE[5:0] / unused[1:0]
CELLTYPE[5:2]
0000
User cell.
0001
RM (Resource Management) cell.
0010
PCF1 (extracted by Programmable Cell Filter 1) cell.
0011
PCF2 (extracted by Programmable Cell Filter 2) cell.
0100
F5RES (F5 reserved for future functions with PTI=111)
cell (only downstream).
0101
COC (cross office check) cell (only downstream).
0111
DBA (dynamic bandwidth allocation) cell.
1000
AIS (alarm indication signal) cell.
1001
RDI (remote defect indication) cell.
1010
CCA (continuity check activation) cell.
Data Sheet
3-98
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
word 27(7:0)
1011
1100
1111
CELLTYPE[1]
0
1
CELLTYPE[0]
0
1
Unused[7:0]
CC (continuity check) cell.
LB (loop back) cell.
Undef (undefined oamtype) cell.
Seg (segment) cell
Ete (end_to_end) cell
F4 (virtual path) cell
F5 (virtual channel) cell
+HDGHU&DSWXUH3URWRFRO0RQLWRULQJ5HJLVWHU6HW8SVWUHDP
For the upstream direction 4 Protocol Monitoring Register sets are provided, one for each CLAV/
ENABLE-group.
At the ports specified in the HEADCAPEN-register always the header of the last cell discarded
due to ’ATM cell header error’ is logged in the corresponding PRMONR-buffer. Additionally the
flag HLOG in the STATR-register is set. During readout of one PRMONR-buffer the buffer is
locked. So every readout of a PRMONR-buffer has to be completed!
3URWRFRO0RQLWRULQJ%XIIHU8SVWUHDP350215$B8$B8
Read Address 72H, 75H, 78H, 7BH
Value after reset 0000H
UDF1(7:0)
UDF2(7:0)
UDF1(7:0)
UDF2(7:0)
User Defined Byte1 (unused[1:0] / PNPHY[5:0]).
User Defined Byte2 (CLAV-group[1:0] / 1 / PNUT[4:0]).
3URWRFRO0RQLWRULQJ%XIIHU8SVWUHDP350215%B8%B8
Read Address 73H, 76H, 79H, 7CH
Value after reset 0000H
VCI(11:4)
VCI(3:0)
VCI(11:0)
PTI(2:0)
CLP
Data Sheet
PTI(2:0)
CLP
Virtual Channel Identifier
Payload Type Identifier
Cell Loss Priority
3-99
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
3URWRFRO0RQLWRULQJ%XIIHU8SVWUHDP350215&B8&B8
Read Address 74H, 77H, 7AH, 7DH
Value after reset 0000H
GFC(3:0) / VPI(11:8)
VPI(7:4)
VPI(3:0)
VCI(15:12)
GFC(3:0)/VPI(11:8)At UNI: Generic Flow Control (GFC)
At NNI: Virtual Path Identifier (VPI)
VPI(7:0)
Virtual Path Identifier
VCI(15:12)
Virtual Channel Identifier
+HDGHU&DSWXUH3URWRFRO0RQLWRULQJ5HJLVWHU6HW'RZQVWUHDP
For the downstream direction only 1 Protocol Monitoring Register set is provided for all CLAV/
ENABLE-groups.
The header of cells discarded due to ’internal cell header error’ is logged in the PRMONR-buffer.
Additionally the flag HLOG in the STATR-register is set. During readout of one PRMONR-buffer
the buffer is locked. So every readout of the PRMONR-buffer has to be completed!
3URWRFRO0RQLWRULQJ%XIIHU'RZQVWUHDP350215$B'
Read Address 7EH
Value after reset 0000H
UDF1(7:0)
UDF2(7:0)
UDF1(7:0)
User defined field 1:
7:6
Two MSBits of Local Connection Identifier (LCI (13:12)).
5:3
HK Bits.
UDF2(7:0)
Port number from UTOPIA Rx downstream:
4:0
PN_UT_DN(4:0).
Data Sheet
3-100
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
3URWRFRO0RQLWRULQJ%XIIHU'RZQVWUHDP350215%B'
Read Address 7FH
Value after reset 0000H
VCI(11:4)
VCI(3:0)
VCI(11:0)
PTI(2:0)
CLP
PTI(2:0)
CLP
Virtual Channel Identifier.
Payload Type Identifier.
Cell Loss Priority.
3URWRFRO0RQLWRULQJ%XIIHU'RZQVWUHDP350215&B'
Read Address 80H
Value after reset 0000H
LCI(11:4)
LCI(3:0)
LCI(11:0)
VCI(15:12)
VCI(15:12)
Local Connection Identifier.
Virtual Channel Identifier.
3URWRFRO0RQLWRULQJ&RQILJXUDWLRQ5HJLVWHU+($'&$3(1
Read/write Address 81H
Value after reset 0000H
unused
unused
EN_D
EN3_U
EN2_U
EN1_U
EN0_U
This register enables/disables the Protocol Monitoring Sets upstream and downstream.
unused(10:0)
Fixed to zero.
EN_D
0
Disables capturing of cells from Clav-group 0-3 in register
PRMONR_D.
1
Enables capturing of cells from Clav-group 0-3 in register
PRMONR_D.
Data Sheet
3-101
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
EN3_U
0
1
EN2_U
0
1
Disables capturing of cells from CLAV-group3 in register
PRMONR3_U.
Enables capturing of cells from CLAV-group3 in register
PRMONR3_U.
.
Disables capturing of cells from CLAV-group2 in register
PRMONR2_U.
Enables capturing of cells from CLAV-group2 in register
PRMONR2_U.
EN1_U
0
1
Disables capturing of cells from CLAV-group1 in register
PRMONR1_U.
Enables capturing of cells from CLAV-group1 in register
PRMONR1_U.
EN0_U
0
1
Disables capturing of cells from CLAV-group0 in register
PRMONR0_U.
Enables capturing of cells from CLAV-group0 in register
PRMONR0_U.
&RQILJXUDWLRQRI3RUWVSHFLILF&RXQWHUV8SVWUHDP
The portspecific counters are stored in an ASIC internal RAM. The contents of this RAM are not
affected by a SW-reset. Every counter has 32 bit length. In case of an overflow the counters
remain on the maximum count value of ‘FFFF’.
For each port0 .. 15 a ‘total incoming cell (POTIC)’-counter is provided, while port16 .. 23 don’t
have a ‘total incoming cell’-counter.
Additionally eight port specific countersets with special counters are provided which can be
assigned to any port by the registers PORTCONF0 .. 7_U.
If two of these eight countersets are configured to count cells from the same port only the
counterset with the lower number will be active.
3RUW6SHFLILF&RXQWHU&RQILJXUDWLRQ8SVWUHDP3257&21)B8B8
Read/write Address 84...8BH
Value after reset 0000H
unused
CNT_POTIC
CNT_POTIC
OR_ALL
CNT_
CNT_POR
POTICOR TENi_U
Data Sheet
OAM_
CNT_U
CNT_PORTi_U(5:0)
3-102
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
1RWH
3'&B&L7RWDOGLVFDUGHGFHOOVGXHWRXQDOORFDWHG3193,9&,DWSRUWL
327,&1B&L7RWDOLQFRPLQJFHOOVZLWKQRQ]HUR*)&ILHOGDWSRUWL
327,&B&L7RWDOLQFRPLQJFHOOVDWSRUWL
327,&25B&L 7RWDO LQFRPLQJ 2$050 FHOOV DW SRUW L %\ WKH IODJ ,1&B7,0&B66' ZRUG ELW RI
&RQQHFWLRQ5$0XSVWUHDPWKLVFRXQWHUFDQEHFRQQHFWLRQVSHFLILFDOO\HQDEOHG
unused(4:0)
Fixed to zero.
CNT_POTICOR_ALL Define the number of connections which are counted:
0
Counts cells in POTICOR_Ci for specific connections enabled by the
flag INC_TIMC_SSD in the connection RAM.
1
Counts cells in POTICOR_Ci for all connections independently of flag
INC_TIMC_SSD in the connection RAM.
CNT_POTIC
0
1
OAM_CNT_U
Disables the POTIC_Ci counter.
Enables the POTIC_Ci counter.
Configures the POTICOR counter:
0
Count RM cells in POTICOR_Ci.
1
Count OAM cells in POTICOR_Ci.
CNT_POTICOR
0
1
CNT_PORTENi_U
0
1
Disables the POTICOR_Ci counter.
Enables the POTICOR_Ci counter.
Disables the counters PDC_Ci and POTICN_Ci.
Enables the counters PDC_Ci and POTICN_Ci.
CNT_PORTi_U(5:0)
Upstream portnumber of the port at which cells will be counted in the
counters: PDC_Ci, POTICN_Ci, POTIC_Ci, POTICOR_Ci.
(1327,&
Read/write Address 8CH
Value after reset 0000H
ENPOTIC(15:8)
ENPOTIC(7:0)
1RWH
327,&7RWDOLQFRPLQJFHOOV
ENPOTIC(15:0)
Data Sheet
Enables counter POTIC at port 0-15.
3-103
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&RQILJXUDWLRQRI3RUWVSHFLILF&RXQWHUV'RZQVWUHDP
The portspecific counters are stored in an ASIC internal RAM. The contents of this RAM are not
affected by a SW-reset. Every counter has 32 bit length. In case of an overflow the counters
remain on the maximum count value of ‘FFFF’.
For each port0 .. 15 a ‘total incoming cell’-counter is provided, while port16 .. 23 have no ‘total
incoming cell’-counter.
Additionally eight port specific countersets with special counters are provided which can be
assigned to any port by the registers PORTCONF0 .. 7_D.
If two of these eight countersets are configured to count cells from the same port only the
counterset with the lower number will be active.
3257&21)B'B'
Read/write Address 8DH...94H
Value after reset 0000H
CNT_POTO CNT_
COR_ALL POTOC
unused
OAM_
CNT_D(0)
1RWH
OAM_
CNT_D(1)
unused
CNT_PORTi_D(5:0)
3272&B&L7RWDORXWJRLQJFHOOVDWSRUWL
3272&25B&L7RWDORXWJRLQJ2$050GLVFDUGHG)50FHOOVDWSRUWL%\WKHIODJ,1&B72)50&B66'
ZRUGELWRI&RQQHFWLRQ5DPGRZQVWUHDPWKLVFRXQWHUFDQEHFRQQHFWLRQVSHFLILFDOO\HQDEOHG
unused(5:1)
Fixed to zero.
CNT_POTOCOR_ALL
0
Counts cells in POTOCOR_Ci counter for specific connections
enabled by the flag INC_TOF5RMC_SSD or INC_TOMC_SSD in the
connection RAM. INC_TOF5RMC_SSD is evaluated if discarded
F5RM and PTI (111) cells are counted in the POTOCOR_Ci counter.
INC_TOMC_SSD is evaluated if OAM or RM cells are counted in the
POTOCOR_Ci counter
1
Counts cells in POTOCOR_Ci counter for all connections
independently of flag INC_TOF5RMC_SSD or INC_TOMC_SSD in
the connection RAM.
CNT_POTOC
0
1
Data Sheet
Disables the POTOC_Ci counter.
Enables the POTOC_Ci counter.
3-104
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
OAM_CNT_D(1:0)Configures and enables the POTICOR counter:
00
Disables the POTOCOR_Ci counter.
01
Counts OAM cells and enables the POTOCOR_Ci counter.
10
Counts RM cells and enables the POTOCOR_Ci counter.
11
Counts discarded F5RM and PTI(111) cells and enables the
POTOCOR_Ci counter.
unused(0)
Not fixed.
CNT_PORTi_D(5:0)
Downstream portnumber of the port at which cells will be counted in the
counters: POTOC_Ci, POTOCOR_Ci.
(13272&
Read/write Address 95H
Value after reset 0000H
ENPOTOC(15:8)
ENPOTOC(7:0)
ENPOTOC(15:0) Enables counter POTOC at port 15..0.
8723,$&RQILJXUDWLRQ5HJLVWHUV
With these registers the enabling/disabling and the mode of all ALP UTOPIA interfaces (UTRXU,
UTTXU, UTRXD, UTTXD) is configured.
8723,$&RQILJXUDWLRQ&2187$
Read/write Address 96H
Value after reset 0000H
UT_PORT_U(15:8)
UT_PORT_U (7:0)
UT_PORT_U(15:0)
0
1
Data Sheet
Disables UTOPIA port 15..0 upstream.
Enables UTOPIA port 15..0 upstream.
3-105
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
8723,$&RQILJXUDWLRQ&2187%
Read/write Address 97H
Value after reset 0000H
UT_PORT_D (23:16)
UT_PORT_U (23:16)
UT_PORT_D(23:16)
0
1
Disables UTOPIA port 23..16 downstream.
Enables UTOPIA port 23..16 downstream.
UT_PORT_U(23:16)
0
1
Disables UTOPIA port 23..16 upstream.
Enables UTOPIA port 23..16 upstream.
8723,$&RQILJXUDWLRQ&2187&
Read/write Address 98H
Value after reset 0000H
UT_PORT_D(15:8)
UT_PORT_D (7:0)
UT_PORT_D(15:0)
0
1
Disables UTOPIA port 15..0 downstream.
Enables UTOPIA port 15..0 downstream.
8723,$&RQILJXUDWLRQ&2187
Read/write Address 99H
Value after reset 0000H
UTP_
16BIT
UTP_
PAR
UTP_CONFIG(1:0)
UTA_
16BIT
UTA_
PAR
UTA_CONFIG(1:0)
unused
UTP_16BIT
0
1
Data Sheet
8bit data bus at PHY side.
16bit data bus at PHY side.
3-106
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
UTP_PAR
0
1
Don’t check parity of PHY receive data.
Check parity of PHY receive data.
UTP_CONFIG(1:0)
Configuration of mode at PHY side:
00
4 x 6 port
01
3 x 8 port
10
2 x 12 port
11
UTOPIA Level 1 (4 x 1 port)
UTA_16BIT
0
1
8bit data bus at ATM side.
16bit data bus at ATM side.
0
1
Don’t check parity of ATM receive data.
Check parity of ATM receive data.
UTA_PAR
UTA_CONFIG(1:0)
Configuration of mode at ATM side:
00
4 x 6 port
01
3 x 8 port
10
2 x 12 port
11
UTOPIA Level 1 (4 x 1 port)
unused(7:0)
Data Sheet
Fixed to zero.
3-107
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
8723,$&RQILJXUDWLRQ&2187
Read/write Address 9AH
Value after reset 003FH
FORCE_
EC_D
EC_MININT_D(6:0)
UT_VPN
unused
UT_THRESH(5:0)
FORCE_EC_D
0
1
No forcing of Empty Cycles downstream.
Force Empty Cycles downstream.
EC_MININT_D(6:0)
Minimal interval (in cell cycles) between 2 Empty Cycles downstream. This bit
is only valid if FORCE_EC_D is equal one.
UT_VPN
0
Don’t change incoming port number.
1
Change incoming port number 0 to1 (can be used to switch between
two LCI ranges for redundancy purposes).
unused
Fixed to zero.
UT_THRESH(5:0)
Queue threshold of UTOPIA demultiplexing buffer (each queue has the same
threshold).
Data Sheet
3-108
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
8723,$'RZQVWUHDP4XHXH2YHUIORZ,QGLFDWLRQ5HJLVWHUV
If a queue overflow occurs in the statistical demultiplexing buffer downstream, an UTOPIA
backpressure is generated for the preceding ASIC so that no further cells will be accepted. Cells
for this queue that are already inside the ALP (UTOPIA input buffer or workbench) will be still
added to the queue so that blocking will be avoided.
87B429
Read Address 9BH
Value after reset 0000H
1RWH
6LQJOHELWVRIWKLVUHJLVWHUDUHUHVHWWDEOHE\ZULWLQJDµ¶WRWKHP
QOV(15:8)
QOV (7:0)
QOV(15:0)
0
1
No queue overflow of port 15..0 at UTOPIA downstream PHY-side.
Queue overflow of port 15..0 at UTOPIA downstream PHY-side.
87B429
Read Address 9CH
Value after reset 0000H
1RWH
6LQJOHELWVRIWKLVUHJLVWHUDUHUHVHWWDEOHE\ZULWLQJDµ¶WRWKHP
unused
QOV (23:16)
unused(7:0)
QOV(23:16)
Fixed to zero.
0
1
Data Sheet
No queue overflow of port 23..16 at UTOPIA downstream PHY-side.
Queue overflow of port 23..16 at UTOPIA downstream PHY-side.
3-109
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&RQILJXUDWLRQRI+HDGHU7UDQVODWLRQ6SHFLDO(QDEOH%LWV
These registers configure the header translation (CAME or internal address reduction, number
of portnumber bits), select the port number source and provide two special Enable bits, one to
enable all traffic measurement counters and the other to enable write access to the registers
TESTR and BISTMODE1/2.
$'5('B93,0
Read/write Address 9EH
Value after reset 0000H
unused
VPIMIN(11:8)
VPIMIN(7:0)
unused(3:0)
VPIMIN(11:0)
Fixed to zero.
Minimal VPI used in address reduction algorithm without CAME (only valid if
bit CAM in MODE register is set to 1).
02'(
Read/write Address 9FH
Value after reset 0000H
unused
TESTR_EN COUNTEN
PN_SOUR PN_SOUR
CE_D
CE_U
M_NUMB(3:0)
unused(3:2)
TESTR_EN
P_NUMB(2:0)
unused
CAM
Fixed to zero.
0
1
The write access to TESTR-register and BIST-register is disabled.
The TESTR-register and the BIST-register are writable.
0
1
All traffic measurement counters will be stopped.
All traffic measurement counters will be enabled.
COUNTEN
PN_SOURCE_D Source of the portnumber downstream:
0
Connection RAM (CONNRAMDO)
1
UTOPIA
PN_SOURCE_U Source of the portnumber upstream:
0
UTOPIA
1
UDF1(5:0)
unused(1:0)
Data Sheet
Fixed to zero.
3-110
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
M_NUMB(3:0)
1RWH
Block size parameter (only valid if bit CAM=1).
,QFDVHRIDGGUHVVUHGXFWLRQZLWKRXW&$0(3B180% 0B180%RU0B180% OHDGVWRD&$0B(55
LQWHUUXSWDQGDOOFHOOVXSVWUHDPZLOOEHGLVFDUGHG
P_NUMB(2:0)
Number of portnumber bits which are mapped into the LCI (if bit CAM=1) or
PN / VPI / VCI supplied to CAME (if CAM=0;
5HPDUN P_NUMB = 7, 6, 5 leads to CAM_ERR interrupt, only P_NUMB =
4, 3, 2, 1, 0 is allowed !).
CAM
0
1
Address reduction with external Address Reduction Circuit (CAME
device PXB 4360 E).
Address reduction with internal Address Reduction Circuit.
&RPPDQG5HJLVWHU&05
Read/write Address A0H
Value after reset 0000H
SWRESET(3:0)
unused
unused
STREQ READONLY
MPREQDEF(4:0)
The command register provides and controls all kinds of possible µP requests.
SWRESET(3:0)
0110 Software reset (leads to an internal active low reset pulse).
1RWH
7KHZKROH$6,&LQFOXGLQJUHJLVWHUVDQG8723,$LQWHUIDFHVLVUHVHW2QO\WKHFRQWHQWVRIWKHLQWHUQDO
5$0VSRUWVSHFLILFFRXQWHUV5:5EXIIHU5;5EXIIHUDUHQRWDIIHFWHG
unused(3:0)
STREQ
Fixed to zero.
0
1
Unspecified.
Start of the specified request (the STREQ bit is reset by the ASIC
when the command is finished).
0
1
Write the specified data.
Read the specified data.
READONLY
MPREQDEF(4:0) MP-request definition:
00000 Read or write one entry from/to POLU RAM using the LCI in the
ADR register.
00001 Read or write one entry from/to connection RAM upstream using
the LCI in the ADR register. (5HPDUN at write accesses the new
LCI2 (defined in WDR0) is used to address VP specific data).
00010 Read or write one entry from/to connection RAM downstream using
the LCI in the ADR register (5HPDUN at write accesses the new
LCI2 (defined in WDR0) is used to address VP specific data).
Data Sheet
3-111
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Data Sheet
Read or write one entry from/to port table upstream using the ADR
register (see Appendix 1: Addressing of Port Table counters
upstream).
Read or write one entry from/to port table downstream using the
ADR register (see Appendix 1: Addressing of Port Table counters
downstream).
Read or write cell type filter 1 upstream (see Appendix 2: Structure/
Transmission Order of Cell Type Filters (x=U, y=1)).
Read or write cell type filter 2 upstream (see Appendix 2: Structure/
Transmission Order of Cell Type Filters (x=U, y=2)).
Read a line from the CAME using the LCI in the ADR register, the
VCI in CAMADRL and the PN/VPI in CAMADRH (not VCON and
P_IP, see page 3-75, <HLink>77, <HLink>128 and <HLink>136).
Write a line in the CAME using the LCI in the ADR register, the VCI
in CAMADRL and the PN/VPI in CAMADRH.
Write a line into the CAME and one entry to connection RAM
upstream using the LCI in the ADR register, the VCI in CAMADRL
and the PN/VPI in CAMADRH.
Not used.
CAME test using ADR register for CAME test configuration and
CAMADRL register for CAME test result (see [9]).
Transfer UPC/NPC parameters from the POLURAM to the POLU
Register File using the LCI in the ADR register. Only for test
purpose.
Transfer updated UPC/NPC parameters from the POLU Register
File to the POLURAM using the LCI in the ADR register. Only for
test purpose.
Read or write cell type filter 1 downstream (see Appendix 2:
Structure/Transmission Order of Cell Type Filters (x=D, y=1)).
Read or write cell type filter 2 downstream (see Appendix 2:
Structure/Transmission Order of Cell Type Filters (x=D, y=2)).
3-112
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
6WDWXV5HJLVWHUVIRU+HDGHU&DSWXUH&$0(
6WDWXV5HJLVWHUIRU+HDGHU&DSWXUH67$75
Read Address A1H
Value after reset 0000H
unused
unused
PMO_
PMO_
PMO_
PMO_
PMO_
HLOG_D HLOG3_U HLOG2_U HLOG1_U HLOG0_U
The STATR register provides the status of all Protocol Monitoring Sets upstream and
downstream.
unused(10:0)
Fixed to zero.
PMO_HLOG_D
0
No external header has been written to PRMONR_D.
1
Indication that downstream an external header has been written to
PRMONR_D. The bit is reset by the ALP after the completion of µP
read access to PRMONR_D.
PMO_HLOG3_U
0
1
No external header has been written to PRMONR3_U.
Indication that for a cell from CLAV-group 3 upstream an external
header has been written to PRMONR3_U. The bit is reset by the ALP
after the completion of µP read access to PRMONR3_U.
0
1
No external header has been written to PRMONR2_U.
Indication that for a cell from CLAV-group 2 upstream an external
header has been written to PRMONR2_U. The bit is reset by the ALP
after the completion of µP read access to PRMONR2_U.
0
1
No external header has been written to PRMONR1_U.
Indication that for a cell from CLAV-group 1 upstream an external
header has been written to PRMONR1_U. The bit is reset by the ALP
after the completion of µP read access to PRMONR1_U.
0
1
No external header has been written to PRMONR0_U.
Indication that for a cell from CLAV-group 0 upstream an external
header has been written to PRMONR0_U. The bit is reset by the ALP
after the completion of µP read access to PRMONR0_U.
PMO_HLOG2_U
PMO_HLOG1_U
PMO_HLOG0_U
Data Sheet
3-113
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
6WDWXV5HJLVWHUIRU&$0(&67$75
Read Address A2H
Value after reset 0000H
unused
unused
STATUS(3:0)
The CSTATR register provides the CAME status after configuration by µP via CMR register.
unused(11:0)
Fixed to zero.
STATUS(3:0)
Status delivered from the CAME after µP requests:
STATUS[3:2] =
00
Ok (STATUS[1:0]=00)
01
Busy (STATUS[1:0]=00)
10
Alarm:
STATUS[1:0] =
00
Mismatch (at search requests).
01
Multimatch (at search requests).
10
Test search fault (at search requests).
00
Refused entry (at write request).
01
Refused line (at write request).
00
Test read fault (at read request).
11
Error:
STATUS[1:0] =
00
Address/data bus parity error.
01
Cascade error.
10
Command cycle error.
Data Sheet
3-114
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
,QWHUUXSW6WDWXV5HJLVWHUV,QWHUUXSW0DVN5HJLVWHUV
The interrupt status registers store potential interrupt causes that occurred. The coding is as
follows:
0: no interrupt cause
1: interrupt cause occurred.
Each interrupt status bit can be reset individually by writing a logical 1 to it. The only exception
is the interrupt status bit RXR_USTR (ISR1, bit9) which is reset automatically. A microprocessor
interrupt is only generated if the corresponding interrupt mask bit is set to 1.
,QWHUUXSW6WDWXV5HJLVWHU,65
Read Address A3H
Value after reset 0000H
1RWH
6LQJOHELWVRIWKLVUHJLVWHUDUHUHVHWWDEOHE\ZULWLQJDµ¶WRWKHP
UTRXFIFO CTY_DIS
_OV_U
_D
unused
CTY_DIS
_U
BOV
PMO
_HLOG
unused
UT_CELL
ERR_D
UT_PAR
ERR_D
RXR_OV
UT_CELL
ERR_U
QOV
UT_PAR
ERR_U
unused(4:1)
Fixed to zero.
UTRXFIFO_OV_U
1
Overflow of UTOPIA receive interface cell buffer upstream.
This interrupt is generated when the 4 cell deep UTOPIA receive
interface FIFO is full and a backpressure to the PHY device is
generated.
CTY_DIS_D
1
Any cell discarded due to cell type recognition downstream.
1
Any cell discarded due to cell type recognition upstream.
1
Overflow of one or more UTOPIA cell queues downstream
(demultiplexing buffer) at PHY-side.
This interrupt is generated for any port when the queue threshold
(UT_THRESH[5:0] in register CONUT3) is reached. After the interrupt
a backpressure signal is generated for the affected port. All cells for
this port that are already inside the ASIC will still be stored in the
queue so that blocking of the ASIC is avoided.
There is no queuespecific backpressure to the microprocessor TXRbuffer. The SW is responsible that cells are not written to a queue in
overflow state.
CTY_DIS_U
QOV
Data Sheet
3-115
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
BOV
1
Overflow of UTOPIA cell buffer downstream (demultiplexing buffer) at
PHY-side.
This interrupt is generated when the 63rd cell is stored in the
demultiplexing buffer (capacity 64 cells). For subsequent cells a
backpressure signal will be generated so that no cells will be lost
inside the ASIC.
1
Indication that one or more cell header have been logged in the
PRMONR-register sets (see STATR-register 6HFWLRQpage
113).
PMO_HLOG
unused(0)
Fixed to zero.
UT_CELLERR_D
1
Start of cell error or cell length error at UTOPIA receive interface
downstream.
Start of cell error: the SOC-pulse is not generated although the partner
device has reported to send a cell and the Enable signal has been
asserted by the ASIC.
Cell length error: an additional SOC-pulse is generated during the
running cell transfer.
UT_PARERR_D
1
Data parity error at UTOPIA receive interface downstream.
1
Receive cell buffer overflow.
This interrupt is generated after the 1st RXR-cell is discarded because
the RXR-buffer is full (capacity 12 cells).
1
Start of cell or cell length error at UTOPIA receive interface upstream.
Start of cell error: the SOC-pulse is not generated although the PHY
device has reported to send a cell and has been enabled by the ASIC.
Cell length error: an additional SOC-pulse is generated during the
running cell transfer.
1
Data parity error at UTOPIA receive interface upstream.
RXR_OV
UT_CELLERR_U
UT_PARERR_U
Data Sheet
3-116
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
,QWHUUXSW6WDWXV5HJLVWHU,65
Read Address A4H
Value after reset 0000H
1RWH
6LQJOHELWVRIWKLVUHJLVWHUDUHUHVHWWDEOHE\ZULWLQJDµ¶WRWKHP
POLVLD
_ERR
unused
EDC
_ERR_D
VLD
_ERR_D
VLD
_ERR_U
RXR
_USTR
unused
EDC
CAM_ERR
_ERR_U
unused(5:3)
POLVLD_ERR
unused
POLU_PAR RAM_PAR RAM_PAR
ERR_U
ERR_D
ERR_U
unused
Fixed to zero.
1
Connection not valid in POLU-RAM upstream.The cell header will not
be written to PRMONR0..3_U.
1
Connection not valid in connection RAM downstream.
This interrupt is generated if the VCON_DO flag of a connection (bit22
of word0 of a connection entry in connection RAM downstream) is not
set.
The cell header will be written to PRMONR_D if possible (see
PRMONR 6HFWLRQpage 100) and the interrupt PMO_HLOG is
set.
1
Connection not valid in connection RAM upstream.
This interrupt is generated if the VCON_UP flag of a connection (bit19
of word0 of a connection entry in connection RAM upstream) is not set.
1
Cell stored in RXR-buffer.
This bit is set until all cells (12 cells maximum) are read out by the mP
and is afterwards reset automatically.
VLD_ERR_D
VLD_ERR_U
RXR_USTR
unused(2)
EDC_ERR_D
Fixed to zero.
1
EDC (CRC10) error in an OAM cell from UTOPIA receive interface
downstream.
The interrupt is only generated if OAM cell processing is enabled (see
bit0 OAM_EN of register DCT_CONFIG 6HFWLRQpage 125).
1
EDC (CRC10) error in an OAM cell from UTOPIA receive interface
upstream.
The interrupt is only generated if OAM cell processing is enabled (see
bit0 OAM_EN of register UCT_CONFIG 6HFWLRQpage 123).
EDC_ERR_U
Data Sheet
3-117
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
CAM_ERR
1
Error during address reduction in CAME.
The affected cell is discarded. All internal errors in the CAME are
reported by this interrupt flag. Additionally the status flags from the
CAME are written to CSIR register.
The cell header will be written to PRMONR0..3_U if possible (see
PRMONR 6HFWLRQpage 99) and the interrupt PMO_HLOG is
generated.
unused(1)
Fixed to zero.
POLU_PARERR_U
1
Error at the RAM interface upstream during a read access from the
external POLU RAM. The cell header will not be written to PRMONR0
.. 3_U.
RAM_PARERR_D
1
Error at the RAM interface downstream during a read access from the
external Connection RAM downstream. During a cell cycle the
corresponding cell is discarded.
The cell header will be written to PRMONR_D if possible (see
PRMONR 6HFWLRQpage 100) and the interrupt PMO_HLOG is
generated.
RAM_PARERR_U
1
unused(0)
Error at the RAM interface upstream during a read access from the
external Connection RAM upstream. During a cell cycle the
corresponding cell is discarded.
The cell header will not be written to PRMONR0 .. 3_U.
Fixed to zero.
,QWHUUXSW0DVN5HJLVWHU,05
Read/write Address A5H
Value after reset 0000H
unused
MBOV
MPMO_
HLOG
MUTRXFI
FO_OV_U
MCTY
_DIS_D
MCTY
_DIS_U
MQOV
MUT_CELL MUT_PAR
MUT_CEL MUT_PAR
unused
MRXR_OV
ERR_D
ERR_D
ERR_U
ERR_U
For every interrupt status bit the corresponding interrupt mask bit is provided (IMR0 for ISR0).
The interrupt mask bit controls whether the setting of an interrupt status bit leads to a
microprocessor interrupt (activation of the interrupt line MPINT_N).
unused(4:1)
Data Sheet
Fixed to zero.
3-118
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
MUTRXFIFO_OV_U
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MCTY_DIS_D
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MCTY_DIS_U
MQOV
MBOV
MPMO_HLOG
unused(0)
Fixed to zero.
MUT_CELLERR_D
0
Microprocessor interrupt is disabled.
1
Microprocessor interrupt is enabled.
MUT_PARERR_D
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MRXR_OV
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MUT_CELLERR_U
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MUT_PARERR_U
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
Data Sheet
3-119
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
,QWHUUXSW0DVN5HJLVWHU,05
Read/write Address A6H
Value after reset 0000H
MPOLVLD MVLD
_ERR
_ERR_D
unused
MEDC
_ERR_D
MVLD
_ERR_U
MRXR
_USTR
unused
MEDC
_ERR_U
MCAM
_ERR
unused
MPOLU_
MRAM_
MRAM_
unused
PARERR_U PARERR_D PARERR_U
For every interrupt status bit the corresponding interrupt mask bit is provided (IMR1 for ISR1).
The interrupt mask bit controls whether the setting of an interrupt status bit leads to a
microprocessor interrupt (activation of the interrupt line MPINT_N).
unused(5:3)
Fixed to zero.
MPOLVLD_ERR
0
Microprocessor interrupt is disabled.
1
Microprocessor interrupt is enabled.
MVLD_ERR_D
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MVLD_ERR_U
MRXR_USTR
unused(2)
MEDC_ERR_D
Fixed to zero.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MEDC_ERR_U
MCAM_ERR
unused(1)
Fixed to zero.
MPOLU_PARERR_U
0
Microprocessor interrupt is disabled.
1
Microprocessor interrupt is enabled.
Data Sheet
3-120
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
MRAM_PARERR_D
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
MRAM_PARERR_U
0
1
Microprocessor interrupt is disabled.
Microprocessor interrupt is enabled.
unused(0)
Fixed to zero.
&$0(,QWHUUXSW6WDWXV5HJLVWHU&6,5
Read Address A7H
Value after reset 0000H
1RWH
6LQJOHELWVRIWKLVUHJLVWHUDUHUHVHWWDEOHE\ZULWLQJDµ¶WRWKHP
unused
unused
STATUS(3:0)
This register gives detailed information about the cause of a CAME interrupt during normal
operation (cell transfer).
unused(11:0)
STATUS(3:0)
Data Sheet
Fixed to zero.
Status delivered by the CAME for PN / VPI / VCI specific interrupts in ISR1.
STATUS[3:2] =
00
Ok (STATUS[1:0]=00)
01
Busy (STATUS[1:0]=00)
10
Alarm:
STATUS[1:0] =
00
Mismatch (at search requests).
01
Multimatch (at search requests).
10
Test search fault (at search requests).
00
Refused entry (at write request).
01
Refused line (at write request).
00
Test read fault (at read request).
11
Error:
STATUS[1:0] =
00
Address/data bus parity error.
01
Cascade error.
10
Command cycle error.
3-121
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
5:50DVN5HJLVWHU50:B0$6.
Read/write Address A9H
Value after reset 0000H
RMW_
MASKA
unused
RMW_
MASK7
unused(4:0)
RMW_MASKi
1RWH
RMW_
MASK6
RMW_
MASK5
RMW_
MASK4
RMW_
MASK3
RMW_
MASK2
RMW_
MASK9
RMW_
MASK8
RMW_
MASK1
RMW_
MASK0
Fixed to zero.
i=[0..A]
In both cases the old RAM value is available after the execution in the RDR
register:
0
Source is WDR-register (new Dword is written into the RAM).
1
Source is RDR-buffer (no change, old Dword is written back).
5($'21/<IODJLQUHJLVWHU&05VHHSDJH KDVKLJKHUSULRULW\WKHQWKH50:B0$6.ELWV
Data Sheet
3-122
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&HOO7\SH5HFRJQLWLRQ&RQILJXUDWLRQ5HJLVWHUV
The registers UCT_CONFIG and DCT_CONFIG configure the celltype recognition upstream
and downstream:
– enabling of OAM Light with provision of some global OAM cell discard functions
– enabling and configuration of programmable cell type filters
– treatment of CRC errors
– enabling of housekeeping processing (only downstream)
– provision of F5RM/F5RES cell discard function for PADACK applications (only downstream).
8&7B&21),*
Read/write Address AAH
Value after reset 0000H
CRC_2_
NODISC
unused
CRC_1_
NODISC
CRC_
NODISC
PCF2_ACT(1:0)
PCF1_ACT(1:0)
PCF1_
EN
UNDEF_
NODISC
LB_
DISC
CC_
DISC
AR_
DISC
PCF2_
EN
OAM_
EN
unused(1:0)
Set to zero.
CRC_2_NODISC
0
Discard cells due to CRC errors if matching PCF2.
1
Discard no cells due to CRC errors if matching PCF2.
1RWH
7KLVIODJLVRQO\YDOLGLI3&)B(1LVVHWWR¶¶
CRC_1_NODISC
0
1
1RWH
Discard cells due to CRC errors if matching PCF1.
Discard no cells due to CRC errors if matching PCF1.
7KLVIODJLVRQO\YDOLGLI3&)B(1LVVHWWR¶¶
CRC_NODISC
0
1
1RWH
Discard OAM cells due to CRC errors.
Discard no OAM cells due to CRC errors.
7KLVIODJLVRQO\YDOLGLI2$0B(1LVVHWWR¶¶
PCF2_ACT(1:0) Selected action for cell types that match PCF2:
00
Forward
01
Discard
10
Drop
11
Copy
1RWH
7KHILOWHUVGRQRWZRUNDWFHOOVZKLFKDUHGLVFDUGHGGXHWRSROLFLQJ
PCF2_EN
0
1
Data Sheet
Disables PCF2 (Programmable Cell Filter 2).
Enables PCF2 (Programmable Cell Filter 2).
3-123
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
PCF1_ACT(1:0) Selected action for cell types that match PCF1:
00
Forward
01
Discard
10
Drop
11
Copy
1RWH
7KHILOWHUVGRQRWZRUNDWFHOOVZKLFKDUHGLVFDUGHGGXHWRSROLFLQJ
PCF1_EN
0
1
Disables PCF1 (Programmable Cell Filter 1).
Enables PCF1 (Programmable Cell Filter 1).
0
1
Discards cells with undefined oamtype at end points (TSP,TEP).
Drops cells with undefined oamtype at end points (TSP,TEP).
0
1
Drops LB cells at end points (TSP,TEP).
Discards LB cells at end points (TSP,TEP).
0
1
Drops CC/CCA cells at end points (TSP,TEP).
Discards CC/CCA cells at end points (TSP,TEP).
0
1
Drops AIS/RDI cells at end points (TSP,TEP).
Discards AIS/RDI cells at end points (TSP,TEP).
0
1
Disables OAM cell processing.
Enables OAM cell processing (OAM Light).
UNDEF_NODISC
LB_DISC
CC_DISC
AR_DISC
OAM_EN
1RWH
)RUPRUHGHWDLOVORRNDWGHVFULSWLRQRI¶2$0/LJKW¶
Data Sheet
3-124
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'&7B&21),*
Read/write Address ABH
Value after reset 0000H
F5RM_
DISC
HK_DIS
CRC_2_
NODISC
CRC_1_
NODISC
CRC_
NODISC
PCF2_ACT(1:0)
PCF1_ACT(1:0)
PCF1_EN
UNDEF_
NODISC
LB_
DISC
CC_
DISC
AR_
DISC
PCF2_
EN
OAM_
EN
F5RM_DISC
0
1
1RWH
Discard no F5RM and F5_PTI=’111’ (F5RES) cells.
Discard F5RM and F5_PTI=’111’ (F5RES) cells.
6SHFLDO3$'$&.DSSOLFDWLRQ)50DQG)B37, ¶¶)5(6FHOOVDUHRQO\GLVFDUGHGDW)HQGSRLQWV
7(3
HK_DIS
0
1
1RWH
Enables House Keeping (HK) processing.
Disables House Keeping (HK) processing.
+RXVH.HHSLQJLVD6LHPHQVSURSULHWDU\LQVLGHQRGHPDLQWHQDQFHSURFHGXUH
CRC_2_NODISC
0
1
1RWH
Discard cells due to CRC errors if matching PCF2.
Discard no cells due to CRC errors if matching PCF2.
7KLVIODJLVRQO\YDOLGLI3&)B(1LVVHWWR¶¶
CRC_1_NODISC
0
1
1RWH
Discard cells due to CRC errors if matching PCF1.
Discard no cells due to CRC errors if matching PCF1.
7KLVIODJLVRQO\YDOLGLI3&)B(1LVVHWWR¶¶
CRC_NODISC
0
1
1RWH
Discard OAM cells due to CRC errors.
Discard no OAM cells due to CRC errors.
7KLVIODJLVRQO\YDOLGLI2$0B(1LVVHWWR¶¶
PCF2_ACT(1:0) Selected action for cell types that match PCF2:
00
Forward
01
Discard
10
Drop
11
Copy
PCF2_EN
0
1
Data Sheet
Disables PCF2 (Programmable Cell Filter 2).
Enables PCF2 (Programmable Cell Filter 2).
3-125
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
PCF1_ACT(1:0) Selected action for cell types that match PCF1:
00
Forward
01
Discard
10
Drop
11
Copy
PCF1_EN
0
1
Disables PCF1 (Programmable Cell Filter 1).
Enables PCF1 (Programmable Cell Filter 1).
0
1
Discards cells with undefined oamtype at end points (TSP,TEP).
Drops cells with undefined oamtype at end points (TSP,TEP).
0
1
Drops LB cells at end points (TSP,TEP).
Discards LB cells at end points (TSP,TEP).
0
1
Drops CC/CCA cells at end points (TSP,TEP).
Discards CC/CCA cells at end points (TSP,TEP).
0
1
Drops AIS/RDI cells at end points (TSP,TEP).
Discards AIS/RDI cells at end points (TSP,TEP).
0
1
Disables OAM cell processing.
Enables OAM cell processing (OAM Light).
UNDEF_NODISC
LB_DISC
CC_DISC
AR_DISC
OAM_EN
1RWH
)RUPRUHGHWDLOVORRNDWGHVFULSWLRQRI¶2$0/LJKW¶
Data Sheet
3-126
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
5HVHW&RQILJXUDWLRQ5HJLVWHU50:B&21)
Read/write Address ACH
Value after reset 0000H
RMW_
RES_A
unused
RMW_
RES_7
RMW_
RES_6
RMW_
RES_5
RMW_
RES_4
RMW_
RES_3
RMW_
RES_2
RMW_
RES_9
RMW_
RES_8
RMW_
RES_1
RMW_
RES_0
The RWR reset register is useful to reset a RAM entry or parts of a RAM entry to ‘0’, because it
is not required to write the ‘0’ into all WDR registers. Additionally in the RMW_MASK register the
source for the next write access has to be selected, that is:
0: for the words that shall be reset
1: for the words, that shall not be changed, the source is the RDR-buffer (no change, old word
is written back).
unused(4:0)
Fixed to zero.
RMW_RES_i
i=[0..A]:
0
Normal write access without reset.
1
Reset (to ’0’) word i of the read/write data at a write access.
Data Sheet
3-127
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
$GGUHVV5HJLVWHUIRU&05&RPPDQGV$'5
Read/write Address ADH
Value after reset 0000H
VCON
P_IP
ADR(13:8)
ADR(7:0)
The ADR register is programmed with the source/destination of several µP commands of the
CMR register.
The P_IP and the VCON bit are only valid for CAME entries. P_IP is used for a reduced search
request (only PN / VPI) at path intermediate points. VCON indicates whether a CAME entry
presents a valid connection. In case that for a incoming cell the VCON bit of the CAME entry is
‘0’, in normal mode (no programming of bit NODIS_CAM in register TESTR) the cell will be
discarded and a interrupt is generated.
VCON
Valid connection flag (used at write accesses to CAME):
0
Connection not valid.
1
Connection valid.
P_IP
Path intermediate point flag (used at write accesses to CAME):
0
Address reduction is performed over PN / VPI / VCI.
1
Path intermediate point; address reduction is performed only over PN
/ VPI.
ADR(13:0)
Address of a µP request (see CMR-register 6HFWLRQpage 111). It may
contain LCI, port table-address or cell filter number.
Data Sheet
3-128
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
6FDQ&RQILJXUDWLRQ5HJLVWHUV
The scan configuration registers define the Range of LCIs (from LCI_min to LCI_max) that is
refreshed by the POLU.
Starting of the POLU refresh has to be done in the following order:
1. write SC_CONR1 with LCIMIN and POLU_REFR_EN=0
2. write SC_CONR2 with LCIMAX
3. write SC_CONR1 with LCIMIN and with POLU_REFR_EN=1.
6&B&215
Read/write Address AEH
Value after reset 0000H
unused
POLU_
REFR_EN
LCI_MIN(13:8)
LCI_MIN(7:0)
unused
Fixed to zero.
POLU_REFR_EN
0
No policing refresh.
1
Policing refresh in the range between LCI_MIN and LCI_MAX.
LCI_MIN(13:0)
Lower limit of LCIs processed by POLU refresh.
6&B&215
Read/write Address AFH
Value after reset 0000H
unused
LCI_MAX(13:8)
LCI_MAX(7:0)
unused
LCI_MAX(13:0)
Data Sheet
Fixed to zero.
Upper limit of LCIs processed by POLU refresh.
3-129
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'0$&RQILJXUDWLRQ5HDG5HJLVWHU
The DMA can be performed either for CONNRAMUP or for CONNRAMDO controlled by
DMA_UD (bit 0 of DCONR). To read the counters from CONNRAMUP and CONNRAMDO the
following steps are necessary:
– Load register DMA_MIN with LCIMIN
– Load register DMA_MAX with LCIMAX
– Load register DCONR with bit DMA_UD=0 and DMA_START=1 ⇒ starts DMA upstream
– Wait until DMA upstream is complete (bit DMA_START=0)
– Load register DMA_MIN with LCIMIN (only if LCIMIN is different for DMA downstream)
– Load register DMA_MAX with LCIMAX (only if LCIMAX is different for DMA downstream)
– Load register DCONR with bit DMA_UD=1 and DMA_START=1 ⇒ starts DMA downstream
– wait until DMA downstream is complete (bit DMA_START=0).
'&215
Read/write Address B0H
Value after reset 0000H
CTR7_
RES
CTR6_
RES
CTR5_
RES
CTR4_
RES
CTR3_
RES
CTR2_
RES
CTR1_
RES
DMA_
DELAY(6)
DMA_
START
DMA_
UD
DMA_DELAY(5:0)
CTR7_RES
0
1
Don’t reset counter.
Reset counter P_TIC0 (upstream) after DMA read.
0
1
Don’t reset counter.
Reset counter P_TIC (upstream) after DMA read.
0
1
Don’t reset counter.
Reset counter TTC (upstream) after DMA read.
0
1
Don’t reset counter.
Reset counter TDC0 (upstream) or P_TOC0 (downstream) after DMA
read.
0
1
Don’t reset counter.
Reset counter TDC1 (upstream) or P_TOC (downstream) after DMA
read.
CTR6_RES
CTR5_RES
CTR4_RES
CTR3_RES
Data Sheet
3-130
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
CTR2_RES
0
1
Don’t reset counter.
Reset counter TIC0 (upstream) or TOC0 (downstream) after DMA
read.
0
1
Don’t reset counter.
Reset counter TIC (upstream) or TOC (downstream) after DMA read.
CTR1_RES
DMA_DELAY(6:0)Delay between two DMA requests.
Delay = (0,1,2,...,127) * 2 * cellcycle.
1RWH
7KHVHELWVFDQEHXVHGWRDYRLG'0$EXUVWVRQWKHµ3EXV
DMA_START
This bit is reset by the ASIC after completion of the DMA; i.e. after the last one
of the connections between LCIMIN (in register DMA_MIN) and LCIMAX (in
register DMA_MAX) has been read out by µP.
While DMA_START=1 it is not possible to write the registers DCONR,
DMA_MIN and DMA_MAX with the exception of bit DMA_START. Writing a
‘0’ to DMA_START resets the running DMA.
0
DMA complete.
1
Start DMA.
DMA_UD
0
1
1RWH
DMA in upstream direction.
DMA in downstream direction.
$FRPSOHWH'0$PXVWEHVSOLWLQD'0$XSVWUHDPDQGD'0$GRZQVWUHDP
Data Sheet
3-131
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
'0$5
Read Address B1H
Value after reset undefined
dword n(15:8/31:24)
dword n(7:0/23:16)
This 16 bit register is used to read from the DMA FIFO. There the words are stored with 32 bit
length (= dword). To read one dword from the DMA FIFO requires two read accesses to the
register DMAR.
For the upstream direction the DMA FIFO is read in the following order :
dword 1(15:0)
dword 1(31:16)
dword 2(15:0)
dword 2(31:16)
dword 3(15:0)
dword 3(31:16)
dword 4(15:0)
dword 4(31:16)
dword 5(15:0)
dword 5(31:16)
dword 6(15:0)
dword 6(31:16)
dword 7(15:0)
dword 7(31:16)
Connection RAM upstream (TIC counter).
Connection RAM upstream (TIC counter).
Connection RAM upstream (TIC0 counter).
Connection RAM upstream (TIC0 counter).
Connection RAM upstream (TDC1 counter).
Connection RAM upstream (TDC1 counter).
Connection RAM upstream (TDC0 counter).
Connection RAM upstream (TDC0 counter).
Connection RAM upstream (TTC counter).
Connection RAM upstream (TTC counter).
Connection RAM upstream (P_TIC counter).
Connection RAM upstream (P_TIC counter).
Connection RAM upstream (P_TIC0 counter).
Connection RAM upstream (P_TIC0 counter).
For the downstream direction the DMA FIFO is read in the following order :
dword 3(15:0)
dword 3(31:16)
dword 4(15:0)
dword 4(31:16)
dword 5(15:0)
dword 5(31:16)
dword 6(15:0)
dword 6(31:16)
Data Sheet
Connection RAM downstream (TOC counter).
Connection RAM downstream (TOC counter).
Connection RAM downstream (TOC0 counter).
Connection RAM downstream (TOC0 counter).
Connection RAM downstream (P_TOC counter).
Connection RAM downstream (P_TOC counter).
Connection RAM downstream (P_TOC0 counter).
Connection RAM downstream (P_TOC0 counter).
3-132
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
7HVW5HJLVWHU6SHFLDO0RGHV7(675
Read/write Address B2H
Value after reset 0000H
LOOP_
TXRX
unused
PARERR
EN_D
HW_LOOP
TESTINT
_TRANS
NODIS_
CAM
POVLD
ERREN
VLDERR
EN_D
PARERR
EN_U
VLDERR PARERR
EN_U
EN_POLU
DMA_
WAIT
MC_DIS
LOOPDU LOOPUD
The register TESTR provides special modes like loops, the disabling of cell discard functions
and multicast. To prevent disturbing of normal mode operation by chance, the write access to
the TESTR-register is only possible if bit TESTR_EN in the MODE-register is set to ‘1’!
unused
Fixed to zero.
LOOP_TXRX
Every change from 0 to 1 starts the transmission of the contents of the TXRregisters to the RXR-registers. In case of RXR-overflow no interrupt is
generated and the contents of RXR is overwritten!
HW_LOOP_TRANS
0
The HW-loops are not transparent, i.e. the cell stream is only looped
back.
1
The HW-loops are transparent, i.e. the cell stream is not only looped
back but also forwarded to transmit UTOPIA.
TESTINT
0
1
All interrupt sources are enabled.
All interrupt sources are disabled: every new write access to the RXRregister will generate a new interrupt with a different interrupt flag
(gives the opportunity to test interrupts regardless whether interrupts
occur).
NODIS_CAM
Cells not valid in CAME:
0
Cells will not leave UTOPIA.
1
Discard no cells (and no interrupt generated).
POVLDERREN
Cells not valid in POLU-RAM:
0
Discard no cells.
1
Discard cells.
VLDERREN_D
Cells not valid in connection RAM downstream:
0
Cells will not leave UTOPIA.
1
Discard no cells (and no interrupt generated).
PARERREN_D
Cells generating a parity error at connection RAM downstream:
0
Cells will not leave UTOPIA.
1
Discard no cells (and no interrupt generated).
PARERREN_U
Cells generating a parity error at connection RAM upstream:
0
Cells will not leave UTOPIA.
1
Discard no cells (and no interrupt generated).
Data Sheet
3-133
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
VLDERREN_U
Cells not valid in connection RAM upstream:
0
Cells will not leave UTOPIA.
1
Discard no cells (and no interrupt generated).
PARERREN_POLUCells generating a parity error at POLU RAM:
0
No POLU action.
1
Cells will be discarded, no policing.
DMA_WAIT
0
1
1RWH
No DMA-request inactive time.
Min. 32 cycles DMA-request inactive time between two active phases
on the MPDREQ_N pin.
7KLVELWDOORZVDGDSWDWLRQWR,QWHO(;'0$WLPLQJ
MC_DIS
0
1
Enables multicast (downstream).
Disables/interrupts multicast (downstream).
0
1
No loop.
Insert test loop downstream to upstream (during loop in downstream
direction only the functionality cell transfer with header translation is
possible; other functions like cell insertion, multicast, etc. are not
available).
LOOPDU
1RWH
:LWKWKHELW+:B/223B75$16WKHORRSFDQEHFRQILJXUHGDVWUDQVSDUHQWRUQRWWUDQVSDUHQW
LOOPUD
0
1
1RWH
No loop.
Insert test loop upstream to downstream (during loop in downstream
direction only the functionality cell transfer with header translation is
possible; other functions like cell insertion, multicast, etc. are not
available).
:LWKWKHELW+:B/223B75$16WKHORRSFDQEHFRQILJXUHGDVWUDQVSDUHQWRUQRWWUDQVSDUHQW
Data Sheet
3-134
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
32/86WDWXV5HJLVWHUV3B67$75
3B67$75
Read Address B3H
Value after reset 0000H
word(15:8)
word(7:0)
word(15:0)
Only for Test. Don’t change the contents for normal policing operation.
3B67$75
Read Address B4H
Value after reset 0000H
word(15:8)
word(7:0)
word(15:0)
Only for Test. Don’t change the contents for normal policing operation.
3B67$75
Read Address B5H
Value after reset 0000H
word(15:8)
word(7:0)
word(15:0)
Data Sheet
Only for Test. Don’t change the contents for normal policing operation.
3-135
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
&$0(9DOLG,QWHUPHGLDWH/&,&$09,/&,
Read Address B6H
Value after reset 0000H
VCON
P_IP
LCI(13:8)
LCI(7:0)
The address reduction test is only started via the command ‘read a line in the CAME’ in the CMR
register.
1RWH
5HVSRQVHRI&$0(LVZULWWHQWR&$09,/&,
VCON
P_IP
LCI(13:0)
Valid connection flag (also in read mode).
Path intermediate point flag (also in read mode).
LCI
'0$5DQJH5HJLVWHUV
DMA_MIN and DMA_MAX define the range of LCI’s that is processed by DMA according to the
settings in the register DCONR.
'0$B0,1
Read/write Address B8H
Value after reset 0000H
unused
LCI_MIN(13:8)
LCI_MIN(7:0)
unused
LCI_MIN(13:0)
Fixed to zero.
Lowest LCI (LCIMIN) of LCI range processed by DMA.
'0$B0$;
Read/write Address B9H
Value after reset 0000H
unused
LCI_MAX(13:8)
LCI_MAX(7:0)
unused
LCI_MAX(13:0)
Data Sheet
Fixed to zero.
Highest LCI (LCIMAX) of LCI range processed by DMA.
3-136
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
%,675HJLVWHUV
The BIST is normally used for test purposes of the ASIC vendor. Inside the ALP the signals
‘BISTDONE’ and ‘BISTERROR’ are stored in registers so that the BIST can be used for an initial
RAM test (only ASIC internal RAMs). With the BIST signals stored in registers the BIST test is
only a ‘go/no go’ test. It is not possible to determine which RAM parts are faulty.
A BIST test of all internal RAMs is performed in the following order:
– set bit ‘TESTR_EN’ in the MODE register to ‘1’
– check the reset values of the BIST registers (BISTMODE1/2=BISTDONE=0000hex;
BISTERROR=0FFFhex)
– BIST self test: set the mode bits of all RAMs to ‘01’ (The BIST self test starts toggling of the
BISTERROR signals. The first ‘0’-state on these signals is captured by the BISTERROR
register to indicate that a BIST error has occurred.)
– wait for about 100 clock cycles
– control the BISTERROR register (BISTERROR=0000hex); that means a BIST error has
occurred and has been recognized for every internal RAM ⇒ the control logic is able to detect
BIST errors
– reset the Bist self test for all internal RAMs (BISTMODE1/2=0000hex)
– reset the BISTERROR register (this register is reset with any write access)
– check reset of BISTERROR register (BISTERROR=0FFFhex)
– BIST test: set the mode bits of all RAMs to ‘10’
– wait until the BISTDONE bit of every internal RAM is set (BISTDONE=0FFFhex)
– check whether Bist errors occurred (BISTERROR /= 0FFFhex).
To prevent disturbing of normal mode operation by chance, the write access to the BISTMODE1/
2-register is only possible if bit TESTR_EN in the MODE-register is set to ‘1’!
After completion of BIST test a software-Reset (see CMR-register 6HFWLRQpage 111) has
to be started because the BIST affects also the control RAM (NCP RAM) of the demultiplexing
buffer in the UTOPIA transmit downstream interface which leads to a malfunction.
%,670RGH5HJLVWHU%,6702'(
Read/write Address BAH
Value after reset 0000H
BIST_TRM(1:0)
BIST_UTTXD0(1:0)
1RWH
BIST_NCP(1:0)
BIST_UTTXD1(1:0)
BIST_UTTXU(1:0)
BIST_UTRXU(1:0)
BIST_RXR(1:0)
BIST_UTRXD(1:0)
$FWLRQVIRU%LVWPRGH
Data Sheet
,QDFWLYH
7HVWRI%,67
6WDUW%,67
'LDJQRVLVQRWXVHG
3-137
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
BIST_TRM(1:0)
Bistmode for TRM RAM. Traffic Measurement Port Table not modified at SW
reset.
BIST_RXR(1:0)
Bistmode for RXR RAM. Rx 12 cell extraction Buffer not modified at SW
reset.
BIST_NCP(1:0)
Bistmode for UTTXD NCP RAM (UTOPIA-Address-RAM). Set to ’0’ with SW
reset.
BIST_UTTXD1(1:0)
Bistmode for UTTXD Buffer RAM 1. UTOPIA Tx-downstream shared memory
Buffer of 64 cells. Set to ’0’ with SW reset.
BIST_UTTXD0(1:0)
Bistmode for UTTXD Buffer RAM 0. UTOPIA Tx-downstream shared memory
Buffer of 64 cells. Set to ’0’ with SW reset.
BIST_UTRXD(1:0)
Bistmode for UTRXD Buffer RAM. UTOPIA Rx-downstream cell FIFO. Set to
’0’ with SW reset.
BIST_UTTXU(1:0)
Bistmode for UTTXU Buffer RAM. UTOPIA Tx-upstream cell FIFO. Set to ’0’
with SW reset.
BIST_UTRXU(1:0)
Bistmode for UTRXU Buffer RAM. UTOPIA Rx-upstream cell FIFO. Set to ’0’
with SW reset.
%,670RGH5HJLVWHU%,6702'(
Read/write Address BBH
Value after reset 0000H
unused
BIST_RWR1(1:0)
1RWH
BIST_RWR0(1:0)
BIST_UCW1(1:0)
BIST_UCW0(1:0)
$FWLRQVIRU%LVWPRGH
unused
Data Sheet
,QDFWLYH
7HVWRI%,67
6WDUW%,67
'LDJQRVLVQRWXVHG
Fixed to zero.
3-138
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
BIST_RWR1(1:0)
Bistmode for RWR RAM 1. µP Read/Write not modified at SW reset.
BIST_RWR0(1:0)
Bistmode for RWR RAM 0. µP Read/Write not modified at SW reset.
BIST_UCW1(1:0)
Bistmode for UCW RAM 1. Upstream workbench not modified at SW reset.
BIST_UCW0(1:0)
Bistmode for UCW RAM 0. Upstream workbench not modified at SW reset.
%,67$FWLYH5HJLVWHU%,67'21(
Read Address BCH
Value after reset 0000H
unused
BISTDONE BISTDONE BISTDONE BISTDONE
_RWR1
_RWR0
_UCW1
_UCW0
BISTDONE BISTDONE BISTDONE BISTDONE BISTDONE BISTDONE BISTDONE BISTDONE
_TRM
_RXR
_NCP
_UTTXD1 _UTTXD0 _UTRXD _UTTXU _UTRXU
unused
Fixed to zero.
BISTDONE_RWR1
0
Bistmode for RWR RAM 1 is busy.
1
Bistmode for RWR RAM 1 is done.
BISTDONE_RWR0
0
1
Bistmode for RWR RAM 0 is busy.
Bistmode for RWR RAM 0 is done.
BISTDONE_UCW1
0
1
Bistmode for UCW RAM 1 is busy.
Bistmode for UCW RAM 1 is done.
BISTDONE_UCW0
0
1
Bistmode for UCW RAM 0 is busy.
Bistmode for UCW RAM 0 is done.
BISTDONE_TRM
0
1
Bistmode for TRM RAM is busy.
Bistmode for TRM RAM is done.
0
1
Bistmode for RXR RAM is busy.
Bistmode for RXR RAM is done.
0
1
Bistmode for UTTXD NCP RAM is busy.
Bistmode for UTTXD NCP RAM is done.
BISTDONE_RXR
BISTDONE_NCP
Data Sheet
3-139
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
BISTDONE_UTTXD1
0
1
Bistmode for UTTXD Buffer RAM is busy.
Bistmode for UTTXD Buffer RAM is done.
BISTDONE_UTTXD0
0
1
Bistmode for UTTXD Buffer RAM 0 is busy.
Bistmode for UTTXD Buffer RAM 0 is done.
BISTDONE_UTRXD
0
1
Bistmode for UTRXD Buffer RAM is busy.
Bistmode for UTRXD Buffer RAM is done.
BISTDONE_UTTXU
0
1
Bistmode for UTTXU Buffer RAM is busy.
Bistmode for UTTXU Buffer RAM is done.
BISTDONE_UTRXU
0
1
Bistmode for UTRXU Buffer RAM is busy.
Bistmode for UTRXU Buffer RAM is done.
%,675HVXOW5HJLVWHU%,67(5525
Read/write Address BDH
Value after reset 01FFH
unused
BISTERR_ BISTERR_ BISTERR_ BISTERR_
RWR1
RWR0
UCW1
UCW0
BISTERR_ BISTERR_ BISTERR_ BISTERR_ BISTERR_ BISTERR_ BISTERR_ BISTERR_
TRM
RXR
NCP
UTTXD1 UTTXD0
UTRXD
UTTXU
UTRXU
1RWH
7KHUHJLVWHULVUHVHWWHGDWHYHU\ZULWHDFFHVVLIELW7(675B(1LQ02'(UHJLVWHULVHTXDO
unused
Fixed to zero.
BISTERR_RWR1
0
Bisterror for RWR RAM 1 occurred.
1
No Bisterror.
BISTERR_RWR0
0
1
Bisterror for RWR RAM 0 occurred.
No Bisterror.
0
1
Bisterror for UCW RAM 1 occurred.
No Bisterror.
BISTERR_UCW1
Data Sheet
3-140
08.2000
3;%(
5HJLVWHU'HVFULSWLRQ
BISTERR_UCW0
0
1
Bisterror for UCW RAM 0 occurred.
No Bisterror.
0
1
Bisterror for TRM RAM occurred.
No Bisterror.
0
1
Bisterror for RXR RAM occurred.
No Bisterror.
0
1
Bisterror for UTTXD NCP RAM occurred.
No Bisterror.
BISTERR_TRM
BISTERR_RXR
BISTERR_NCP
BISTERR_UTTXD1
0
1
Bisterror for UTTXD Buffer RAM 1 occurred.
No Bisterror.
BISTERR_UTTXD0
0
1
Bisterror for UTTXD Buffer RAM 0 occurred.
No Bisterror.
BISTERR_UTRXD
0
1
Bisterror for UTRXD Buffer RAM occurred.
No Bisterror.
BISTERR_UTTXU
0
1
Bisterror for UTTXU Buffer RAM occurred.
No Bisterror.
BISTERR_UTRXU
0
1
Bisterror for UTRXU Buffer RAM occurred.
No Bisterror.
Data Sheet
3-141
08.2000
3;%(
2SHUDWLRQ
2SHUDWLRQ
0XOWLFDVW
The Multicast light functionality is a sequential multicast. A multicast cell, arrived at the input cell
queue of the UTOPIA transmit interface downstream, is hold in the first entry of the input queue
and copied to the output shared buffer queues given by the linked list structure in
CONNRAMDO. The indication for a multicast cell is bit MC_ANCHOR in Dword2 of
CONNRAMDO (see VHFWLRQpage 78). The cell is copied to the queues/ports given by
the PN of each LCI included in the linked list. The ALP supports spatial and logical multicast.
When the selected LCIs include different ports/queues it is a spatial multicast. If the selected
LCIs are defined for the same port/queue it is a logical multicast. The example in ILJXUH describes a spatial multicast into three queues.
Multicast cell
Output shared buffer
Input cell queue from UTOPIA
cell 1
Queue 1
cell 2
LCIa from cell in queue
...
Queue 2
LCIb from
RAM
entry
of LCIa
...
VPIa/VCIa/PNa=1
NEXT_LCIb
MC_ANCHOR=1
cell 3
Queue 24
Downstream
Connection
RAM
LCIc from
RAM
entry
of LCIb
...
VPIb/VCIb/PNb=2
NEXT_LCIc
MC_ANCHOR=1
VPIc/VCIc/PNc=24
NEXT_LCI=don’t care
MC_ANCHOR=0
Cell 1..3 = identical copies of the
same cell with different headers
and port numbers
LCI pointer
)LJXUH
([DPSOHIRU6SDWLDO0XOWLFDVW
To initiate a multicast, the microprocessor has to set the MC_ANCHOR bit in Dword2 of the
connection entry in CONNRAMUP. The NEXT_LCI entry in Dword2 defines the LCI of the
following connection in the multicast chain. This LCI has to be valid if the MC_ANCHOR bit is
set. Otherwise this entry is "don’t care".
Data Sheet
4-142
08.2000
3;%(
2SHUDWLRQ
8723,$&RQILJXUDWLRQ
The ALP provides five registers for UTOPIA interface configuration. The registers CONUT1A-C
(see VHFWLRQpage 105, VHFWLRQpage 106 and VHFWLRQpage 106) are
used to enable/disable each of the 24 UTOPIA ports in both upstream and downstream
direction. The register CONUT2 (see VHFWLRQpage 106) is used to set the data bus width
(8 or 16 bit) and the UTOPIA mode (Level 1 or 2) on the PHY and the ATM side. To enable the
forced inserting of empty cell cycles in downstream direction and to set the queue threshold of
the UTOPIA buffer the register CONUT3 (see VHFWLRQ page 108) is used. The
microprocessor can monitor the status of the UTOPIA interface via the two UTOPIA status
registers UT_QOV1 and UT_QOV2 (see VHFWLRQpage 109 and VHFWLRQpage
109). These registers indicate on which queue an overflow occured.
5$0$FFHVV
The microprocessor cannot access the external RAMs (POLURAM and CONNRAM) directly. It
has to use the read and write transfer registers of the ALP. The ALP uses a read-modify-write
type access.
Read-Modify-Write-Access :
First write the LCI to register ADR (see VHFWLRQpage 128) and the new contents for this
LCI to the write registers from WDR0L to WDRAH (see VHFWLRQpage 69). To select the
Dwords of the selected entry which should not be changed (read-only) set the associated mask
bits in the mask register RMW_MASK (see VHFWLRQpage 122). Using bits MPREQDEF in
the command register CMR (see VHFWLRQpage 111) the source RAM must be selected.
Set bit READONLY to ’0’ and the start bit STREQ to ’1’. Setting the last mentioned bit starts the
read-modify-write process. The microprocessor now has to poll the STREQ bit. When the ALP
finished the RAM access, this bit will be reset. After that, the microprocessor can read the old
RAM entries via the read registers from RDR0L to RDRAH (see VHFWLRQpage 69).
Read-Only-Access :
First write the LCI to register ADR (see VHFWLRQ page 128). The source RAM must be
selected by using bits MPREQDEF in the command register CMR (see VHFWLRQpage 111).
Set the bit READONLY to ’1’ and the start bit STREQ to ’1’. Note, that the bit READONLY has
a higher priority than the mask register bits. Therefore the mask register has no effect during a
read-only-access. The setting of the last bit starts the read-modify-write process. The
microprocessor now has to poll the STREQ bit. When the ALP has finished the RAM access,
this bit will be reset. After that, the microprocessor can read the old RAM entries via the read
registers from RDR0L to RDRAH (see VHFWLRQpage 69).
&$0($FFHVV
The microprocessor is responsible for the configuration of the external address reduction circuit
CAME. Therefore a write access to the CAME is necessary and can be done via a set of five
registers which are provided by the ALP. First the microprocessor writes the LCI of the
connection to the address register ADR (see VHFWLRQ page 128). The VCI of the
connection is written to register CAMADRL (see VHFWLRQpage 90). The VPI and the PN
are written to register CAMADRH (see VHFWLRQpage 90). After this the microprocessor
has to set register CMR (see VHFWLRQpage 111) to value 0x0048 (write line to CAME and
start transfer). The transfer is finished after bit STREQ is reset by the ALP. By reading register
Data Sheet
4-143
08.2000
3;%(
2SHUDWLRQ
CSTATR (see VHFWLRQ page 114) status information about the CAME after a
microprocessor access are available.
3ROLFLQJ&RQILJXUDWLRQ
To configurate the policing unit and to start the policing process execute the following steps. The
policing unit has the capability of policing 16384 connections independently. Because of that,
the Leaky Bucket algorithm has to be defined for each policed connection. This has to be done
via the entries in the POLURAM, which consists of 11 Dwords (see VHFWLRQpage 71). With
the Dwords 0 to 10 the variables of the Leaky Buckets algorithm are defined. Dword 10 is used
for setting F4/F5 policing options, POLU operation mode and policing path definition. The
POLURAM access is done as described in VHFWLRQ page 143. Set the POLU to normal
mode via bit TOM in the POLU configuration register P_CONRL (see VHFWLRQpage 91).
Besides tagging and discarding of cells via the POLU can be disabled with this register (bits
DISC_INH and TAG_INH). The contents of the P_CONRL register are transferred to the POLU
by setting bit VALID_CONF in register P_CONRH (see VHFWLRQpage 92). After this the
LCI range of the connections which should policed has to be defined using registers SC_CONR1
and SC_CONR2 (see VHFWLRQpage 129 and VHFWLRQpage 129). First write the
lower LCI (LCImin) to register SC_CONR1 with bit POLU_REFR_EN = ’0’. Then write the upper
LCI (LCImax) to register SC_CONR2. To enable the policing write LCImin to register
SC_CONR1 with bit POLU_REFR_EN = ’1’. To stop the policing the microprocessor has to reset
this bit again.
&RQQHFWLRQ6HWXS
The following steps are required to set up a connection through the ALP using the CAME (here
e.g. for upstream direction). Write the LCI for the connection to the address register ADR (see
VHFWLRQpage 128). The VCI of the connection is written to the CAME address register
CAMADRL (see VHFWLRQpage 90). The PN and the VPI of the connection are written to
the CAME address register CAMADRH (see VHFWLRQ page 90). Write the connection
specific parameters to the write registers WDR0L and WDR0H (register see VHFWLRQpage
69; for connection specific parameters see VHFWLRQ page 75, Dword0). If OAM light
functions are not used, set all OAM parameters to ’0’. Set bit VCON_UP to indicate a valid
connection and bit EN_TRAF_MEAS_UP when traffic measurement should be enabled for this
connection. Set registers from WDR1L to WDR6H to value 0x0000. Herewith the counters are
reset. Write the value 0x0049 to the command register CMR (see VHFWLRQpage 111). This
has the effect of writing one line into the CAME and one entry to the CONNRAMUP using the
LCI in register ADR, the VCI in register CAMADRL and the PN and VCI in register CAMADRH.
The CONNRAMUP is written to with the contents of the write transfer registers (WDRxx).
&HOO,QVHUWLRQDQG([WUDFWLRQ
To insert user defined cells the ALP provides one set of 27 registers from TXR0 to TXR26 (see
VHFWLRQ page 94). These registers can be programmed by the microprocessor. The
registers from TXR0 to TXR2 are used to program the cell header and registers from TXR3 to
TXR26 are used to insert the payload. After data is written to the transmit cell registers, the
microprocessor can control the insertion via the configuration of the transmit cell buffer register
TXR_CONFIG (see VHFWLRQpage 94). Using bit TRANSM_DIR it is selectable whether the
cell is inserted in up- or in downstream direction. Bit HTON is used to enable header translation.
Data Sheet
4-144
08.2000
3;%(
2SHUDWLRQ
By setting bit START_TR the insertion starts. After the cell is inserted, the ALP resets bit
START_TR. It is strongly recommended not to start the transmission in upstream direction while
the bit UTRXFIFO_OV_U in register ISR0 is set to ’1’ (see VHFWLRQpage 115). When this
bit is set, an input queue overflow of the UTOPIA receive interface upstream occurs. It is also
strongly recommended not to start the transmission in downstream direction while bit BOV in the
register ISR0 or bit UT_QOV of the corresponding port (see VHFWLRQ page 109 and
VHFWLRQpage 109) are set to ’1’. This indicates a buffer/queue overflow in the UTOPIA
transmit interface downstream.
Any cells copied or dropped from the cell stream can be read from the AOP by the processor
with 27 reads to the RXR register. The reads do not need to be consecutive. With bit RXR_USTR
set to ’1’ the ALP indicates that a cell is stored in the cell receive buffer. After read out the
complete set of cells, this bit is reset by ALP automatically.
'0$&RQILJXUDWLRQDQG$FFHVV
The ALP supports DMA for a fast transfer of connection counter information from CONNRAMUP
and CONNRAMDO to the microprocessor RAM. The microprocessor can control the DMA
access via three registers called DMA_MIN, DMA_MAX and DCONR (see VHFWLRQpage
136, VHFWLRQpage 136 and VHFWLRQpage 130). First write the range of LCI values
for DMA transfer to the DMA_MIN (lower LCI value) and DMA_MAX (upper LCI value). Then
configure the DCONR register, i.e. select the counters which will be reset by the DMA, the delay
between two DMA bursts on the microprocessor bus using bits DMA_DELAY and the direction
on which the counters should read out by bit DMA_UD (up- or downstream). When the DMA is
configurated set bit DMA_START to initiate the DMA transfer. With the external pin
MPDREQ = ’0’ the ALP indicates that a new LCI entry has been written into the ALP DMA buffer.
The microprocessor response with setting MPACK to ’0’. Than the microprocessor can read out
the connection counters by 14 read accesses to DMAR in upstream or 8 read accesses to
DMAR in downstream direction. The inactive time between two read accesses (duration of ’high’
on MPRD) must be at least one ALP SYSCLK cycle. With MPDREQ = ’1’ the ALP indicates that
the DMA buffer is empty. The microprocessor has to set MPACK to ’1’ for the DMA can performe
the next LCI. When the next LCI entry has been written to the ALP DMA buffer, the pin MPDREQ
becomes active again. The microprocessor has to repeat the read out procedure until the ALP
finished the DMA access and indicates this state by reseting bit DMA_START. Note, that a fast
transfer can be accomplished by connecting the external pin MPDACK permanently high.
Data Sheet
4-145
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
,QWHUIDFH'HVFULSWLRQ
8723,$,QWHUIDFH
UTOPIA Handshaking at the PHY side:
• If one of the ports of the upstream receive line is selected (RXADRU) by the ALP and this port
is able to transmit one cell, RXCLAVU is asserted. By asserting RXENBU the ALP forces the
transmission of a whole cell. RXSOCU indicates the Start Of Cell.
• In downstream direction the ALP selects one port and if the port is able to receive one cell
TXCLAVD is asserted. When the transmission to this port starts, TXENBD and the TXSOCD
is set.
UTOPIA Handshaking at the ATM side:
• For the upstream transmit line the ALP represents one of 24 ports. Its valid port address is
programmable. If the ALP is selected and TXCLAVU is asserted, then TXENBU is set, if one
cell is available for transmission.
• The cells downstream can be received from up to 24 ports. The selected ALP with
programmable port address asserts RXCLAVD, if it is able to receive one cell. When the
transmission to this port starts, RXENBD and RXSOCD is set.
In the following figures three UTOPIA configurations with the corresponding system architecture
are depicted. )LJXUH depicts the ALP between the PHYs and an other ATM Layer device e.g.
AOP, ABM or ASP. For this application the UTOPIA interface at the ATM side is in slave mode.
)LJXUH and depicts an ALP between PHYs used as multiplexor for access networks or
backbone applications.
RXCLAVU(3:0)
RXADRU(3:0)
RXENBU(3:0)
STM-1
TXDATU(15:0)
TXSOCU
TXCLAVU(3:0)
TXADRU(3:0)
TXENBU(3:0)
UTOPIA Master
RXSOCU
Tx UTOPIA Slave
RXDATU(15:0)
TXPRTYU
upstream
STM-1
Rx UTOPIA Master
ALP
RXPRTYU
ATM-Layer
Device
TXSOCD
1
6
TXCLAVD(3:0)
6x
25.6 MBit/s
TXADRD(3:0)
TXENBD(3:0)
Rx UTOPIA Slave
TXDATD(15:0)
RXPRTYD
downstream
TXPRTYD
Tx UTOPIA Master
6
6x
25.6 MBit/s
RXDATD(15:0)
RXSOCD
RXCLAVD(3:0)
RXADRD(3:0)
UTOPIA Master
1
RXENBD(3:0)
)LJXUH
8723,$,QWHUIDFH&RQILJXUDWLRQZLWK6ODYH0RGHDWWKH$706LGH
Data Sheet
5-146
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
ALP
RXCLAVU(3:0)
RXADRU(3:0)
RXENBU(3:0)
TXDATU(15:0)
TXCLAVU(3:0)
TXADRU(3:0)
TXENBU(3:0)
1
TXSOCD
1
6
TXCLAVD(3:0)
6x
25.6 MBit/s
)LJXUH
TXADRD(3:0)
TXENBD(3:0)
downstream
TXDATD(15:0)
Rx UTOPIA Master
TXPRTYD
Tx UTOPIA Master
6
6x
25.6 MBit/s
STM-4
Framer
TXSOCU
UTOPIA Slave
STM-1
Tx UTOPIA Master
RXSOCU
upstream
RXDATU(15:0)
STM-1
TXPRTYU
Rx UTOPIA Master
RXPRTYU
RXPRTYD
RXDATD(15:0)
RXSOCD
RXCLAVD(3:0)
RXADRD(3:0)
RXENBD(3:0)
8723,$,QWHUIDFH&RQILJXUDWLRQZLWK0DVWHU0RGHDWWKH$706LGH
RXCLAVU(3:0)
1
RXADRU(3:0)
RXENBU(3:0)
IWE8
Tx UTOPIA Master
RXSOCU
TXPRTYU
upstream
STM-1
RXDATU(15:0)
Rx UTOPIA Master
ALP
RXPRTYU
TXDATU(15:0)
TXSOCU
TXCLAVU(3:0)
TXADRU(3:0)
TXENBU(3:0)
8
1
TXSOCD
1
TXCLAVD(3:0)
TXADRD(3:0)
IWE8
8
)LJXUH
Data Sheet
TXENBD(3:0)
Rx UTOPIA Slave
TXDATD(15:0)
RXENBD(3:0)
downstream
8
TXPRTYD
Tx UTOPIA Master
IWE8
RXADRD(3:0)
RXCLAVD(3:0)
RXSOCD
RXDATD(15:0)
RXPRTYD
8723,$,QWHUIDFH&RQILJXUDWLRQZLWK0DVWHU0RGHIRU7[DQG6ODYH0RGHIRU
5['LUHFWLRQDWWKH$706LGH
5-147
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
The following table gives an overview over the UTOPIA signals:
7DEOH
8723,$,QWHUIDFH6LJQDOV
xxDATy(15:0)
Data bus
xxADRy(3:0)
Address
xxPRTYy
Data path Parity
xxENBy(3:0)
Enable
xxCLAVy(3:0)
Cell available
xxSOCy
Start of Cell
UTzzzCLK
UTOPIA clock
xx=RX: receive line / xx=TX: transmit line
y=U: upstream / y=D: downstream
zzz=PHY: PHY side / zzz=ATM: ATM side
%DFNSUHVVXUH0HFKDQLVP
Backpressure means that cell transmission is disabled even if cells are available from the
transmitting port of the preceding ASIC. In this case no RXENBU / RXCLAVD is set by the ALP
in response to an asserted RXCLAVU / TXENBD.
Upstream line: A backpressure is only asserted if an adjacent ASIC asserts a backpressure to
the ALP.
Downstream line: A backpressure is asserted by the ALP if an empty cell cycle time slot is
needed, e.g. for microprocessor request or for cell insertion from the microprocessor add buffer,
or in case of queue or buffer overflow of the statistical demultiplexing buffer. A PHY overflow
leads only indirectly to a backpressure when the corresponding queue of the statistical
multiplexing buffer overflows.
$/37KURXJKSXW
Nominally the ALP can cope with an UTOPIA frequency of up to F =51,84 Mhz. However the
average net cell rate over UTOPIA interface should be significantly lower due to the limits
imposed by the time needed for internal data processing at the chosen ALP core frequency F .
The maximal allowed net UTOPIA throughput is given by:
B
= F * 53 *8 / 32 bit/s
{ATM cell: 53 * 8 bit}
{internal clock cycles per ATM cell: 32}
For F = 51,84 Mhz we get B = 686,88 Mbit/s.
However with this throughput no empty cell time slots in the ALP core will occur which are
necessary for microprocessor access to external RAMs, insertion of cells from the add buffer as
well as the refresh of policing data. The latter one reduces the maximum allowed net throughput
by about 1%, while the time needed for completing microprocessor requests is inversely
proportional to the frequency of empty cell time slots. In order to be able to read out e.g. the
UTOPIA
CORE
UTMAX
CORE
CORE
Data Sheet
UTMAX
5-148
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
billing counters of 16384 connections within a time interval smaller then 0,5 seconds, the
maximal allowed net throughput has to be reduced by a further 3%.
([WHUQDO5$0,QWHUIDFH
The ALP chip involves three RAM interfaces, CONNRAMUP and POLURAM for the upstream
and CONNRAMDO for the downstream part. The RAM interfaces support access to the external
synchronous SRAMs using bidirectional 32 bit data bus. The MSB of the data bus is used as
parity signal.
Depending on the maximum number of connections supported two RAM types can be
configured by the HW Pin AD25 (RAMVER). Connected to ground selects the
1M SSRAM(32k*32) and to high selects the 2M SSRAM (64k*32). The selection is identical for
all three RAM Interfaces. The Toshiba RAM types TC55V1325FF-7 for 1M SSRAM and
TC55V2325FF-7 for 2M SSRAM are recommended. Other RAM types should fulfil the
specification of Toshiba.
&2115$083
CONNRAMUP is used to store:
– Traffic counters.
– Parts of the internal header (namely HK bits).
– Control flags and internal pointers.
The connection data for one LCI requires 8 x 32bit words in the upstream connection RAM, so
the whole CONNRAMUP has a capacity of 4Mbit for 16k connections or 2 Mbit for 8k
connections. Up to 2 SSRAMs are supported.
32/85$0
The POLURAM is used to store:
– State variables and constant parameters of the policing algorithm.
– Control flags for UPC/NPC configuration.
The policing data for one LCI requires 11 x 32bit words in the policing RAM, so the whole
POLURAM has a capacity of 6Mbit for 16k connections or 3 Mbit for 8k connections. The
POLURAM can be omitted if no UPC/NPC is required. Up to 3 SSRAMs are supported.
Data Sheet
5-149
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
SYSCLK
RAMA DR(14: 0)
RAMA DR(17:1 5)
➋
➊
IO(31:0)
IO(31:0)
A(14:0)
ADSC
A DS C
ADV
CL K
ADV
CE
CONN
CE
GW RAM
GW
OE UP
OE
RDATU(31: 0)
RS CU(1:0)
RAD VU
RCEU(1:0)
RGWU
R OE U
226 Ω
BW1
BW1
BW2
BW2
BW3
BW3
BW4
BW4
MODE
MODE
ZZ
ZZ
10 kΩ
+3.3 V
10 kΩ
+3.3 V
10 kΩ
GND
32K x 32bit
SRAM
1 kΩ
ADSP
A DS P
BWE
B WE
CE 2
CE2
CE 2
CE2
+3.3 V
GND
RDA TD(31: 0)
IO(31:0)
RSCD( 1:0)
A DS C
RADVD
ADV
RCED( 1:0)
CE
RGWD
GW
➊
➋
A(14:0)
OE
PXB 4350 E
ALP
+3.3 V
10 kΩ
A DS P
+3.3 V
10 kΩ
B WE
+3.3 V
10 kΩ
CE2
1 kΩ
32K x 32bit
S RA M
RO ED
CLK
CONN
RAM
DO
CE2
GND
BW1
BW2
BW3
BW4
MODE
226 Ω
ZZ
GND
➌
➋
POLDAT(31:0)
IO(31:0)
POLADSC( 2:0)
A DS C
POLADV
ADV
POLCE(2:0)
CE
POLGW
GW
➊
A(14:0)
POLOE
CLK
POLU
RAM
OE
A DS P
+3.3 V
10 kΩ
B WE
+3.3 V
10 kΩ
CE2
1 kΩ
CE2
GND
32K x 32bit
SRAM
+3.3 V
10 kΩ
BW1
BW2
BW3
BW4
MODE
226 Ω
ZZ
GND
)LJXUH
Data Sheet
&RQQHFWLRQ5$08SVWUHDP,QWHUIDFH6LJQDOV
5-150
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
&2115$0'2
The CONNRAMDO is used to store:
– Traffic Counters.
– The external header (i.e PN, VPI and VCI).
– For Multicast light the pointer to the next entry of the linked list.
– Control flags and internal pointers.
The connection data for one LCI requires 7 x 32bit words in the downstream connection RAM,
so the whole CONNRAMDO has a capacity of 4Mbit for 16k connections or 2 Mbit for 8k
connections. Up to 2 SSRAMs are supported.
The following table shows all possible RAM configurations of the ALP for the usage of the 1M
and 2M SSRAMs types depending on the selection of RAM types controlled by the HW-Pin
RAMVERS and the number of needed connections. The POLURAM is not fully used for the
support of 8k connections with 2M SSRAMs.
7DEOH
3RVVLEOH5$0&RQILJXUDWLRQVRIWKH$/3
Number of supported Connections
16k
HW-Pin RAMVER (AD25)
0 for 1M
1 for 2M
Number of CONNRAMUP
2
2
1
Number of CONNRAMDO
-
2
2
1
Number of POLURAM
-
3
3
2
8k
0 for 1M
1 for 2M
0LFURSURFHVVRUDQG&RQWURO,QWHUIDFH
MPDAT(15:0)
MPADR(7:0)
MPWR
3;%(
$/3
MPRD
MPCS
PLFURSURFHVVRU
L(;
MPINT
MPRDY
MPDREQ
MPDACK
)LJXUH
0LFURSURFHVVRU,QWHUIDFH
The ALP chip has an asynchronous microprocessor interface. The interface consists of an 16
bit wide common data bus with 8 address lines as required for interfacing 80x86 processors.
Bytewise access is not supported. The asynchronous bus access is working with a handshake
mechanism for data flow control. During the inactive state the data bus is switched to high
Data Sheet
5-151
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
impedance, it becomes active only when Chip Select is active.The pins MPDREQ and MPDACK
are used for DMA access. When DMA buffer is not empty, the ALP set the MPDREQ pin to zero.
The microprocessor can now read the DMAR register and give a receipt by setting MPDACK to
zero. If DMA buffer is empty, MPDREQ will be one.
7DEOH
0LFURSURFHVVRU,QWHUIDFH6LJQDOV
6LJQDO
'HVFULSWLRQ
MPDAT(15:0)
Bidirectional common data bus between the microprocessor and the ALP.
Its signals will be tristated when MPCS or MPRDY is high.
MPADR(7:0)
Address bus for the interface.
MPWR
Write signal for the interface (active low).
MPRD
Read signal for the interface (active low).
MPCS
Chip Select signal used to address the ALP (active low).
MPINT
Interrupt Request (active low). This pin is an open drain output.
MPDREQ
DMA request signal indicating that data is to be read out from the DMA
buffer (active low). After the falling edge of the last possible read access
(which empties the receive buffer), the MPDREQ pin becomes inactive
within 60ns to avoid an additional read access of the microprocessor.
MPRDY
Ready output signal for microprocessor write and read access (active
high). This pin is put low by the ALP immediately after the falling edge of
the microprocessor read or write signals MPRD/MPWR and remains
inactive until the ALP has put or get the required data via the bus
MPDAT(15:0). During the first clock period after the low-high change it is
driven high by the ASIC. Afterwards it is held high by a pull-up. During the
inactive time of MPRDY the microprocessor performs wait states.
Data Sheet
5-152
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
-7$*%RXQGDU\6FDQ,QWHUIDFH
TCK
3;%(
$/3
TMS
TDI
TDO
TRST
)LJXUH
-7$*%RXQGDU\6FDQ,QWHUIDFH
The JATG/boundary scan pins TRST, TDI, TCK, TMS, and TDO are required for board test
purposes. The boundary scan is conformal to IEEE 1149.1a (JTAG) serial test bus protocol and
the specification [7]. The ID code of the ALP can be read out from the boundary scan identity
code register. The boundary scan ID number is 523B9069H. Additionally internal control pads
are provided to switch specific output or input/output pins to tristate.
7DEOH
%RXQGDU\6FDQ,QWHUIDFH
TRST
Asynchronous Reset for the Test-Access-Port-Controller
TDI
Test Data Input with internal pull-up resistor
TCK
Test clock with internal pull-up resistor
TMS
Test Mode Select input with internal pull-up resistor
TDO
Test Data Output
1RWH&RQWUROSDGLVDFWLYHKLJKDQGVZLWFKHVWKHFRUUHVSRQGLQJSLQRUJURXSRISLQVWRWULVWDWH
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
0
B24
MPCS
I
1
A24
MPINT
O
2
D22
MPDACK
I
3
-
Control pad for MPDREQ
-
4
B23
MPDREQ
O
Data Sheet
5-153
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
5
-
Control pad for MPRDY
-
6
C23
MPRDY
O
7
-
Control pad for MPDAT(15:0)
-
8
A23
MPDAT(0)
I/O
10
D21
MPDAT(1)
I/O
12
B22
MPDAT(2)
I/O
14
C22
MPDAT(3)
I/O
16
A22
MPDAT(4)
I/O
18
D20
MPDAT(5)
I/O
20
B21
MPDAT(6)
I/O
22
C21
MPDAT(7)
I/O
24
A21
MPDAT(8)
I/O
26
D19
MPDAT(9)
I/O
28
B20
MPDAT(10)
I/O
30
C20
MPDAT(11)
I/O
32
A20
MPDAT(12)
I/O
34
D18
MPDAT(13)
I/O
36
B19
MPDAT(14)
I/O
38
C19
MPDAT(15)
I/O
40
A19
RXDATU(0)
I
41
D17
RXDATU(1)
I
42
B18
RXDATU(2)
I
43
C18
RXDATU(3)
I
44
A18
RXDATU(4)
I
45
D16
RXDATU(5)
I
46
B17
RXDATU(6)
I
47
C17
RXDATU(7)
I
48
A17
RXDATU(8)
I
49
D15
RXDATU(9)
I
50
B16
RXDATU(10)
I
Data Sheet
5-154
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
51
C16
RXDATU(11)
I
52
A16
RXDATU(12)
I
53
B15
RXDATU(13)
I
54
D14
RXDATU(14)
I
55
C15
RXDATU(15)
I
56
-
Control pad for RXADRU(3:0), RXENBU(3:0),
TXDATD(15:0), TXADRD(3:0), TXPRTYD, TXENBD(3:0)
and TXSOCD
57
A15
RXADRU(0)
O
58
B14
RXADRU(1)
O
59
A14
RXADRU(2)
O
60
C14
RXADRU(3)
O
61
C13
RXPRTYU
I
62
B13
RXENBU(0)
O
63
A13
RXENBU(1)
O
64
D13
RXENBU(2)
O
65
C12
RXENBU(3)
O
66
B12
RXCLAVU(0)
I
67
A12
RXCLAVU(1)
I
68
D12
RXCLAVU(2)
I
69
C11
RXCLAVU(3)
I
70
B11
RXSOCU
I
71
A11
UTPHYCLK
I
72
B10
TXDATD(0)
O
73
D11
TXDATD(1)
O
74
C10
TXDATD(2)
O
75
A10
TXDATD(3)
O
76
B9
TXDATD(4)
O
77
D10
TXDATD(5)
O
78
C9
TXDATD(6)
O
79
A9
TXDATD(7)
O
Data Sheet
5-155
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
80
B8
TXDATD(8)
O
81
C8
TXDATD(9)
O
82
A8
TXDATD(10)
O
83
D9
TXDATD(11)
O
84
B7
TXDATD(12)
O
85
A7
TXDATD(13)
O
86
C7
TXDATD(14)
O
87
D8
TXDATD(15)
O
88
B6
TXADRD(0)
O
89
A6
TXADRD(1)
O
90
C6
TXADRD(2)
O
91
B5
TXADRD(3)
O
92
D7
TXPRTYD
O
93
C5
TXENBD(0)
O
94
A5
TXENBD(1)
O
95
B4
TXENBD(2)
O
96
D6
TXENBD(3)
O
97
C4
TXCLAVD(0)
I
98
A4
TXCLAVD(1)
I
99
B3
TXCLAVD(2)
I
100
D5
TXCLAVD(3)
I
101
A3
TXSOCD
O
102
-
Control pad for POLDAT(31:0)
-
103
B1
POLDAT(0)
I/O
105
C2
POLDAT(1)
I/O
107
C1
POLDAT(2)
I/O
109
E4
POLDAT(3)
I/O
111
D2
POLDAT(4)
I/O
113
D3
POLDAT(5)
I/O
115
D1
POLDAT(6)
I/O
Data Sheet
5-156
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
117
F4
POLDAT(7)
I/O
119
E2
POLDAT(8)
I/O
121
E3
POLDAT(9)
I/O
123
E1
POLDAT(10)
I/O
125
G4
POLDAT(11)
I/O
127
F2
POLDAT(12)
I/O
129
F3
POLDAT(13)
I/O
131
F1
POLDAT(14)
I/O
133
H4
POLDAT(15)
I/O
135
G2
POLDAT(16)
I/O
137
G3
POLDAT(17)
I/O
139
G1
POLDAT(18)
I/O
141
J4
POLDAT(19)
I/O
143
H2
POLDAT(20)
I/O
145
H3
POLDAT(21)
I/O
147
H1
POLDAT(22)
I/O
149
K4
POLDAT(23)
I/O
151
J2
POLDAT(24)
I/O
153
J3
POLDAT(25)
I/O
155
J1
POLDAT(26)
I/O
157
L4
POLDAT(27)
I/O
159
K2
POLDAT(28)
I/O
161
K3
POLDAT(29)
I/O
163
K1
POLDAT(30)
I/O
165
M4
POLDAT(31)
I/O
167
L2
POLADSC(0)
O
168
L3
POLADSC(1)
O
169
L1
POLADSC(2)
O
170
M2
POLADV
O
171
N4
POLCE(0)
O
Data Sheet
5-157
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
172
M3
POLCE(1)
O
173
M1
POLCE(2)
O
174
N2
POLGW
O
175
N1
POLOE
O
176
-
Control pad for RDATU(31:0)
-
177
N3
RDATU(0)
I/O
179
P3
RDATU(1)
I/O
181
P2
RDATU(2)
I/O
183
P1
RDATU(3)
I/O
185
P4
RDATU(4)
I/O
187
R3
RDATU(5)
I/O
189
R2
RDATU(6)
I/O
191
R1
RDATU(7)
I/O
193
R4
RDATU(8)
I/O
195
T3
RDATU(9)
I/O
197
T2
RDATU(10)
I/O
199
T1
RDATU(11)
I/O
201
U2
RDATU(12)
I/O
203
T4
RDATU(13)
I/O
205
U3
RDATU(14)
I/O
207
U1
RDATU(15)
I/O
209
V2
RDATU(16)
I/O
211
U4
RDATU(17)
I/O
213
V3
RDATU(18)
I/O
215
V1
RDATU(19)
I/O
217
W2
RDATU(20)
I/O
219
W3
RDATU(21)
I/O
221
W1
RDATU(22)
I/O
223
V4
RDATU(23)
I/O
225
Y2
RDATU(24)
I/O
Data Sheet
5-158
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
227
Y1
RDATU(25)
I/O
229
Y3
RDATU(26)
I/O
231
W4
RDATU(27)
I/O
233
AA2
RDATU(28)
I/O
235
AA1
RDATU(29)
I/O
237
AA3
RDATU(30)
I/O
239
AB2
RDATU(31)
I/O
241
Y4
RSCU(0)
O
242
AB3
RSCU(1)
O
243
AB1
RADVU
O
244
AC2
RCEU(0)
O
245
AA4
RCEU(1)
O
246
AC3
RGWU
O
247
AC1
ROEU
O
248
AD2
RAMADR(0)
O
249
AB4
RAMADR(1)
O
250
AD1
RAMADR(2)
O
251
AF2
RAMADR(3)
O
252
AE3
RAMADR(4)
O
253
AF3
RAMADR(5)
O
254
AC5
RAMADR(6)
O
255
AE4
RAMADR(7)
O
256
AD4
RAMADR(8)
O
257
AF4
RAMADR(9)
O
258
AC6
RAMADR(10)
O
259
AE5
RAMADR(11)
O
260
AD5
RAMADR(12)
O
261
AF5
RAMADR(13)
O
262
AC7
RAMADR(14)
O
263
AE6
RAMADR(15)
O
Data Sheet
5-159
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
264
AD6
RAMADR(16)
O
265
AF6
RAMADR(17)
O
266
-
Control pad for RDATD(31:0)
-
267
AC8
RDATD(0)
I/O
269
AE7
RDATD(1)
I/O
271
AD7
RDATD(2)
I/O
273
AF7
RDATD(3)
I/O
275
AC9
RDATD(4)
I/O
277
AE8
RDATD(5)
I/O
279
AD8
RDATD(6)
I/O
281
AF8
RDATD(7)
I/O
283
AC10
RDATD(8)
I/O
285
AE9
RDATD(9)
I/O
287
AD9
RDATD(10)
I/O
289
AF9
RDATD(11)
I/O
291
AC11
RDATD(12)
I/O
293
AE10
RDATD(13)
I/O
295
AD10
RDATD(14)
I/O
297
AF10
RDATD(15)
I/O
299
AC12
RDATD(16)
I/O
301
AE11
RDATD(17)
I/O
303
AD11
RDATD(18)
I/O
305
AF11
RDATD(19)
I/O
307
AE12
RDATD(20)
I/O
309
AC13
RDATD(21)
I/O
311
AD12
RDATD(22)
I/O
313
AF12
RDATD(23)
I/O
315
AE13
RDATD(24)
I/O
317
AF13
RDATD(25)
I/O
319
AD13
RDATD(26)
I/O
Data Sheet
5-160
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
321
AD14
RDATD(27)
I/O
323
AE14
RDATD(28)
I/O
325
AF14
RDATD(29)
I/O
327
AC14
RDATD(30)
I/O
329
AD15
RDATD(31)
I/O
331
AE15
RSCD(0)
O
332
AF15
RSCD(1)
O
333
AC15
RADVD
O
334
AD16
RCED(0)
O
335
AE16
RCED(1)
O
336
AF16
RGWD
O
337
AE17
ROED
O
338
AC16
SYSCLK
I
339
AD17
RESET
I
340
-
Control pad for ARCDAT(16:0)
-
341
AF17
ARCDAT(0)
I/O
343
AE18
ARCDAT(1)
I/O
345
AC17
ARCDAT(2)
I/O
347
AD18
ARCDAT(3)
I/O
349
AF18
ARCDAT(4)
I/O
351
AE19
ARCDAT(5)
I/O
353
AD19
ARCDAT(6)
I/O
355
AF19
ARCDAT(7)
I/O
357
AC18
ARCDAT(8)
I/O
359
AE20
ARCDAT(9)
I/O
361
AF20
ARCDAT(10)
I/O
363
AD20
ARCDAT(11)
I/O
365
AC19
ARCDAT(12)
I/O
367
AE21
ARCDAT(13)
I/O
369
AF21
ARCDAT(14)
I/O
Data Sheet
5-161
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
371
AD21
ARCDAT(15)
I/O
373
AE22
ARCDAT(16)
I/O
375
AC20
ARCADR(0)
O
376
AD22
ARCADR(1)
O
377
AF22
ARCADR(2)
O
378
AE23
ARCADR(3)
O
379
AC21
ARCRES
O
380
AD23
ARCCS
O
381
AF23
ARCWE
O
382
AE24
ARCOE
O
383
AC22
ARCCLK
O
384
AF24
SMODE
I
385
AE26
SENAB
I
386
AD25
RAMVERS
I
387
-
Control pad for RXCLAVD(0)
-
388
-
Control pad for RXCLAVD(1)
-
389
-
Control pad for RXCLAVD(2)
-
390
-
Control pad for RXCLAVD(3)
-
391
AC26
RXCLAVD(0)
I/O
393
AA23
RXCLAVD(1)
I/O
395
AB25
RXCLAVD(2)
I/O
397
AB24
RXCLAVD(3)
I/O
399
AB26
RXDATD(0)
I
400
Y23
RXDATD(1)
I
401
AA25
RXDATD(2)
I
402
AA24
RXDATD(3)
I
403
AA26
RXDATD(4)
I
404
W23
RXDATD(5)
I
405
Y25
RXDATD(6)
I
406
Y24
RXDATD(7)
I
Data Sheet
5-162
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
407
Y26
RXDATD(8)
I
408
V23
RXDATD(9)
I
409
W25
RXDATD(10)
I
410
W24
RXDATD(11)
I
411
W26
RXDATD(12)
I
412
U23
RXDATD(13)
I
413
V25
RXDATD(14)
I
414
V24
RXDATD(15)
I
415
V26
RXPRTYD
I
416
-
Control pad for RXADRD(3:0) and RXENBD(3:0)
-
417
T23
RXADRD(0)
I/O
419
U25
RXADRD(1)
I/O
421
U24
RXADRD(2)
I/O
423
U26
RXADRD(3)
I/O
425
R23
RXENBD(0)
I/O
427
T25
RXENBD(1)
I/O
429
T24
RXENBD(2)
I/O
431
T26
RXENBD(3)
I/O
433
R25
RXSOCD
I
434
P23
TXMS
I
435
R24
RXMS
I
436
R26
UTATMCLK
I
437
-
Control pad for TXDATU(15:0), TXPRTYU and TXSOCU -
438
P26
TXDATU(0)
O
439
P24
TXDATU(1)
O
440
N24
TXDATU(2)
O
441
N25
TXDATU(3)
O
442
N26
TXDATU(4)
O
443
N23
TXDATU(5)
O
444
M24
TXDATU(6)
O
Data Sheet
5-163
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
445
M25
TXDATU(7)
O
446
M26
TXDATU(8)
O
447
M23
TXDATU(9)
O
448
L24
TXDATU(10)
O
449
L25
TXDATU(11)
O
450
L26
TXDATU(12)
O
451
K25
TXDATU(13)
O
452
L23
TXDATU(14)
O
453
K24
TXDATU(15)
O
454
K26
TXPRTYU
O
455
-
Control pad for TXCLAVU(0)
-
456
-
Control pad for TXCLAVU(1)
-
457
-
Control pad for TXCLAVU(2)
-
458
-
Control pad for TXCLAVU(3)
-
459
J25
TXCLAVU(0)
I/O
461
K23
TXCLAVU(1)
I/O
463
J24
TXCLAVU(2)
I/O
465
J26
TXCLAVU(3)
I/O
467
H25
TXSOCU
O
468
-
Control pad for TXADRU(3:0) and TXENBU(3:0)
-
469
H24
TXADRU(0)
I/O
471
H26
TXADRU(1)
I/O
473
J23
TXADRU(2)
I/O
475
G25
TXADRU(3)
I/O
477
G26
TXENBU(0)
I/O
479
G24
TXENBU(1)
I/O
481
H23
TXENBU(2)
I/O
483
F25
TXENBU(3)
I/O
485
F26
MPADR(0)
I
486
F24
MPADR(1)
I
Data Sheet
5-164
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
7DEOH
$/3%RXQGDU\6FDQ7DEOH
%RXQGDU\6FDQ 3,11U 6LJQDO1DPH
1XPEHU
7\SH
487
E25
MPADR(2)
I
488
G23
MPADR(3)
I
489
E24
MPADR(4)
I
490
E26
MPADR(5)
I
491
D25
MPADR(6)
I
492
F23
MPADR(7)
I
493
D24
MPWR
I
494
D26
MPRD
I
&ORFN$QG5HVHW,QWHUIDFH
SYSCLK
RESET
UTPHYCLK
UTATMCLK
)LJXUH
ARCRES
3;%(
$/3
ARCCLK
&ORFNDQG5HVHW,QWHUIDFH
ALP System Clock (SYSCLK):
The ALP system (core) clock range is 25 Mhz up to 51.84 Mhz.
Reset Input Signal (RESET):
The RESET signal is fed in via a LVTTL-compatible input. With low level (GND) it causes an
asynchronous reset of the internal circuit. The reset must be asserted for a minimum of four
clock cycles. After the reset is accepted the outputs are hold in inactive state and all bidirectional
I/Os are switched to tristate until RESET is released. At the low to high transition on the RESET
line follows an internal synchronous reset.
UTOPIA clocks (UTPHYCLK, UTATMCLK):
Two UTOPIA clock inputs (one for the PHY- and one for the ATM- side), independent from each
other and from SYSCLK, must be provided. The frequency of the UTOPIA clocks must be lower
than or equal to SYSCLK.
Data Sheet
5-165
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
CAME clock (ARCCLK):
It is derived from SYSCLK by dividing frequency by a factor of two.
CAME Reset Output Signal (ARCRES):
It is a LVCMOS low active output. It is asserted by ALP for four SYSCLK periods after the rising
edge of RESET.
&$0(,QWHUIDFH
ARCCLK
CLK
ARCCS
CS
ARCWE
WE
ARCOE
OE
ARCRES
RES
ARCADR(3:0)
CAME
(Master)
ADR(3:0)
1k Ω
EN16
GND
ARCDAT(16:0)
DAT(16:0)
+ 3.3 V
10kΩ
DAT(32:17)
CI(2:0) CO(2:0) CA
ALP
10kΩ
1kΩ
+ 3.3 V
GND
CO(2:0) CI(2:0) CA
CLK
CS
WE
CAME
(Slave)
OE
RES
ADR(3:0)
1kΩ
EN16
GND
DAT(16:0)
+ 3.3 V
)LJXUH
Data Sheet
10kΩ
DAT(32:17)
&$0(,QWHUIDFHIRUN&RQQHFWLRQV
5-166
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
ALP
ARCCLK
CLK
ARCCS
CS
ARCWE
WE
ARCOE
OE
CAME
(Master)
RES
ARCRES
ADR(3:0)
ARCADR(3:0)
1kΩ
EN16
GND
DAT(16:0)
ARCDAT(16:0)
+ 3.3 V
10 kΩ
DAT(32:17)
1 kΩ
CI(2:0) CO(2:0) CA
GND
)LJXUH
&$0(,QWHUIDFHIRUN&RQQHFWLRQV
For the address reduction of the 32 bit input address consisting of concatenated PN/VPI/VCI
values down to the 14 bit LCI up to two parallel cascaded CAME chips are supported. From the
ALP’s perspective they behave like a single chip.
In NNI mode the sum of the length of PN (up to 6 bit), VPI (12bit) and VCI (16bit) exceed 32bit,
which can be maximally processed by CAME.
In this case only the (16 - (number of PN bits)) least significant VPI bits are mapped into the input
address.
During the connection setup the CAMEs are initialized by SW, i.e. the input addresses (PN/VPI/
VCI) of valid connections are stored at the addresses of the corresponding LCIs. At cell arrival
an inverse operation is performed: The PN/VPI/VCI value of the cell is passed to the CAMEs,
which search for an corresponding entry and return its LCI.
In some important cases (e.g. the ALP is configurated as an intermediate point of a virtual path,
or F4-OAM cells are received at a virtual path terminating point) pure PN/VPI translation takes
place and the VCI part is ignored.
ARCCLK is half of the ALP core frequency given by SYSCLK.
Data Sheet
5-167
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
'DWD6WUXFWXUHDW&$0('DWD%XV
CAME Data bit(16) is used as parity line and completes the ARCDAT(1:15) and ACRADR(0:3)
to odd parity.
6HDUFKSURFHVVLQJIRU2$0))ORZ
Write to address CH
Wait for command
execution
Read from address 6H
Read from address EH
bit: 15 14 13 12 11 10
PN(3:0)
V
9
8
I
7
6 5 4
VPI(11:0)
3
2
1
0
LCI(13:0)
S3 S2 S1 S0
6HDUFKSURFHVVLQJIRUXVHUFHOOV
Write to address DH
Write to address 5H
Wait for command
execution
Read from address 6H
Read from address EH
bit: 15 14 13 12 11 10
PN(3:0)
V
9
8
6 5 4
VPI(11:0)
VCI(15:0)
I
7
3
2
1
0
LCI(13:0)
S3 S2 S1 S0
6HDUFKSURFHVVLQJDFWLYDWHGYLDWKHPLFURSURFHVVRU
Write to address EH
Write to address 6H
Wait for command
execution
Read from address 6H
Read from address EH
Data Sheet
bit: 15 14 13 12 11 10
PN(3:0)
V
I
9
8
7
6 5 4
VPI(11:0)
VCI(15:0)
3
2
1
0
LCI(13:0)
S3 S2 S1 S0
5-168
08.2000
3;%(
,QWHUIDFH'HVFULSWLRQ
&$0(:ULWHFRPPDQGIRUFRQILJXUDWLRQRIWKHFRQQHFWLRQ
Write to address 2H
Write to address BH
Write to address 3H
Wait for command
execution
Read from address 6H
Read from address EH
bit: 15 14 13 12 11 10
V I
PN(3:0)
9
8
7 6 5 4
LCI(13:0)
VPI(11:0)
VCI(15:0)
3
2
1
0
S3 S2 S1 S0
&$0(5HDGFRPPDQGIRUYHULILFDWLRQRIWKHFRQQHFWLRQHQWU\
bit: 15 14 13 12 11 10
Write to address 0H
Wait for command
execution
Read from address 1H
Read from address 9H
Read from address 6H
Read from address EH
9
PN(3:0)
V
8
7 6 5
LCI(13:0)
4
3
2
1
0
VPI(11:0)
VCI(15:0)
I
S3 S2 S1 S0
&$0(7HVWDQG&RQILJXUDWLRQFRPPDQG
bit: 15 14 13 12 11 10
Write to address 7H
Wait for command
execution
Read from address 7H
Read from address FH
9
8 7 6 5 4
Testmode(13:0)
3
2
1
0
Testmode(13:0)
S3 S2 S1 S0
7HVW,QWHUIDFH
There are several additional test pins provided for board test. Please let them unconnected or
connected to ground as described in section 1.4, part "Additional Testpins".
Data Sheet
5-169
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
(OHFWULFDO&KDUDFWHULVWLFV
$EVROXWH0D[LPXP5DWLQJV
7DEOH
$EVROXWH0D[LPXP5DWLQJV
3DUDPHWHU
6\PERO
Storage Temperature
7S
-40 to 125
°C
Junction Temperature
7J
max. 125
°C
Supply Voltage
9DD
-0.3 to 3.9
V
Input Voltage for 3.3V pads
9IN
-1.0 to 9DD+0.3
V
Input Voltage for 5V compatible pads
9IN
-1.0 to 6.5
V
Output Voltage
9OUT
DC Input Currents
,IN
-10 to 10
µA
Power Dissipation
3V
1.7
W
1RWH
/LPLW9DOXHV
8QLW
V
6WUHVVHV DERYH WKRVH OLVWHG KHUH PD\ FDXVH SHUPDQHQW GDPDJH WR WKH GHYLFH ([SRVXUH WR DEVROXWH
PD[LPXPUDWLQJFRQGLWLRQVIRUH[WHQGHGSHULRGVPD\DIIHFWGHYLFHUHOLDELOLW\
2SHUDWLQJ&RQGLWLRQV
7DEOH
2SHUDWLQJ&RQGLWLRQV
3DUDPHWHU
6\PERO
Supply voltage
9DD
3.14 to 3.47
V
Ground
9SS
0
V
Ambient temperature under bias
7A
-45 to 85
°C
Junction temperature
7J
max. 110
°C
Data Sheet
6-170
/LPLW9DOXHV
8QLW
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
'&&KDUDFWHULVWLFVIRUDOO,QWHUIDFHV
7DEOH
'&&KDUDFWHULVWLFV
3DUDPHWHU
6\PERO
/LPLW9DOXHV
PLQ
W\S
PD[
8QLW
3.47
V
7HVW&RQGLWLRQ
Supply Voltage
9DD
3.14
Input Low Voltage
9IL
9SS
-0.5
0.8
V
Input High Voltage
9IH
2.0
9DD
+0.3
V
LVTTL (3.3V)
2.0
5.5
V
5-Volt compatible
1.4
2.0
V
-10
-1..+1
10
µA
9IN=9DD or 9SS
35
115
222
µA
9IN=9DD for Inputs
with Pulldown
resistors
-35
-115
-214
µA
9IN=9SS for Inputs
with Pullup resistors
9DD
V
,OH=- 4 mA
0.2
0.4
V
,OH= 4 mA
-1..+1
10
µA
Switching Threshold
9T
Input Current
,IN
3.3
Output High Voltage
9OH
Output Low Voltage
9OL
Three-state
Output Leakage Current
,OZ
-10
Input Capacitance
&IN
2.5
5
pF
Output Capacitance
&OUT
2
5
pF
1RWH
2.4
7KH OLVWHG FKDUDFWHULVWLFV DUH HQVXUHG RYHU WKH RSHUDWLQJ UDQJH RI WKH LQWHJUDWHG FLUFXLW 7\SLFDO
FKDUDFWHULVWLFV VSHFLI\ PHDQ YDOXHV H[SHFWHG RYHU WKH SURGXFWLRQ VSUHDG ,I QRW RWKHUZLVH VSHFLILHG
W\SLFDOFKDUDFWHULVWLFVDSSO\DW7$ °&DQGWKHJLYHQVXSSO\YROWDJH
Data Sheet
6-171
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
&DSDFLWDQFHV
7DEOH
&DSDFLWDQFHV
3DUDPHWHU
6\PERO
PLQ
/LPLW9DOXHV
PD[
8QLW
Input Capacitance
&IN
2.5
5
pF
Output Capacitance
&OUT
2
5
pF
Load Capacitance at:
UTOPIA PHY side
RAMADR(17:0)
MPDAT(15:0), MPRD
POLURAMDAT(31:0)
other outputs
&FO1
&FO2
&FO3
&FO4
&FO5
85
85
50
40
30
pF
pF
pF
pF
pF
$&&KDUDFWHULVWLFV
7A = -40 to 85°C , 9CC = 3.3 V ± 5 % , 9SS = 0 V
All inputs are driven to 9IH = 2.4 V for a logical “1”
and to 9IL = 0.4 V for a logical “0”
All outputs are measured at 9H = 2.0 V for a logical “1”
and at
9L = 0.8 V for a logical “0”
The AC testing input/output waveforms are shown below.
VH
VH
Test Points
VL
Device
under
Test
VL
CLOAD = 50 pF max
ac_int.ds4
)LJXUH
Data Sheet
,QSXW2XWSXW:DYHIRUPIRU$&0HDVXUHPHQWV
6-172
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
&ORFNDQG5HVHW,QWHUIDFH
1
SYSCLK
3
2
ARCCLK
4
RESET
)LJXUH
&ORFNDQG5HVHW,QWHUIDFH7LPLQJ'LDJUDP
7DEOH
&ORFNDQG5HVHW,QWHUIDFH$&7LPLQJ&KDUDFWHULVWLFV
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
1
7SYSCLK : Period SYSCLK
1A
)SYSCLK : Frequency SYSCLK
2
Delay SYSCLK to ARCCLK
3
3
7ARCCLK : Period ARCCLK
38.6
3A
)ARCCLK : Frequency ARCCLK
4
Pulse width RESET low
7DEOH
&ORFN)UHTXHQFLHV
3DUDPHWHU
19.3
8QLW
ns
51.84
MHz
15
ns
ns
25.92
MHz
7SYSCLK
5
6\PERO
PLQ
8QLW
51.84
MHz
Core-clock
SYSCLK
UTOPIA clock at PHY-side
UTPHYCLK
<ISYSCLK
MHz
UTOPIA clock at ATM-side
UTATMCLK
<ISYSCLK
MHz
<ISYSCLK/2
MHz
µP clock1)
1)
25
/LPLW9DOXHV
PD[
Supplied only to i386EX µP
Data Sheet
6-173
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
'0$,QWHUIDFH
1
1
PH2
2
PH1
3
PH2
PH1
4
5
PH2
6
PH1
7
PH2
8
386EX: CLK2
T1
T2
T2
386EX: CLKOUT
386EX: RD
2
MPDREQ
3
4
MPDACK
)LJXUH
'0$,QWHUIDFH7LPLQJ'LDJUDP
7DEOH
&ORFNDQG5HVHW,QWHUIDFH$&7LPLQJ&KDUDFWHULVWLFV
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
8QLW
1
7CLK2 : Period CLK2
40
ns
1A
)CLK2 : Frequency CLK2
25
MHz
2
7RDMPDREQ
90
ns
3
7SYSCLK : Period SYSCLK
7SYSCLK
ns
4
7RDMPACK
200
ns
8723,$,QWHUIDFH
The AC Characteristic of the UTOPIA Interface fulfils the UTOPIA Standard [1 and 2].
Data Sheet
6-174
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
65$0,QWHUIDFH
1
SYSCLK
2
3
ADSC, ADV, A(17:0)
GW, CE, OE
4
RDATx / POLDAT Output
5
6
RDATx / POLDAT Input
7
)LJXUH
65$0,QWHUIDFH*HQHULF7LPLQJ'LDJUDP
7DEOH
65$0,QWHUIDFH$&7LPLQJ&KDUDFWHULVWLFVIRUS)/RDG
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
1
7SYSCLK : Period SYSCLK
1A
)SYSCLK : Frequency SYSCLK
2
SYSCLK Low Pulse Width
3
19.3
8QLW
ns
51.84
MHz
40
60
%
SYSCLK High Pulse Width
40
60
%
4
Delay SYSCLK rising to ADSC, ADV,
A(14:0), GW, CE, OE
2
15
ns
5
Delay SYSCLK rising to RDATx / POLDAT 2
Output
15
ns
6
Setup time RDATx / POLDAT Input before 10
SYSCLK rising (all read cycles)
ns
7
Hold time RDATx / POLDAT Input after
SYSCLK rising (all read cycles)
ns
1RWH
2
7KH665$0LQWHUIDFHLVGHVLJQHGWRIXOILOWKH7RVKLED665$0VSHFLILFDWLRQ7\SH7&9))0
665$0N[RU7\SH7&9))0665$0N[,IRWKHU665$0¶VDUHXVHGSOHDVH
FKHFNZKHWKHUWKHVHDUHFRPSOLDQWWR7RVKLED7KH$/3GRHVQRWXVHWKH%:($'63DQG6QRR]HPRGH
Data Sheet
6-175
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
0LFURSURFHVVRU,QWHUIDFH
0LFURSURFHVVRU:ULWH&\FOH
MPADR
1
9
MPCS
8
2
MPWR
3
6
5
MPRDY
4
7
MPDAT
)LJXUH
0LFURSURFHVVRU:ULWH&\FOH7LPLQJ'LDJUDP
i td 4
7DEOH
0LFURSURFHVVRU:ULWH&\FOH$&7LPLQJ&KDUDFWHULVWLFV
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
8QLW
1
Setup time MPADR before MPCS low
0
ns
2
Setup time MPCS before MPWR low
0
ns
3
Delay MPRDY low after MPWR low
1
4
MPDAT setup time before MPWR high
5
5
Pulse width MPRDY low
3 x 7clock
6
MPRDY high to MPWR high
10
ns
7
Hold time MPDAT after MPWR high
5
ns
8
Hold time MPCS after MPWR high
5
ns
9
Hold time MPADR after MPWR high
5
ns
Data Sheet
6-176
15
ns
ns
4 x 7clock
ns
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
0LFURSURFHVVRU5HDG&\FOH
)LJXUH
0LFURSURFHVVRU5HDG&\FOH7LPLQJ'LDJUDP
7DEOH
0LFURSURFHVVRU5HDG&\FOH$&7LPLQJ&KDUDFWHULVWLFV
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
8QLW
1
Setup time MPADR before MPCS low
0
ns
2
Setup time MPCS before MPRD low
0
ns
3
Delay MPRDY low after MPRD low
1
15
ns
4
Pulse width MPRDY low
4 x 7clock
5 x 7clock
ns
5
MPDAT valid before MPRDY high
5
ns
6
MPRDY high to MPRD high
5
ns
7
Hold time MPDAT after MPRD high
2
ns
8
Hold time MPCS after MPRD high
5
ns
9
Hold time MPADR after MPRD high
5
ns
10
Delay MPRD low to MPDAT low
impedance
1
15
ns
11
Delay MPRD high to MPDAT high
impedance
1
15
ns
Data Sheet
6-177
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
%RXQGDU\6FDQ7HVW,QWHUIDFH
1
TCK
3
2
TDI
TMS
5
4
TDO
6
TRST
ITT10215
)LJXUH
%RXQGDU\6FDQ7HVW,QWHUIDFH7LPLQJ'LDJUDP
7DEOH
%RXQGDU\6FDQ7HVW,QWHUIDFH$&7LPLQJ&KDUDFWHULVWLFV
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
8QLW
1
7TCK : Period TCK
1A
)TCK : Frequency TCK
2
Setup time TMS, TDI before TCK rising
10
ns
3
Hold time TMS, TDI after TCK rising
10
ns
4
Delay TCK falling to TDO valid
10
ns
5
Delay TCK falling to TDO high impedance
10
ns
6
Pulse width TRST low
Data Sheet
100
ns
10
200
6-178
MHz
ns
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
$&&KDUDFWHULVWLFVRI&$0(,QWHUIDFH
1
2
n-1
n
ARCCLK
ARCCS
ARCOE
ARCWE
ARCADR(3:0)
ARCDAT(16:0)
Start (first write)
)LJXUH
End (last read)
([DPSOHRI([HFXWLRQ7LPLQJIRU:ULWH&RPPDQG5HTXHVW
7DEOH
'XUDWLRQRI&RPPDQG([HFXWLRQ
3DUDPHWHU
/LPLW9DOXHV
PLQ W\S PD[
8QLW
Cell processing search, PN/VPI reduction
13
clock cycles
Cell processing search, PN/VPI/VCI reduction
14
clock cycles
Search request by the microprocessor
14
clock cycles
CAME Write command
10
clock cycles
CAME Read command
13
clock cycles
Test and configuration of the CAME
9
clock cycles
Data Sheet
6-179
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
SYSCLK
1
ARCCLK
3
2
4
4
4
4
4
4
4
4
ARCCS
ARCOE
ARCWE
ARCADR(3:0)
4
5
6
ARCDATA(16:0)
)LJXUH
&$0(5HDG&\FOH
SYSCLK
1
4
4
ARCCLK
2
3
4
4
4
4
4
4
4
4
4
4
ARCCS
ARCOE
ARCWE
ARCADR(3:0)
ARCDATA(16:0)
)LJXUH
Data Sheet
&$0(:ULWH&\FOH
6-180
08.2000
3;%(
(OHFWULFDO&KDUDFWHULVWLFV
7DEOH
3DUDPHWHUVIRU5HDG:ULWH$FFHVV
1R
3DUDPHWHU
8QLW
PLQ
/LPLW9DOXHV
W\S
PD[
1
ARCCLK frequency
0.01
25.92
MHz
2
ARCCLK low pulse width
40
60
%
3
ARCCLK high pulse width
40
60
%
4
Path delay SYCLK to ARCCLK,
ARCCS, ARCWE, ARCOE, ARCADR,
and ARCDAT
3
15
ns
5
Setup time of ARCDAT in read cycle to 5
SYSCLK ↑
ns
6
Hold time of ARCDAT in read cycle from 4
SYSCLK ↑
ns
Data Sheet
6-181
08.2000
3;%(
3DFNDJH2XWOLQHV
GPA05990
3DFNDJH2XWOLQHV
3%*$
(Plastic Ball Grid Array)
)LJXUH
6RUWVRI3DFNLQJ
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
7-182
08.2000
3;%(
3DFNDJH2XWOLQHV
7DEOH 7KHUPDO5HVLVWDQFH
3DUDPHWHU
Junction to case
Junction to ambient air without air flow
Junction to ambient air with air flow 1.0 m/s
Junction to ambient air with air flow 2.0 m/s
Junction to ambient air with air flow 3.0 m/s
Data Sheet
6\PERO
5thJC
5thJA
5thJA
5thJA
5thJA
7-183
/LPLW9DOXHV
3.8
18.7
16.2
15.2
14.4
8QLW
K/W
K/W
K/W
K/W
K/W
08.2000
3;%(
5HIHUHQFHV
5HIHUHQFHV
1.
2.
3.
4.
5.
6.
7.
8.
9.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
UTOPIA Level 1 Specification Version 2.01, March 21, 1994, ATM Forum
UTOPIA Level 2 Specification Version 1.0, June 1995, ATM Forum
IEEE 1596.3 Standard for Low-Voltage Differential Signals for SCI, Draft 1.3, Nov. 95
Joint Test Action Group JTAG standard IEEE std. 1149.1
T. Worster, W. Fischer, S. Davis, A. Hayter, “Buffering and flow control for statistical
multiplexing in an ATM switch”, International Switching Symposium ISS’95, April 1995
‘ATM Networks: Concepts, Protocols, Applications’, Händel, Schröder, Huber, AddisonWesley, 1994, ISBN 0-201-42274-3
ITU-T Recommendation I.610 “B-ISDN Operation and Maintenance Principles and
Functions”, 11/95
Bellcore TA-NWT 1248
PXB 4360 E CAME, Data Sheet 04.2000 DS2
$FURQ\PV
ABM = PXB 4330 E $TM %uffer 0anager
ABR = $vailable %it 5ate
ABT = $TM %lock 7ransfer
AIS = $larm ,ndication 6ignal (OAM function)
ALP = PXB 4350 E $TM /ayer 3rocessor
AOP = PXB 4340 E $TM 2AM 3rocessor
ARC = $ddress 5eduction &ircuit (CAME PXB 4360 E)
BIP-16 = %it ,nterleaved 3arity, 16 bit
BR = %ackward 5eporting (PM function)
byte = octet = 8 bit
CAME = &ontent $ddressable 0emory (lement
CC = &ontinuity &heck (OAM function)
CCA = &ontinuity &heck $ctivation
CDV = &ell 'elay 9ariation
CLP = &ell /oss 3riority of standardized ATM cell
DBR = 'eterministic %it 5ate
double word = 32 bit
F4 = Virtual Path Layer
F5 = Virtual Channel Layer
FIFO = )irst-Ln-Iirst-Rut buffer
FM = )orward 0onitoring (PM cell type)
HK = +ouse.eeping bits of UDF1 field in UTOPIA cell format
HT = +eader 7ranslation
I/O = ,nput / 2utput
ICC = ,nternal &ontinuity &heck (proprietary OAM function)
IP = ,ntermediate 3oint
ITU-T = ,nternational 7elecommunications 8nion - 7elecommunications standardization
sector
IWE8 = PXB 4220 ,nterZorking (lement for 8 channels
LB = /oopEack (OAM function)
LB = /eaky %ucket
LCI = /ocal &onnection ,dentifier
Data Sheet
8-184
08.2000
3;%(
5HIHUHQFHV
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LIC = /ine ,nterface &ard or Line Interface Circuit
LOC = /oss 2f &ontinuity (OAM state)
LPS = /ine 3rotection 6witching
LSB = /east 6ignificant %it
MBS = 0aximum %urst 6ize
MCR = 0inimum &ell 5ate
NPC = 1etwork 3arameter &ontrol
octet = byte = 8 bit
OAM = 2peration Dnd 0aintenance
OEP = 2riginating (nd 3oint
OSP = 2riginating 6egment 3oint
PCR = 3eak &ell 5ate
PM = 3erformance 0onitoring (OAM function)
PN = 3ort 1umber
PTI = 3ayload 7ype ,ndication field of standardized ATM cell
RAM = 5andom $ccess 0emory
RDI = 5emote 'efect ,ndication (OAM function)
RM = 5esource 0anagement Cell
RWR RAM = µP Read/Write RAM
RXR RAM = Rx 12 cell extraction Buffer
SCR = 6ustainable &ell 5ate
SSRAM = 6ynchronous 6tatic 5$0
tbd = Wo Ee Gefined
TEP = 7erminating (nd 3oint
TM = 7raffic 0anagement
TRM RAM = 7Uaffic 0easurement Port Table
UCW RAM = Upstream workbench
UPC = 8ser 3arameter &ontrol
UTOPIA = 8niversal 7est and 2Seration ,nterface for $TM
UTRXD Buffer = 87OPIA 5[-Gownstream cell FIFO
UTRXU Buffer = 87OPIA 5[-Xpstream cell FIFO
UTTXD Buffer = 87OPIA 7[-Gownstream shared memory Buffer
UTTXU Buffer = 87OPIA 7[-Xpstream cell FIFO
VC- = 9irtual &hannel specific
VCC = 9irtual &hannel &onnection
VCI = 9irtual &hannel ,dentifier of standardized ATM cell
VP- = 9irtual 3ath specific
VPC = 9irtual 3ath &onnection
VPI = 9irtual 3ath ,dentifier of standardized ATM cell
word = 16 bit
Data Sheet
8-185
08.2000