INFINEON PXB4219

D at a S hee t, DS 3 , M ay 2 00 2
IWE8
Interworking Element for 8 E1/T1
Lines
PXB4219 / PXB4220 / PXB4221
V er s i o n 3 . 3
Datacom
N e v e r
s t o p
t h i n k i n g .
Edition 2002-05-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 5/6/02.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D at a S hee t, DS 3 , M ay 2 00 2
IWE8
Interworking Element for 8 E1/T1
Lines
PXB4219 / PXB4220 / PXB4221
V er s i o n 3 . 3
Datacom
N e v e r
s t o p
t h i n k i n g .
PXB4219 / PXB4220 / PXB4221
Revision History:
2002-05-06
Previous Version:
03.2000
DS3
Page
Subjects (major changes since last revision)
234 ff.
Jitter characteristics of the ICRC included
252 ff.
Electrical characteristics of Framer, UTOPIA and RAM interface changed
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PXB4219 / PXB4220 / PXB4221
Table of Contents
Page
1
1.1
1.2
1.3
1.3.1
1.3.2
1.4
1.5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differences Between PXB4220 And PXB4219 . . . . . . . . . . . . . . . . . . . . .
Differences Between PXB4220 And PXB4221 . . . . . . . . . . . . . . . . . . . . .
17
18
20
21
22
22
24
24
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Not Connected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
26
27
30
30
31
33
34
35
36
36
3
3.1
3.1.1
3.1.2
3.1.2.1
3.1.2.2
3.2
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AAL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unstructured CES Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structured CES Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
38
38
38
38
39
40
41
4
4.1
4.1.1
4.1.1.1
4.1.1.2
4.1.1.3
4.1.1.4
4.1.1.5
4.1.2
4.2
4.2.1
4.2.1.1
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Transmit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Transmit Buffer Filling Level . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Discarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell rate de-coupling: Idle/Unassigned Cell Insertion . . . . . . . . . . . .
Cell Payload Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HEC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup of ATM Transmit Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Receive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
45
45
46
46
47
47
48
49
49
49
Data Sheet
5
2002-05-06
PXB4219 / PXB4220 / PXB4221
4.2.1.2
HEC Check: Header Error Detection and Correction . . . . . . . . . . . .
4.2.1.3
Cell Payload Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1.4
Idle, Physical Layer or Unassigned Cell Deletion . . . . . . . . . . . . . . .
4.2.2
Setup of ATM Receive Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
AAL Segmentation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1.1
Segmentation Port Decorrelation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1.2
Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1.3
Transport of the Framer Port Number . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1.4
Transport of CAS Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1.5
CAS Conditioning and Freezing Upstream . . . . . . . . . . . . . . . . . . . .
4.3.1.6
Segmentation Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1.7
Padding Partially Filled Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Setup of AAL Segmentation Channels . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
AAL Reassembly Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.1
Port and Channel Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.2
Sequence Number Protection field check . . . . . . . . . . . . . . . . . . . . .
4.4.1.3
Sequence Number field check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.4
RTS Extraction and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.5
Pointer Field Detection and Verification . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.6
CAS Conditioning and Freezing Downstream . . . . . . . . . . . . . . . . . .
4.4.1.7
Insertion of Dummy Cells at Cell Loss . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.8
Reassembly Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.9
Handling of Reassembly Buffer Overflow . . . . . . . . . . . . . . . . . . . . .
4.4.1.10
Handling of Reassembly Buffer Underflow . . . . . . . . . . . . . . . . . . . .
4.4.1.11
Synchronization of SDT Structure with Port Structure . . . . . . . . . . . .
4.4.2
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.1
Setup of Reassembly Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.2
Physical Reassembly Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.3
Initialization of the Reassembly Buffer . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.4
Re-Initialization of the Reassembly Buffer . . . . . . . . . . . . . . . . . . . . .
4.5
Internal Clock Recovery Circuit (ICRC) . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2
Frame Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3
Frame Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4
RTS Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.5
RTS Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.6
ICRC Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7
RTS Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.8
Fractional Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.9
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.10
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
6
51
52
52
54
55
55
55
56
56
57
57
58
58
59
61
61
61
61
62
62
62
63
63
63
64
64
65
65
65
66
67
72
73
74
74
74
75
76
76
76
77
77
77
2002-05-06
PXB4219 / PXB4220 / PXB4221
4.5.11
4.5.11.1
4.5.11.2
4.5.11.3
4.5.11.4
4.6
4.6.1
4.6.2
4.6.3
4.7
4.8
4.8.1
4.8.2
4.8.3
4.9
4.10
4.11
4.11.1
4.11.2
4.11.2.1
4.11.2.2
4.11.2.3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Block
PLL-SRTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL-FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL-ACM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRTS with ACM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OAM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upstream Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Downstream Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mapping of Channels to Timeslots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AAL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unstructured CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structured CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structured CES with CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.2
5.1.2.1
5.1.2.2
5.1.3
5.1.3.1
5.1.3.2
5.1.4
5.2
5.2.1
5.2.2
5.2.2.1
5.2.2.2
5.2.3
5.3
5.4
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Generic Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
FALC Mode (FAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Generic Interface Mode (GIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Synchronous Modes (SYM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Synchronous Mode at 2.048 MHz (SYM2) . . . . . . . . . . . . . . . . . . . 102
Synchronous Mode at 8.192 MHz (SYM8) . . . . . . . . . . . . . . . . . . . 104
Echo Canceller Mode (EC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Port Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Back Pressure/ATM Cell Discarding . . . . . . . . . . . . . . . . . . . . . . . . . . 108
General Backpressure Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 108
Port Specific Backpressure Mechanism . . . . . . . . . . . . . . . . . . . . . 109
Sideband Signals of the UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . 109
IMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Clock Recovery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Data Sheet
7
77
77
78
78
80
81
81
81
81
82
83
83
83
84
85
86
87
87
88
88
89
90
2002-05-06
PXB4219 / PXB4220 / PXB4221
5.5
5.5.1
5.5.2
5.6
5.7
5.8
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
114
114
115
117
118
119
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.2
6.1.2.1
6.1.2.2
6.1.2.3
6.1.2.4
6.1.2.5
6.1.3
6.1.3.1
6.1.4
6.1.4.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.7.1
6.2.7.2
6.2.8
Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Configuration RAM’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM1: Receive Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM1: ATM Receive Reference Slot . . . . . . . . . . . . . . . . . . . . . . .
RAM1: ATM Receive Continuation Slot . . . . . . . . . . . . . . . . . . . . . .
RAM1: AAL Receive Reference Slot . . . . . . . . . . . . . . . . . . . . . . . .
RAM1: AAL Receive Continuation Slot . . . . . . . . . . . . . . . . . . . . . .
RAM1: ATM or AAL Receive Idle Slot . . . . . . . . . . . . . . . . . . . . . . .
RAM2: Transmit Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM2: ATM Transmit Reference Slot . . . . . . . . . . . . . . . . . . . . . . .
RAM2: ATM Transmit Continuation Slot . . . . . . . . . . . . . . . . . . . . .
RAM2: AAL Transmit Reference Slot . . . . . . . . . . . . . . . . . . . . . . .
RAM2: AAL Transmit Continuation Slot . . . . . . . . . . . . . . . . . . . . . .
RAM2: ATM or AAL Transmit Idle Slot . . . . . . . . . . . . . . . . . . . . . .
RAM3: Transmit Port Configuration Extended . . . . . . . . . . . . . . . . . . .
RAM3: AAL Transmit Reference Slot . . . . . . . . . . . . . . . . . . . . . . .
RAM4: Transmit Port Configuration Extended . . . . . . . . . . . . . . . . . . .
RAM4: AAL Transmit Conditioning Slot . . . . . . . . . . . . . . . . . . . . . .
External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Statistics Counter thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Insertion Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Extraction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segmentation/ATM Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segmentation Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reassembly/ATM Transmit Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
121
121
121
123
123
126
127
127
127
128
129
132
133
134
134
135
136
137
137
140
141
142
143
144
145
146
146
146
7
7.1
7.2
7.3
7.4
7.5
7.6
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Configuration Registers (pcfN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASIC Configuration Register (acfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OAM Control Register (oamc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OAM-Counter Enable Register for ATM Ports (catm) . . . . . . . . . . . . . . .
OAM-Counter Enable Register for AAL Ports (caal) . . . . . . . . . . . . . . . .
Byte-Pattern Register bp3 and bp2 (bp32) . . . . . . . . . . . . . . . . . . . . . . .
148
151
154
156
157
158
159
Data Sheet
8
2002-05-06
PXB4219 / PXB4220 / PXB4221
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
7.33
7.34
7.35
7.36
7.37
7.38
7.39
7.40
7.41
7.42
7.43
7.44
7.45
7.46
7.47
7.48
7.49
Byte-Pattern Register bp1 and bp0 (bp10) . . . . . . . . . . . . . . . . . . . . . . .
ATM Control Register (atmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Idle/Unassigned Cell Control Register (rxid) . . . . . . . . . . . . . . . . . . .
TX Idle/Unassigned Cell Control Register (txid) . . . . . . . . . . . . . . . . . . .
Loopback Control Register (lpbc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Fill Register for Partially Filled Cells (cfil) . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask Register 1 (imr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Enable Register (time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Delineation FSM Status Register (cdfs) . . . . . . . . . . . . . . . . . . . . . .
Version Register (vers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Monitor Register (ckmo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Status Register 1 (isr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Interrupt Status 1 Register (eis1) . . . . . . . . . . . . . . . . . . . . . . .
Extended Interrupt Status 2 Register (eis2) . . . . . . . . . . . . . . . . . . . . . . .
Extended Interrupt Status 3 Register (eis3) . . . . . . . . . . . . . . . . . . . . . . .
Extended Interrupt Status 4 Register (eis4) . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Status Register 2 (isr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Mode Register (opmo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FT Clock Select Register (ftcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Filter VCI Pattern 1 Register (cfvp1) . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Filter VCI Mask 1 Register (cfvm1) . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Filter VCI Pattern 2 Register (cfvp2) . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Filter VCI Mask 2 Register (cfvm2) . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Filter Payload Type Register (cfpt) . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register (cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Filter Read Pointer Register (cfrp) . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Register (thrshld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Configuration Register (utconf) . . . . . . . . . . . . . . . . . . . . . . . . .
CAS 1 Register (cas1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAS 2 Register (cas2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAS 3 Register (cas3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Register for Ports 0 and 1 (thrsp01) . . . . . . . . . . . . . . . . . . . .
Threshold Register for Ports 2 and 3 (thrsp23) . . . . . . . . . . . . . . . . . . . .
Threshold Register for Ports 4 and 5 (thrsp45) . . . . . . . . . . . . . . . . . . . .
Threshold Register for Ports 6 and 7 (thrsp67) . . . . . . . . . . . . . . . . . . . .
Extended Interrupt Status 0 Register (eis0) . . . . . . . . . . . . . . . . . . . . . . .
LCD Timer Register (lcdtimer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Source Register (irs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask (irm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Clock Recovery Circuit Configuration Register (icrcconf) . . . . . .
Configuration Register Downstream of Port N (condN) . . . . . . . . . . . . . .
Interrupt Source of Port N (irsN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask of Port N (irmN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
9
160
161
162
163
164
165
166
167
168
169
170
171
173
174
175
176
177
178
180
181
182
183
184
185
186
187
188
189
191
192
193
194
195
196
197
198
199
200
201
202
204
206
207
2002-05-06
PXB4219 / PXB4220 / PXB4221
7.50
7.51
7.52
7.53
7.54
7.55
7.56
7.57
7.58
7.59
7.60
7.61
7.62
7.63
7.64
7.65
7.66
7.67
Test Input of Port N (tsinN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register Upstream Direction of Port N (conuN) . . . . . . . .
Average Buffer Filling of Port N (avbN) . . . . . . . . . . . . . . . . . . . . . . . . . .
ACM Shift Factor of Port N (asfN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time of Initial Free Run of Port N (tiniN) . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Out of Lock Detection of Port N (tresh) . . . . . . . . . . . . . . . . . .
ICRC Parity Errors at Clock Recovery Interface (per) . . . . . . . . . . . . . . .
ICRC Synchronization Errors at Clock Recovery Interface (scri) . . . . . .
ICRC Clock Recovery Interface FIFO Overflow (crifo) . . . . . . . . . . . . . .
ICRC Version Register (icrcv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRTS Receive FIFO Underflow of Port N (sruN) . . . . . . . . . . . . . . . . . . .
SRTS Receive FIFO Overflow of Port N (sroN) . . . . . . . . . . . . . . . . . . . .
SRTS Generator Reset of Port N (srrN) . . . . . . . . . . . . . . . . . . . . . . . . .
SRTS Invalid Value Processed of Port N (sriN) . . . . . . . . . . . . . . . . . . . .
ACM Data Too Late of Port N (atlN) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Out Of Lock Register of Port N (oolN) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register of Port N (statN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Output Register of Port N (tsoutN) . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Translating AAL Statistics Counters into the ATM Forum CES Version 2 MIB
228
Jitter Characteristics of the Internal Clock Recovery Circuit . . . . . . . . . . 230
ACM Jitter Tolerance in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
ACM Jitter Tolerance in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SRTS Jitter Tolerance in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
SRTS Jitter Tolerance in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
ACM Jitter Transfer in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
ACM Jitter Transfer in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
SRTS Jitter Transfer in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SRTS Jitter Transfer in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9
9.1
9.2
9.3
9.4
9.5
9.6
9.6.1
9.6.2
9.6.2.1
9.6.2.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framer Interface in FAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framer Interface in GIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
10
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
242
242
243
244
245
246
247
247
248
248
251
2002-05-06
PXB4219 / PXB4220 / PXB4221
9.6.2.3
9.6.2.4
9.6.3
9.6.4
9.6.5
9.6.6
9.6.6.1
9.6.6.2
9.6.7
9.6.8
Framer Interface in SYM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framer Interface in EC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
254
256
256
260
261
262
262
264
265
266
10
10.1
10.2
10.3
Testmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
268
268
268
268
11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
12
12.1
12.2
12.3
12.4
12.4.1
12.4.2
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATM Adaptation Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Residual Time Stamp SRTS . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Clock Method ACM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Associated Signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Contacts for SRTS Patent Fee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
15
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Data Sheet
11
274
274
278
280
281
281
282
2002-05-06
PXB4219 / PXB4220 / PXB4221
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Data Sheet
Page
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical IWE8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Line Card for 8 T1/E1 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Echo Canceller Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Cell delineation state diagram (Figure 5/I.432.1) . . . . . . . . . . . . . . . . . 50
Maintenance state transition diagram for cell delineation events (Figure 2/
I.432.3) 50
HEC: Receiver mode of Operation (Figure 3/ITU I.432.1) . . . . . . . . . . 51
HEC Detection According to ATM Forum . . . . . . . . . . . . . . . . . . . . . . 52
Pre-assigned cell header values at the UNI for use by the physical layer
(excluding the HEC field) (Table 1/I.361) 53
Pre-defined header field values [11] . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SAR-PDU of AAL Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Synchronization of SRTS Generation with the Start of Segmentation . 60
Reassembly Buffer Initialization: No CDV . . . . . . . . . . . . . . . . . . . . . . 67
Reassembly Buffer Initialization: positive CDV at Start Up . . . . . . . . . 68
Reassembly Buffer Initialization: Negative CDV at Start Up . . . . . . . . 69
Reassembly Buffer Initialization for structured CES: positive CDV at Start
Up 70
Block Diagram of the ICRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Influence of Damping on Lock in Time. . . . . . . . . . . . . . . . . . . . . . . . . 79
Connection of IWE8 to QuadFALC . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Framer Interface in FAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Framer Interface in GIM T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Framer Interface in GIM E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Framer Interface in SYM2 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Framer Interface in SYM8 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Framer Interface in EC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UTOPIA Receive and Transmit Interfaces in Slave Mode . . . . . . . . . 107
Utopia Sideband Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
IMA Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Connection of IWE8 to an Intel Type Microprocessor . . . . . . . . . . . . 115
Connection of IWE8 to an Motorola Type Microprocessor . . . . . . . . 116
External RAM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
RAM Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Structure of the IWE8 external RAM . . . . . . . . . . . . . . . . . . . . . . . . . 137
Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
ACM Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . . . 230
12
2002-05-06
PXB4219 / PXB4220 / PXB4221
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
ACM Jitter Tolerance in E1 Mode with Jitter Attenuator . . . . . . . . . .
ACM Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . . . . .
ACM Jitter Tolerance in T1 Mode with Jitter Attenuator . . . . . . . . . .
SRTS Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . .
SRTS Jitter Tolerance in E1 Mode with Jitter Attenuator. . . . . . . . . .
SRTS Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . . . .
SRTS Jitter Tolerance in T1 Mode with Jitter Attenuator . . . . . . . . . .
ACM Jitter Transfer in E1 Mode without Jitter Attenuator . . . . . . . . .
ACM Jitter Transfer in E1 Mode with Jitter Attenuator . . . . . . . . . . . .
ACM Jitter Transfer in T1 Mode without Jitter Attenuator . . . . . . . . .
ACM Jitter Transfer in T1 Mode with Jitter Attenuator . . . . . . . . . . . .
SRTS Jitter Transfer in E1 Mode without Jitter Attenuator . . . . . . . .
SRTS Jitter Transfer in E1 Mode with Jitter Attenuator . . . . . . . . . . .
SRTS Jitter Transfer in T1 Mode without Jitter Attenuator . . . . . . . .
SRTS Jitter Transfer in T1 Mode with Jitter Attenuator . . . . . . . . . . .
Input/Output Waveforms for AC Measurements . . . . . . . . . . . . . . . .
Clock and Reset Interface Timing Diagram . . . . . . . . . . . . . . . . . . . .
Framer Receive Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . .
Framer Transmit Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . .
Framer Receive Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . . .
Framer Transmit Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . .
Framer Interface Timing for SYM 2.048 MHz . . . . . . . . . . . . . . . . . .
Framer Interface Timing in SYM 8.192 MHz . . . . . . . . . . . . . . . . . . .
Framer Interface Timing in EC Mode . . . . . . . . . . . . . . . . . . . . . . . . .
Setup and hold time definition (single- and multi PHY) . . . . . . . . . . .
Tri-state timing (multi-PHY, multiple devices only). . . . . . . . . . . . . . .
Timing of the IMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery Interface Timing Diagram . . . . . . . . . . . . . . . . . . . .
Intel Mode Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . .
Intel Mode Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . .
Motorola Mode Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . .
Package Outline: P-BGA-256 (Plastic Metric Quad Flat Package)
Structure of the AAL1 SAR-PDU . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Informative and Example Algorithm State Machine (Fig. III.2/I.363.1)
The Concept of Synchronous Residual Time Stamp (SRTS) (Fig. 5/
I.363.1) 278
Figure 77
Generation of Residual Time Stamp (RTS) (Fig.6/ I.363.1) . . . . . . . .
Figure 78
Example Multiframe Structure for 3x64 Kbit/s E1 with CAS. . . . . . . .
Data Sheet
13
231
232
232
233
234
235
235
236
237
238
238
239
240
241
241
247
247
248
250
251
252
254
255
256
257
257
260
261
262
263
264
265
266
273
274
276
279
282
2002-05-06
PXB4219 / PXB4220 / PXB4221
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Page
Generic Framer Interface (73 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UTOPIA Interface (36 pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
IMA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Recovery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Not Connected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Functions of IWE8 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ATM Cell Discarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Activation sequence for ATM transmit ports . . . . . . . . . . . . . . . . . . . . 48
Activation sequence for ATM receive ports . . . . . . . . . . . . . . . . . . . . 54
Definition of the CAS Signalling Conditioning Nibbles. . . . . . . . . . . . . 57
Relationship between Cell Filling and Segmentation Buffer Subblock Size
58
Table 17
Table 18
Table 19
Table 20
Cell Filling level values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Activation sequence for AAL segmentation channels . . . . . . . . . . . . . 59
Activation sequence for AAL reassembly channels . . . . . . . . . . . . . . 66
Relationship between Cell Filling and Reassembly Buffer Subblock Size
66
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 36
Table 38
Table 39
Table 40
Table 41
Data Sheet
Coding of Slot Type in internal configuration RAMs . . . . . . . . . . . . . . 87
RAM slot positions for ITU-T G.804 compliant ATM mapping . . . . . . 87
AAL Idle slot positions for structured CES in AAL mode . . . . . . . . . . 89
AAL Idle slot positions for structured CES with CAS in AAL mode. . . 91
Time slot Mapping in T1 Translation Mode 0 . . . . . . . . . . . . . . . . . . . . 96
F-Channel Format in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Clock Recovery Interface frame format . . . . . . . . . . . . . . . . . . . . . . 112
Configuration of the Microprocessor Interface Mode via PMT and TBUS .
115
Master Clock Frequency Depending on Mode. . . . . . . . . . . . . . . . . . 119
Statistics Counters for ATM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Statistics Counters for AAL Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Clock and Reset Interface AC Timing Characteristics . . . . . . . . . . . 247
Framer Transmit Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . 250
Framer Transmit Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . . 252
Framer Interface AC Timing Characteristics in SYM2 Mode . . . . . . 254
Framer Interface Timing in SYM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Framer Interface Timing in EC Mode . . . . . . . . . . . . . . . . . . . . . . . . 256
14
2002-05-06
PXB4219 / PXB4220 / PXB4221
Table 42
Table 43
Table 44
Table 45
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Data Sheet
Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY) .
258
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY). .
258
Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) . .
259
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) . . .
259
Clock Recovery Interface AC Timing Characteristics . . . . . . . . . . . . 261
Intel Mode Write Cycle AC Characteristics . . . . . . . . . . . . . . . . . . . . 262
Intel Mode Read Cycle AC Timing Characteristics . . . . . . . . . . . . . . 263
Motorola Mode AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . 264
RAM Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . 266
Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . 267
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Bit allocation of channel associated 64 kbit/s time slot 16 for channel associated signalling 281
Allocation of Channel Associated Signalling Bits to 24 Frame Multiframe.
283
15
2002-05-06
PXB4219 / PXB4220 / PXB4221
Your Comments
We welcome your comments on this document. We are continuously trying improving
our documentation. Please send your remarks and suggestions by e-mail to
[email protected]
Please provide in the subject of your e-mail:
device name (IWE8), device number (PXB4219 / PXB4220 / PXB4221), device version
(Version 3.3),
and in the body of your e-mail:
document type (Data Sheet), issue date (2002-05-06) and document revision number
(DS3).
Data Sheet
16
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
1
Overview
The Interworking Element for 8 E1/T1 Lines PXB4219 / PXB4220 / PXB4221 (IWE8) is
a member of Infineon’s ATM chip set. Together with framing and line interface
components (e.g. Infineon’s QuadFALC PEB 22554) the IWE8 serves as gateway
between Asynchronous Transfer Mode (ATM) networks and timeslot based PDH
networks.
Each of the 8 E1 or T1 input and output ports can be configured independently to operate
in one of two basic modes:
ATM Mode
ATM mode ports operate as an ATM User Network Interface (UNI) at 2.048 Mbit/s (E1)
or 1.544 Mbit/s (T1).
The device supports mapping of ATM cells in T1/E1 frames according to ITU-T G.804,
“ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)” [26] and ATM Forum,
“ATM on Fractional E1/T1” [9].
It implements all Transmission Convergence (TC) sublayer functions of the Physical
Layer (PHY) defined in ITU-T I.432, “B-ISDN User-network Interface - Physical layer
Specification” [32]
AAL Mode
AAL mode ports operate as an ATM Circuit Emulation Service Interworking Function
(CES-IWF) between Constant Bit Rate (CBR) equipment and an ATM network as
described by the ATM Forum, “Circuit Emulation Services Version 2.0" [10]. (only PXB
4220/4221)
The CBR circuits are converted into ATM constant bit-rate virtual channels using the
ATM Adaptation Layer type 1 (AAL1) as defined in I.363.1, “B-ISDN ATM Adaptation
Layer Specification, Types 1 and 2" [31] or without any ATM Adaptation Layer overhead,
which will be referred as AAL type 0 throughout the rest of this document.
The IWE8 provides the segmentation and reassembly function.
Both the “Unstructured DS1/E1 Service” and the “Structured DS1/E1 N x 64 kbit/s Basic
Service” as described in the “Circuit Emulation Services Version 2.0" by the ATM Forum
in [10] are supported. For simplicity reasons the shorthand notation “Unstructured CES”
will be used to identify the “Unstructured DS1/E1 Service” while the “Structured DS1/E1
N x 64 kbit/s Service” will be referred to as “Structured CES” throughout the rest of this
document.
Data Sheet
17
2002-05-06
Interworking Element for 8 E1/T1 Lines
IWE8
PXB4219 /
PXB4220 /
PXB4221
Version 3.3
1.1
Features
• Full duplex ATM Packetizer/Depacketizer for 8 E1/T1
highways
• Configurable to T1 or E1 mode via external pin
• 8 T1/E1 ports configurable independently to ATM or
AAL Mode
• ATM Mode (PXB 4219/4220/4221):
– ATM cell mapping into PDH according to ITUT G.804 [26]
– B-ISDN User-Network interface - Physical Layer
according to ITU-T I.432 [32]
– B-ISDN User-Network interface - Physical Layer oparation at 1544 KBit/s and 2048
KBit/s according to ITU-T I.432.3 [34]
• AAL Mode (PXB 4220/4221):
– AAL1 according to ITU-T I.363.1 [31] or transparent without any adaptation layer
overhead (AAL0)
– T1/E1 unstructured service according to ATM Forum af-vtoa-0078.000 [10] section
3
– Structured T1/E1 N x 64 Kbit/s service according to [10] section 2 with M channels
of N x 64 Kbit/s (M,N = 1to 24 for T1) (M,N = 1to 32 for E1)
– Channel Associated Signalling (CAS) support according to [10]
– Echo Canceller Mode
– Partially filled cells with programmable filling thresholds
– Selectable Sequence Count Algorithm:
– Robust/Fast according to ITU-T I.363.1 [30]
– According to ETSI (prl-ETS 300353 annex D) [17]
– Fast: Saves 6 ms during reassembly for 1 x 64 Kbit/s connection
– AAL0 option: 48 Bytes user payload per ATM Cell, without AAL overhead
– Reassembly buffer can compensate up to +/- 4 ms Cell Delay Variation (CDV)
– Statistics counters per channel for lost/misinserted/errored cells etc.
Type
Package
PXB4219 / PXB4220 / PXB4221
P-BGA-256
Data Sheet
18
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
•
•
•
•
•
•
•
•
•
•
•
– Internal clock recovery circuit using Synchronous Residual Time Stamp (SRTS) or
Adaptive Clock Method (ACM) for unstructured CES ports. For SRTS a patent fee
needs to be paid. Optionally, it’s possible to order the PXB 4221 device, which
comes without SRTS clock recovery.
– Trunk freezing and conditioning according to Bellcore TR-NWT-000170 [14]
IMA interface:
– Programmable threshold between read and write pointer of Mapping Buffer
– Output Signal for buffer threshold crossing
– Output Signal for discarded cell
– Output pins for port number indication
8 generic framer interfaces with integrated transmit clock selector supporting
– Synchronous Mode (SYM)
– Generic Interface Mode (GIM)
– FALC Mode (FAM): Glue-less interface for Infineon’s Framer and Line Interface
Components (FALC)
– Echo Canceller Mode (EC): ATM cells are duplicated internally and transmitted via
two framer ports
UTOPIA industry standard interface:
– Level 2 in slave mode; 8 data, 5 address lines
– Level 1 in master/slave mode
– UTOPIA clock up to 38.88 MHz
16-bit generic microprocessor interface for control and configuration of the chip runs
either in Intel 386EX or Motorola compatible mode
External synchronous Flow-Through SSRAM 1 x 64K x 33 bit or 1 x 64K x 32 bit
required
Build-in data path loops for test
Cell insertion/extraxtion via microprocessor interface
3.3 Volt power supply with 5 Volt tolerant inputs
Typical power dissipation 1 Watt
P-BGA 256 package
Temperature range from -40° to +85°C
Data Sheet
19
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
Logic Symbol
MPDATA[0-15]
RXCLK
RXADR[0-4]
MPADR[0-17]
Microprocessor
Interface
TDO
TDI
TMS
TCK
TRST
OUTTR
UTTR
Test Interface
SDI
SDOD
SSP
SDOR
SCLK
CR Interface
ITST[0-3]
1.2
RXDAT[0-7]
MPCS
RXPTY
MPWR
RXSOC
MPRD
RXCLAV
MPRDY
RXENB
MPIR1,2
TXCLK
PXB 4220
TXADR[0-4]
RMADR[0-15]
TXDAT[0-7]
RMDAT[0-32]
TXPTY
RMCS
TXSOC
RMOE
TXCLAV
RMWR
Framer Interface
Figure 1
Data Sheet
PN0
UNCHEC
ATBTC
FTMFS[0-7]
FTFRS[0-7]
FTDAT[0-7]
FTCKO[0-7]
FRMFB[0-7]
FRFRS[0-7]
FRDAT[0-7]
FRCLK[0-7]
FRLOS[0-7]
RMADC
PN2
TXENB
RMCLK
PN1
RAM
Interface
UTOPIA
Interface
(Level 2)
IMA Interface
Logic Symbol
20
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
1.3
Typical Applications
Figure 2 illustrates three typical application areas which utilize the IWE8 chip in Line
Interface Cards (LICs) or Network Interface Controllers (NICs).
Application 1 utilizes the IWE8 as an internetworking device for communication between
a narrowband Time-Slot based network and an ATM network.
Application 2 utilizes the IWE8 chip to enable the use of an existing T1/E1 access line
for connection to an ATM network.
In application 3, the IWE8 chip enables terminals using a Leased Line or Time-Slot
based service to convert from T1/E1 network connection to ATM network connection
without noticeable changes to the subscriber.
Application 1
PBX
0
DS1/E1 Links
IWETM
PBX
8
7
DS1/E1 Links
Structured Circuit Emulation
Service for DS1/E1
(Nx64kbit/s with/without
partially filled cells) over ATM
ATM Links
Application 2
Multiservice
Switch
0
IWETM 8
7
ATM
Network
NNI/UNI 2.048 Mbps,
NNI/UNI 1.544 Mbps
(I.432.2, G.804)
ATM Links
Application 3
PBX
0
DS1/E1 Links
IWETM 8
PBX
Figure 2
7
DS1/E1 Links
Unstructured Circuit Emulation
Service for DS1/E1 (with/
without partially filled cells) for
Leased Lines over ATM
Typical IWE8 Applications
The PXB 4220 IWE8 chip is designed to handle up to eight T1/E1 ports. It transfers data
between the Pulse Code Modulation (PCM)-highway and an UTOPIA ATM Interface.
Data Sheet
21
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
1.3.1
Line Card
Figure 3 shows an example Line Interface Card (LIC) utilizing the IWE8 in a switch
environment. Two Infineon Quad Framer and Line Interface Component (QuadFALC,
PEB 22554) chips are connected at the PCM ports. An ATM Layer circuit is connected
at the UTOPIA Interface port and could be implemented using Infineon PXB 4350 ATM
Layer Processor (ALP) chip.
T1/E1
Lines
Serial
Interface
UTOPIA
Interface
Switching
Network
FT SSRAM
64 K x 36 Bit
Mag.
QuadFALC
PEB 22554
ATM Layer
Circuit
e.g. ALP
PXB 4350
IWE8
Mag.
Figure 3
Clock Supply
Clock = 25 MHz
QuadFALC
PEB 22554
Line Card for 8 T1/E1 Channels
External synchronous SRAM is always required for proper IWE8 operation. The IWE8
requires only one main operating clock of 12 times the datarate of one port. An
emergency clock of 32.768 MHz is optional. The Framer and Utopia interface clocks can
be completely asynchronous with respect to the main clock. A microprocessor controls
and operates the IWE8 via a generic 16-bit interface.
1.3.2
Echo Canceller
In communication links reflections resulting in an electrical echo are due to hybrid splits
or imperfect terminations in subscriber loops. Acoustical echoes may occur due to poor
isolation of microphone and speaker of some telephone systems. These electrical and
acoustical echoes disturb the quality of the transmission. To ensure high quality, pure
data transmission the ITU-T suggests in the recommendation G.131 [22] the use of echo
cancellers. Echo cancellation is extremely desirable for data links with total round trip
transmission times of more than 50 ms.
Data Sheet
22
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
IWU
PDH
network
FALC LH
PEB2255
SIDEC
PEB20954
Near End
Figure 4
IWE8
PXB4220
ATM
network
Far End
Echo Canceller Application
The echo cancelling function itself is performed in STM. In the application above the
IWE8 is used to translate voice ATM channels into STM channels and vice versa.
Infineon’s Smart Integrated Digital Echo Canceller (SIDEC, PEB 20954) is used for
cancellation of the echo that is generated by reflection on the near end side and heard
by the far end speaker. The SIDEC can cancel end echo paths (SDH or PDH network
on near end side) up to 128 ms. For details see [21]
Data Sheet
23
2002-05-06
PXB4219 / PXB4220 / PXB4221
Overview
1.4
Differences Between PXB4220 And PXB4219
The IWE8 type PXB4219 does only support the ATM mode used for ITU-T G.804
compliant ATM cell mapping into the plesiochronous digital hierarchy (PDH) at line rates
of 1544 kbit/s and 2048 kbit/s. The AAL mode is not available.
1.5
Differences Between PXB4220 And PXB4221
The IWE8 type PXB4220 uses an internal clock recovery mechanism (SRTS) which is
patented by Bellcore.
Related Patents are:
• Bellcore patent No. 5,260,978
(Synchronous Residual Time Stamp for Timing Recovery in a broadband network)
• Bellcore patent No. 4,839,306
(Method and apparatus for multiplexing circuit and packet traffic)
Infineon Technologies is not allowed to collect SRTS license fees on the IWE8 on behalf
of Bellcore. Contacts for license issues are given in Chapter 13.
Every IWE8 customer must get in contact with Bellcore legal department by himself to
clarify whether his application needs to license the SRTS functionality.
For customers who do not want to use the built-in SRTS mechanism, Infineon provides
a special version of the IWE8. The name of this device is PXB4221 and covers the same
functionality (pin and register compatible) like the PXB4220. SRTS is physically and
permanently disabled, so that no patent fees have to be paid.
Data Sheet
24
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2
Pin Descriptions
2.1
Pin Diagram
A
B
C
D
E
F
G
H
J
L
M
N
P
R
S
T
U
V
W
Y
P-BGA-256
1
GND
FT CKO_4
T CK
T MS
MPWR_N
MPDA T _2
MPDA T _5
MPDA T _8
MPDA T _12 MPDA T _15 RFCLK
PN_0
MPA DR_1
MPA DR_4
MPA DR_6
MPADR_9
2
FTMFS_7
FT DA T _7
FT CKO_5
T DO
MPCS_N
MPDA T _1
MPDA T _4
MPDA T _7
MPDA T _11 MPDA T _13 CLOCK
MPIR1_N
MPA DR_2
MPA DR_5
MPA DR_8
MPADR_12 MPA DR_15 CLK52
3
FRMFB_7
FRFRSN_7
FT FRSN_7
N. C.
T RST _N
MPRD_N
MPDA T _3
MPDA T _6
MPDA T _10 MPDA T _14 RE SE T _N
MPIR2_N
MPA DR_3
MPA DR_7
MPA DR_11 MPADR_14 LICE C
4
FRLOS_7
FRDA T _7
FT CKO_7
GND
T DI
VDD
MPDA T _0
GND
MPDA T _9
MPA DR_0
GND
MPA DR_10 VDD
5
FRFRSN_6
FT FRSN_6
FRCLK_7
FT CKO_6
6
FRCLK_6
FRMFB_6
FT MFS_6
VDD
7
FTFRSN_5
FRLOS_6
FRDA T _6
FT DA T _6
8
FRFRSN_5
FT DA T _5
FT MFS_5
GND
9
FRLOS_5
FRCLK_5
FRDA T _5
FRMFB_5
10
FRFRSN_4
FT DA T _4
FT MFS_4
11
T SCSH
FRDA T _4
12
FRCLK_4
13
MPA DR_13 MPA DR_16 E 1DS1
T XA DR_1
T XA DR_0
T XA DR_3
TSCE N
T XA DR_2
RXA DR_2
RXA DR_0
T XA DR_4
RXA DR_3
RXA DR_1
RXA DR_4
PN_1
PN_2
VDD
TXCLA
T XSOC
T XDA T _0
T XE NB_N
TXDA T _1
T XDA T _2
T XDA T _3
GND
TXDA T _4
T XDA T _5
T XDA T _6
T XDA T _7
TXPRT
UT T R_N
T XCLK
FT FRSN_4
VDD
RXCLA
RXSOC
A T BT C
FRMFB_4
VDD
RXDA T _3
RXDA T _2
RXDA T _1
RXDA T _0
FRLOS_4
FT FRSN_3
FT MFS_3
RXDA T _7
RXDA T _6
RXDA T _5
RXDA T _4
FTDA T _3
FRFRSN_3
FT CKO_3
GND
GND
RXCLK
RXE NB_N RXPRT
14
FRMFB_3
FRDA T _3
FRCLK_3
FT MFS_2
RMDA T _3
RMDA T _0
RMCLK
OUT T R_N
15
FRLOS_3
FT FRSN_2
FT DA T _2
VDD
VDD
RMDA T _4
RMDA T _1
PMT
16
FRFRSN_2
FT CKO_2
FRMFB_2
FRLOS_2
RMDA T _9
RMDA T _7
RMDA T _5
RMDA T _2
17
FRDA T _2
FT MFS_1
FT FRSN_1
GND
FT FRSN_0
VDD
FRCLK_0
RMA DR_7
RMA DR_3
VDD
GND
RMDA T _10 RMDA T _8
RMDA T _6
18
FRCLK_2
FT DA T _1
FRMFB_1
FRLOS_1
FRFRSN_0
FRDA T _0
RMA DR_14 RMA DR_10 RMA DR_6
RMA DR_2
RMADC_N RMDA T _32 RMDA T _28 RMDA T _25 RMDA T _21 RMDA T _19 RMDA T _16 TBUS
19
FRFRSN_1
N. C.
FRCLK_1
FT DA T _0
FRMFB_0
RMA DR_15 RMA DR_12 RMA DR_9
RMA DR_5
RMA DR_1
RMOE _N
RMWR_N
RMDA T _29 RMDA T _26 RMDA T _23 RMDA T _20 RMDA T _15 RMDA T _14 RMDA T _13 RMDA T _
20
FTCKO_1
FRDA T _1
FT MFS_0
FT CKO_0
FRLOS_0
RMA DR_13 RMA DR_11 RMA DR_8
RMA DR_4
RMA DR_0
UNCHE C
RMCS_N
RMDA T _30 RMDA T _27 RMDA T _24 SCLK
Figure 5
2.2
VDD
MPRDY
MPADR_17 GND
PBGA 256
Bottom View
GND
RMDA T _31 GND
RMDA T _22 VDD
SSP
RMDA T _11 SDI
RMDA T _18 RMDA T _17 SDOR
SDOD
Pin Configuration
Pin Definitions and Functions
Output Pull Up and Pull Down Type Definitions
PUx
Pull Up of strength x (x = A, B) is implemented. The
corresponding current is specified in Chapter 9.4
PDx
Pull Down of strength x (x = A) is implemented. The
corresponding current is specified in Chapter 9.4
Tri
Tri-stated when inactive
Data Sheet
25
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2.2.1
Table 1
Generic Framer Interface
Generic Framer Interface (73 pins)
Pin No.
Symbol
Input (I)
Function
Output (O)
G17, C19,
A18, C14,
A12, B9,
A6, C5
FRCLK[7:0]
I
Framer Receive Clock
Receive clock for the framer interface
F18, B20,
A17, B14,
B11, C9,
C7, B4
FRDAT[7:0]
I
PDA
Framer Receive Data
Receive data input of the framer interface
E19, C18,
C16, A14,
C11, D9,
B6, A3
FRMFB[7:0]
I
PUA
Framer Receive Multiframe Begin
Indication that a new multi-/superframe is
available on the receive side of the framer
interface
E18, A19,
A16, B13,
A10, A8,
A5, B3
FRFRS[7:0]
O
PUA
Framer Receive Frame Synchronization
Pulse
Indication that a new frame is available on
the receive side of the framer interface
E20, D18,
D16, A15,
B12, A9,
B7, A4
FRLOS[7:0]
I
PDA
Framer Receive Loss of Signalling
Indication that CAS bits are invalid, IWE8
will start CAS freezing
D20, A20, FTCKO[7:0]
B16, C13,
B1, C2, D5,
C4
O/I
PDA
Framer Transmit Clock
Transmit clock for the framer interface.
• Recovered clock output from the ICRC
• Framer receive clock output from pin
FRCLKN
• Output of the clock derived from RFCLK
• Input for an external clock recovery
device
D19, B18,
C15, A13,
B10, B8,
D7, B2
O
PUA
Framer Transmit Data
Transmit data output of the framer interface
Data Sheet
FTDAT[7:0]
26
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 1
Generic Framer Interface (73 pins) (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
C20, B17,
D14, D12,
C10, C8,
C6, A2
FTMFS[7:0]
O
PUA
Framer Transmit Multiframe
Synchronization
Indication that a new multi-/superframe is
available on the transmit side of the framer
interface
E17, C17,
B15, C12,
D10, A7,
B5, C3
FTFRS[7:0]
O
PUA
Framer Transmit Frame Synchronization
Pulse
Indication that a new frame is available on
the transmit side of the framer interface
L1
RFCLK
I
Reference Clock
SYM and EC mode: Central framer interface
clock for all framer ports
FAM and GIM: Optional SRTS/ACM
reference or emergency clock for the framer
receive interface in case of clock failure
2.2.2
Table 2
UTOPIA Interface
UTOPIA Interface (36 pins)
Pin No.
Symbol
Input (I)
Function
Output (O)
Y11, W11,
V11, U11,
Y12, W12,
V12, U12
RXDAT[7:0]
O
PUA
UTOPIA Receive Data Bus
Byte-wide data driven from PHY to ATM
layer. RxData[7] is the MSB.
Y13
RXPTY
O
PUA
UTOPIA Receive Odd Parity Bit
Odd parity for RXDAT[0:7] driven by the
PHY layer.
W10
RXSOC
O
PDA
UTOPIA Receive Start-of-Cell
Active high signal asserted by the PHY layer
when RXDAT[0:7] contains the first valid
byte of a cell.
Data Sheet
27
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 2
UTOPIA Interface (36 pins) (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
V10
RXCLAV
Slave: O
Master: I
PDA
UTOPIA Receive Cell Available
Slave: RXCLAV is an active high signal
asserted by the PHY layer to indicate that it
has data available for transfer to the ATM
layer.
Master: RXCLAV is an active high signal
asserted by the ATM layer to indicate that it
has data available for transfer to the PHY
layer.
V13
RXCLK
I
UTOPIA Receive Clock
Transfer/synchronization clock from the
ATM layer to the PHY layer for
synchronizing transfers on RXDAT[0:7].
W13
RXENB
Slave: I
Master: O
PUA
UTOPIA Receive Enable
Slave: Active low signal asserted by the
ATM layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
Master: Active low signal asserted by the
PHY layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
V4, U5, Y3, RXADR[4:0]
Y4, V5
I
PUA
UTOPIA Receive Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to select the appropriate
MPHY device. RXADR[4] is the MSB.
Y6, V7,
W7, Y7,
V8, W8,
Y8, U9
TXDAT[7:0]
I
PUA
UTOPIA Transmit Data Bus
Byte-wide true data driven from ATM to
PHY layer. TXDAT[7] is the MSB.
V9
TXPTY
I
PUA
UTOPIA Transmit Odd Parity Bit
TXPTY is the odd parity bit over TXDAT[0:7]
driven by the ATM layer.
W6
TXSOC
I
PDA
UTOPIA Transmit Start-of-Cell
Active high signal asserted by the ATM
layer when TXDAT[0:7] contains the first
valid byte of the cell.
Data Sheet
28
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 2
UTOPIA Interface (36 pins) (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
V6
TXCLAV
Slave: O
Master: I
PDA
UTOPIA Transmit Cell Available
Slave: TXCLAV is an active high signal
asserted by the PHY layer to indicate it can
accept data.
Master: TXCLAV is an active high signal
asserted by the ATM layer to indicate it can
accept data.
Y9
TXCLK
I
UTOPIA Transmit Clock
Data transfer/synchronization clock
provided by the ATM layer to the PHY layer
for synchronizing transfers on TXDAT[0:7].
U7
TXENB
Slave: I
Master: O
PUA
UTOPIA Transmit Enable
Slave: Active low signal asserted by the
W2, Y1,
W3, Y2,
W4
Data Sheet
TXADR[4:0]
I
PUA
ATM layer during cycles when
TXDAT[0:7] contains valid cell data.
Master: Active low signal asserted by
the PHY layer during cycles when
TXDAT[0:7] contains valid cell data.
UTOPIA Transmit Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to poll and select the
appropriate MPHY device. TXADR4 is the
MSB.
29
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2.2.3
Table 3
IMA Interface
IMA Interface
Pin No.
Symbol
Input (I)
Output (O)
Function
Y10
ATBTC
O
Tri
ATM Transmit Buffer Threshold
Crossing
Indicates if the difference between the write
and read pointer of the mapping buffer
became smaller than a SW selectable
threshold
L20
UNCHEC
O
Tri
Uncorrectable HEC Error
Indicates if a cell has been discarded due to
an uncorrectable HEC error
M1, W5,
Y5
PN[2:0]
O
Tri
Port Number
Indicates the port number where the cell
causing ATBT or UNCHEC being asserted
came from
2.2.4
Table 4
Clock Recovery Interface
Clock Recovery Interface
Pin No.
Symbol
Input (I)
Function
Output (O)
Y18
SDI
I
Serial Data Input
Clock recovery frame input.
Y20
SDOD
O
Tri
Serial Data Output Data
Clock recovery frame output
W20
SDOR
O
Tri
Serial Data Output Reset
Clock recovery reset frame output
T17
SSP
O
Tri
Serial Synchronization Pulse
Frame synchronization pulse output
T20
SCLK
O
Tri
Serial Clock
Clock output of the clock recovery interface.
Runs at the same frequency than the
CLOCK input
Data Sheet
30
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2.2.5
Table 5
Pin No.
Microprocessor Interface
Microprocessor Interface
Symbol
Input (I)
Function
Output (O)
G4, F2, F1, MPDAT[15:0]
G3, G2,
G1, H3, H2,
H1, J4, J3,
J2, J1, K2,
K3, K1
I/O
PUA
Microprocessor Data Bus
This bidirectional three-state bus provides
the general-purpose data path between the
IWE8 and an external master. The bus uses
little endian word order. MPDAT15 is the
MSB.
M4, N1,
MPADR[17:0]
N2, N3, P1,
P2, R1, P3,
R2, T1, P4,
R3, T2, U1,
T3, U2, V1,
T4
I
Microprocessor Address Bus
Provides the address of the current bus
cycle. Addresses are 16-bit aligned.
MPADR17 is the MSB of the bus
E2
MPCS
I
Microprocessor Chip Select
This signal is driven by the bus master to
indicate a read or write access.
E1
MPWR/
MPRW
I
Microprocessor Write Enable (Intel Bus
Mode)
This signal is driven by the bus master to
indicate a write data transfer
Read/Write Enable (Motorola Bus Mode)
This three-state signal is driven by the bus
master to indicate the direction of the bus’s
data transfer
F3
MPRD/
MPTS
I
Microprocessor Read Enable (Intel Bus
Mode)
This signal is driven by the bus master to
indicate a read data transfer
Microprocessor Transfer Start (Motorola
Bus Mode)
This signal is asserted by the bus master to
indicate the start of a bus cycle that
transfers data to or from the device
Data Sheet
31
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 5
Microprocessor Interface (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
L4
MPRDY
MPTA
O
Tri
Microprocessor Ready (Intel Bus Mode)
This three-state output indicates that the
device has accepted date from the master
(write) or has driven the data bus with valid
data (read)
Microprocessor Transfer Acknowledge
(Motorola Bus Mode)
This three-state output indicates that the
device has accepted date from the master
(write) or has driven the data bus with valid
data (read)
M2
MPIR1
O
PUB
Microprocessor Interrupt Request 1
Main interrupt pin indicating a special event
in the IWE8.
M3
MPIR2
O
PUB
Microprocessor Interrupt Request 2
This signal is generated by timer set 2 to
indicate that a counter expired
Data Sheet
32
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2.2.6
Table 6
External RAM Interface
External RAM Interface
Pin No.
Symbol
Input (I)
Function
Output (O)
K20, K19,
K18, K17,
J20, J19,
J18, J17,
H20, H19,
H18, G20,
G19, F20,
G18, F19
RMADR[15:0]
O
Tri
RAM Address Bus
This bus provides the address of the current
bus cycle. RMADR15 is the MSB.
V14, W15,
Y16, U14,
V15, W16,
Y17, V16,
W17, U16,
V17, W18,
Y19, W19,
V19, U19,
U18, V20,
U20, T18,
T19, R18,
P17, R19,
R20, P18,
P19, P20,
N18, N19,
N20, M17,
M18
RMDAT[32:0]
I/O
PUB
RAM Data Bus
This bidirectional three-state bus provides
the data path between the IWE8 and the
external memory. RMDAT32 is parity bit,
RMDAT31 is the MSB.
M20
RMCS
O
Tri
RAM Chip Select
This signal enables read or write accesses
to the external memory
L19
RMOE
O
Tri
RAM Output Enable
This signal enables the outputs of the
external memory
M19
RMWR
O
Tri
RAM Write Enable
This output is asserted when a write access
to the external memory
Data Sheet
33
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 6
External RAM Interface (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
L18
RMADC
O
Tri
RAM Address Control
This output is asserted to indicate a valid
address on RMADR[15:0]
W14
RMCLK
O
Tri
RAM Clock
Clock output for the external RAM. It runs at
the same frequency as CLOCK input
2.2.7
Test Interface
Table 7
Test Interface
Pin No.
Symbol
Input (I)
Output (O)
Function
D2
TDO
O
Tri
Boundary Scan Test Data Output
E4
TDI
I
PUA
Boundary Scan Test Data Input
C1
TCK
I
PUA
Boundary Scan Test Clock
D1
TMS
I
PUA
Boundary Scan Test Mode Select
0 = normal operation
1 = Enable boundary scan test mode
E3
TRST
I
PDA
Boundary Scan Test Reset
V3
TSCEN
A11
TSCSH
I
PDA
Internal Test Pins
TSCEN and TSCSH must be low for proper
operation
Y15
PMT
PDA
V18
TBUS
Internal Test Pins
00 = Intel mode
01 = prohibited
10 = prohibited
11 = Motorola Mode
Data Sheet
34
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 7
Test Interface (cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Function
W9
UTTR
I
PUA
Utopia TRI-STATE
0 = tristate all Utopia outputs
1 = normal operation
Y14
OUTTR
I
Output TRI-STATE
0 = tristate all outputs and disable all pull-up
and pull-down resistors
1 = normal operation
2.2.8
Miscellaneous
Table 8
Miscellaneous
Pin No.
Symbol
Input (I)
Output (O)
Function
W1 1)
E1/T1
I
PUA
E1 or T1 Mode Select
0 = T1 mode
1 = E1 mode
U3 1)
EC
I
PUA
Echo Canceller Mode Select
0 = echo canceller mode
1 = standard mode
L2
CLOCK
I
Master Clock
Used to clock the core of the device
L3 2)
RESET
I
PDA
Master Hardware Reset
Asynchronous reset of all flip-flops
V2
CLK52
I
51.84 MHz SRTS Reference Clock
external reference clock for SRTS. If SRTS
mode is not used, it can be connected to VSS
Data Sheet
35
2002-05-06
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
2.2.9
Table 9
Power Supply
Power Supply
Pin No.
Symbol
D6, D11,
D15, F4,
F17, K4,
L17, R4,
R17, U6,
U10, U15
VDD
Input (I)
Function
Output (O)
Power Supply Voltage
A1, D4, D8, GND
D13, D17,
H4, H17,
N4, N17,
U4, U8,
U13,U17
2.2.10
Table 10
Not Connected Pins
Not Connected Pins
Pin No.
Symbol
B19, D3
N.C.
Data Sheet
Ground
Input (I)
Function
Output (O)
Not Connected
36
2002-05-06
PXB4219 / PXB4220 / PXB4221
Functional Description
3
Functional Description
All functional parts of the device are implemented in hardware. Configuration of the
functional blocks has to be done by software via the micro controller interface.
The IWE8 provides two independent data paths for upstream, towards the ATM network,
and downstream, from the ATM network, direction. For dedicated functional tests
loopbacks between both are available.
Each of the 8 ports connected to the data path works independent from the others. It can
be switched to ATM or AAL mode and provides access to the E1/T1 Framer at different
framer interface protocols.
Data Sheet
37
2002-05-06
PXB4219 / PXB4220 / PXB4221
Functional Description
3.1
Operating Modes
3.1.1
ATM Mode
A port that is configured to ATM mode offers ITU-T G.804 [26] compliant ATM cell
mapping into PDH frames at E1 or T1 datarates. ATM mode can be enabled via “p_atm”
in register “pcfN”.
3.1.2
AAL Mode
A port that is configured to AAL mode offers ATM Forum [10] compliant circuit emulation
services via AAL1 as defined in ITU-T I.361.1 [31]. A port N can be configured to AAL
mode via “p_atm” in register “pcfN”.
Some features of the AAL mode are controlled by the internal registers “acfg”, “caal”,
“bp32”, “bp10” and “cfil”. The features controlled by these registers are common to all
AAL ports.
Some features of the AAL mode can be controlled per port, by programming the port
configuration registers “pcfN”.
Some features of the AAL mode can be controlled per channel, by programming the
channel specific “AAL Reference Slot” in the internal configuration RAM’s (RAM1 for
receive ports, RAM2, RAM3 and RAM4 for transmit ports).
3.1.2.1
Unstructured CES Mode
A 2.048 Mbit/s (E1) or 1.544 Mbit/s (T1) bitstream is packed into ATM cells without any
framing. No alignment between octets in E1 or T1 frames and octets in the ATM cells is
done.
For this Unstructured T1/E1 Circuit Emulation Service (CES) the ATM adaptation layer
type 1(AAL1) with Unstructured Data Transfer (UDT) as defined in ITU-T I.363.1[31] is
used. The use of partially filled cells is possible.
For clock recovery the IWE8 supports the Synchronous Residual Time Stamp (SRTS)
method and Adaptive Clock Method (ACM).
• SRTS is possible on channels with completely filled cells
• ACM can be used on both, channels with partially and completely filled cells
A port is programmed to unstructured CES via “p_ces” in the Port Configuration Register
“pcfN”.
Per port a Segmentation Buffer with a maximum size of 16 cells and a Reassembly
Buffer with a maximum size of 256 cells is implemented in external RAM.
Data Sheet
38
2002-05-06
PXB4219 / PXB4220 / PXB4221
Functional Description
3.1.2.2
Structured CES Mode
A port is programmed for the Structured T1/E1 Nx64 kbit/s Basic Service (Structured
CES) via the port configuration register “pcfN” (“p_ces” = 0).
The structured circuit emulation service is intended to carry N of the 24 (T1) or 32 (E1)
timeslots across the ATM network.
An emulated Nx64 kbit/s circuit will be referred to as a channel throughout this
document. It is possible that several channels share the same physical interface port.
In structured CES mode neither SRTS nor ACM clock recovery is possible.
Data Sheet
39
2002-05-06
PXB4219 / PXB4220 / PXB4221
Functional Description
3.2
Functional Block Diagram
External RAM
AAL Segmentation / AAL Reassembly Buffers
ATM Transmit / ATM Receive Buffers
Cell Insertion / Cell Extraction Buffers
Statistics Counters, Threshold Timers
x8
Framer
Receive
Interface
SL
External
RAM
Interface
RTS
Buffer
OR
UR
CR
Octet
Receive
Processing
OQ
Output
Queue
Cell Receive
Processing /
AAL
Segmentation
IE
x8
Cell Insertion
Serial
Loop
Cell Extraction
Tx E1/T1
FT
x8
Framer
Transmit
Interface
CK
OT
CT
Cell Transmit
Processing /
AAL
Reassembly
Octet
Transmit
Processing
EQ
Clock &
Reset
JTAG
Interface
OM
Event
Queue
MP
OAM
Processing
Microprocessor
Interface
Rx UTOPIA
Internal
Clock
Recovery
Circuit
JT
RM
UTOPIA
Receive
Interface
Rx E1/T1
FR
x8
UT
UTOPIA
Transmit
Interface
External
Clock
Recovery
Interface
RB
Tx UTOPIA
ICRC
Upstream/Downstream
Loop
CV
IQ
Interrupt
Queue
To Microprocessor
Figure 6
Data Sheet
Block Diagram
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Functional Description
3.3
Table 11
Functional Block Description
Functions of IWE8 Blocks
Block
Functions
FR
Framer Receive interfaces
• FRCLK synchronization
• 8 bit serial to parallel conversion
• Frame and multiframe synchronization
• Timeslot counter
• Timeslot assignment and channel configuration (RAM1)
OR
Octet Receive processing
ATM ports:
• Cell delineation
• HEC check: Header error detection and correction
• Cell payload de scrambling
• Idle or Unassigned Cell Deletion
• Statistics counter event generation
• Write to ATM Receive Buffer
AAL ports:
• Segmentation port de correlation
• Segmentation
• SN/SNP generation
• SDT pointer generation
• RTS value insertion
• Statistics counter event generation
• Write to Segmentation Buffer
OQ
Output Queue
• FIFO containing 256 addresses of cells to be sent to UTOPIA Receive
CR
Cell Receive processing
ATM ports:
• Read cells from ATM receive buffer
AAL ports:
• Read cells from AAL segmentation buffer
• Padding of partially filled cells
UR
UTOPIA Receive interface
• Cell level handshake
• Mapping of framer port number into ATM header in UTOPIA level 1
mode and UTOPIA level 2 single PHY mode
• Output buffer for 4 cells
Data Sheet
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Functional Description
Table 11
Functions of IWE8 Blocks
Block
Functions
UL
Upstream Loop
• Cell loopback from Cell Receive to Cell Transmit processing
• Loopback buffer for 4 cells
DL
Downstream Loop
• Cell loopback from UTOPIA Transmit to UTOPIA Receive
• Loopback buffer for 4 cells
UT
UTOPIA Transmit interface
• Cell level handshake
• Evaluation of framer port number from ATM header in UTOPIA level 1
mode and UTOPIA level 2 singel PHY mode
• Input buffer for 4 cells
CT
Cell Transmit processing
Port and channel identification
ATM ports:
• Write cells to ATM transmit buffer
AAL ports:
• Port and channel identification
• SNP field check
• SN field check
• SDT pointer detection and verification
• RTS value extraction
• Extracting reassembly buffer filling for ACM
• CAS processing
• Statistics counter event generation
• Insertion of dummy cells at cell loss
• Write to Reassembly Buffer
Data Sheet
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Functional Description
Table 11
Functions of IWE8 Blocks
Block
Functions
OT
Octet Transmit processing
ATM ports:
• Reading octets from ATM Transmit Buffer
• Cell rate de coupling: idle/unassigned cell insertion
• Cell payload scrambling
• HEC generation
AAL ports:
• Read octets from Reassembly Buffer
• Handling of Reassembly Buffer Overflow
• Handling of Reassembly Buffer underflow
• Reassembly Buffer initialization to compensate CDV
• Synchronization of AAL1 start of structure with synchronization pulse of
framer port
• Statistics counter event generation
FT
Framer Transmit interfaces
• FTCLK synchronization
• 8 bit parallel to serial conversion
• Generation of frame and multiframe synchronization signals
• Timeslot counter
• Timeslot assignment and channel configuration (RAM2, RAM3)
SL
Serial Loop
• Serial loopback from Framer Transmit to Framer Receive
OM
OAM processing
• Processing of OAM counter events
• Interrupt queue control
• Microprocessor access control to external RAM
EQ
Event Queue
• FIFO of 256 OAM counter events
MP
Microprocessor interface
• Synchronization of asynchronous microprocessor interface signals
• Internal registers
• Interrupt generation
RM
External RAM interface
• Generation of external RAM interface signals
• Generation of basic RAM cycle
• Access control to external RAM for different blocks
• Parity generation and checking
Data Sheet
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Functional Description
Table 11
Functions of IWE8 Blocks
Block
Functions
CV
External Clock Recovery interface
• Generation of serial communication frames to external clock recovery
circuit, containing RTS values and or ACM buffer filling
• Generation of synchronization for RTS generation by external clock
recovery circuit.
• Reception of frames with RTS values from external clock recovery
circuit
RB
RTS Buffer
• Buffer for 2 incoming RTS values per port
CK
Clock & Reset
• Clock distribution
• Reset control
JT
JTAG interface
• Boundary Scan register
• TAP controller
ICRC
Internal Clock Recovery Circuit
• Synchronous Residual Time Stamp SRTS
• Adaptive Clock Method ACM
External
RAM
ATM Transmit Buffer
• Compensate packetization delay on the PDH interface.
• Maximum size of 256 ATM cells per port.
• Maximum size of 64 octets per ATM cell.
ATM Receive Buffer
• Maximum size of 16 ATM cells per port.
• Maximum size of 64 octets per ATM cell.
Segmentation Buffer
• Compensate segmentation delay in the ATM network.
• 1024 bytes per port (unstructured CES)
• 256 bytes per timeslot (structured CES)
Reassembly Buffer
• Compensate the Cell Delay Variation (CDV) of the ATM network.
• 512 bytes per timeslot. (structured CES)
Data Sheet
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Operational Description
4
Operational Description
4.1
ATM Transmit Functions
For ports configured to ATM mode the following data flow is valid:
The Cell Transmit Processing block is responsible for:
• Cell discarding
• Write ATM cells except of UDF octet to ATM Transmit Buffer
The Octet Transmit Processing block is responsible for:
•
•
•
•
Reading octets from ATM Transmit Buffer
Cell rate de-coupling: idle/unassigned cell insertion
Cell payload scrambling
HEC generation
The ATM transmit functions are controlled by the internal registers “catm”, “atmc” and
“txid”. The features controlled by these registers are common to all ATM ports.
Some features of the ATM transmit functions can be controlled per port, by programming
the port specific “ATM Transmit Reference Slot” in the internal configuration RAM2
4.1.1
Operation
4.1.1.1
ATM Transmit Buffer Filling Level
The amount of buffered data in transmit direction of each port is adjustable in granularity
of bytes or cells. This allows a controlled transmission delay while maintaining a
continuous ATM cell flow. The feature is implemented using the port specific back
pressure mechanism of the UTOPIA interface (Chapter 5.2.2).
The granularity and range of filling level are set independently per port in the “p_thr_m”
bits of the Port Configuration Registers (“pcfN”, see Chapter 7.1). The port specific
threshold value is defined via the corresponding Threshold Port Register (“thrspN”, see
Chapter 7.38 to Chapter 7.41)
2 Modes are supported:
• Mode 1 (p_thr_m = 01B) allows the definition of threshold values in the range of 0 to
255 cells. The actual value equals the contents of thrspN.
• Mode 2 (p_thr_m = 10B) allows the definition of threshold values in the range of 0 to
222 bytes. The actual value equals 53 * C + B, with C representing the 2 most
significant bits of thrspN and B representing the 6 least significant bits of thrspN.
All other values of p_thr_m will switch off this feature and reset the internal counter.
To avoid deadlock conditions, the contents of the common 8 cell UTOPIA input buffer
will always be flushed into the port specific Transmit Buffers independent from their back
Data Sheet
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Operational Description
pressure state. This results in two side effects, which have to be taken into account for
the calculation of threshold values.
• After back pressure state has been entered, up to 8 additional cells may be transferred
from the UTOPIA input buffer to the port buffer.
• Before a certain cell can cause port specific back pressure, it has to traverse the
UTOPIA input buffer, resulting in a delay of 4.2 to 16.8 µs.
4.1.1.2
Cell Discarding
The discarding of cells is available for ATM ports. It can depend on
• Buffer filling level and CLP (Bit 0 of the 4th ATM header octet)
• Buffer filling level and CLPI (Cell Loss Priority Internal, bit 6 of the UDF octet at the
UTOPIA interface)
The bit ENB, bit 5 of the UDF octet at the UTOPIA interface, is responsible for the
decision if discarding shall base on CLP or CLPI. For bit locations see Figure 30.
The buffer threshold for discarding cells is configured by register “thrshld” and applies to
all ports.
Cells that are going to be extracted via the microprocessor interface will be ignored by
the cell discard mechanism
Table 12
ENB
ATM Cell Discarding
CLPI
CLP
Discarding
0
x
0
No
0
x
1
Yes, if buffer threshold has been exceeded
1
0
x
No
1
1
x
Yes, if buffer threshold has been exceeded
4.1.1.3
Cell rate de-coupling: Idle/Unassigned Cell Insertion
When the ATM Transmit Buffer of a port is empty, idle or unassigned cells are
transmitted to provide cell rate de-coupling.
Idle cells are transmitted as defined in the ITU-T I.361 [30]. Unassigned cells can be
inserted, as defined in the B-ISDN UNI and NNI physical layer generic criteria [15].
The 4 MSBs of header octet 1 and the 4 LSBs of header octet 4 are programmable in
the “prg_tx_hd” field of the TX Idle/Unassigned Cell Control Register (txid, see
Chapter 7.10). All other header bits will be 0.
Data Sheet
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Operational Description
octet 1
GFC[3:0]/VPI[11:8] = prg_tx_hd[7:4]
VPI[7:4] = 0000B
octet 2
VPI[3:0] = 0000B
VCI[15:12] = 0000B
octet 3
octet 4
VCI[11:4] = 0000_0000B
VCI[3:0] = 0000B
PTI[2:0] = prg_tx_hd[3:1]
octet 5
UDF
octet 6
prg_tx_pl[7:0]
.
CLP =
prg_tx_
hd[0]
.
octet 53
prg_tx_pl[7:0]
• If idle cell insertion according to ITU-T I.361 or ITU-T I.432.1 is desired, the
“prg_tx_hd” field of “txid” should be set to 0000_0001B.
• If unassigned cell insertion at the NNI or uncontrolled UNI according to ITU-T I.361 is
desired, the “prg_tx_hd” field of “txid” should be set to 0000 XXX0. For X any value is
allowed.
The payload of idle or unassigned cells consists of the same octet which is repeated 48
times. It is programmable by the “prg_tx_pl” field of the “txid” register.
• For ITU-T I.432.1 compliant idle cells, the “prg_tx_pl” field of “txid” should be set to
0110_1010B.
• The pre-assigned values of the information field of all unassigned cells are for further
study (ITU-T I.361 [30])
4.1.1.4
Cell Payload Scrambling
ITU-T I.432.3 [34] recommends the self-synchronizing scrambler x43+1 for payload
scrambling at E1 datarates. For T1 no scrambling is recommended.
The scrambler function is implemented in the device. It can be disabled per port by the
x43_scrambling bit in the “ATM Transmit Reference Slot” in RAM2.
4.1.1.5
HEC Generation
The HEC generation is implemented according to ITU-T I.432.1 [33] using the generator
polynomial x8 + x2 + x + 1. To significantly improve the cell delineation performance in
the case of bit-slips it is recommended that
• the check bits are added (modulo 2) to an 8-bit pattern (coset) before being inserted
in the last octet of the header.
• the recommended pattern is “0101 0101".
Data Sheet
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Operational Description
• the receiver must subtract (equal to add modulo 2) the same pattern from the 8 HEC
bits before calculating the syndrome of the header.
As an example, if the first 4 octets of the header were all zeros the generated header
before scrambling would be “00000000_00000000_00000000_00000000_01010101”.
The starting value for the polynomial check is 0s (binary)
The coset value is programmable in the ATM Control Register (“atmc”, see
Chapter 7.8).
4.1.2
Setup of ATM Transmit Ports
Each ATM transmit port can be configured in the “channel_mode” field of the “ATM
Transmit Reference Slot” in RAM2 to operate in “Inactive”, “Active” or “Standby” mode.
In “Inactive” mode, byte-pattern 0 “bp0” is continuously sent to the framer transmit
interface.
In “Active” mode, user cells or idle/unassigned cells are sent to the framer transmit
interface.
In “Standby” mode, only idle/unassigned cells are sent to the framer transmit interface.
When activating ATM transmit ports, it is important to follow the initialization sequence
as shown in Table 13. Step 2 must be held at least 250 µs to internally reset the ATM
transmit port. During this time the device connected to the Framer Receive Interface has
to be in normal operation allowing the IWE8 to synchronize itself on the frame pulse.
Table 13
Activation sequence for ATM transmit ports
Step
pcfN.
p_tx_act
ATM Transmit Reference Slot.
channel_mode
1
0 = inactive
00 = Inactive
2
1 = active
00 = Inactive
3
1 = active
01 or 11 = Active
Data Sheet
Minimum Time
250 µs
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Operational Description
4.2
ATM Receive Functions
For ports configured to ATM mode the following data flow is valid:
The Octet Receive Processing block is responsible for:
•
•
•
•
•
•
Cell delineation
HEC check: Header error detection and correction
Cell payload de-scrambling
Idle or Unassigned Cell Deletion
Statistics counter event generation
Write cells except of UDF octet to ATM Receive Buffer
The Cell Receive Processing block is responsible for:
• Read cells from ATM Receive Buffer
The ATM receive functions are controlled by the internal registers “catm”, “atmc” and
“rxid”. The features controlled by these registers are common to all ATM ports.
Some features can be controlled per port. They were configured by programming the
port specific “ATM Receive Reference Slot” in the internal configuration RAM.
4.2.1
Operation
4.2.1.1
Cell Delineation
The cell delineation algorithm is implemented according to the ITU-T Recommendation
I.432.1 [33].
To support detection of “Out of Cell Delineation” (OCD) anomalies and “Loss of Cell
Delineation” (LCD) defect, the IWE8 generates an interrupt in eis4 (Chapter 7.22)
whenever the SYNC state is left or entered. The generation of interrupts is controllable
on a per port basis through fields in the “ATM Receive Reference Slot” of RAM1
(Chapter 6.1.1.1). It is also possible to see the current state of the cell delineation FSM
(Finite State Machine) in the Cell Delineation FSM Status Register (“cdfs”, see
Chapter 7.15).
The software can then start a timer (e.g. timer_set_1 provided by the IWE8) to establish
the LCD defect state.
As octet boundaries are available within the receive physical layer prior to cell
delineation, the cell delineation process is performed octet by octet in the HUNT state.
As long as the cell delineation is not in the SYNC state, received octets are discarded.
The ALPHA and DELTA parameters, which influence the robustness of the algorithm
against false misalignment due to bit errors (ALPHA) and false delineation in the re
synchronization process (DELTA), are programmable to values between 0 and 15 in the
ATM Control Register (atmc, see Chapter 7.8), These settings are common for all ATM
ports. ITU-T I.432.1 [33] recommends:
Data Sheet
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Operational Description
• for the Cell-based Physical Layer, ALPHA = 7 and DELTA = 8.
• for the Frame-based Physical Layer, ALPHA = 7 and DELTA = 6.
• for other systems, values for ALPHA and DELTA are for further study.
Bit by bit
Correct HEC
HUNT
Incorrect HEC
PRESYNC
Cell by
cell
ALPHA consecutive
incorrect HEC
DELTA consecutive
correct HEC
SYNC
Cell by
cell
Note - The "correct HEC" means the header has no bit error (syndrome is zero) and has not
been corrected
Figure 7
Cell delineation state diagram (Figure 5/I.432.1)
note 1
note 3
OCD
anomally
Working
LCD defect
note 2
note 4
note1
Triggered by state transition (Case A) due to alpha consecutive incorrect HEC´s in the cell
delineation process (Fig. 5 of ITU-T Recommendation I.432.1)
note2
Triggered by state transition (Case B) due to delta consecutive correct HEC´s in thecell delineation
process (Fig. 5 of ITU-T Recommendation I.432.1)
note3
Triggered by 50 continuous ms in the OCD anomaly maintenance state
note4
Triggered by 50 continuous ms in the cell delineation "Sync" state (Fig.5 of ITU-T Recommendation
I.432.1)"
Figure 8
Data Sheet
Maintenance state transition diagram for cell delineation events
(Figure 2/ I.432.3)
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Operational Description
The Loss of Cell Delineation (LCD) state is entered whenever the Out of Cell (OCD) state
is continuously active for more than an user defined period of time, ITU-T I.432.1
recommends a persistence time of 50ms.
For each port a separate timer is implemented. All timers can be enabled via the ´lcd_en´
bit in the LCD Timer Register (“lcdtimer”, see Chapter 7.43). The global preload value is
defined by the “lcd_val” bits in lcdtimer. After expiration of each timer, an “lcd_start”
interrupt is generated, indicated in the Interrupt Status Register 1 (isr1, see
Chapter 7.18) and the Extended Interrupt Status Register 0 (eis0, see Chapter 7.42).
If enabled, the timer is started at the transition from SYNC to OCD-state. After expiration
LCD state is entered. Whenever the SYNC state is entered before the timer expires, the
timer is reset.
The transition from LCD to Working state follows the same procedure. If after the LCD
state the SYNC state is entered again, the timer is started and after expiration the
maintenance state machine is in working state again. In parallel an “lcd_end” interrupt is
generated indicated in “isr1” and “eis0”. If synchronization is lost again during the timer
period, LCD state is reentered and the timer is reset.
To force resynchronization of the cell delineation process, the microprocessor can force
individual ports to enter the HUNT state, by setting the bit “go_hunt” in the corresponding
“ATM Receive Reference Slot” of RAM1 (Chapter 6.1.1.1).
4.2.1.2
HEC Check: Header Error Detection and Correction
The Header Error Control (HEC) is implemented according to the ITU-T I.432.1 B-ISDN
user-network interface - Physical layer specification [33].
According to the HEC algorithm, cells are discarded when a multi-bit header error is
detected in the Correction mode or a header error is detected in the Detection mode.
According to the HEC algorithm, cells are corrected when a single-bit error is detected
in the Correction mode.
.
Multi-bit error
detected
(Cell discarded)
No error
detected
(No action)
Corrrection
Mode
No error detected
(No action)
Detection
Mode
Error detected
(Cell discarded)
Single-bit error detected
(Correction)
Figure 9
HEC: Receiver mode of Operation (Figure 3/ITU I.432.1)
The pure HEC detection mode as recommended by the ATM Forum is selectable via bit
“a_hec_algor” in register acfg (see Chapter 7.2)
Data Sheet
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Operational Description
.
No error
detected
Figure 10
Detection
Mode
Error detected
Cell discarded
HEC Detection According to ATM Forum
No discarding of HEC errored cells as an option is available and selectable via bit
“a_hec_mode” in the register acfg (Chapter 7.2). In this case an errored HEC is
indicated by setting the most significant bit in the UDF field at the UTOPIA receive
interface.
4.2.1.3
Cell Payload Descrambling
ITU-T I.432.3 [34] recommends the self-synchronizing scrambler x43+1 for payload
scrambling at E1 datarates. For T1 no scrambling is recommended.
The self-synchronizing scrambler function is implemented in the device. It can be
disabled per port by the x43_descrambling bit in the “ATM Receive Reference Slot” in
RAM1.
4.2.1.4
Idle, Physical Layer or Unassigned Cell Deletion
According to ITU-T I.361 [30], idle cells, physical layer OAM cells and cells reserved for
use by the physical layer are not passed to the ATM layer at the UNI.
Data Sheet
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Operational Description
Octet 1
Octet 2
Octet 3
Octet 4
Idle cell identification (Notes
1 and 2)
0000/0000
0000/0000
0000/0000
0000/0001
Physical OAM cell
identification (Note 2) layer
0000/0000
0000/0000
0000/0000
0000/1001
Reserved for use of the
physical layer (Notes 1, 2
and 3)
PPPP/0000
0000/0000
0000/0000
0000/PPP1
P: Indicates the bit is available for use by the physical layer
Values assigned to these but have no meaning with respect to the fields occupying the corresponding bit
positions at the ATM layer
Notes:
1 In the case of physical layer cells, the bit in the location of the CLP indication is not used for the CLP
mechanism as specified in 3.4.2.3.2/I.150.
2 Cells having header values which are identified as idle, physical layer OAM, and reserved for use by the
physical layer are not passed to the ATM layer from the physical layer.
3 Specific pre-assigned physical layer cell header values are given in Recommendation I.432
Figure 11
Pre-assigned cell header values at the UNI for use by the physical
layer (excluding the HEC field) (Table 1/I.361)
In contrast to this the ATM-Forum recommends in the User-network interface
specification that the receiving ATM entity is responsible for extraction and discarding of
unassigned and idle cells.
Use
Octet 1
Octet 2
Octet 3
Octet 4
invalid
XXXX/0000
0000/0000
0000/0000
0000/XXX1
unassigned
0000/0000
0000/0000
0000/0000
0000/XXX0
X: Indicates “don’t care” bits
Figure 12
Pre-defined header field values [11]
The RX Idle/Unassigned Cell Control Register (rxid, see Chapter 7.9) can be used in
order to achieve ITU-T or ATM-Forum compliance.
The 4 MSBs of header octet 1 and the 4 LSBs of header octet 4 of the received cells to
be discarded are programmable in bits “prg_rx_hd”. All other header bits must be 0. On
top the “msk_rx_hd” field of “rxid” allows to mask all or some of these bits. The masked
bits are considered as “don’t care”.
• If ITU-T I.361 compliance is desired, the “prg_rx_hd” field should be set to 0000 0001.
If only idle cells should be deleted, the “msk_rx_hd” should be set to 0000 0000.
Data Sheet
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Operational Description
If all physical layer cells should be deleted, the “msk_rx_hd” should be set to 1111
1110.
• For ATM Forum compliance, the “prg_rx_hd” field should be set to 0000 0000.
The “msk_rx_hd” should be set to 1111 1110. This configuration will delete all
unassigned cells.
The deletion of idle, physical layer or unassigned cells can be enabled or disabled per
port by “delete_idle_cells” in the “ATM Receive Reference Slot” of RAM1
(Chapter 6.1.1.1).
4.2.2
Setup of ATM Receive Ports
Each ATM receive port can be configured in the “channel_mode” field of the “ATM
Receive Reference Slot” in RAM1 to operate in “Inactive”, “Active” or “Standby” mode.
In “Inactive” mode, no data is accepted from the framer receive interface.
In “Active” mode, data is accepted from the framer receive interface, cells are written into
the ATM Receive Buffer and cell addresses are written into the Output Queue.
In “Standby” mode, data is accepted from the framer receive interface but no cells are
written into the ATM Receive Buffer or the Output Queue. This mode can be used to test
the cell delineation.
When activating ATM receive ports, it is important to follow the initialization sequence as
shown in Table 14. Step 2 must be held at least 250 µs to internally reset the ATM
receive port. During this time the device connected to the Framer Transmit Interface has
to be in normal operation allowing the IWE8 to synchronize itself on the frame pulse.
Table 14
Activation sequence for ATM receive ports
Step
pcfN.
p_rx_act
ATM Receive Reference Slot.
channel_mode
1
0 = inactive
00 = Inactive
2
1 = active
00 = Inactive
3
1 = active
01 or 11 = Active
Data Sheet
Minimum Time
250 µs
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Operational Description
4.3
AAL Segmentation Functions
This function implements the Convergency Sublayer for Structured Data Transfer (SDT)
and Unstructured Data Transfer as well as the Segmentation Sublayer for AAL type 1 as
described in ITU-T recommendation I.363.1 [31]. The structure of AAL1 SAR-PDU is
shown in Chapter 12.
The Octet Receive Processing block is responsible for:
•
•
•
•
•
•
•
Segmentation port decorrelation
Segmentation
SN/SNP generation
SDT pointer generation
RTS value insertion
Statistics counter event generation
Write to Segmentation Buffer
The Cell Receive Processing block is responsible for:
• Read cells from Segmentation Buffer
• Padding of partially filled cells
4.3.1
Operation
4.3.1.1
Segmentation Port Decorrelation
In synchronous systems, the microprocessor may activate a number of channels
consecutively, in phase with the segmentation period of a particular channel, causing a
large number of cells to be generated within the same 125 µsec period. This would result
in a large number of cells residing in the Output Queue and increase the Cell Delay
Variation (CDV).
To avoid this, a decorrelation circuit has been implemented in the “Octet Receive
processing” (OR), that inserts a random waiting period between activation of a channel
and start of cell segmentation. This feature can be activated by setting bit “dcor” in the
“AAL Receive Reference Slot” of the channel in RAM1. Otherwise segmentation is
started as soon as the channel has been activated by the microprocessor (field
“channel_mode”)
The decorrelation circuit consists of a free-running 5-bit counter at a frequency of FCLOCK/
3360 (7.5 KHz if FCLOCK= 25 MHz) a register containing a random number (bits
“dcor_random_nr”) and a comparator. Each time an octet for this channel is received the
counter is compared with the random value. Only when both values are equal,
segmentation is started.
When using the decorrelation circuit make sure that the random number is written to the
“dcor_random_nr” field of the “AAL Receive Reference Slot” before activating the
channel with “channel_mode”
Data Sheet
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Operational Description
In SDT mode, the cells are segmented when the first (multi) frame synchronization pulse
after segmentation start is received from the framer receive interface of that channel.
The resulting SC value and pointer field of the first cell transmitted will both be 0.
4.3.1.2
Segmentation
The segmentation and reassembly function can be programmed to use, alternatively to
the standard AAL type 1 SAR-PDU, a SAR-PDU that is referred to as AAL type 0 and
consists of 48 octets payload without any overhead. The selection is done by
programming the “AAL0” field in the “AAL Receive Reference Slot”.
AAL Type 0
Figure 13 shows the AAL type 0 SAR-PDU. It is possible to fill only part of the SAR-PDU
payload with User Information octets by programming field “part_fill” in the “AAL Receive
Reference Slot” of RAM1 to values smaller than 48.
A A L user info
D um m y Fill
N o cte ts
SAR
SDU
PDU
A TM H eader
A TM -S D U = S A R -P D U
5 o cte ts
4 8 o cte ts
A TM Layer
= S e g m e n ta tio n & R ea sse m b ly
= S e rvice D a ta U n it
= P ro to co l D a ta U n it
Figure 13
SAR-PDU of AAL Type 0
AAL Type 1 SDT Structure Length
For Structured Circuit Emulation Service as defined by the ATM-Forum in “Circuit
Emulation Services Version 2.0" [10] Structured Data Transfer (SDT) is used. The
structure length used for SDT in ATM cells is:
• N
when frame-based SDT is selected
• N x 16 when CRC multiframe-based SDT is selected for E1 ports
• N x 24 when superframe-based SDT or extended superframe-based SDT is
selected for T1 ports.
The selection between frame-based or multiframe-based SDT is done by the bit
“sdt_mfs” in the “AAL Receive Reference Slot”.
4.3.1.3
Transport of the Framer Port Number
If the UTOPIA interface is configured for level 2 MPHY mode, the framer port number is
transported via the UTOPIA address bits. In UTOPIA level 1 and UTOPIA level 2 single
PHY mode the framer port number is mapped into the ATM Header (see Chapter 5.2.3).
Data Sheet
56
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.3.1.4
Transport of CAS Information
The four CAS bits for each time slot are transported within one multiframe from the
framer to the IWE8. A signalling buffer in the internal RAM (256 x 4 x 2bit) holds the CAS
bits from the framer interface. The activation of CAS packetization can be done via
“p_cas” in the register “pcfN”.
The CAS bits will be packed in a signalling substructure after the payload of one
multiframe has been packetized.
4.3.1.5
CAS Conditioning and Freezing Upstream
Normally the framer device is responsible for signalling freezing or signalling
conditioning in case of line failure. If the framer doesn’t support the feature the IWE8 can
also fulfill the requirements according to Bellcore TR-NWT-000170 [14].
Pin “FRLOS = 1" indicates that the CAS information from the framer device is invalid and
CAS conditioning or freezing upstream is starting. This state remains active until valid
CAS bits are available indicated by “FRLOS = 0".
CAS freezing means that the last valid CAS information is repeated as long as the error
cause exists. In case of CAS conditioning for each timeslot individual CAS conditioning
nibbles are sent instead. Selection between both procedures is done by setting
“sig_cond” in the “AAL Receive Reference Slot”. If the channel bandwidth is one slot, the
signalling conditioning nibbles are defined in the field “next_slot_nr” of the “AAL Receive
Reference Slot”. If the channel bandwidth is more than one slot, the signalling
conditioning nibbles are defined in the “sig_cond_nibble” of the “AAL Receive
Continuation Slot”. In the latter case the signalling conditioning nibbles defined in the first
“AAL Receive Continuation Slot” are used for the first two slots.
Table 15
Definition of the CAS Signalling Conditioning Nibbles.
Slot Number
Channel Bandwidth = 1 Slot
Channel Bandwidth >= 2 Slots
1
“next_slot_nr” of the “AAL
Receive Reference Slot”
“sig_cond_nibble” of the first “AAL
Receive Continuation Slot”
2
-
“sig_cond_nibble” of the first “AAL
Receive Continuation Slot”
3
-
“sig_cond_nibble” of the second
“AAL Receive Continuation Slot”
N
-
“sig_cond_nibble” of the N-1th
“AAL Receive Continuation Slot”
Data Sheet
57
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.3.1.6
Segmentation Buffer
The Segmentation Buffer is located in external RAM providing 256 bytes of memory for
each timeslot, totalling to 64 KB for 8 ports with 32 timeslots each. The buffer for each
timeslot consists of 4 blocks with 64 octets:
Buffer size = 8 Ports x 32 Channels x 4 Blocks x 64 Octets
[1]
In unstructured CES mode, one Segmentation Buffer per port provides 16 blocks.
In structured CES mode, a Segmentation Buffer per channel with a variable capacity
depending on the number of channels and the cell filling level is automatically configured
by the IWE8. The number of memory blocks depends on the bandwidth of the channel.
Thus for structured CES with N x 64-kbit/s there are N x 4 blocks per connection. Each
channel can occupy 1, 2 or 4 block-groups (4, 8 or 16 blocks). The first block-group
defines the reference slot number of the channel. The second, third and fourth blockgroups define the number of the corresponding interface slot of the channel.
The one-to-one relationship between timeslots and groups of memory blocks allows
dynamic re-configuration of a specific channel without disturbing other channels of the
same port.
Table 16
Relationship between Cell Filling and Segmentation Buffer
Subblock Size
Cell Filling
AAL0
(octets)
Cell Filling
AAL1, no
SDT
(octets)
Cell Filling
AAL1, with
SDT
(octets)
Octets per
block
Cells per
block
Octets per
cell
25-48
25-47
25–47
64
1
64
4-24
4-24
4–24
64
2
32
4.3.1.7
Padding Partially Filled Cells
The value, used for dummy fill of partially filled cells, is programmable in the Cell Fill
Register for Partially Filled Cells (“cfil”, see Chapter 7.12). The fill octets carry no
information and are ignored at the receiver.
Table 17 shows valid values for the cell filling level, which can be configured in the field
part_fill of RAM1: AAL Receive Reference Slot (see Chapter 6.1.1.3) and RAM2: AAL
Transmit Reference Slot (see Chapter 6.1.2.3). All other values are illegal.
Data Sheet
58
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
Table 17
Cell Filling level values
ATM Adaptation
Layer Type
Partially Filled
Completely Filled
Minimum
Maximum
AAL0
4
47
48
AAL1
4
46
471)
AAL1 with CAS
4+Cb2)
46
471)
1)
P format, cell may have only 46 user data octets in non-P format
2)
Cb: Required bytes for the CAS subblock in an ATM cell = RoundUp(N/2)
4.3.2
Setup of AAL Segmentation Channels
In “Inactive” mode, no data is accepted from the framer receive interface.
In “Active” mode, data is accepted from the framer receive interface, segmented and
cells are written into the Segmentation Buffers and the Output Queue.
In “Standby” mode, data is accepted from the framer receive interface but no cells are
written in the Segmentation Buffers.
In “Substitute” mode, data is accepted from the framer receive interface, but substituted
by a programmable byte-pattern selected by “subst_bpslct” in the “AAL Receive
Reference Slot”. Cells are written into the Segmentation Buffers and the Output Queue.
This mode can be used for trunc conditioning to indicate idle (bit pattern = Ox7F) or outof-service conditions (bit pattern = Ox1A) according to af-vtoa-0078 [10] and TR-NWT000170 [14]
When activating the AAL segmentation channels, it is important to follow the initialization
sequence as shown in Table 18. Step 2 must be held at least 250 µs to internally reset
the AAL channel. During this time the device connected to the Framer Receive Interface
has to be in normal operation allowing the IWE8 to synchronize itself on the frame pulse.
Table 18
Activation sequence for AAL segmentation channels
Step
pcfN
p_rx_act
AAL Receive Reference Slot.
channel_mode
1
0 = inactive
00 = Inactive
2
1 = active
00 = Inactive
3
1 = active
01 or 11 = Active
Minimum Time
250 µs
The RTS value stored in the RTS buffer of the port is loaded from the Internal Clock
Recovery Circuit ICRC or from the Clock Recovery Interface. A new value will be
Data Sheet
59
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
provided by the ICRC once every cycle of 8 cells. To guarantee that the value stored in
the RTS buffer of the port is correct, the procedure indicated in Figure 14 is followed.
Start of
Segmentation
1st Cycle of 8 Cells;
Dummy RTS Value Transmitted
0
1
Reset of RTS
generator
Figure 14
2
3
4
5
6
2nd Cycle of 8 Cells;
Dummy RTS Value Transmitted
3rd Cycle of 8 Cells;
1st RTS Value Transmitted
7
1st RTS Value
Received
2nd RTS Value
Received
Synchronization of SRTS Generation with the Start of Segmentation
After the start of segmentation, during the 1st cycle of 8 cells, the RTS generator of the
corresponding port is reset. If an external clock recovery circuit is used, it is reset by
writing a reset frame for the corresponding port on the Clock Recovery Interface. During
this cycle a dummy RTS value is transmitted.
During the 2nd cycle of 8 cells, the IWE8 expects to receive the first valid RTS value
while transmitting a dummy RTS value.
During the following cycles of 8 cells the RTS value received in the previous cycle will be
transmitted.
The dummy RTS value is programmable with “a_dummy_srts” in the register “acfg” and
is common for all ports. It must be programmed before the a_crv_en bit in “acfg” is made
active. Otherwise the first 2 RTS values transmitted will be fixed at “0000”.
If the ICRC does not provide new RTS values to the RTS Transmit Buffer (buffer
underflow), the last received value is repeated. If too many RTS values are provided
(buffer overflow), the values in excess will be omitted and a “rts_overflow” bit in the
Extended Interrupt Status Register 2 “eis2” is set.
Data Sheet
60
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.4
AAL Reassembly Functions
When AAL type 0 is enabled in the “AAL Transmit Reference Slot”, the SAR-PDU and
SAR-SDU processing is disabled.
When AAL type 0 is disabled in the “AAL Transmit Reference Slot”, the SAR-PDU
header is processed according to AAL type 1 as defined in ITU-T I.363.1 [31].
For ports configured to AAL mode the following data flow is valid:
The cell transmit processing block is responsible for:
•
•
•
•
•
•
•
•
•
Port and channel identification
SNP field check
SN field check
SDT pointer detection and verification
SRTS value extraction
CAS processing
Statistics counter event generation
Insertion of dummy cells at cell loss
Write to Reassembly Buffer
The octet transmit processing block is responsible for:
•
•
•
•
•
•
Read octets from Reassembly Buffer
Handling of Reassembly Buffer Overflow
Handling of Reassembly Buffer underflow
Reassembly Buffer initialization to compensate CDV
Synchronization of SDT structure with port structure
Statistics counter event generation
4.4.1
Operation
4.4.1.1
Port and Channel Identification
Before an incoming cell is processed, it is determined to which port and channel the cell
is destined. This information is retrieved from the UTOPIA interface (see Chapter 5.2.3).
4.4.1.2
Sequence Number Protection field check
When an un-correctable multi-bit error is detected the Sequence Number (SN) field of
the SAR-PDU header is declared invalid, otherwise the SN field is valid. The function can
be enabled or disabled by the bit “snp_check” in the “AAL Transmit Reference Slot”. If
disabled the SN of all incoming cells are declared valid.
Data Sheet
61
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.4.1.3
Sequence Number field check
This function implements the sequence number processing. It can be enabled via bit
“sn_check” in the “AAL Transmit Reference Slot”. If enabled, selection can be made
between Robust and Fast Sequence Count Algorithm as defined in the ITU-T I.363.1 [31]
by “sn_fast” in the “AAL Transmit Reference Slot”. If SN check is disabled, all cells are
accepted, no cells are discarded, lost and misinserted cells are not detected.
4.4.1.4
RTS Extraction and Verification
When the clock recovery verification is enabled (“crv_en” in the “AAL Transmit
Reference Slot”), and the port is configured for SRTS (“p_rts” = 1), RTS values are
extracted and verified.
The RTS value consists of the four CSI bits of the cells with odd SC values within a cycle
of 8 cells. A RTS value is accepted as correct if the following condition is true:
• The SN field is valid
• Four consecutive odd SC values (1, 3, 5 or 7) were received in the previous cycle of
8 cells
Otherwise the dummy RTS-value is used.
When the start of a new cycle is detected, the RTS value of the previous cycle is written
to the ICRC.
4.4.1.5
Pointer Field Detection and Verification
When SDT is enabled (“sdt” = 1 in the “AAL Transmit Reference Slot”), it is assumed that
the channel is using Structured Data Transfer. The SAR-PDU payload is supposed to be
of the P format under the following conditions:
• The SN field is valid
• Even SC value (0, 2, 4 or 6)
• The CSI field = 1
When the “sdt_once” bit in the “AAL Transmit Reference Slot” is set to 1, only the first
cell with CSI bit = 1 in a cycle of 8 cells is supposed to contain a P format SAR-SDU. The
other cells with CSI bit = 1 within the same cycle are treated as non-P format. This
operation is recommended by ITU-T I.363.1 [31]
In the cells that are supposed to contain a P format SAR-SDU, the pointer field is verified
and accepted under the following conditions:
• The parity bit is correct as defined in the ITU-T I.363.1 [31]
• The value of the offset field is between 0 and 93 or is the dummy value 127.
If an invalid pointer field (93 < pointer < 127) is detected, its content is replaced by the
dummy value (127). The SAR-SDU is processed as if it would have been received with
a dummy pointer value. The P format of the SAR-PDU payload is assumed and the first
octet of the SAR-PDU payload is not processed as user information.
Data Sheet
62
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
The bit “sdt_par” in the “AAL Transmit Reference Slot” allows to disable the verification
of the parity bit in the pointer field.
For multiframe based SDT the bit “sdt_mfs” in the “AAL Transmit Reference Slot” has to
be set.
4.4.1.6
CAS Conditioning and Freezing Downstream
An internal signalling buffer holds the CAS bits. In case of buffer underflow or pointer
mismatch the IWE8 provides downstream CAS conditioning and freezing according to
Bellcore TR-NWT-000170 [14].
The selection between both is done individually for each channel via Bit “cond_en” in the
“AAL Transmit Conditioning Slot” of RAM4. Values for conditioning can be selected via
the “cond_down_nibble” bits in the same register.
The spare and alarm indication bits of the first E1 frame can be programmed by setting
bits cas0portN in the registers “cas1” and “cas2”. The CAS information of idle time slots
can be chosen by setting bits in the register “cas3”.
4.4.1.7
Insertion of Dummy Cells at Cell Loss
Upon cell loss detection, the sequence count algorithm will insert dummy cells into the
Reassembly Buffer to maintain bit count integrity. The maximum amount of
consecutively inserted cells is 6.
These dummy cells are physically inserted when reading the Reassembly Buffer. The
Reassembly Buffer itself contains only control field in front of the payload of the next
accepted cell, indicating the amount of dummy cells to be inserted.
Inserted dummy cells are not taken into account for the ACM Reassembly Buffer filling
level calculation. This means that the buffer filling level is incorrect as long as dummy
cells are physically inserted.
The data octet used for the dummy cells is the byte-pattern selected by the “starv_bpslct”
field of the “AAL transmit reference slot” of RAM3.
4.4.1.8
Reassembly Buffer
The purpose of the Reassembly Buffer is to compensate the Cell Delay Variation (CDV)
of the ATM network.
It is located in external RAM providing 512 byte of memory for each timeslot, totalling to
128 KB for 8 ports with 32 timeslots each. The buffer for each timeslot consists of 8
memory blocks with 64 octets:
Buffer size = 8 Ports x 32 Channels x 8 Blocks x 64 Octets
Data Sheet
63
[2]
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
The number of memory blocks used depends on the bandwidth of the channel (N*64kbit/s). Thus for structured CES with N*64-kbit/s there are N x 8 memory blocks per
connection.
The one-to-one relationship between timeslots and groups of memory blocks allows
dynamic re-configuration of a specific channel without disturbing other channels of the
same port.
4.4.1.9
Handling of Reassembly Buffer Overflow
Overflow is detected when, at the moment of storing an accepted cell, the extra payload
of the new cell in the buffer would exceed the logical size of the Reassembly Buffer.
For AAL type 1 two possible actions exist:
• The cell is discarded.
Re-initialization of the Reassembly Buffer as described in Chapter 4.4.2.4 is in line
with the ITU-T I.361.1 [31]
• The cell is accepted but the Reassembly Buffer is automatically re-initialized.
Re-initialization is done automatically without disturbing the microprocessor.
The action chosen is determined by the “auto_reinit_of” field in the “AAL Transmit
Reference Slot” in RAM3.
When using AAL type 0, the accepted cell is considered to be a misinserted cell and
rejected.
4.4.1.10 Handling of Reassembly Buffer Underflow
An underflow period is detected when no octets are available in the Reassembly Buffer
to be passed to the framer transmit interface. During the underflow period starvation
octets are passed to the framer transmit interface and Statistics Counter 12 increments
if enabled.
For AAL type 1, the underflow is considered to be caused by an extremely late cell. The
length of the underflow period is measured by counting the number of transmitted
starvation octets, expressed as a number of starvation cells that are counted by
Statistics Counter 13 if enabled
For resolving the underflow two possibilities exist:
• Manual re-initialization:
Re-initialization of the Reassembly Buffer as described in Chapter 4.4.2.4 is in line
with the ITU-T I.361.1 [31]
• Automatic re-initialization:
As soon as start of underflow is detected, the Reassembly Buffer is re-initialized
without disturbing the microprocessor. Thus, the underflow status for the device is no
longer valid although the underflow condition still exists. No starvation cells due to
underflow will be inserted and counter 13 will not increment
Data Sheet
64
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
The action chosen is determined by the “auto_reinit_uf” field in the “AAL Transmit
Reference Slot” in RAM3.
For AAL type 0 the detection of an underflow period is considered to be the detection of
cell loss. For this reason a dummy cell is inserted. The inserted dummy cell must be
reflected in the buffer filling level of the Reassembly Buffer.
4.4.1.11 Synchronization of SDT Structure with Port Structure
In normal operation the “ATM start of structure” is synchronized with the “Port start of
structure”. Since this synchronization may get lost, the coincidence of both events is
monitored. If they do mismatch, a two bit error counter is incremented. Upon reaching a
programmable threshold, the Reassembly Buffer is re-initialized and Statistics Counter
14 is incremented if enabled. The threshold value is programmed in the “sdt_oos_nr”
field of the “AAL Transmit Reference Slot” in RAM2. If the Statistics Counter 14 should
reflect “atmfCESPointerReframes” as defined in [10], “sdt_oos_nr” should be set to
“00”.
To compensate cell loss the Sequence Count algorithm inserts dummy cells filled with
starvation octets. In case the cell filling level is 46 octets or less, the bit count integrity
won’t be violated as the length of the AAL-user information within one SAR-SDU is
always the same. When operating with a cell-filling of 47 octets, the AAL-user
information maybe 47 octet in case of non-P format or 46 octet in case of P format SARPDU. As the information on the lost cell’s SAR-PDU format is not available, it is possible
that an excess of starvation octets is transmitted. As a result, the “ATM start of structure”
might be out of phase with the “Port start of structure”.
The following procedure is implemented for re-synchronization:
• At the end of expanding a burst of dummy cells a flag is set, indicating that a phase
shift might occur. The maximum phase shift is 2 octets (e.g. 2 cells with pointers are
lost within a sequence of eight cells)
• When an “ATM start of structure” is received and a positive phase shift is detected
lower than or equal to 2 octets, an equal number of octets is deleted in the
Reassembly Buffer and the flag is reset.
• When the detected phase shift is larger than the allowed value or negative the flag is
reset and the Reassembly Buffer is re-initialized.
• When no phase shift is detected the flag is reset.
4.4.2
Setup
4.4.2.1
Setup of Reassembly Channels
Each AAL transmit channel can be configured in the “channel_mode” field of the “AAL
Transmit Reference Slot” to operate in “Inactive”, “Standby” or “Active” mode.
Data Sheet
65
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
• In “Inactive” mode, no cells are accepted from the “UTOPIA Transmit interface”, and
byte-pattern 0 is sent to the framer transmit interface.
• In “Standby” mode, cells are accepted from the “UTOPIA Transmit interface”, but bytepattern 0 is sent to the framer transmit interface.
• In “Active” mode, cells are accepted from the “UTOPIA Transmit interface”, and user
data octets are sent to the framer transmit interface.
When activating the AAL reassembly channels, it is important to follow the initialization
sequence as shown in Table 19. Step 2 must be held at least 250 µs to internally reset
the AAL channel. During this time the device connected to the Framer Transmit Interface
has to be in normal operation allowing the IWE8 to synchronize itself on the frame pulse.
Table 19
Activation sequence for AAL reassembly channels
Step
pcfN.
p_tx_act
AAL Transmit Reference Slot.
channel_mode
1
0 = inactive
00 = Inactive
2
1 = active
00 = Inactive
3
1 = active
01 or 11 = Active
4.4.2.2
Minimum Time
250 µs
Physical Reassembly Buffer Size
Based on the cell filling level, AAL type and use of SDT, a memory block can be divided
into subblocks, where the user data octets of a single cell are stored. The size of the
memory subblock per Reassembly Buffer is automatically adapted. Table 20 shows this
relationship.
Table 20
Relationship between Cell Filling and Reassembly Buffer Subblock
Size
Cell Filling
AAL0
(octets)
Cell Filling
AAL1, no
SDT
(octets)
Cell Filling
AAL1, with
SDT
(octets)
Octets per
block
Cells per
block
Octets per
cell
33–48
32–47
31–47
64
1
64
17–32
16–31
15–30
64
2
32
9–16
8–15
7–14
64
4
16
4–8
4–7
4–6
64
8
8
The physical Reassembly Buffer size used for a N x 64 kbit/s connection is given by:
Physical Size(octets) = N x 8 x Cell Filling x Cells per Block.
Data Sheet
66
[3]
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.4.2.3
Initialization of the Reassembly Buffer
Before a channel is activated, the Reassembly Buffer must be configured properly to
compensate Cell Delay Variation (CDV).
In order to avoid buffer underflow due to large cell distances the amount of initial
starvation octets that are passed to the framer interface upon arrival of the first cell needs
to be set. On the other hand this number needs to be as small as possible to avoid
excessive delay. The logical Reassembly Buffer size can be adjusted in order to detect
too small cell distances by Reassembly Buffer overflow.
All parameters are defined in the “AAL Transmit Reference Slot” in RAM3. The amount
of starvation octets given to the framer transmit interface after arrival of the first cell is
defined by “starv_ini”. The contents of the starvation octets can be defined by
“starv_bpslct” and the logical Reassembly Buffer size can be configured with “buff_lsize”.
The following sections give an overview on the Reassembly Buffer operation and
initialization.
Unstructured Data Transfer:
After activation of a channel both SAR Receiver and Framer Transmit Interface start
operation. As long as no reassembled cell is available in the Reassembly Buffer it is
considered to be in underflow condition and starvation octets are passed to the Framer
Transmit Interface.
As soon as the first reassembled cell is available in the Reassembly Buffer the device
starts building up the Reassembly Buffer threshold level. This is done by passing an
additional amount of starvation octets to the framer Transmit Interface
Reassembly Buffer
Filling Level [octets]
buff_lsize
Example:
part_fill = 16 octets
N = 16
no CDV
4
0
Time
Time
Framer
Interf.
T0
T0+TS
Starvation octets
Data octets
Figure 15
Data Sheet
T0+T
T0+2*T
T0: First cell arrival time
TS: (starv_ini+1) * 125µs / N
T: Average cell distance
Reassembly Buffer Initialization: No CDV
67
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
As the transmission of the reassembled cell stream is delayed by “starv_ini”+1 octets,
there will be “starv_ini”+1 octets of the previous cell left in the Reassembly Buffer if the
following cell arrives without CDV.
If the maximum positive CDV is the same as the maximum negative CDV the expectation
interval has a length of 2 x CDV. Assuming N octets of data are transmitted within one
frame period of 125µs the amount of data transmitted in this interval is:
N
∆ = 2 × CDV × --------------125 µ s
[4]
The worst case for buffer underflow is given if the first cell has maximum positive CDV.
Reassembly Buffer
Filling Level [octets]
Example: part_fill = 16 octets; N = 16
1st cell has max. pos. CDV = 15,625µs
2nd cell has max. neg. CDV = -15,625µs
buff_lsize
4
Time
0
Time
Framer
Interf.
T0 T0-CDV+TS
T0-CDV
Starvation octets
Data octets
Figure 16
T0+T
T0+T+CDV
T0: First cell arrival time (theoretical)
TS: (starv_ini + 1) * 125µs / N
T: Average cell distance
T0+2*T
T0+2*T-CDV
Reassembly Buffer Initialization: positive CDV at Start Up
In this case the amount of starvation octets inserted after receipt of the first cell has to
be bigger than the amount of data transmitted during the expectation interval. Otherwise
the Reassembly Buffer will enter underflow condition at any time a cell with maximum
positive CDV is followed by a cell with maximum negative CDV.
N
starvini ≥ ∆ – 1 = 2 × CDV × --------------- – 1 ≥ 0
125 µ s
[5]
The worst case for buffer overflow is given if the first cell has maximum negative CDV
and then any cell with maximum negative CDV is followed by a cell with maximum
positive CDV.
Data Sheet
68
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
Reassembly Buffer
Filling Level [octets]
buff_lsize
Example: part_fill = 16 octets; N = 16
1st cell has max. neg. CDV = 15,625µs
2nd cell has max. pos. CDV = -15,625µs
4
Time
0
Time
Framer
Interf.
T0+T
T0+CDV+TS
T0+T-CDV
T0+CDV
T0: First cell arrival time (theoretical)
TS: (starv_ini + 1) * 125µs / N
Starvation octets
Data octets
T: Average cell distance
Figure 17
T0
T0+2*T
T0+2*T+CDV
Reassembly Buffer Initialization: Negative CDV at Start Up
If the first cell has maximum negative CDV there will be “starv_ini” + 1 octets left in the
Reassembly Buffer when the following cell arrives with maximum negative CDV. In case
the following cell arrives with maximum positive CDV it will be “starv_ini” + 1 plus the
amount of data to be transmitted in the expectation interval. Just after cell arrival the
filling level of the Reassembly Buffer is at its maximum:
N
bufflsize ≥ partfill + starvini + 1 + ∆ = partfill + 4 × CDV × --------------125 µ s
[6]
The delay introduced by the Reassembly Buffer is:
starvini × 125 µ s
delay = -----------------------------------------N
[7]
Structured Data Transfer:
After activation of a channel both SAR Receiver and Framer Transmit Interface start
operation. As long as no reassembled cell in P format is accepted the Reassembly Buffer
it is considered to be in underflow condition and starvation octets are passed to the
Framer Transmit Interface.
After that, “starv_ini” + 1 starvation octets are given to the Framer Transmit Interface.
Then, the transmitter reads as many octets from the Reassembly Buffer as indicated by
the pointer field. For each octet one starvation octet is given to the Framer Transmit
Interface. The next octet to be read from the Reassembly Buffer is the “ATM Start of
Structure” (The octet where the AAL1 pointer field points at).
After that, starvation octets are passed to the Framer Transmit Interface until the “Port
Start of Structure” is detected. A “Port Start of Structure” occurs when the Framer
Data Sheet
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Operational Description
Transmit Interface requests the first time-slot octet belonging to the channel in the frame
or the multiframe.
From that moment on, the “ATM Start of Structure” and “Port Start of Structure” are
synchronous and the contents of the Reassembly Buffer are passed to the framer
transmit interface.
The worst case for buffer underflow is given, if the first cell has maximum positive CDV,
the contents of the pointer field is “0” and the “Port Start of Structure” occurs right after
the transmission of “starv_ini” + 1 starvation octets.
Example: part_fill = 16 octets; N = 16
1st cell has max. pos. CDV = 15,625µs
2nd cell has max. neg. CDV = -15,625µs
Reassembly Buffer
Filling Level [octets]
buff_lsize
4
Time
0
Time
Framer
Interf.
T0+T
T0 T0-CDV+TS
T0-CDV
T0+T+CDV
T0+2*T
T0+2*T-CDV
Port Start of Structure
ATM Start of Structure
Starvation octets
Data octets
Figure 18
T0: First cell arrival time (theoretical)
TS: (starv_ini + 1) * 125µs / N
T: Average cell distance
Reassembly Buffer Initialization for structured CES: positive CDV at
Start Up
In this case the amount of starvation octets inserted after receipt of the first P format cell
has to be bigger than the amount of data transmitted during the expectation interval as
defined in (4). Otherwise the Reassembly Buffer will enter underflow condition at any
time a cell with maximum positive CDV is followed by a cell with maximum negative CDV.
2 × CDV × N
starvini ≥ ∆ – 1 = --------------------------------- – 1 ≥ 0
125 µ s
[8]
The worst case for buffer overflow is given, if the first P format cell has maximum
negative CDV, the contents of the pointer field is at its maximum value Pmax and the
“Port Start of Structure” occurs right before the receipt of that P format cell. In that case
the complete frame needs to be stored in the Reassembly Buffer
If the first cell has maximum negative CDV there will be “starv_ini” + 1 octets left in the
Reassembly Buffer at any time a cell with maximum positive CDV is followed by a cell
Data Sheet
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2002-05-06
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Operational Description
with maximum negative CDV. the following cell arrives with maximum negative CDV. In
case the following cell arrives with maximum positive CDV it will be “starv_ini” + 1 plus
the amount of data to be transmitted in the expectation interval. Just after cell arrival the
filling level of the Reassembly Buffer is at its maximum:
To allow CDV compensation and SDT structure synchronization, the logical size should
be programmed to a minimum value given by:
bufflsize ≥ partfill + starvini + 1 + ∆ + FR × N + Pmax
[9]
N
bufflsize ≥ partfill + 4 × CDV × --------------- + FR × N + Pmax
125 µ s
[10]
with FR being the number of frames in a structure:
FR = 0: when SDT is not used
FR = 1: for frame based SDT
FR = 16: for multi-frame based SDT in E1 mode
FR = 24: for multi-frame based SDT in T1 mode
Pmax is the maximum number of payload octets from the pointer field to the start of
structure:
Pmax = N x FR, if N x FR < 2 x part_fill
Pmax = 2 x part_fill, if N x FR > 2 x part_fill
The logical Reassembly Buffer size is limited by its physical size. The relation is given by:
bufflsize ≤ 8 × N × partfill × cellsperblock – S × partfill
[11]
where
S = 0: in case of Fast Sequence Count Algorithm
S = 1: in case of Robust Sequence Count Algorithm
When the robust SC algorithm is used, the decision on cell acceptance is delayed until
the next cell is received. As the cell is temporarily stored in the Reassembly Buffer, there
must always be space for that cell. Therefore, the physical size of the Reassembly Buffer
must be at least the logical size plus one cell.
In the fast SC algorithm the intermediate storage of a cell is not required. The cell is
stored immediately in the Reassembly Buffer, when accepted.
The delay introduced by the Reassembly Buffer is:
starvini × 125 µ s
( starvini + FR × N + P max ) × 125 µ s
------------------------------------------ ≥ delay ≤ --------------------------------------------------------------------------------------------N
N
Data Sheet
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[12]
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.4.2.4
Re-Initialization of the Reassembly Buffer
For re-initialization of the Reassembly Buffer by the microprocessor, the processor has
to set the “mcp_reinit” bit in the “AAL Transmit Reference Slot” in RAM2, wait for 1.5
frames and reset “mcp_reinit”.
Data Sheet
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Operational Description
4.5
Internal Clock Recovery Circuit (ICRC)
The Internal Clock Recovery Circuit (ICRC) may generate RTS values in upstream
direction and a 8.192, 2.048 or 1.544 MHz transmit clock in downstream direction. Each
port works independently using its own set of control registers and error counters. The
Cell delay variation is assumed to be less than +/- 4 ms.
According to ITU-T 432.1 [33] SRTS clock recovery is only defined for unstructured CES.
Therefore, ports supporting SRTS clock recovery have to be configured for only one
channel in unstructured CES with completely filled ATM cells.
The ICRC supports two Framer Interface formats
• FALC Mode (FAM, see Chapter 5.1.1) with a transmit clock frequency of 8.192 MHz
for both E1 and T1.
• Generic Interface Mode (GIM, see Chapter 5.1.2) with a transmit clock frequency of
2.048 MHz in case of E1 and 1.544 MHz in case of T1.
These modes can be selected via bits “om” in the Operation Mode Register (opmo, see
Chapter 7.24) and bit “gim” in the Internal Clock Recovery Circuit Configuration Register
(“icrcconf”, see Chapter 7.46).
Transmit clocks are generated by internal PLLs based on SRTS, ACM or both. The
method of transmit clock generation is selected via bits "srt" and "acm" in the
Configuration Register Downstream of Port N ("condN", see Chapter 7.47). Generation
of RTS values is enabled via bit “rtsg” in the Configuration Register Upstream of Port N
(“conuN”, see Chapter 7.51). If ACM is used, the corresponding RTS generator can be
kept disabled.
For communication between the ICRC and the rest of the chip a frame based protocol is
used. The internal interface as well as its protocol is the same as defined for the external
clock recovery interface (see Chapter 5.4).
The ICRC contains the following sub blocks:
Data Sheet
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2002-05-06
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Operational Description
Receive
Line
Clock
RTS
generation
lgc
2.43 MHz
32.768 MHz
Transmit
Line
Clock
lpcr
RTS
0
1
1
0
lc8
rtsi
0
Loopback11
0
1
Frame
Receiver 1
rtso
RTS
Receive
FIFO
1
0
SDOR
PDSYN
1
0
RTS
Frame
Buffer Filling Receiver 2
lgs
PLL
ACM
(ACM)
Microprocessor Interface, Test and Control
4.5.1
Frame
Generator
lptu
PLL
Figure 19
RTS
Transmit
FIFO
ena
ena
PLL
SRTS
PLL
FILTER
0
1
Clock
lprd lpru Recovery
Interface
0
SDI
1 0
1
2.43 MHz Fractional
Divider
1
0
SDOD
lptd
SCLK
CLK52
RFCLK
Block Diagram of the ICRC
Data Flow
In transmit direction the ICRC generates RTS values for each port independently and
writes them into the RTS Transmit FIFO.
Received RTS values are written to the port specific RTS Receive FIFO to compensate
cell delay variation. RTS values for each port are processed at a frequency equal to the
SRTS period (8 cells). ACM values are processed immediately by the corresponding
PLL.
4.5.2
Frame Generator
This block generates 32-bit control frames that are used for communication with the rest
of the system.
For synchronization with the system the received synchronization signal PDSYN is used.
However, if this signal can’t be extracted from the received bit stream by the frame
receiver, the frames are generated by means of an internal synchronization counter.
The frame output is put in tri-state during power down of the internal interface. As soon
as the internal synchronization counter is synchronized on PDSYN signal, the frame
output is enabled.
4.5.3
Frame Receiver
This block is implemented twice. Once for SRTS and ACM data via port SDOD and once
for the “reset SRTS logic” command via port SDOR.
Data Sheet
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Operational Description
The frame receiver is synchronized to the received synchronization signal PDSYN by
means of an internal synchronization counter. In case no sync signal is received, frames
are synchronized to the counter. The synchronization between PDSYN and the internal
counter is checked each time PDSYN is received. A synchronization error is indicated
via bit “scri” in the Interrupt Source Register (“irs”, see Chapter 7.44) at the start of a
series of wrong synchronized frames. Synchronization errors are counted and the
internal synchronization counter is synchronized on the new received synchronization
pulse. An errored frame (parity error) is indicated via bit “per” in “irs” but processed as a
normal frame.
In case the internal interface to the ICRC is switched off by the system, SCLK keeps
working. The ICRC detects the following errors:
• Parity error: Because SDOD and SDOR are continuously high, the odd parity is
violated.
• Synchronization error: Because PDSYN is continuously low, synchronization is not
possible.
For ACM, the Reassembly Buffer filling level is measured in number of octets and
passed to the ICRC each time a accepted cell is stored in the Reassembly Buffer.
The arrival time between 2 ACM data values is verified. The assumed maximum CDV is
4 ms. The maximum cell distance without CDV is 0.276 ms for T1 and 0.221 ms for E1.
In case the next ACM data value is not arrived within 10 ms, an error indicated in register
“atlN” is generated.
4.5.4
RTS Receive FIFO
This block is implemented for each port.
The RTS Receive FIFO compensates the Cell Delay Variation (CDV), the delay of the
system interface with it's FIFO and the phase difference between reading and writing of
the RTS Receive FIFO. Each RTS Receive FIFO provides space for 8 RTS values. After
reaching the initial filling level of 5 RTS values, delay variations of +3 / -5 RTS values
can be compensated. This corresponds to a maximum CDV of -4.4 / +7.3 ms (E1) or 5.8 / +9.7 ms (T1).
In case of overflow (register “sroN”) or underflow (register “sruN”) the PLL-SRTS is put
in free running mode and the FIFO is restarted. These events are indicated in the SRTS
Receive FIFO Underflow Register (sruN, see Chapter 7.60) and the SRTS Receive
FIFO Overflow Register (sroN, see Chapter 7.61).
In case of SRTS the PLL start-up is delayed until 5 RTS values are received. This will
take 7.3 ms for E1 and 9.7 ms for T1. During this time PLL-SRTS is free running (and bit
“frr” of register “statN” is set).
If the PLL block does not use RTS values (bit “srt”=0 in register “condN”) or the port is in
power down mode (bit “pwd”=1 in register “condN”) no data is written to this FIFO. In
Data Sheet
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2002-05-06
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Operational Description
case bit “ena” of register “tsinN” is set, a value from the SRTS Receive FIFO is read by
reading register “tsout”.
In cases where the network clocks of RTS generator and RTS receiver have a frequency
offset, the SRTS algorithm will generate a service frequency with the same frequency
offset. The rate of RTS value generation and consumption depends on the service
clocks. In this special case, the rate of RTS value consumption is different from the rate
of RTS value generation. Enabling the ACM algorithm will not help as the FIFO is read
by the clock generated by PLL-SRTS. As a result the SRTS Receive FIFO will generate
regular (every 20 minutes) under- or overflows.
4.5.5
RTS Transmit FIFO
Each RTS generator stores the RTS value and its port number in the RTS Transmit
FIFO. When the frame generator starts generating a new frame, it reads from the FIFO
the source address and the next RTS value.
4.5.6
ICRC Loopback Modes
Loopbacks are available for each port and for the system interface of the circuit.
Each port has 2 loopbacks. The first, situated near the framer, performs a loopback on
the clock signals. It is controlled by the bit “lgc” in the Configuration Register
Downstream Direction of Port N (condN, see Chapter 7.47), which sends the generated
clock back to the RTS generator, and “lc8” in “condN”, which sends the received clock
back to the framer interface. The second has the same internal structure. It allows to
send received RTS values of all ports back to the RTS Transmit FIFO (“lpcr”=1 in register
“condN”). Thus, this loop has a variable delay with a guaranteed maximum of RTS
Transmit FIFO depth x Frame-period. If “lgs”=1 in register “condN”, generated RTS
values are sent via the receive FIFO to the PLL.
Another loopback block is situated at the clock recovery interface. It is controlled by the
bits “lptd”, “lptu”, “lprd” and “lpru” in the ICRC configuration register “icrcconf”. Not all loop
back possibilities of this block carry useful data, but the parity can always be tested.
4.5.7
RTS Injection
In case bit “ena” of the Test Input of Port N register (tsinN, see Chapter 7.50) is set, the
RTS Transmit FIFO receives a new RTS value from field “rtsi” of “tsinN” at the moment
the microprocessor writes data to that register. RTS values coming from the RTS
generator of port N are ignored in this case. RTS values coming from the clock recovery
interface and which have to be returned because of loopback “lpcr”, have priority over
register “tsinN”.
During this test, the clock recovery or, in case of loopback, the receive FIFO receives the
RTS values written in field rtsi. It is advisable to power down the circuit(s) which do not
Data Sheet
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2002-05-06
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Operational Description
work properly with these RTS values via bit “pwd” of “condN”. If “srt” in “condN” is reset,
the output of the RTS Receive FIFO is not used by PLL-SRTS.
4.5.8
Fractional Divider
The fractional divider generates a 2.43 MHz clock from the 51.84 MHz clock provided via
the CLK52 pin. This is done by selecting 3 out of 64 clock pulses of 51.84 MHz. The
resulting 2.43 MHz clock contains jitter components of 810 kHz and above, with a
maximum peak to peak jitter of 19 ns.
4.5.9
Clocks
For an overview on the required clocks for the ICRC please refer to Chapter 8.1.
4.5.10
Power Management
Different Power down modes are available for the ICRC:
• for each port via bit “pwd” in “condN”
• for the Clock Recovery Interface via bit “pdcri” in “icrcconf”.
• for the complete ICRC by means of the “a_icrc_dwn” bit in the “acfg”. This feature
reduces the power consumption by approximately 50 mW. Once the ICRC is switched
off, it can only be enabled by hardware reset of the whole device.
4.5.11
PLL Block
This block is implemented for each port. It consists of 3 PLLs: PLL-SRTS, PLL-ACM and
PLL-FILTER.
The bits “srt” and “acm” in the register “condN” define, which PLL is connected to PLLFILTER and used for clock recovery. Each PLL may be used exclusively or in
combination.
4.5.11.1 PLL-SRTS:
PLL-SRTS is used for clock recovery using the SRTS method. It has a cut-off frequency
of 20 to 50 Hz.
The phase detector of PLL-SRTS has a linear range which optimized for jitter tolerance
requirements. It is defined by a “window” of accepted RTS values. Each time PLL-SRTS
detects values, which fall out of the window, or processes invalid values, it is forced in
hold over for 1 SRTS period, bit “hov” of register “statN” is set and the
SRTS Invalid Value Processed Counter (“sriN”, see Chapter 7.63) is incremented. In
case the number of out of window conditions during 16 SRTS periods exceeds the value
given by field “tr_srts” of register “treshN”, an out of lock message, indicated with bit “ols”
of register “oolN” is generated. During start-up of the RTS Receive FIFO, PLL-SRTS is
free running and bit “frr” of register “statN” is set.
Data Sheet
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2002-05-06
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Operational Description
4.5.11.2 PLL-FILTER
The PLL “PLL-FILTER” has a very low cut off frequency and a tuning range of +/ -240
ppm. It reduces jitter which is generated in, or passed through PLL-SRTS. Although PLLFILTER is placed behind PLL-ACM, it has little or no functionality in case of ACM, as
PLL-ACM has a lower cut off frequency.
If more out of lock detections during 16 SRTS periods are detected than defined with
“tr_filt” in “tresh”, an out of lock message, indicated by bit “olf” of register “oolN”, is
generated.
4.5.11.3 PLL-ACM
The PLL-ACM is a control system with feedback of 2nd order. Its phase is adjusted
according to the filling level of the Reassembly Buffer.
The average buffer filling level as defined in bits “avb” in the Average Buffer Filling
Register (“avbN”, see Chapter 7.52) is subtracted from the current buffer filling level.
The result is amplified in order to adjust the cut off frequency and to define the system’s
damping (number of bytes, needed to drive the DCO over its tuning range. The loop gain
is programmed in the ACM Shift Factor Register (asfN, see Chapter 7.53). Although
adjustable, the PLL-cut-off frequency is generally less than 1 Hz. In conjunction with a
low pass filter, CDV is very small.
The behaviour of the PLL is characterized by rise time and lock in time. The rise time is
the time when the clock output enters the predefined tuning range for the first time. The
lock in time is defined as the time after which the clock stays within the accepted
deviation.
f/f0
2d
Mp
1
0.9
Tr, Tr1: Rise time
Tp:
Peak time
Tl:
Lock in time
Mp:
Peak overshoot
2d:
Tuning range
Target frequency
f 0:
0.1
Tr1
Figure 20
Data Sheet
Tr
Tl
Tp
t
Transient Parameters
78
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
The tuning range of the DCO is limited to the value programmed to bits “tur” in register
“condN”. If the phase detector requests a higher frequency deviation the DCO enters
out-of-range condition. In this case the DCO’s output will be clipped and bit “max” of
register “statN” will be set. If the number of out-of-range conditions during 16 ATM cells
exceeds the value given by field “tr_acm” of register “treshN”, an out-of-lock message,
indicated via field “ola” of register “oolN”, is generated.
Increasing the loop-gain reduces the damping of the PLL-ACM. This will reduce the rise
time but results in overshoot and long lock-in times.
Reducing the loop-gain increases the damping. This results in lower cut off frequencies,
and prevents overshoot. Thus, CDV is less likely to drive the PLL out of lock. The rise
and lock-in time are increased. If the loop-gain is too low, the amount of bytes required
to drive the DCO over it's tuning range could cause a data buffer over- or underflow.
Optimized damping allows minimum lock-in time without overshoot. In this case PLLACM’s frequency is moving asymptotically to the correct value.
f/f0
dl
dl: low damping
dh: high damping
do: optimized damping
do
1
dh
0.1
Tr(dl)
Figure 21
Tr(do) = Tl(do)
Tr(dh) = Tl(dh)
t
Influence of Damping on Lock in Time
PLL-ACM tries to keep the number of bytes in the Reassembly Buffer at the average
buffer filling value programmed to register “avbN”. This value should be equivalent to the
number of bytes stored in the Reassembly Buffer during start-up, as defined by the value
programmed in the “starv_ini” field of the “AAL Transmit Reference Slot” in RAM3.
Data Sheet
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Operational Description
During start-up and restart, PLL-ACM will be free running for 8 x tiniN[tini] x TData as
programmed in the Time of Initial Free Run Register (“tiniN”, see Chapter 7.54). During
this time the data buffer is filled with an initial number of bytes. As tiniN[tini] is 2 bit longer
than "stav_ini" in the AAL Transmit Reference Slot of RAM3 it is possible to choose a
longer-than-necessary initialization time, to compensate start-up time differences.
After the initial free run, PLL-ACM will start locking in. The lock in time depends on:
• The difference between the initial number of bytes in the data buffer (see “starv_ini” of
the “AAL Transmit Reference Slot” in RAM3) and the value programmed in register
“avbN”.
• The damping, which is influenced by register “asfN”.
• The maximum allowed frequency deviation given by “tur” of register “condN”.
• The required frequency deviation.
During this lock-in process, the output frequency might temporarily reach the
programmed minimum or maximum value. This strongly depends on the initial difference
of the data buffer filling from the value given by “avbN”.
As re-initialization of the data buffer is not reported to the ICRC, PLL-ACM will detect a
huge difference between data buffer filling and the value given by “avbN”. As a result the
output frequency will be driven to it's lowest allowed value and stays there for a relative
long period of time. For this reason it is important to program the field “tur” in register
“condN” with the smallest possible value.
4.5.11.4 SRTS with ACM:
The combination of SRTS and ACM is used when the derived network clock of the SRTS
generator differs from the derived network clock of the SRTS receiver. The maximum
difference is relatively small (+/-4.6 ppm) and should be compensated by ACM. In this
case the shifting of the difference between ACM data and register “avbN”, as
programmed in register “asfN”, has to be reduced. Stable operation of PLL-ACM in
parallel with PLL-SRTS can not be guaranteed if the shifting is not reduced. The cut off
frequency of PLL-ACM has to be much lower than the cut off frequency of PLL-SRTS,
as these PLLs are working in parallel in this case. This will also reduce the effects of
CDV, because the cut off frequency of PLL-ACM is reduced. The tuning range (register
“condN”, field “tur”) can not be reduced as PLL-ACM has to compensate jitter which is
generated by or passed through PLL-SRTS.
Data Sheet
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2002-05-06
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Operational Description
4.6
Internal Queues
4.6.1
Event Queue
All the functional blocks that process octets or cells can generate counter events, i.e.
commands to increment a particular counter in the external RAM. All counter events are
written in a FIFO queue that can store 256 counter events.
A counter event contains the statistics counter address in external RAM and an
increment value.
4.6.2
Output Queue
When a cell is completely stored in the ATM Receive or Segmentation Buffer, it is ready
to be transmitted to the ATM layer over the UTOPIA receive interface. The external RAM
address of the cell is stored in a common Output Queue (OQ).
The Output Queue is a First In First Out (FIFO) queue with a maximum of 256 cell
address entries. It is common to ATM and AAL mode ports.
As long as the Output Queue is not empty, the Cell Receive processing (CR) will write
the corresponding cell from external RAM to the UTOPIA Receive interface (UR).
4.6.3
Interrupt Queue
The Interrupt Queue in external RAM is handled as a FIFO which is written whenever a
counter reaches its threshold value.
When there are interrupts in the Interrupt Queue, the “iq_ne” bit in the interrupt status
register 1 “isr1” will be set to 1. When the corresponding bit is not masked in the “imr1”
register an interrupt will be generated on the MPIR1 pin.
The microprocessor should react on the interrupt by reading the Interrupt Queue. When
“oam_act” is set to 1, the MPADR(12:1) address bits are don’t care. The next Interrupt
Queue entry will automatically be provided.
Each Interrupt Queue entry identifies a particular OAM counter that has reached its
threshold value. The counter is identified by its “port_nr”, “channel_nr” and “counter_nr”.
When the microprocessor reads the counter value and the “dest_read” bit of the register
oamc is set to 1, the counter is automatically reset.
Each Interrupt Queue entry also indicates whether there are still more interrupts in the
queue in the “iq_ne” field of the interrupt status register “isr1”. This allows the software
to read the Interrupt Queue until it is empty without having to read the interrupt status
register “isr1” again.
When the statistics function is disabled (oamc[oam_act] = 0), the µP can read and write
all addresses of the Interrupt Queue.
Data Sheet
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Operational Description
4.7
OAM Processing
The OAM processing block (OM) will read Statistics Counter events from the Event
Queue as long as the Event Queue is not empty. The OM will read the Statistics Counter
value “count_value” and the Statistics Counter threshold from external RAM. If the
Statistics Counter is not yet at its maximum value 4000 0000H, the value is increased
with the increment value given by the counter event. If the Statistics Counter threshold
is active (“thres_act” = 1) and the Statistics Counter equals or exceeds the threshold
value “thres_value”, the OM block will write an interrupt entry in the Interrupt Queue in
external RAM. The new Statistics Counter value with indication whether an interrupt was
generated in the “int_gen” field will finally be written into external RAM.
The “dest_read” bit determines whether a read operation from the microprocessor in the
Statistics Counter address space in external RAM causes a reset of the Statistics
Counter value.
The OM block can be disabled via bit “oam_act” in the OAM control register (“oamc”, see
Chapter 7.3).
In normal operation, counter event processing should be activated (oam_act = 1). In this
case the microprocessor can only read indirectly in the Interrupt Queue.
For RAM test and initialization, the “oam_act” should be set to 0. In this mode, the
microprocessor can write and read the complete external RAM.
The use of the Statistics Counter thresholds allows the software to reduce the number
of generated interrupts and to decide at what error level an interrupt should be
generated.
When the software wants to use polling mode, the thresholds can be made inactive, and
no interrupts will be generated. The software will read all the Statistics Counters on
regular time intervals in this mode.
A combination of both methods is also possible, all the Statistics Counters are read and
reset on regular time intervals. However thresholds can be used as an extra guard: a
Statistics Counter that reaches an exceptionally high value will cause an interrupt.
For a detailed list of all implemented Statistics Counters refer to Chapter 6.2.1. For
information how to translate Statistics Counters into the ATM Forum CES MIB as defined
in [10] refer to Chapter 8.2.
Data Sheet
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2002-05-06
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Operational Description
4.8
Loopback Modes
4.8.1
Upstream Loop
The Upstream Loop block (UL) allows cells that are received at the Framer Interface and
forwarded to the UTOPIA Receive Interface to be send back via the UTOPIA Transmit
Interface to the Transmitter Interface. The UL block contains a buffer of 4 ATM cells.
To activate the Upstream Loop, the “p_ulp” bit in the Port Configuration Register (pcfN,
see Chapter 7.1) must be set to 1.
When a cell is available in the UL buffer, the UTOPIA transmit interface will de-assert the
TXCLAV signal, to prevent the ATM layer component from sending cells during the
processing of the loopback cell.
For ATM mode ports, all cells are looped regardless of their header. The loop is always
transparent allowing looped cells to be visible on the UTOPIA receive interface.
For AAL mode ports, it is possible to make a single channel loop using a VCI filter. When
the “vci_flt_ulp” bit in the Loopback Control Register (lpbc, see Chapter 7.11) is set to 0
all cells are looped. When the bit is set to 1, only those cells with the 5 LSB bits of the
VCI matching the “vci_val_ulp” field of the “lpbc” register will be looped. Loopback can
be switched from transparent to non-transparent by setting the “tulp” bit in the “lpbc”
register. If the loopback is non-transparent, looped cells are not visible on the UTOPIA
receive interface.
4.8.2
Downstream Loop
It is possible to loop ATM cells that are coming in on the UTOPIA transmit interface to
the UTOPIA receive interface through the Downstream Loop (DL) block. The DL block
contains a buffer of 4 ATM cells.
When a cell is available in the DL buffer and in the Output Queue, the UTOPIA receive
interface will transmit cells from both buffers with alternating priority.
To activate the downstream UTOPIA loop, the “p_dlp” bit in the Port Configuration
Register (pcfN, see Chapter 7.1) must be set to 1.
When the downstream UTOPIA loopback is active for at least one port, the UTOPIA
transmit interface will only assert the RxCLAV signal to 1 when a free space of one ATM
cell is available in both the DL buffer and the UT input buffer.
The loopback can be made transparent or non-transparent by setting the “tdlp” bit in the
Loopback Control Register (lpbc, see Chapter 7.11). If the loopback is made nontransparent, the looped cells are not transferred to the “Cell Transmit Processing” block
CT.
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.8.3
Serial Loop
The framer transmit clock, data, framesync and multi-framesync signals can be looped
from the Framer Transmit Interface to the Framer Receive Interface per port. This
feature can be enabled by setting the “p_slp” bit in the Port Configuration Register (pcfN,
see Chapter 7.1).
The loopback can be made transparent or non-transparent by setting the “tslp” bit in the
Loopback Control Register (lpbc, Chapter 7.11). If the loopback is made transparent, all
transmitted data is also visible on FTDAT. Otherwise, if non-transparent, all 1s are
transmitted on FTDAT.
Data Sheet
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2002-05-06
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Operational Description
4.9
Cell Insertion
This block allows the insertion of predefined cells stored in the Cell Insertion Buffer into
the UTOPIA receive cell stream.
The Cell Insertion Buffer, located in external RAM, offers space for one ATM cell. The
ATM cell except of the UDF octet needs to be written to the Cell Insertion Buffer via the
Microprocessor interface. When transferring the cell to the UTOPIA receive interface an
UDF of 00H will be inserted.
Cell insertion is activated by setting the bit “insert_cell” in the Command Register (“cmd”,
see Chapter 7.31) the cell is then read from the Cell Insertion Buffer and forwarded to
the UTOPIA Receive Interface.
The port number is generated randomly. Depending on the UTOPIA mode selection, it
will be mapped either on the UTOPIA address bus or in the ATM header
(“mapping_mode” = 2, 3, 4 or 5 in register “utconf”) overwriting the predefined values.
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.10
Cell Extraction
Cells coming in downstream direction from the UTOPIA Transmit Interface can be
extracted to the Cell Extraction Buffer instead of the Reassembly/ATM Transmit Buffer.
The Cell Extraction Buffer offers space for 254 ATM cells. It is located in the external
RAM.
Incoming cells are written to the Extraction Buffer if
• their VCI matches to a pattern predefined in the Cell Filter VCI Pattern 1 Register
(cfvp1, see Chapter 7.26) where each bit of the VCI can be masked via the Cell Filter
VCI Mask Register 1 (cfvm1, Chapter 7.27)
• or their VCI matches to a pattern predefined in the Cell Filter VCI Pattern 2 Register
(cfvp2, see Chapter 7.28) where each bit of the VCI can be masked via the Cell Filter
VCI Mask Register 1 (cfvm1, Chapter 7.29)
• or their PTI matches to one of two pattern defined in the Cell Filter Payload Type
Register (“cfpt”, see Chapter 7.30) each of these patterns can also be masked via
“cfpt”.
Once a cell has been extracted to the cell Extraction Buffer, it is indicated by the bit
“cf_fifo_n_empty” in the Extended Interrupt Status Register (“eis1”, see Chapter 7.19).
Cells can be read with the help of the read pointer (“rdptr”) in the Cell Filter Read Pointer
Register (“cfrp”, Chapter 7.32). The rdptr can have values between 02H and FFH. This
value is a pointer to the current base-address, at which the microprocessor can read the
next extracted cell from the Extraction Buffer.
MPADR = 26000H + 20H · rdptr
[13]
RMADR = 03000H + 10H · rdptr
[14]
After reading the cell the rdptr has to be incremented by the microprocessor and written
back. If the rdptr is incremented to its maximum value FFH the value 02H has to be
written back instead.
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
4.11
Mapping of Channels to Timeslots
The two LSB bits of a slot entry identify the slot type:
Table 21
Coding of Slot Type in internal configuration RAMs
Slot Type
Bit 1
Bit 0
ATM/AAL Idle
0
0
ATM/AAL Continuation
1
0
ATM/AAL Reference
X
1
4.11.1
ATM Mode
The IWE8 supports any mapping scheme of ATM cells into N of the 32 timeslots of the
framer interfaces.
The mapping scheme is defined by programming 32 slot positions in the internal RAMs.
RAM1 is used for receive port configuration and RAM2 for transmit port configuration.
• For each configuration exactly one timeslot should be programmed as the “ATM
Reference Slot”.
• Depending on the Link data rate 29 (E1) or 23 (T1) timeslots should be programmed
as “ATM Continuation Slots”.
• The remaining unused slots should be programmed as “AAL Idle Slots”.
For mapping of ATM cells in T1/E1 frames according to ITU-T G.804 [26] the internal
RAM slot positions should be programmed as shown in Table 22.
Table 22
RAM
RAM slot positions for ITU-T G.804 compliant ATM mapping
E1
Slot Slot
RAM Slot Type
T1 in FAM
Slot
RAM Slot Type
T1 in GIM
Slot
RAM Slot Type
ATM Idle
1
ATM Continuation
0
0
ATM Idle
1
1
ATM Reference
1
ATM Reference
2
ATM Reference
2
2
ATM Continuation
2
ATM Continuation
3
ATM Continuation
3
3
ATM Continuation
3
ATM Continuation
4
ATM Continuation
4
4
ATM Continuation
ATM Idle
5
ATM Continuation
5
5
ATM Continuation
4
ATM Continuation
6
ATM Continuation
6
6
ATM Continuation
5
ATM Continuation
7
ATM Continuation
7
7
ATM Continuation
6
ATM Continuation
8
ATM Continuation
8
8
ATM Continuation
ATM Idle
9
ATM Continuation
9
9
ATM Continuation
ATM Continuation
10
ATM Continuation
Data Sheet
7
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Operational Description
Table 22
RAM
RAM slot positions for ITU-T G.804 compliant ATM mapping
E1
Slot Slot
T1 in FAM
T1 in GIM
RAM Slot Type
Slot
RAM Slot Type
Slot
RAM Slot Type
10
10
ATM Continuation
8
ATM Continuation
11
ATM Continuation
11
11
ATM Continuation
9
ATM Continuation
12
ATM Continuation
12
12
ATM Continuation
ATM Idle
13
ATM Continuation
13
13
ATM Continuation
10
ATM Continuation
14
ATM Continuation
14
14
ATM Continuation
11
ATM Continuation
15
ATM Continuation
15
15
ATM Continuation
12
ATM Continuation
16
ATM Continuation
16
16
ATM Idle
ATM Idle
17
ATM Continuation
17
17
ATM Continuation
13
ATM Continuation
18
ATM Continuation
18
18
ATM Continuation
14
ATM Continuation
19
ATM Continuation
19
19
ATM Continuation
15
ATM Continuation
20
ATM Continuation
20
20
ATM Continuation
ATM Idle
21
ATM Continuation
21
21
ATM Continuation
16
ATM Continuation
22
ATM Continuation
22
22
ATM Continuation
17
ATM Continuation
23
ATM Continuation
23
23
ATM Continuation
18
ATM Continuation
24
ATM Continuation
24
24
ATM Continuation
25
25
ATM Continuation
26
26
27
ATM Idle
ATM Idle
19
ATM Continuation
ATM Idle
ATM Continuation
20
ATM Continuation
ATM Idle
27
ATM Continuation
21
ATM Continuation
ATM Idle
28
28
ATM Continuation
ATM Idle
ATM Idle
29
29
ATM Continuation
22
ATM Continuation
ATM Idle
30
30
ATM Continuation
23
ATM Continuation
ATM Idle
31
31
ATM Continuation
24
ATM Continuation
ATM Idle
However, it is possible to define other ATM cell mappings, e.g. ATM cells in less than 32
64 kbit/s channels. However, RAM slot 1 has always to be defined as Reference Slot.
4.11.2
AAL Mode
4.11.2.1 Unstructured CES
For unstructured CES according to ATM-Forums CES Specification [10] there is only
one channel per port. Therefore, the internal configuration RAMs 1 to 3 have only to be
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
programmed with one Reference Slot at RAM slot 0. This slot number is used to identify
the channel (“channel_nr” = 0).
4.11.2.2 Structured CES
For AAL ports with structured CES (Nx64 kbit/s) service, the timeslots are grouped into
channels containing N of 32 timeslots. The mapping of the N x 64 kbit/s channels into an
T1/E1 frame is done by programming the 32 positions of the internal configuration RAMs
(RAM1 for receive ports, RAM2 and RAM3 for transmit ports).
It is possible to define more than one channel of N timeslots within one frame. In this
case each channel has its own reference slot, followed by N-1 continuation slots.
Additional unused frame slots that do not belong to any channel should be programmed
as “AAL Idle Slot”.
The timeslot in the group of N timeslots with the lowest frame slot number is called the
reference slot. The corresponding frame slot position in the internal RAM should be
programmed as an “AAL Reference Slot”. The slot number of the AAL Reference Slot is
used to identify the channel (“channel_nr”).
The other frame slot positions of the channel should be programmed as “AAL
Continuation Slots”. The reference slot number, as defined by the “ref_slot_nr” field
entry, is used to identify the channel the continuation slot belongs to. The N timeslots of
a channel do not need to have consecutive frame slot numbers. They can be deliberately
chosen out of the 32 frame slots.
Table 23
AAL Idle slot positions for structured CES in AAL mode
Slot number
E1
T1 in FAM
T1 in GIM
0
AAL Idle
AAL Idle
AAL Ref./Cont./Idle
1
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
2
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
3
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
4
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
5
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
6
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
7
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
8
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
9
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
10
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
11
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
12
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
Data Sheet
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Operational Description
Table 23
AAL Idle slot positions for structured CES in AAL mode
Slot number
E1
T1 in FAM
T1 in GIM
13
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
14
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
15
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
16
AAL Idle
AAL Idle
AAL Ref./Cont./Idle
17
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
18
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
19
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
20
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
21
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
22
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
23
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
24
AAL Ref./Cont./Idle
AAL Idle
AAL Idle
25
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
26
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
27
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
28
AAL Ref./Cont./Idle
AAL Idle
AAL Idle
29
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
30
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
31
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
The channel mapping can be dynamically reconfigured without disturbing other active
channels of the same port.
4.11.2.3 Structured CES with CAS
If a port is used for structured CES with CAS, additional signalling is inserted into the
channel overhead. The associated RAM slots, 0 in T1 mode and RAM slots 0 and 16 in
E1 mode, need to be configured as reference slots with “sdt_mfs” = 1.
Please note, that all settings of the AAL Reference Slot refer to the channel payload.
Therefore, in case of T1 mode in FAM or E1 mode the channel has to be set to inactive
(“channel_mode” = 0) with no bandwidth assigned (“band_width” = 0).
In T1 mode in GIM things are different. RAM slot 0 may also be used for user data, with
“channel_mode” and “band_width” set according to the requirements of the user data
carried via that slot.
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
Table 24
AAL Idle slot positions for structured CES with CAS in AAL mode
Slot number
E1
T1 in FAM
0
AAL Reference
“channel_mode” = 0
“band_width” = 0
“sdt_mfs” = 1
AAL Reference
AAL Reference
“channel_mode” = 0 “sdt_mfs” = 1
“band_width” = 0
“sdt_mfs” = 1
1
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
2
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
3
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
4
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
5
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
6
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
7
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
8
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
9
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
10
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
11
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
12
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
13
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
14
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
15
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
16
AAL Reference
AAL Idle
“channel_mode” = 0
“band_width” = 0
AAL Ref./Cont./Idle
17
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
18
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
19
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
20
AAL Ref./Cont./Idle
AAL Idle
AAL Ref./Cont./Idle
21
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
22
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
23
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
24
AAL Ref./Cont./Idle
AAL Idle
AAL Idle
25
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
Data Sheet
91
T1 in GIM
2002-05-06
PXB4219 / PXB4220 / PXB4221
Operational Description
Table 24
AAL Idle slot positions for structured CES with CAS in AAL mode
Slot number
E1
T1 in FAM
T1 in GIM
26
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
27
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
28
AAL Ref./Cont./Idle
AAL Idle
AAL Idle
29
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
30
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
31
AAL Ref./Cont./Idle
AAL Ref./Cont./Idle
AAL Idle
Data Sheet
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Interface Description
5
Interface Description
5.1
Generic Framer Interface
The selection of the Echo Canceller mode is done via an external pin (Pin EC = 0).
In standard mode (Pin EC = 1), 4 sub modes can be selected via the “om” bits in the
Operation Mode Register (“opmo”, see Chapter 7.24)
•
•
•
•
FALC mode (FAM)
Generic Interface mode (GIM)
Synchronous mode with an external reference clock of 8 MHz (SYM8)
Synchronous mode with an external reference clock of 2 MHz (SYM2)
Depending on the level of the E1/T1 pin FAM and GIM can run based on E1 or T1
frames. SYM2 and SYM8 will always use E1 frame formats.
A clock selector for the Framer transmit clock is integrated in the IWE8. Depending on
bits “ftckn” in the FT Clock Select Register (“ftcs”, see Chapter 7.25) selection between
the following clocks is done:
• the line clock FRCLK
• the SRTS regenerated clock from internal or external clock recovery circuit
• the clock derived from the external reference clock (pin RFCLK).
The data on the Generic Framer Interface is structured in frames repeated every 125µs.
Each frame is divided into timeslots, where the least sigificant slot is transmitted first. The
data bits in each slot are transmitted starting with the most significant bit.
5.1.1
FALC Mode (FAM)
The IWE8 can be directly connected to Infineon’s “Framer and Line interface
components” (FALC) as shown in Figure 22.
QuadFALCTM
Figure 22
Data Sheet
IWE8
SCLKR
RDO
SYPR
RMFB
FREEZE
FRCLKn
FRDATn
FRFRSn
FRMFBn
FRLOSn
XMFS
SYPX
XDI
SCLKX
FTMFSn
FTFRSn
FTDATn
FTCKOn
Connection of IWE8 to QuadFALC
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Interface Description
The data is transferred between the FALC and the IWE8 via a system internal highway.
FRCLK[0:7]
Framer Receive Clock
Receive system clock of 8.192 MHz (falling)
FRDAT[0:7]
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of FRCLK
FRMFB[0:7]
Framer Receive Multiframe Begin
Depending on bits “p_ces” in “pcfN”:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused
FRMFB is always sampled with the falling edge of FRCLK.
FRFRS[0:7]
Framer Receive Frame Synchronization Pulse
FRFRS is generated at the beginning of timslot0 of each frame
FRLOS[0:7]
Framer Receive Loss of Signalling
FTCKO[0:7]
Framer Transmit Clock
depending on bits ftckn in ftcs:
00 =
depending on bit “rts_eval” in “opmo”:
0 = Transmit clock input with 8.192 MHz (falling)
1 = Clock of ICRC is used as transmit clock and is
also switched to FTCKO pins (FTCKO is output
pin)
01 =
FRCLK
10 =
Clock derived from RFCLK
11 =
No clock
FTDAT[0:7]
Framer Transmit Data
FTDAT is clocked with the falling edge of FTCKO:
FTMFS[0:7]
Framer Transmit Multiframe Synchronization
Depending on bit p_ces in pcfN:
Data Sheet
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Double frame mode: FTMFS is asserted every
2 frames (250 µs)
1 = CRC multiframe mode: FTMFS is asserted
every 16 frames (2 ms)
1=
Unstructured CES: Unused, constant low level
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Interface Description
FTFRS[0:7]
Framer Transmit Frame Synchronization Pulse
FTFRS is generated at the beginning of timslot0 of every frame
RFCLK
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
The receive system clock and transmit system clock are both 8.192 MHz, and may be
independent from each other. The datarate is 2048 Mbit/s. This means that each bit lasts
for 4 clock cycles.
Data on the system internal highway is structured in frames of 256 bits every 125 µs. It
is transmitted in 32 slots numbered from 0 to 31 with slot 0 transmitted first. The data bits
of a slot are numbered from 1 to 8. The first transmitted bit ‘bit 1’ is the most significant
bit. Figure 23 shows the bit ordering.
Framer Receive Interface:
FRCLKn
FRDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FRMFBn
FRFRSn
timeslot 31
timeslot 0
timeslot 1
Framer Transmit Interface:
FTCKOn
FTDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FTMFSn
FTFRSn
timeslot 31
Figure 23
5.1.1.1
timeslot 0
timeslot 1
Framer Interface in FAM
T1 Mode
In T1 mode (Pin E1/T1 = 0) there is one F-channel carrying the F-bit (Frame Alignement
Signal/Data Link (FS/DL)) and 24 data channels numbered from 0 to 23. When using the
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
QuadFALC in translation mode 0 (See QuadFALC datasheet) these channels are
mapped into the 32 frame slots as shown in Table 25
.
Table 25
Time slot Mapping in T1 Translation Mode 0
Frame slot
T1 channel
Frame slot
0
F channel (FS/DL)
16
1
channel 1
17
channel 13
2
channel 2
18
channel 14
3
channel 3
19
channel 15
4
T1 channel
20
5
channel 4
21
channel 16
6
channel 5
22
channel 17
7
channel 6
23
channel 18
8
24
9
channel 7
25
channel 19
10
channel 8
26
channel 20
11
channel 9
27
channel 21
12
28
13
channel 10
29
channel 22
14
channel 11
30
channel 23
15
channel 12
31
channel 24
The F-channel only contains the F-bit. Its location in the F channel is shown in Table 26.
Table 26
F-Channel Format in T1 Mode
MSB
bit 1
F channel
bit 2
bit 3
bit 4
LSB
bit 5
bit 6
bit 7
bit 8
F-bit
5.1.1.2
E1 Mode
In E1 mode (Pin E1/T1 = 1) there are 32 channels numbered from 0 to 31. The channels
are directly mapped into the corresponding 32 frame slots.
Data Sheet
96
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.1.2
Generic Interface Mode (GIM)
The Generic Interface Mode (GIM) makes the framer interface more universal, so that
other framer/ line interface units or T1/E1 transceivers can be connected directly to the
IWE8. Depending on the E1/T1 pin, the interface can be adopted to line bit rates of 1.544
MHz (T1 rate) or 2.048 MHz (E1 rate). The mode is enabled by setting bit om = 01B in
“opmo”, see Chapter 7.24. Make sure that no clocks are applied to the transmitter when
switching to GIM.
5.1.2.1
T1 Mode
FRCLK[0:7]
Framer Receive Clock
Receive clock input at 1.544 MHz
FRDAT[0:7]
Framer Receive Data
depending on bit “frri” in “opmo”:
FRMFB[0:7]
0=
FRDAT is sampled with the falling edge of FRCLK
1=
FRDAT is sampled with the rising edge of FRCLK
Framer Receive Multiframe Begin
Depending on bits p_ces in pcfN:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused, no constant level
allowed
Depending on bit “rfpp” in “opmo”:
0=
FRMFB is active low
1=
FRMFB is active high
FRMFB is always sampled with the falling edge of FRCLK.
FRFRS[0:7]
Framer Receive Frame Synchronization Pulse
Permanently inactive
FRLOS[0:7]
Framer Receive Loss of Signalling
FTCKO[0:7]
Framer Transmit Clock
depending on bits ftckn in ftcs:
Data Sheet
00 =
depending on bit “rts_eval” in “opmo”:
0 = Transmit clock input with 1.544 MHz
1 = Clock of ICRC is used as transmit clock and is
also switched to FTCKO pins (FTCKO is output
pin)
01 =
FRCLK
97
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
FTDAT[0:7]
FTMFS[0:7]
10 =
Clock derived from RFCLK
11 =
No clock
Framer Transmit Data
depending on bit “ftri” in “opmo”:
0=
FTDAT is clocked with the falling edge of FTCKO
1=
FTDAT is clocked with the rising edge of FTCKO
Framer Transmit Multiframe Synchronization
Depending on bit p_ces in pcfN:
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Superframe frame mode: FTMFS is asserted
every 12 frames (1.5 ms)
1 = Extended superframe mode: FTMFS is
asserted every 24 frames (3 ms)
1=
Unstructured CES: Inactive level
Depending on bit “tfpp” in “opmo”:
0=
FTMFS is active low
1=
FTMFS is active high
FTFRS[0:7]
Framer Transmit Frame Synchronization Pulse
FTFRS is asserted synchronously to the transmission of the F-bit
of each frame.
RFCLK
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
Data Sheet
98
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
Framer Receive Interface:
FRCLKn
FRDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
184
185
186
187
188
189
190
191
192
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FRMFBn
timeslot 23
timeslot 0
timeslot 1
Framer Transmit Interface:
FTCKOn
FTDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
184
185
186
187
188
189
190
191
192
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FTMFSn
FTFRSn
timeslot 23
Figure 24
Data Sheet
timeslot 0
timeslot 1
Framer Interface in GIM T1
99
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.1.2.2
E1 Mode
FRCLK[0:7]
Framer Receive Clock
Receive clock input with 2.048 MHz
FRDAT[0:7]
Framer Receive Data
depending on bit “frri” in “opmo”
FRMFB[0:7]
0=
FRDAT is sampled with the falling edge of FRCLK
1=
FRDAT is sampled with the rising edge of FRCLK
Framer Receive Multiframe Begin
Depending on bits p_ces in pcfN:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused, no constant level
allowed
depending on bit “rfpp” in “opmo”:
0=
FRMFB is active low
1=
FRMFB is active high
FRMFB is always sampled with the falling edge of FRCLK.
FRFRS[0:7]
Framer Receive Frame Synchronization Pulse
Permanently inactive
FRLOS[0:7]
Framer Receive Loss of Signalling
FTCKO[0:7]
Framer Transmit Clock
depending on bits ftckn in ftcs:
FTDAT[0:7]
FTMFS[0:7]
Data Sheet
00 =
depending on bit “rts_eval” in “opmo”:
0 = Transmit clock input with 2.048 MHz
1 = Clock of ICRC is used as transmit clock and is
also switched to FTCKO pins (FTCKO is output
pin)
01 =
FRCLK
10 =
Clock derived from RFCLK
11 =
No clock
Framer Transmit Data
depending on bit “ftri” in “opmo”:
0=
FTDAT is clocked with the falling edge of FTCKO
1=
FTDAT is clocked with the rising edge of FTCKO
Framer Transmit Multiframe Synchronization
100
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
Depending on bit p_ces in pcfN:
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Double frame mode: FTMFS is asserted every
2 frames (250 µs)
1 = CRC multiframe mode: FTMFS is asserted
every 16 frames (2 ms))
1=
Unstructured CES: Inactive level
Depending on bit “tfpp” in “opmo”:
0=
FTMFS is active low
1=
FTMFS is active high
FTFRS[0:7]
Framer Transmit Frame Synchronization Pulse
FTFRS is asserted synchronously to the transmission of the first
bit of the first timeslot of each frame.
RFCLK
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
Framer Receive Interface:
FRCLKn
FRDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FRMFBn
timeslot 31
timeslot 0
timeslot 1
Framer Transmit Interface:
FTCKOn
FTDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FTMFSn
FTFRSn
timeslot 31
Figure 25
Data Sheet
timeslot 0
timeslot 1
Framer Interface in GIM E1
101
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.1.3
Synchronous Modes (SYM)
In these modes, transmit and receive channels are synchronized. Therefore, they may
be used for synchronization of frame and multiframe based protocols, e.g. Frame based
SDT on E1-Lines.
Only one central clock, the external reference clock RFCLK, is used to clock the data on
the different ports. Two synchronous modes working at 2.048 MHz and 8.192 MHz for
E1lines are available. T1 is not supported.
For each of these modes a submode exists, providing global or port specific
synchronization.
If global synchronization of all transmit and receive channels is desired, bit “symn” in
“opmo” has to be deasserted. In this case FRMFB[0] is used for frame and multiframe
synchronization in receive and transmit direction of all ports.
Port specific frame and multiframe synchronization of transmit and receive channels is
enabled if bit “symn” in “opmo” is set. In this case frame and multiframe synchronization
in receive and transmit direction of each port is based on the corresponding FRMFB.
After reset all outputs and inout ports of the framer interface are tristated. They will be
enabled by setting bit “p_tx_act” of the corresponding “Port Configuration Register”
(“pcfN”, see Chapter 7.1).
5.1.3.1
Synchronous Mode at 2.048 MHz (SYM2)
In SYM2 mode the framer interface is clocked with a 2.048 MHz clock connected to
RFCLK. The mode is enabled by setting bit om = 11B in “opmo”, see Chapter 7.24
All transmit and receive timeslots will be aligned to each other.
FRCLK[0:7]
Framer Receive Clock
Unused
FRDAT[0:7]
Framer Receive Data
depending on bit “frri” in “opmo”
FRMFB[0:7]
0=
FRDAT is sampled with the falling edge of RFCLK
1=
FRDAT is sampled with the rising edge of RFCLK
Framer Receive Multiframe Begin
Depending on bits p_ces in pcfN:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused, no constant level
allowed
depending on bit “rfpp” in “opmo”:
Data Sheet
102
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
0=
FRMFB is active low
1=
FRMFB is active high
depending on bit “symn” in “opmo”:
0=
FRMFB[0] is used for frame and multiframe
synchronization in receive and transmit direction of
all ports. FRMFB[1:7] are unused
1=
FRMFB[N] is used for frame and multiframe
synchronization in receive and transmit direction of
corresponding ports
FRMFB is always sampled with the opposite clock-edge of
FRDAT.
FRFRS[0:7]
Framer Receive Frame Synchronization Pulse
Unused
FRLOS[0:7]
Framer Receive Loss of Signalling
FTCKO[0:7]
Framer Transmit Clock
Unused
FTDAT[0:7]
Framer Transmit Data
depending on bit “frri” in “opmo”:
0=
FTDAT is clocked with the rising edge of RFCLK
1=
FTDAT is clocked with the falling edge of RFCLK
FTMFS[0:7]
Framer Transmit Multiframe Synchronization
Unused
FTFRS[0:7]
Framer Transmit Frame Synchronization Pulse
Unused
RFCLK
Reference Clock
Central framer interface clock with 2.048 MHz
RFCLK
FRDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FRMFB
FTDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
timeslot 31
4
5
timeslot 0
6
7
8
9
10
11
12
13
14
15
16
timeslot 1
FRDATn sampled with rising edge of RFCLK
Figure 26
Framer Interface in SYM2 E1
Data Sheet
103
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.1.3.2
Synchronous Mode at 8.192 MHz (SYM8)
In SYM8 mode the framer interface is clocked with an 8.192 MHz clock connected to
RFCLK. The mode is enabled by setting bit om = 10B in “opmo”, see Chapter 7.24
All timeslots (transmit and receive) will be aligned to each other.
FRCLK[0:7]
Framer Receive Clock
Unused
FRDAT[0:7]
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of RFCLK
FRMFB[0:7]
Framer Receive Multiframe Begin
Depending on bits p_ces in pcfN:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused
depending on bit “rfpp” in “opmo”:
0=
FRMFB is active low
1=
FRMFB is active high
depending on bit “symn” in “opmo”:
0=
FRMFB[0] is used for frame and multiframe
synchronization in receive and transmit direction of
all ports. FRMFB[1:7] are unused
1=
FRMFB[N] is used for frame and multiframe
synchronization in receive and transmit direction of
corresponding ports
FRMFB is always sampled with the opposite clock-edge of
FRDAT.
FRFRS[0:7]
Framer Receive Frame Synchronization Pulse
Unused
FRLOS[0:7]
Framer Receive Loss of Signalling
FTCKO[0:7]
Framer Transmit Clock
Unused
FTDAT[0:7]
Framer Transmit Data
FTDAT is clocked with the falling edge of RFCLK:
FTMFS[0:7]
Framer Transmit Multiframe Synchronization
Unused
Data Sheet
104
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
FTFRS[0:7]
Framer Transmit Frame Synchronization Pulse
Unused
RFCLK
Reference Clock
Central framer interface clock with 8.192 MHz
RFCLK
FRDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FRMFB
FTDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
timeslot 31
Figure 27
5.1.4
4
5
6
7
8
9
10
11
timeslot 0
12
13
14
15
16
timeslot 1
Framer Interface in SYM8 E1
Echo Canceller Mode (EC)
In this mode (pin EC = 0) transmit and receive channels are synchronized.
The framer interface is clocked with an 8.192 MHz clock connected to RFCLK.
All receive channels and the channels transmitted on even ports (near-end signal with
echo) are synchronized by means of the FTFRS[0] pin. Shift exists between odd and
even FTDAT ports
FRCLK[0:7]
Framer Receive Clock
Unused
FRDAT[0:7]
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of RFCLK
FRMFB[0:7]
Framer Receive Multiframe Begin
Unused
FRFRS[0:7]
Framer Receive Frame Synchronization Pulse
Unused
FRLOS[0:7]
Framer Receive Loss of Signalling
FTCKO[0:7]
Framer Transmit Clock
Unused
FTDAT[0:7]
Framer Transmit Data
FTDAT is clocked with the falling edge of RFCLK:
Data Sheet
105
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
FTMFS[0:7]
Framer Transmit Multiframe Synchronization
Unused
FTFRS[0:7]
Framer Transmit Frame Synchronization Pulse
FTFRS[0] is asserted synchronously to the transmission of the
first bit of the first timeslot of each frame. FTFRS[1:7] are unused
RFCLK
Reference Clock
Central framer interface clock with 8.192 MHz
RFCLK
FRDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FTFRS0
FTDATn
even ports
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248
249
250
251
252
253
254
255
256
1
2
3
4
timeslot 31
FTDATn
odd ports
5
6
7
8
9
10
11
12
timeslot 0
13
14
15
16
timeslot 1
B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2
251
252
253
254
timeslot 31
255
256
1
2
3
4
5
timeslot 0
Figure 28
Framer Interface in EC Mode
Data Sheet
106
6
7
8
9
10
11
12
13
14
15
16
249
250
timeslot 1
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.2
UTOPIA Interface
IWE8
Figure 29
RXADR[0-4]
RXDAT[0-7]
RXPTY
RXSOC
RXCLAV
RXENB
RXCLK
UTOPIA
Receive
Interface
(Level 2)
TXADR[0-4]
TXDAT[0-7]
TXPTY
TXSOC
TXCLAV
TXENB
TXCLK
UTOPIA
Transmit
Interface
(Level 2)
UTOPIA Receive and Transmit Interfaces in Slave Mode
The UTOPIA receive and transmit interfaces are implemented according to the ATM
forum UTOPIA Level 2 Specification [6] and to the UTOPIA Level 1 Specification [5] .
For UTOPIA level 2 compliant mode, the device is compatible to a PHY layer with 8 data
lines and 5 address lines.
In UTOPIA level 1 compliant mode the interface can be configured to ATM and PHY
layer with 8 data lines. In this case the address lines should be left unconnected.
According to the UTOPIA standard the ATM-Layer polls the PHY-Ports via the UTOPIA
address lines. If the address matches the programmed address range, the PHY controls
the flow of data via the TXCLAV or RXCLAV signal.
In transmit direction the PHY indicates via assertion of TXCLAV whether the
corresponding port is capable of accepting data. In case data can not be transferred to
the addressed port due to overrun of the programmed threshold of the port-specific cell
buffer, the TXCLAV won’t be activated.
In receive direction, RXCLAV is activated, if data is available at the addressed port.
Depending on the value of the “utmaster” bit in the “UTOPIA Configuration Register”
(“utconf”, see Chapter 7.34) the IWE8 will either act as an ATM -Layer (master mode)
or PHY-Layer (slave mode). As an ATM-Layer, the IWE8 can only work in UTOPIA level
1 compliant mode. As PHY Layer, IWE8 supports both, single PHY in UTOPIA level 1
compliant mode and single/multi PHY in UTOPIA level 2 compliant mode. The selection
between UTOPIA level 1 and level 2 can be done via the “utlevel” bit in “utconf”.
5.2.1
Port Addresses
The device can implement up to 8 PHY-Ports (= framer ports).
Data Sheet
107
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
In case it is configured for UTOPIA level 2 MPHY mode, the amount of implemented PHY
ports can be selected via the associated address range (“utconf[utrange]” with
utconf[mapping_mode] = 0).
In addition, the transmission of the UTOPIA port number via a user-defined field in the
ATM header enables multi PHY operation even in UTOPIA level 1 mode and UTOPIA
level 2 single PHY mode as described in Chapter 5.2.3.
In UTOPIA level 2 MPHY mode no port number mapping into the ATM header is done.
However, using this feature in UTOPIA level 2 mode, will give access to all PHY ports
while the UTOPIA interface block is running in single PHY mode. For UTOPIA level 2
compliant multi PHY operation, “mapping_mode” should be reset. In this case the UDF
field is set to all zero.
In UTOPIA level 2 MPHY mode the port number is transported via the address pins.
“utbaseadr” in “utconf” defines the base address under which the ports will be
accessible. In UTOPIA level 1 mode, “utbaseadr” has to be set to "0" otherwise cells are
discarded.
If the device is in single PHY mode, it will react on the address, written into “utbaseadr”.
In multi PHY mode, the device will be accessible inside a window from “utbaseadr” to
“utbaseadr” + “utrange”. Where the nth port can be accessed at “utbaseadr” + n.
5.2.2
Back Pressure/ATM Cell Discarding
Backpressure describes the mechanism that controls the TXCLAV signal in UTOPIA
PHY mode. IWE8 supports two kinds of backpressure mechanisms, a general and a port
specific one.
Cells that are destined to inactive ports or channels are generally discarded.
5.2.2.1
General Backpressure Mechanism
The general backpressure mechanism depends only on the filling level of the 4 cell
UTOPIA input buffer.
General backpressure is active in all UTOPIA configurations:
• UTOPIA level 1compliant mode (utlevel=1)
• UTOPIA level 2 PHY mode, where the selection between ports is done by ATM
header fields (mapping_mode!=0)
• UTOPIA level 2 PHY mode, with port selection by ATM header fields disabled
(mapping_mode=0) and the port threshold mode (“p_thr_m” bits in “pcfN”) disabled.
The general threshold is defined in the “Threshold Register” (“thrshld”, see
Chapter 7.33).
Data Sheet
108
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.2.2.2
Port Specific Backpressure Mechanism
In addition to the general backpressure mechanism, port specific backpressure is
available for ATM ports, when using the IWE8 as a UTOPIA level 2 PHY device
(“utconf[utlevel]” =0, “utmaster” = 0, “mapping_mode” =0 and “pcfN[p_atm]” =1). It needs
to be explicitly enabled with the “p_thr_m” bits in the “Port Configuration Registers”
(“pcfN”, see Chapter 7.1).
Whenever the port transmit buffer filling level falls below the programmed value and the
port is selected via the UTOPIA PHY address, the TXCLAV signal is activated, allowing
another data transfer for that port. If this transfer exceeds the predefined buffer filling
level, the UTOPIA interface immediately enters backpressure state for this port.
When using the port specific backpressure mechanism (“p_thr_m” = 01B or 10B) the
general threshold defined in the “Threshold Register” (“thrshld”, see Chapter 7.33)
should be higher than the port specific threshold defined in the “Threshold Port Register”
(“thrspN”, see Chapter 7.38 to Chapter 7.41).
5.2.3
Sideband Signals of the UTOPIA Interface
In UTOPIA level 1 mode or UTOPIA level 2 single PHY mode, the framer port number
("port_nr[2:0]") can be transmitted via the UTOPIA interface. The field contains the
number of the physical (framer) port associated with that ATM cell. Its location inside the
ATM header is configurable via the “mapping_mode” bits in “utconf” (Chapter 7.34).
Possible locations are: GFC[3:1], VPI[7:5], VCI[15:13], VCI[7:5] or UDF[2:0].
In AAL mode, the channel number ("channel_nr", first timeslot number of a channel,
reference timeslot) has to be transmitted on the UTOPIA transmit interface via VCI[4:0].
If no discarding of cells with uncorrectable HEC error is selected on a specific port via
bits “a_hec_mode” in the register “acfg” (Chapter 7.2) and "p_cell_disc" in the register
"pcfN" (Chapter 7.1) an HEC error flag (HEF) indicates corrupted HEC by setting the
most significant bit in the user defined octet at the UTOPIA interface.
The bit ENB, bit 5 of the user defined octet, is responsible for the decision if cell
discarding shall base on CLP or CLPI.
Data Sheet
109
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
MSB
LSB
port_nr[2:0]
GFC[3:1] / VPI[11:9]
port_nr[2:0]
VPI[7:5]
VPI[4]
VPI[3:0]
port_nr[2:0]
VCI 15..13
VCI[12]
VCI[11:8]
port_nr[2:0]
VCI[7:5]
channel_nr[3:0]
VCI[3:0]
PTI
HEF CLPI ENB
UDF[7] UDF[6] UDF[5]
Figure 30
Data Sheet
GFC[0]
/ VPI[8]
channel_
nr[4]
Header octet 2
Header octet 3
VCI[4]
CLP
port_nr[2:0]
UDF[2:0]
UDF[4:3]
Header octet 1
Header octet 4
User Defined Field
Utopia Sideband Signals
110
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.3
IMA Interface
The IWE8 has provisions to support the Inverse Multiplexing over ATM (IMA) protocol
implemented in an external component. These are:
• An IMA interface
• A programmable threshold between read and write pointer of the mapping buffer.
If an Uncorrectable HEC Error (UNCHEC) is detected, the cell is discarded and the
UNCHEC signal will be asserted. At the same time the port number, where the cell came
from, will be available at pins PN[0:2].
The ATM Transmit Buffer Threshold Crossing (ATBTC) signal becomes active when the
difference between write and read pointer of the ATM Transmit Buffer becomes smaller
than the threshold selected with bits “bufthr” in the “Operation Mode Register” (“opmo”,
see Chapter 7.24). At the same time the Port Number, where the cell came from, will be
available at pins PN[0:2].
At the IMA interface the IWE8 operates in cycles of 12 system clocks. ATBTC can
become active during cycle #3, the UNCHEC can become active during cycle #9. The
Port number is always active for 6 cycles.
0
1
2
3
4
5
6
7
8
9
10
11
CLOCK
ATBTC
UNCHEC
PN0..2
Figure 31
IMA Interface Protocol
For more detailed information on the IMA interface refer to the Application Hint “Inverse
Multiplexing for ATM (IMA) with the Interworking Element IWE8”.
Data Sheet
111
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.4
Clock Recovery Interface
It is possible to use an external device for clock recovery instead of the ICRC. Therefore
an external clock recovery interface is provided.
It allows the transmission and reception of serial communication frames containing
SRTS values or ACM buffer filling levels to and from an external clock recovery circuit.
The usage is controlled by the bits “rtsgen” and “rts_eval” in the Operation Mode
Register (“opmo”, see Chapter 7.24).
The Clock Recovery Interface is a 5 line serial interface: 1 data input SDI, 2 data outputs
SDOD and SDOR and 1 synchronization output SSP. The interface allows connection to
external clock recovery circuits. Two methods for clock recovery are supported:
Synchronous Residual Time Stamp (SRTS) and Adaptive Clock Method (ACM). The
IWE8 also allows a combination of SRTS and ACM.
The data sent over the serial lines is always formatted in frames of 32 bits.
The SSP pulse indicates the frame start for both directions. The inter-frame delay should
be equivalent to the payload of 8 ATM cells (e.g. for completely filled cells without SDT
every 3008 clock periods). Each valid frame is supposed to contain a valid RTS value
Table 27 shows the interface frame format. Bit [31] is sent first. When no data is to be
sent, idle frames are transmitted consisting of bits [31:1] all 1 and parity bit[ 0] = 0.
Table 27 also indicates which data fields are used on the different interface signals.
Table 27
Clock Recovery Interface frame format
Bits
Data field
SDI
SDOD
SDOR
31- 29
111
Yes
Yes
Yes
28 - 25
RTS[3:0]
Yes
Yes
No
24 - 11
buffer_fill[13:0]
No
Yes
No
10
RTS_valid
No
Yes
No
9-8
00
Yes
Yes
Yes
7-5
port_nr[2:0]
Yes
Yes
Yes
4-2
type[2:0]
001: RTS only
010: “buffer_fill” only
011: RTS + “buffer_fill”
111: reset RTS logic
others: not used
No
No
No
No
Yes
Yes
Yes
No
No
No
No
Yes
1
frame_invalid
Yes
Yes
Yes
0
odd_parity
Yes
Yes
Yes
Data Sheet
112
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
To allow the external SRTS generation logic to synchronize with the cell segmentation
process, the IWE8 will output a frame with type = 111 on the SDOR signal when the
segmentation of the first ATM cell for a selected channel starts. The first two sequences
of 8 ATM cells will contain a dummy RTS value which is programmable in the “ASIC
Configuration Register” (“acfg”, see Chapter 7.2). From the third sequence on the
values received on the SDI input will be used.
The IWE8 has internal ‘RTS Buffers’ for 2 RTS values per port. When one of the ‘RTS
Buffers’ overflows, the value in excess will be omitted and a bit in the Extended Interrupt
Status Register 2 (eis2, see Chapter 7.20) will be set. When ‘RTS Buffer’ underflow
occurs, the last received RTS value will be repeated in the next sequence of 8 ATM cells.
The RTS value extracted from a cycle of 8 ATM cells with sequence count 0 to 7, is
transmitted on SDOD when the cell with sequence count 1 from the next cycle is
received. The ‘RTS_valid’ field is used to indicate whether the extracted RTS value is
correct or not. An extracted RTS is accepted as valid if in the previous cycle of 8 cells
the cells with SN = 1, 3, 5 and 7 were present and were accepted as valid cells.
The buffer filling level is transmitted for use with the Adaptive Clock Method (ACM) and
is expressed as a number of octets contained in the ‘Reassembly Buffer’. The buffer
filling level is transmitted every time when a new ATM cell for the selected channel is
received.
Data Sheet
113
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.5
Microprocessor Interface
IWE8 contains internal registers, 4 internal RAMs and an external RAM that can be read
and written via the Microprocessor Interface.
As access to the internal registers is 16-bit oriented, the Microprocessor Address Bus
(MPADR) is designed for 16-bit boundaries. Access to the 32-bit-wide internal or
external RAM has to be executed in two consecutive 16 bit cycles.
The Microprocessor data bus (MPDAT) has “little endian” word order. Little to big endian
conversion may be implemented either by initialization of the Microcontroller or by
hardwiring MPDAT[0:7] to DATA[8:15] and MPDAT[8:15] to DATA[0:7] respectively,
The 32 bit oriented accesses have to be done by two consecutive 16 bit accesses, the
first with MPADR[0] = 0 and the second with MPADR[0] = 1. The IWE8 will not verify
whether the address bits MPADR[17:1] during the second access are the same as
during the first access.
The data of the first of two consecutive write cycles (MPADR[0] = 0) is written temporarily
into an internal write-cache register. The second write cycle (MPADR[0] = 1) causes the
data to be written into internal or external RAM. Bits [15:0] are written from the internal
write-cache register and bits [31:16] are transferred from MPDAT
During the first of two consecutive read cycles (MPADR[0] = 0), the 32 bit data are
actually read from internal or external RAM. Bits [15:0] are transferred to the databus
MPDAT. Bits [31:16] are written into an internal read-cache register. During the second
read (MPADR[0] = 1) the read-cache register is transferred to the databus. When only
bits [15:0] are needed, the second read cycle can be omitted.
For proper operation without acknowledge handshake via MPRDY 23 waitstates can be
used.
5.5.1
Interrupt Handling
The IWE8 provides two independent interrupt pins MPIR1 and MPIR2. The interrupt
handling software should read the interrupt status registers to identify the causes of the
interrupt.
MPIR1 is the main interrupt pin indicating a special event in the IWE8. The interrupt
cause can be determinded by reading Interrupt Status Register 1 ("isr1", see
Chapter 7.18). Each of the interrupt sources can be individually masked in the
corresponding interrupt mask register. If the interrupt source is masked, the interrupt pin
MPIR1 will not be asserted when the corresponding event occurs.
MPIR2 is an auxiliary interrupt pin. The IWE8 provides two sets of 8 independent timers
in external RAM (timer set 1 and 2). Timer set 2 can be used independently from the rest
of the IWE8 driver software. When one of the timers of timer set 2 expires, a bit will be
set in the Interrupt Status Register 2 ("isr2", see Chapter 7.23) and MPIR2 will be
asserted.
Data Sheet
114
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.5.2
Microprocessor Interface Mode
The IWE8 microprocessor interface allows connection of Intel type microprocessors as
well as Motorola type microprocessors (e.g. the PowerPC).
The Microprocessor Interface Mode is determined via the status of the pins PMT and
TBUS at the positive edge of the internal reset. Therefore, PMT and TBUS levels have
to be kept at least 3 clock cycles after deassertion of RESET.
Table 28
Configuration of the Microprocessor Interface Mode via PMT and TBUS
PMT
TBUS
Mode
0
0
Intel Mode
1
1
Motorola Mode
The mode currently assigned to the microprocessor interface is visible via “mtypsel” in
the “Version Register” (“vers”, see Chapter 7.16).
Intel Mode
The connection of the 16 bit Intel compatible asynchronous microprocessor interface to
an Intel 386EX processor is shown in Figure 32.
If the ready signal at pin MPRDY shall be used, a glue logic between MPRDY of the
IWE8 and RDY of the 386EX is required, which generates an active low signal with 1
microprocessor cycle length after a rising edge detection of the MPRDY signal.
Intel i386 EX
IWE8
MPIR2
MPIR1
INTi
INTj
CSn
RD
WR
DATA[0-15]
ADR[1-18]
Figure 32
MPCS
MPRD
MPWR
MPDAT[0-15]
MPADR[0-17]
Connection of IWE8 to an Intel Type Microprocessor
Motorola Mode
Figure 33 shows the connection of the 16 bit Motorola compatible asynchronous
interface to the IBM “PowerPCTM”.
Data Sheet
115
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
MC 68xxx
IWE8
INTi
INTj
TA
MPIR2
MPIR1
MPTA
CSn
TS
RD/WR
DATA[0-15]
A[1-18]
Figure 33
Data Sheet
MPCS
MPTS
MPRW
MPDAT[0-15]
MPADR[0-17]
Connection of IWE8 to an Motorola Type Microprocessor
116
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.6
External RAM Interface
The IWE8 needs to be connected to an external synchronous SRAM of 64k x 33 bits with
parity protection or 64k x 32 bits without parity protection.
For proper operation FT (Flow Through) SSRAM is needed. Pipelined SSRAM can not
be used, as this type has additional registered outputs.
A possible connection with 1 SRAM 64k x 36 component is shown in Figure 34.
.
SRAM 64K x 36
IWE8
CLK
A[0-15]
CS
WR
OE
ADSC
D[0-35]
RMCLK
RMADR[0-15]
RMCS
RMWR
RMOE
RMADC
RMDAT[0-32]
Figure 34
External RAM Connection
The IWE8 has a fixed RAM interface cycle of 12 clock periods. A sequence of
6 consecutive read cycles (addresses AR1 to AR6), a dummy address cycle and
5 consecutive write cycles (addresses AW1 to AW5) is continuously repeated. The
timing of RMADC and RMOE is always fixed as shown in Figure 35. Whether the IWE8
reads data from the external RAM or writes data into the external RAM is controlled by
the RMCS and RMWR signals. In Figure 35, data R1 and R3 are actually read by the
IWE8, and data W1 and W3 are actually written into the external RAM.
RMCLK
RMADR
W5
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
W1 W2 W3 W4 W5
R1
RMADC
RMOE
RMDAT
W5
R6
W1 W2 W3 W4 W5
RMWR
RMCS
RAM cycle
Figure 35
Data Sheet
RAM Interface Protocol
117
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.7
Boundary Scan Interface
The boundary scan interface implements the Test Access Port (TAP) as defined in IEEE
Standard 1149.1-1990 [19] including the optional TRST reset signal.
The device identification register, the instruction register and boundary-scan register are
described in the electrical characteristics.
Data Sheet
118
2002-05-06
PXB4219 / PXB4220 / PXB4221
Interface Description
5.8
Master Clock
The basic processing time of an octet in the IWE8 is 12 clock cycles. As the time needed
to process one octet for each of the 8 ports must be less than the time required to transfer
one octet over a framer interface, this leads to the condition:
m × o × T CLOCK < f × b × T FramerClk
[15]
with:
m = 12 master-clockcycles needed for one octet per port
o = 8 ports
f = Framer-clockcycles per bit
b = 8 bits per octet
T
Clock
f
> ------ × T
FramerClk
12
Table 29
[16]
Master Clock Frequency Depending on Mode
Mode
TCLOCK
FCLOCK
FAM, SYM8 and EC
< 1/3 x TFramerCLK
> 3 x FFramerCLK = 3 x 8.192 MHz
GIM E1 and SYM2
< 1/12 x TFramerCLK > 12 x FFramerCLK = 12 x 2.048 MHz
GIM T1
< 1/12 x TFramerCLK > 12 x FFramerCLK = 12 x 1.544 MHz
Data Sheet
119
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
6
Memory Structure
The IWE8 occupies an address space of 256k x 16 bits. The lower 128k x 16 bits are
used for internal registers and internal configuration RAM’s. The upper 128k x 16 bits are
used to address external RAM.
MPADR[17:0]
3FFFFH
RMADR[15:0]
128k × 16
64k × 32
FFFFH
External RAM
0000H
20000H
1FFFFH
Not used
00A00H
009FFH
512 × 16
256 × 32
Internal RAM4
00800H
007FFH
512 × 16
256 × 32
Internal RAM3
00600H
005FFH
512 × 16
256 × 32
Internal RAM2
00400H
003FFH
512 × 16
256 × 32
Internal RAM1
00200H
001FFH
512 × 16
Internal Registers
00000H
Figure 36
Memory Model
The 4 internal configuration RAMs are organized as 256 x 32 bit memories.
The external RAM is organized as a 64k x 32 bit parity protected memory.
Accesses to internal configuration RAM’s or external RAM are always 32 bit oriented.
Data Sheet
120
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
6.1
Internal Configuration RAM’s
The 4 internal 256 x 32 bit configuration RAM’s (RAM1, RAM2, RAM3 and RAM4) are
used to assign the timeslots of the Framer Receive and Framer Transmit interfaces to
ATM channels. For each port there are 32 entries. RAM1 is used to define the timeslots
of the Framer Receive ports, and RAM2 and RAM3 are used to define the Framer
Transmit ports. RAM4 is responsible for CAS conditioning and freezing in transmit
direction
When the contents of the internal RAMs have been altered by the software, the internal
state machines will load the new values within the next 1.5 frame cycles (187.5 µs). Up
to that point of time the previous values are used.
6.1.1
RAM1: Receive Port Configuration
Read/write Address 00200H to 003FFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR
6.1.1.1
17 16 15 14 13 12 11 10
9
0
1
0
0
0
0
0
0
0
8
7
6
port_nr
[2:0]
5
4
3
2
1
0
slot[4:0]
RAM1: ATM Receive Reference Slot
Read/write Address 00200H to 003FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
Not used
23
16
Not used
15
8
Not used
7
ocd_start ocd_end
_intrpt
_intrpt
Data Sheet
0
go_hunt
delete_
x43_
idle_cells descram
bling
121
channel_mode[1:0]
ref_slot
=1
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
ocd_start_
intrpt
ocd_end_
intrpt
go_hunt
Generate interrupt when OCD state starts
0=
Disabled
1=
Enabled
Generate interrupt when OCD state ends
0=
Disabled
1=
Enabled
Go to hunt state
0=
Cell delineation finite state machine normal operation
1=
Cell delineation finite state machine forced in hunt state
Only the transition 0 → 1 forces the hunt state. Counter (number
of times SYNC state is left) is not incremented. Ocd_start
interrupt is not generated.
delete_idle_ Delete idle/unassigned cells enable
cells
x43_de
scrambling
channel_
mode
ref_slot
0=
Disabled
1=
Enabled
ATM cell payload descrambling enable
0=
Disabled
1=
Enabled
Channel mode
00 =
Inactive mode
01 =
Active mode (normal mode)
10 =
Standby mode
11 =
Active mode (normal mode)
Reference slot indicator
1=
This slot is a reference slot
Note: To allow IWE8 internal initialization, all channels must remain in inactive mode for
at least 250 µs after activation of the port (i.e. setting pcfN[p_rx_act] = 1). During
this time the device connected to the Framer Receive Interface has to be in normal
operation.
Data Sheet
122
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
6.1.1.2
RAM1: ATM Receive Continuation Slot
Read/write Address 00200H to 003FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
Not used
23
16
Not used
15
8
Not used
7
0
Not used
ref_slot_nr[4:0]
cont_slot
=1
ref_slot_nr
Reference slot number
Number of the reference slot of this channel
cont_slot
Continuation slot indicator
1=
ref_slot
This slot is a continuation slot
Reference slot indicator
0=
6.1.1.3
ref_slot
=0
This slot is not a reference slot
RAM1: AAL Receive Reference Slot
Read/write Address 00200H to 003FFH
Reset value: Not applicable. RAM must be reset and initialized via SW
.
31
24
next_slot_nr[4:0]
sdt_mfs
sig_cond
23
subst_bpslct[1:0]
16
dcor
dcor_random_nr[4:0]
15
aal0
8
part_fill[5:0]
7
Data Sheet
srts
band_
width[4]
0
123
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
band_width[3:0]
sdt
channel_mode[1:0]
ref_slot
=1
next_slot_nr Next slot number
If band_width > 0 next_slot_nr points to the next slot of this channel.
If band_width = 0 and CAS is activated next_slot_nr[3:0] will be used as
signalling conditioning nibbles.
If band_width = 0 and CAS is not activated next_slot_nr is don’t care.
sdt_mfs
sig_cond
srts
subst_
bpslct
dcor
dcor_
random_nr
SDT multiframe pulse select
X=
If [aal0] = 1 or [sdt] = 0 or pcfN[p_ces] = 1
0=
Start of structure is frame pulse
1=
Start of structure is multiframe pulse as defined by
pcfN[p_tx_mfs]
Signalling conditioning upstream
0=
CAS freezing upstream enabled in "loss of signal" condition
1=
CAS conditioning upstream enabled in "loss of signal" condition
SRTS enable
Enables RTS value insertion into AAL1 SAR-PDUs
X=
If pcfN[p_srts] = 0 or [aal0] = 1
0=
Disabled
1=
Enabled
Substitute byte-pattern select
00 =
Select byte-pattern 0, defined in bp10[bp0]
01 =
Select byte-pattern 1, defined in bp10[bp1]
10 =
Select byte-pattern 2, defined in bp32[bp2]
11 =
Select byte-pattern 3, defined in bp32[bp3]
Decorrelation circuit enable
0=
Disabled
1=
Enabled
Decorrelation random Number
X=
aal0
Data Sheet
if [dcor] = 0
AAL0 enable
124
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
part_fill
0=
Disabled (AAL1 is used)
1=
Enabled (instead of AAL1)
Partially filled cell filling level
4 to
48
AAL0:
[aal0] = 1
4 to
47
AAL1 unstructured CES:
[aal0] = 0, pcfN[p_ces] = 1
4 to
47
AAL1 structured CES without CAS1):
[aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 0
4+Cb AAL1 structured CES with CAS2):
to 46 [aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 1
band_width
sdt
channel_
mode
ref_slot
band_width
N-1
Structured CES (with N = number of timeslots of the channel)
1FH
Unstructured CES (pcfN[p_ces] = 1)
SDT enable
X=
If pcfN[p_ces] = 1 or [aal0] = 1
0=
Disabled
1=
Enabled
Channel mode
00 =
Inactive mode
01 =
Active mode (normal mode)
10 =
Standby mode
11 =
Substitute mode
Reference slot indicator
1=
This slot is a reference slot
1)
non-P format, cell may have only 46 user data octets in P format
2)
Cb: Required bytes for the CAS sub-block in an ATM cell
Note: To allow IWE8 internal initialization, all channels must remain in inactive mode for
at least 250 µs after activation of the port (i.e. setting pcfN[p_rx_act] = 1). During
this time the device connected to the Framer Receive Interface has to be in normal
operation.
Data Sheet
125
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
6.1.1.4
RAM1: AAL Receive Continuation Slot
Read/write Address 00200H to 003FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
next_slot_nr[4:0]
Not used
23
16
Not used
sig_cond_nibble[3:0]
fourth_
slot_nr[4]
15
8
fourth_slot_nr[3:0]
third_slot_nr[4:1]
7
0
third_slot
_nr[0]
ref_slot_nr[4:0]
cont_slot
=1
ref_slot
=0
next_slot_nr Next slot number
Number of the next slot of this channel. When no continuation slots exist,
the entry “next_slot_nr” should refer to the reference slot.
sig_cond_
nibble
4 bits for signalling conditioning
It is possible to have different signalling conditioning nibbles for all slots
of a channel except for the first two slots of a channel. The first slot in a
channel will always use the same nibbles as the first continuation slot.
fourth_slot_ Fourth slot number
nr
Number of the fourth slot of this channel
X=
third_slot_
nr
If [band_width] < 3
Third slot number
Number of the third slot of this channel
X=
If [band_width] < 2
ref_slot_nr
Reference slot number
Number of the reference slot of this channel
cont_slot
Continuation slot indicator
1=
ref_slot
Reference slot indicator
0=
Data Sheet
This slot is a continuation slot
This slot is not a reference slot
126
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
6.1.1.5
RAM1: ATM or AAL Receive Idle Slot
Read/write Address 00200H to 003FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
Not used
23
16
Not used
15
8
Not used
7
0
Not used
cont_slot
ref_slot
=0
Continuation slot indicator
0=
ref_slot
This slot is not a continuation slot
Reference slot indicator
0=
6.1.2
cont_slot
=0
This slot is not a reference slot
RAM2: Transmit Port Configuration
Read/write Address 00400H to 005FFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR
6.1.2.1
17 16 15 14 13 12 11 10
9
0
0
0
0
0
0
0
0
1
8
7
6
port_nr
[2:0]
5
4
3
2
1
0
slot[4:0]
RAM2: ATM Transmit Reference Slot
Read/write Address 00400H to 005FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
Data Sheet
127
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
31
24
Not used
23
16
Not used
15
8
Not used
7
0
Not used
x43_scram
bling
channel_
mode
ref_slot
x43_
scrambling
channel_mode[1:0]
ref_slot
=1
ATM cell payload scrambling enable
0=
Disabled
1=
Enabled
Channel mode
00 =
Inactive mode
01 =
Active mode (normal mode)
10 =
Standby mode
11 =
Active mode (normal mode)
Reference slot indicator
1=
This slot is a reference slot
Note: RAM slot 1 has always to be configured always as reference slot.
Note: To allow IWE8 internal initialization, all channels must remain in inactive mode for
at least 250 µs after activation of the port (i.e. setting pcfN[p_tx_act] = 1). During
this time the device connected to the Framer Transmit Interface has to be in
normal operation.
6.1.2.2
RAM2: ATM Transmit Continuation Slot
Read/write Address 00400H to 005FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
Data Sheet
128
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
31
24
next_slot_nr[4:0] = 00000
Not used
23
16
Not used
15
8
Not used
7
0
Not used
ref_slot_nr[4:0]
cont_slot
=1
ref_slot
=0
next_slot_nr Next slot number
0=
This field must be all 0 for ATM continuation slots
ref_slot_nr
Reference slot number
Number of the reference slot of this channel
cont_slot
Continuation slot indicator
1=
ref_slot
This slot is a continuation slot
Reference slot indicator
0=
6.1.2.3
This slot is not a reference slot
RAM2: AAL Transmit Reference Slot
Read/write Address 00400H to 005FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
next_slot_nr[4:0]
Not used
snp_
check
23
sc_fast
16
sdt_mfs
sdt_oos_nr[1:0]
sdt_par
15
aal0
sdt_once
crv_en
mcp_
reinit
8
part_fill[5:0]
7
Data Sheet
sn_
check
band_
width[4]
0
129
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Memory Structure
band_width[3:0]
sdt
channel_mode[1:0]
ref_slot
=1
next_slot_nr Next slot number
Number of the second slot of this channel. When no continuation slots
exist, the entry “next_slot_nr” should refer to the reference slot.
X=
snp_check
sn_check
sc_fast
sdt_mfs
sdt_oos_nr
sdt_par
Data Sheet
If pcfN[p_ces] = 1
SNP field check enable
X=
If [aal0] = 1 or [sn_check] = 0
0=
Disabled
1=
Enabled
SN field check enable
X=
If [aal0] = 1
0=
Disabled
1=
Enabled
SC algorithm select
X=
If [aal0] = 1 or [sn_check] = 0
0=
Standard SC algorithm
1=
Fast SC algorithm
SDT multiframe pulse select
X=
If [aal0] = 1 or [sdt] = 0 or pcfN[p_ces] = 1
0=
Start of structure is frame pulse
1=
Start of structure is multiframe pulse
Number of SDT out of sync errors before re-initialization buffer
X=
If [aal0] = 1 or [sdt] = 0
00 =
Re-initialize after 1 out of sync error (recommended)
01 =
Re-initialize after 2 out of sync error
10 =
Re-initialize after 3 out of sync error
11 =
Not allowed, IWE8 will not be able to re-initialize
SDT pointer parity check enable
X=
If [aal0] = 1 or [sdt] = 0
0=
Disabled
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Memory Structure
1=
sdt_once
crv_en
Enabled
SDT pointer appears once in 8 cell cycle
X=
If [aal0] = 1 or [sdt] = 0
0=
All cells with CSI bit = 1 and even SN are supposed to contain a
P format SAR-SDU.
1=
Only the first cell with CSI bit = 1 and even SN in a cycle of 8 cells
is supposed to contain a P format SAR-SDU. (recommended for
SDT)
Data to Clock Recovery interface enable (RTS values and/or ACM buffer
filling levels) This bit may only be set for one channel per port.
X=
if (pcfN[p_srts] = 0 and pcfN[p_acm] = 0) or acfg[a_crv_en] = 0
0=
Disabled
1=
Enabled
Only one channel per port may have crv_en set to 1.
mcp_reinit
aal0
part_fill
Microprocessor forced reassembly buffer reinitialization
The SW should set and reset this bit to continue proper operation.
0=
Disabled
1=
Enabled
AAL0 enable
0=
Disabled (AAL1 is used)
1=
Enabled (instead of AAL1)
Partially filled cell filling level
4 to
48
AAL0:
[aal0] = 1
4 to
47
AAL1 unstructured CES:
[aal0] = 0, pcfN[p_ces] = 1
4 to
47
AAL1 structured CES without CAS1):
[aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 0
4+Cb AAL1 structured CES with CAS2):
to 47 [aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 1
band_width
sdt
Data Sheet
band_width
N
(with N = number of timeslots for this channel)
X=
if pcfN[p_ces] = 1
Structured Data Transfer enable
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Memory Structure
channel_
mode
ref_slot
X=
If pcfN[p_ces] = 1 or [aal0] = 1
0=
Disabled
1=
Enabled
Channel mode
00 =
Inactive mode
01 =
Active mode (normal mode)
10 =
Standby mode
11 =
Active mode (normal mode)
Reference slot indicator
1=
This slot is a reference slot
1)
non-P format, cell may have only 46 user data octets in P format
2)
Cb: Required bytes for the CAS sub-block in an ATM cell
Note: To allow IWE8 internal initialization, all channels must remain in inactive mode for
at least 250 µs after activation of the port (i.e. setting pcfN[p_rx_act] = 1). During
this time the device connected to the Framer Transmit Interface has to be in
normal operation.
6.1.2.4
RAM2: AAL Transmit Continuation Slot
Read/write Address 00400H to 005FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
next_slot_nr[4:0]
Not used
23
16
Not used
15
8
Not used
slot_index[4:0]
7
0
Not used
ref_slot_nr[4:0]
Data Sheet
132
cont_slot
=1
ref_slot
=0
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
next_slot_nr Next slot number
Number of the next slot of this channel. When no continuation slots exist,
the entry “next_slot_nr” should refer to the reference slot.
slot_index
Index number of the current slot
X=
if pcfN[p_cas] = 0
2=
3=
...
30 =
1st continuation slot
2nd continuation slot
...
29th continuation slot
ref_slot_nr
Reference slot number
Number of the reference slot of this channel
cont_slot
Continuation slot indicator
1=
ref_slot
Reference slot indicator
0=
6.1.2.5
This is a continuation slot
This slot is not a reference slot
RAM2: ATM or AAL Transmit Idle Slot
Read/write Address 00400H to 005FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
Not used
23
16
Not used
15
8
Not used
idle_
bpslct[1]
7
0
idle_
bpslct[0]
idle_bpslct
Not used
ref_slot
=0
Idle slot byte-pattern select
00 =
Data Sheet
cont_slot
=0
Select byte-pattern 0, defined in bp10[bp0]
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Memory Structure
cont_slot
01 =
Select byte-pattern 1, defined in bp10[bp1]
10 =
Select byte-pattern 2, defined in bp32[bp2]
11 =
Select byte-pattern 3, defined in bp32[bp3]
Continuation slot indicator
0=
ref_slot
This is not a continuation slot
Reference slot indicator
0=
6.1.3
This slot is not a reference slot
RAM3: Transmit Port Configuration Extended
Read/write Address 00600H to 007FFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR
17 16 15 14 13 12 11 10
9
0
1
0
0
0
0
0
0
1
8
7
6
port_nr
[2:0]
5
4
3
2
1
0
slot[4:0]
RAM3 needs only to be programmed in the case of an “AAL Transmit Reference Slot’.
In all other cases the RAM3 entry is don’t care.
6.1.3.1
RAM3: AAL Transmit Reference Slot
Read/write Address 00600H to 007FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
Not used
starv_bpslct[1:0]
starv_ini[10:8]
23
16
starv_ini[7:0]
15
8
buff_lsize[13:6]
7
0
buff_lsize[5:0]
Data Sheet
auto_
reinit_of
134
auto_
reinit_uf
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
starv_bpslct Starvation byte-pattern select
starv_ini
00 =
Select byte-pattern 0, defined in bp10[bp0]
01 =
Select byte-pattern 1, defined in bp10[bp1]
10 =
Select byte-pattern 2, defined in bp32[bp2]
11 =
Select byte-pattern 3, defined in bp32[bp3]
Number of starvation octets sent at reassembly buffer initialization.
0..
The actual number of starvation octets sent is starv_ini + 1
2046
2047 An unlimited number of starvation octets will be sent
buff_lsize
Logical size of reassembly buffer in octets
auto_reinit_ Automatic reassembly buffer reinitialization at overflow
of
X=
If [aal0] =1
0=
µP controlled reassembly buffer initialization
1=
automatic reassembly buffer initialization
auto_reinit_ Automatic reassembly buffer reinitialization at underflow
uf
6.1.4
X=
If [aal0] = 1
0=
µP controlled reassembly buffer initialization
1=
automatic reassembly buffer initialization
RAM4: Transmit Port Configuration Extended
Read/write Address 00800H to 009FFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR
17 16 15 14 13 12 11 10
9
0
0
0
0
0
0
0
1
0
8
7
6
port_nr
[2:0]
5
4
3
2
1
0
slot[4:0]
RAM4 needs only to be programmed in the case of an “AAL Transmit Reference Slot”
and in case of CAS usage. In all other cases the RAM4 entry is don’t care.
Data Sheet
135
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
6.1.4.1
RAM4: AAL Transmit Conditioning Slot
Read/write Address 00800H to 009FFH
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
24
Not used
23
16
Not used
15
8
Not used
7
0
Not used
cond_en
cond_down_nibble[3:0]
cond_down
_nibble
CAS conditioning nibbles in downstream for the slot
cond_en
Conditioning enable
Data Sheet
0=
CAS downstream freezing enabled in underrun or pointer
mismatch condition
1=
CAS downstream conditioning enabled in underrun or pointer
mismatch condition
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Memory Structure
6.2
External RAM
The IWE8 requires an external 64K × 32 bit RAM. A 33th bit is added for parity.
MPADR[17:0]
RMADR[15:0]
64k × 16
3FFFFH
30000H
32k × 32
Reassembly / ATM Transmit Buffers
32k × 16
2FFFFH
28000H
8000H
16k × 32
7FFFH
Segmentation / ATM Receive Buffers
27FFFH
8128 x 16
26040H
4000H
4064 x 32
3FFFH
Cell Extraction Buffer
3020H
32 × 16
2603FH
16 × 32
26020H
301FH
Cell Insertion Buffer
32 × 16
2601FH
3010H
16 × 32
26000H
300FH
Timers
8k × 16
25FFFH
24000H
22000H
3000H
4k × 32
2FFFH
Interrupt queue
2000H
4k × 32
1FFFH
8k × 16
23FFFH
Statistics Counter thresholds
8k × 16
21FFFH
1000H
4k × 32
20000H
0FFFH
Statistics Counters
Figure 37
6.2.1
FFFFH
0000H
Structure of the IWE8 external RAM
Statistics Counters
Read/write Address 20000H to 21FFFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 4K × 32 bits: 8 ports x 32 channels x 16 counters.
The statistics counters are incremented when the “channel_mode” is active or standby,
and when the corresponding enable bit in the “catm” or “caal” register is set.
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
counter_nr[3:0]
0
1
Data Sheet
0
0
0
0
port_nr
[2:0]
channel_nr[4:0]
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Memory Structure
Table 30
Statistics Counters for ATM Ports 1)
counter_nr
Counter contents
0 2)
Number of discarded cells due to output queue, ATM Receive Buffer
overflow
1
Number of received cells with correctable HEC errors
2
Number of received cells with non-correctable HEC errors
3
Number of times cell delineation SYNC state is left, except when forced
by the processor
4
Number of discarded cells due to ATM transmit buffer overflow
5
Number of cells which have been discarded because of CLP or CLPI
6
Not used
7
Not used
8
Not used
9
Not used
10
Not used
11
Not used
12
Not used
13
Not used
14
Not used
15
Not used
1)
For ATM ports, the counters are located in channel_nr = 00000B
2)
Counter_nr 0 is common to all ports and is located in port_nr = 111B channel_nr = 11111B
Table 31
Statistics Counters for AAL Ports1)
Counter_nr
Counter contents
0 2)
Number of discarded cells due to Output Queue or Segmentation Buffer
overflow
1
Not used
2
Number of cells written to the Reassembly Buffer. It excludes cells that
were discarded for any reason and cells that are inserted instead of lost
cells (atmfReassembledCells)
3
Number of times incoming MFB pulse is not synchronous to SDT start of
structure upstream (AAL1)
Data Sheet
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Memory Structure
Table 31
Statistics Counters for AAL Ports1) (cont’d)
4
Number of cells causing a Reassembly Buffer overflow (AAL0 & AAL1).
It includes accepted cells that are causing the filling level to exceed the
predifined threshold and discarded cells due to the attempt of writing to
the Reassembly Buffer when the threshold is already exceeded.
5
Number of end of Reassembly Buffer overflow (AAL0 & AAL1). The
value is incremented upon acceptance of the next cell after Reassembly
Buffer overflow.
6
The count of the number of AAL1 header errors detected including those
corrected. Header errors include correctable and uncorrectable CRC,
plus bad parity. (atmfCESHdrErrors)
7
Number of times that the sequence number of an incoming AAL1 SARPDU causes a transition of the SC algorithm from "sync" to "out of
sequence" and from "invalid" to "out of sync"
8
Number of downstream “misinserted cells” detected by the AAL1
sequence count algorithm (atmfCESMisinsertedCells)
9
Number of downstream cells discarded by the AAL1 sequence count
algorithm
10
Number of rejected AAL1 SDT pointers due to parity error or wrong
pointer value (93 < pointer <127)
11
Number of SC cycles with more than one AAL1 SDT pointer field if only
one pointer is expected (sdt_once = 1)
12
Number of start of reassembly buffer underflow (AAL0 & AAL1)
(atmfCESBufUnderflow)
13 3)
Number of inserted starvation cells (AAL0 & AAL1) due to reassembly
buffer underflow
14
Number of times the Reassembly Buffer is re-initialized due to AAL1
start of structure is out of sync with port start of structure (see
Chapter 4.4.1.11)
This records the count of the number of events in which the AAL1
reassembler found that an SDT pointer is not where it is expected, and
the pointer must be reacquired. This count is only meaningful for
structured CES. (atmfCESPointerReframes)
15
Number of downstream “lost cells” detected by the AAL1 sequence
count algorithm (atmfCESLostCells)
1)
For AAL ports with unstructured CES, the counters are located in channel_nr = 00000B
2)
Counter_nr 0 is common for all ports and is located in port_nr = 111B channel_nr = 11111B
Data Sheet
139
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
3)
If
the
“auto-re-initialization
on
underflow”
feature
is
enabled
(RAM3.AAL Transmit
Reference Slot.auto_reinit_uf = 1B), the re-initialization of the Reassembly Buffer will terminate an underflow
status as soon as start of underflow is detected. Thus, the underflow status for the device is no longer valid
although the underflow condition still exists. No starvation cells due to underflow will be inserted and counter
13 will not increment Therefore, it is recommended to disable “auto-re-initialization on underflow”
(RAM3.AAL Transmit Reference Slot.auto_reinit_uf = 0B) and perform the re-initialization of the reassembly
buffer by software.
The format of the counter entries is as follows:
31
24
int_gen
count_value[30:24]
23
16
count_value[23:16]
15
8
count_value[15:8]
7
0
count_value[7:0]
int_gen
interrupt queue entry generated
Indicates if an interrupt queue entry was generated for this counter. Only
one interrupt queue entry per counter can be generated.
0=
False
1=
True
count_value counter value
4000_0000H indicates the maximum value. The counter will not
increment beyond this value
6.2.2
Statistics Counter thresholds
Read/write Address 22000H to 23FFFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 4K × 32 bits: 8 ports x 32 channels x 16 counter thresholds
Data Sheet
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Memory Structure
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
0
0
0
1
port_nr
[2:0]
channel_nr
[4:0]
0
counter_nr
[3:0]
0
The format of the counter threshold entries is as follows:
31
24
thres_act
thres_value[30:24]
23
16
thres_value[23:16]
15
8
thres_value[15:8]
7
0
thres_value[7:0]
thres_act
threshold active
thres_value
6.2.3
0=
Disabled
1=
Enabled
threshold value
Thresholds beyond 4000 0000H will never create an interrupt queue
entry as the counter stops at this value
Interrupt Queue
Read/write Address 24000H to 25FFFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 4K × 32 bits
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
Data Sheet
0
0
1
0
interrupt_queue_addr[11:0]
141
0
0
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
For reading the Interrupt Queue refer to Chapter 4.6.3.
Each interrupt queue entry identifies a particular statistics counter that has reached its
threshold value. The format of the interrupt queue entries is as follows:
31
24
Not used
23
16
Not used
15
8
iq_ne
not used
port_nr
[2:0]
channel_
nr[4]
7
0
channel_nr[3:0]
iq_ne
6.2.4
counter_nr[3:0]
interrupt queue not empty
0=
interrupt queue is empty, no further entries
1=
interrupt queue is not empty, further entries can be read
Timers
Read/write Address 26000H to 2601FH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 16 × 32 bits: 2 timer sets x 8 timers
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
timer_nr[3:0]
0
timer_nr[3]
timer_nr
[2:0]
Data Sheet
0
0
1
1
0
0
0
Timer number
Selects the timer set
0=
Timer set 2 indicated on MPIR2
1=
Timer set 1 indicated on MPIR1
Timer number
Number of the associated timer
142
2002-05-06
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Memory Structure
The format of the timer entries is as follows:
31
24
Not used
23
16
Not used
15
8
timer_en
timer_value[14:8]
7
0
timer_value[7:0]
timer_en
Timer enable
The timer_en bit can be used by the SW to start/stop/pause the timer.
Upon reaching timer_value = 0 the timer_en will be reset to 0
timer_value
0=
Disabled
1=
Enabled
Timer value
When timer_en is set to 1, the timer_value will be decremented every
12 x 512 x TCLOCK (245.8 µS if fCLOCK = 25 MHz). The timer_value will
stop at 7FFFH indicated by an interrupt status bit in isr1 for timer set 1 or
in isr2 for timer set 2.
Note: Internal register bit oamc[tim_set1_en] = 0 will disable all timers in set 1.
Internal register bit time[tim_set2_en] = 0 will disable all timers in set 2.
6.2.5
Cell Insertion Buffer
Read/write: Address 26020H to 2603FH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 16 × 32 bits: 1 cell x 16 doublewords
MPADR[17:0]
RMADR[15:0]
2603FH
301FH
Not Used
301EH
2603CH
Data Sheet
143
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
MPADR[17:0]
RMADR[15:0]
2603BH
301DH
ATM Cell Payload
3012H
26024H
26023H
Not Used
26022H
3011H
26021H
ATM Header
3010H
26020H
The ATM header to be used for cell insertion has to be programmed at
MPADR = 26020H.
The format of the ATM Header entry is as follows:
31
24
VCI[3:0]
CLP
PTI[2:0]
23
16
VCI[11:4]
15
8
VPI[3:0]
VCI[15:12]
7
0
GFC[3:0] or VPI[11:8]
6.2.6
VPI[7:4]
Cell Extraction Buffer
Read/write Address 26040H to 27FFFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 8127 × 32 bits: 254 cells x 16 doublewords
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
double_word
[3:0]
0
1
Data Sheet
0
0
1
1
cell_nr[7:0] + 2
144
2002-05-06
PXB4219 / PXB4220 / PXB4221
Memory Structure
For reading the extraction buffer, refer to Chapter 4.10.
MPADR[17:0]
27FFFH
RMADR[15:0]
Cell #254
3FFFH
·
26060H
Cell #2
3030H
2605FH
302FH
Not Used
2605AH
302DH
26059H
302CH
ATM Cell #1 Payload
26042H
3021H
26041H
ATM Cell #1 Header
3020H
26040H
The format of the ATM header entry is as follows:
31
24
VCI[3:0]
CLP
PTI[2:0]
23
16
VCI[11:4]
15
8
VPI[3:0]
VCI[15:12]
7
0
GFC[3:0] or VPI[11:8]
6.2.7
VPI[7:4]
Segmentation/ATM Receive Buffers
Read/write Address 28000H to 2FFFFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 16K × 32 bits: 8 ports x 32 channels x 4 cells x 16 doublewords
Data Sheet
145
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PXB4219 / PXB4220 / PXB4221
Memory Structure
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
double_word
[3:0]
0
1
6.2.7.1
0
1
port_nr
[2:0]
channel_nr
[4:0]
cell_nr
[1:0]
ATM Receive Buffer
The SW does not need to access the ATM Receive Buffers.
6.2.7.2
Segmentation Buffer
The ATM header to be used for each channel has to be programmed at the address
given by:
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
0
1 port_nr[2:0]
ref_slot_nr[4:0]
00B
0000B
0
0
All other locations should never be accessed as the data changes continuously.
The format of the ATM header entry in the cell insertion buffer is as follows:
31
24
VCI[3:0]
PTI[2:0]
23
CLP
16
VCI[11:4]
15
8
VPI[3:0]
VCI[15:12]
7
0
GFC[3:0] or VPI[11:8]
6.2.8
VPI[7:4]
Reassembly/ATM Transmit Buffers
Read/write Address 30000H to 3FFFFH
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 32K × 32 bits: 8 ports x 32 channels x 8 cells x 16 doublewords
Data Sheet
146
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PXB4219 / PXB4220 / PXB4221
Memory Structure
RMADR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MPADR
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
double_word
[3:0]
0
1
1
port_nr
[2:0]
channel_nr
[4:0]
cell_nr
[2:0]
The SW does not need to access the Reassembly/ATM Transmit Buffers.
Data Sheet
147
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7
Register Description
The internal registers occupy the lowest addresses. Accesses to the internal registers
are 16 bit oriented.
Entry size = 16 bit
Note: N = 0 .. 7
Table 32
Internal Registers
MPADR
Width Name
Register
00000H + N
14
pcfN
Port Configuration Register of Port N
00008H
16
acfg
ASIC Configuration Register
00009H
3
oamc
OAM Control Register
0000AH
6
catm
OAM-Counter Enable Register for ATM Ports
0000BH
16
caal
OAM-Counter Enable Register for AAL Ports
0000CH
16
bp32
Byte-pattern Register 3 and 2
0000DH
16
bp10
Byte-pattern Register 1 and 0
0000EH
16
atmc
ATM Control Register
0000FH
16
rxid
RX Idle/unassigned Cell Control Register
00010H
16
txid
TX Idle/unassigned Cell Control Register
00011H
9
lpbc
Loopback Control Register
00012H
8
cfil
Cell Fill Register for Partially Filled Cells
00013H
16
imr1
Interrupt Mask Register 1
00014H
1
time
Timer Enable Register
00015H
16
cdfs
Cell Delineation FSM Status Register
00016H
9
vers
Version Register
00017H
8
ckmo
Clock Monitor Register
00018H
16
isr1
Interrupt Status Register 1
00019H
2
eis1
Extended Interrupt Status Register 1
0001AH
8
eis2
Extended Interrupt Status Register 2
0001BH
8
eis3
Extended Interrupt Status Register 3
0001CH
16
eis4
Extended Interrupt Status Register 4
0001DH
8
isr2
Interrupt Status 2 Register
0001EH
14
opmo
Operation Mode Register
0001FH
16
ftcs
FT Clock Select Register
00020H
16
cfvp1
Cell Filter VCI Pattern Register 1
Data Sheet
148
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PXB4219 / PXB4220 / PXB4221
Register Description
Table 32
Internal Registers
MPADR
Width Name
Register
00021H
16
cfvm1
Cell Filter VCI Mask Register 1
00022H
16
cfvp2
Cell Filter VCI Pattern Register 2
00023H
16
cfvm2
Cell Filter VCI Mask Register 2
00024H
12
cfpt
Cell Filter Payload Type Register
00025H
5
cmd
Command Register
00026H
8
cfrp
Cell Filter Read Pointer
00027H
16
thrshld
Threshold Register
00028H
14
utconf
UTOPIA Configuration Register
00029H
16
cas1
CAS 1 Register
0002AH
16
cas2
CAS 2 Register
0002BH
4
cas3
CAS 3 Register
0002CH
16
thrshp01
Threshold Register Ports 0 and 1
0002DH
16
thrshp23
Threshold Register Ports 2 and 3
0002EH
16
thrshp45
Threshold Register Ports 4 and 5
0002FH
16
thrshp67
Threshold Register Ports 6 and 7
00030H
16
eis0
Extended Interrupt Status Register 0
00031H
16
lcdtimer
LCD Timer Register
00032H- 00100H
Unused
00101H
11
irs
Interrupt Source Register
00102H
11
irm
Interrupt Mask Register
00103H
9
icrcconf
ICRC Configuration Register
00104H+ N x 32
13
condN
Configuration Downstream Register of Port N
00105H+ N x 32
7
irsN
Interrupt Source of Port N
00106H+ N x 32
7
irmN
Interrupt Mask of Port N
00107H+ N x 32
5
tsinN
Test input Register of Port N
00108H+ N x 32
1
conuN
Configuration Upstream Register of Port N
0010CH+ N x 32
14
avbN
Average Buffer Filling of Port N
0010DH+ N x 32
4
asfN
ACM Shift Factor of Port N
0010EH+ N x 32
13
tiniN
Time of Initial Free Run of Port N
0010FH+ N x 32
12
treshN
Threshold Out Of Lock Detection of Port N
00110H
12
per
Parity Errors at Clock Recovery Interface
00111H
12
scri
Synchronization Errors at Clock Recovery
Interface
Data Sheet
149
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PXB4219 / PXB4220 / PXB4221
Register Description
Table 32
Internal Registers
MPADR
Width Name
Register
00112H
12
crifo
ICRC Clock Recovery Interface FIFO Overflow
00113H
12
icrcv
ICRC Version Register
00114H+ N x 32
8
sruN
SRTS FIFO Underflow of Port N
00115H+ N x 32
8
sroN
SRTS FIFO Overflow of Port N
00116H+ N x 32
8
srrN
SRTS Generator Reset of Port N
00117H+ N x 32
8
sriN
SRTS Invalid Value Processed of Port N
00118H+ N x 32
8
atlN
ACM Data Too Late of Port N
00119H+ N x 32
3
oolN
Out of Lock Register of Port N
0011AH+ N x 32
3
statN
Status Register of ICRC of Port N
0011BH+ N x 32
5
tsoutN
Test Output Register of Port N
Data Sheet
150
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.1
Port Configuration Registers (pcfN)
Read/write Address 00000H + N
Reset value: 0000.
15
8
p_cell_
disc
Not used
p_thr_m[1:0]
p_cas
p_atm
p_ces
p_acm
7
p_srts
0
p_slp
p_cell_disc
p_thr_m
p_cas
p_dlp
p_rx_act p_rx_em p_tx_act
p_tx_mfs
Port Cell Discard Enable
X=
When p_atm = 0 or acfg.a_hec_mode = 0
0=
Port in IMA mode:
No cell discard upon detection of uncorrectable HEC error.
The MSB in the UDF field of the ATM cell header at UTOPIA
interface will indicate the results of the HEC check
1=
Port in standard mode:
Cell discard upon detection of uncorrectable HEC error
Port threshold mode
This bit is relevant in ATM mode (p_atm=1) only.
00 =
Port specific backpressure to UTOPIA is disabled. Entering this
value causes a reset of the corresponding filling level counter.
Resetting this counter during operation may result in an
inappropriate backpressure.
01 =
Port specific backpressure to UTOPIA is enabled
Crossing the value defined in thrspN will result in port specific
backpressure. Values can range from 0 to 255 cells.
10 =
Port specific backpressure to UTOPIA is enabled
Crossing the value defined in thrspN will result in port specific
backpressure. The amount of bytes defining the threshold value
equals 53 * C + B. With C representing the 2 most significant bits
of thrspN and B representing the 6 least significant bits of thrspN.
Values can range from 0 to 222 bytes.
11 =
Port specific backpressure to UTOPIA is disabled
Port CAS enable
0=
Data Sheet
p_ulp
Disabled
151
2002-05-06
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Register Description
1=
p_atm
p_ces
p_acm
p_srts
p_slp
p_ulp
p_dlp
p_rx_act
Data Sheet
Enabled
Port ATM mode
0=
AAL (CES) mode port
1=
ATM (PHY) mode port
Port circuit emulation service
X=
When p_atm = 1
0=
Structured (N × 64 kbit/s)
1=
Unstructured
Port ACM enable
X=
When p_atm = 1
0=
Disabled
1=
Enabled
Port SRTS enable
For the PXB4220 this bit enables SRTS clock recovery. This is only
useful for AAL ports in unstructured CES.
For the PXB4221 this bit is tied to "0". Writing "1" has no effect.
X=
When p_atm = 1
0=
Disabled
1=
Enabled
Port serial loopback enable
0=
Disabled
1=
Enabled
Port upstream UTOPIA loopback (works even if UTOPIA interface is
disabled)
0=
Disabled
1=
Enabled
Port downstream UTOPIA loopback
0=
Disabled
1=
Enabled
Port receive activate
0=
Disabled
1=
Enabled
152
2002-05-06
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Register Description
p_rx_em
p_tx_act
p_tx_mfs
Port receive emergency mode
Enables the automatic switch over to emergency mode
0=
Disabled
1=
Enabled
Port transmit activate
0=
Disabled (Framer outputs tristated)
1=
Enabled
Port transmit multiframe signal at pin FTMFS
E1/T1 = 0:
0=
T1 Superframe mode (12 frames = 1.5 ms)
1=
T1 Extended superframe mode (24 frames = 3 ms)
E1/T1 = 1:
Data Sheet
0=
E1 Double frame mode (2 frames = 250 µs)
1=
E1 CRC multiframe mode (16 frames = 2 ms)
153
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Register Description
7.2
ASIC Configuration Register (acfg)
Read/write Address 00008H
Reset value: 0000H
15
8
a_icrc_
dwn
a_hec_
algor
a_hec_
mode
a_sw_
reset
a_ut_en
a_dummy
_rts[3]
a_ur_en a_crv_en
7
0
a_dummy_rts[2:0]
a_icrc_dwn
a_emg_bpslct[1:0]
a_ovf_
cnt_en
a_ptr_
prty
a_even_
pck
ICRC power down
Once the SRTS block is switched off, it can only be enabled by hardware
reset of the whole device.
0=
Enabled
1=
Disabled
a_hec_algor HEC detection, correction
a_hec_
mode
a_sw_reset
a_ut_en
a_ur_en
Data Sheet
0=
HEC algorithm according to ITU-T
1=
HEC algorithm according to ATM Forum
Handling in case of faulty HEC
0=
Standard mode:
Cell discard upon detection of uncorrectable HEC error
1=
as defined in pcfN.p_cell_disc
Software reset
Reset registers 0000H to 0031H including this bit.
0=
Normal
1=
Reset
UTOPIA transmit enable
0=
Disabled
1=
Enabled
UTOPIA receive enable
0=
Disabled
1=
Enabled
154
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Register Description
a_crv_en
Clock recovery interface enable
0=
Disabled
1=
Enabled
a_dummy_
rts
Dummy RTS value
Dummy RTS value that will be transmitted in the first and second SRTS
period after start of segmentation.
a_emg_
bpslct
Emergency byte-pattern select
a_ovf_cnt_
en
a_ptr_prty
00 =
Byte-pattern 0, defined in bp10[bp0] selected
01 =
Byte-pattern 1, defined in bp10[bp1] selected
10 =
Byte-pattern 2, defined in bp32[bp2] selected
11 =
Byte-pattern 3, defined in bp32[bp3] selected
Output queue overflow counter enable
0=
Disabled
1=
Enabled
SDT pointer even parity generation
0=
Disabled: Fixed value in bit 7 of pointer field: “0”.
1=
Enabled (recommended)
a_even_pck Even parity check for internal/external RAM and UTOPIA
Data Sheet
0=
Odd parity check enabled (default operation)
The parity checkers expect the normal parity.
1=
Even parity check enabled
The parity checkers expect the inverse parity. This mode tests
the proper operation of the parity generators/checkers.
155
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Register Description
7.3
OAM Control Register (oamc)
Read/write Address 00009H
Reset value: 0000H
15
8
Not used
7
0
Not used
tim_
set1_en
dest_
read
oam_
act
tim_set1_en Timer set 1 enable
dest_read
oam_act
Data Sheet
0=
Disabled
1=
Enabled
Destructive read mode
0=
Disabled
1=
Enabled: OAM counter values in the external RAM are reset after
being read by the micro-processor.
(Only accepted if “oam_act” = 1)
OAM active
0=
The protocol monitoring is disabled and the microprocessor can
read and write the complete external RAM for test.
1=
The protocol monitoring is enabled and the RAM arbiter grants
both the protocol monitoring and the microprocessor access to
the external RAM. Reading any address of Interrupt Queue by
the microprocessor always yields the first interrupt in the queue.
156
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Register Description
7.4
OAM-Counter Enable Register for ATM Ports (catm)
Read/write Address 0000AH
Reset value: 0000H
15
8
Not used
7
5
0
Not used
cnt_atm_en
Data Sheet
cnt_atm_en[5:0]
OAM-counter enable for ATM ports
X=
When pcfN[p_atm] = 0
0=
Disabled
1=
Enabled
157
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PXB4219 / PXB4220 / PXB4221
Register Description
7.5
OAM-Counter Enable Register for AAL Ports (caal)
Read/write Address 0000BH
Reset value: 0000H
15
8
cnt_aal_en[15:8]
7
0
cnt_aal_en[7:0]
cnt_aal_en
Data Sheet
OAM-counter enable for AAL ports
X=
When pcfN[p_atm] = 1
0=
Disabled
1=
Enabled
158
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PXB4219 / PXB4220 / PXB4221
Register Description
7.6
Byte-Pattern Register bp3 and bp2 (bp32)
Read/write Address 0000CH
Reset value: FFFFH
15
8
bp3[7:0]
7
0
bp2[7:0]
bp3
Byte-pattern 3
bp2
Byte-pattern 2
Data Sheet
159
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.7
Byte-Pattern Register bp1 and bp0 (bp10)
Read/write Address 0000DH
Reset value: FFFFH
15
8
bp1[7:0]
7
0
bp0[7:0]
bp1
Byte-pattern 1
bp0
Byte-pattern 0
Data Sheet
160
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.8
ATM Control Register (atmc)
Read/write Address 0000EH
Reset value: 7655H
15
8
alpha[3:0]
delta[3:0]
7
0
coset[7:0]
alpha
Number of consecutive incorrect HEC (SYNC → HUNT)
delta
Number of consecutive correct HEC (PRESYNC → SYNC)
coset
Coset value x-ored with HEC
Data Sheet
161
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.9
RX Idle/Unassigned Cell Control Register (rxid)
Read/write Address 0000FH
Reset value: 0101H
15
8
prg_rx_hd[7:4]
prg_rx_hd[3:0]
7
0
msk_rx_hd[7:0]
prg_rx_hd
Programmable RX idle/unassigned cell header octet 1[7:4]
00H according to I.361
prg_rx_hd
Programmable RX idle/unassigned cell header octet 4[3:0]
01H according to I.361
msk_rx_hd
Mask RX idle/unassigned cell header bits
Each bit masks the corresponding bit in prg_rx_hd
0=
Not masked:
1=
Masked
Note: Other header bits must be zero
Data Sheet
162
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.10
TX Idle/Unassigned Cell Control Register (txid)
Read/write Address 00010H
Reset value: 016AH
15
8
prg_tx_hd[7:4]
prg_tx_hd[3:0]
7
0
prg_tx_pl[7:0]
prg_tx_hd
Programmable TX idle/unassigned cell header octet 1[7:4]
00H according to I.361
prg_tx_hd
Programmable TX idle/unassigned cell header octet 4[3:0]
01H according to I.361
prg_tx_pl
Programmable TX idle/unassigned cell payload octet
6AH according to I.432
Note: Other header bits are fixed to zero
Data Sheet
163
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.11
Loopback Control Register (lpbc)
Read/write Address 00011H
Reset value: 0000H
15
8
Not used
tslp
7
tulp
0
tdlp
vci_flt_
ulp
vci_val_ulp[4:0]
t
tslp
tulp
tdlp
vci_flt_ulp
vci_val_ulp
Transparent serial loop
0=
Non-transparent
1=
Transparent
Transparent upstream UTOPIA loop
X=
When pcfN[p_atm] = 1
0=
Non-transparent
1=
Transparent
Transparent downstream UTOPIA loop
0=
Non-transparent
1=
Transparent
VCI filter enable for upstream UTOPIA loop
0=
Disabled (all VCIs are looped)
1=
Enabled (VCI selected by vci_val_ulp is looped)
5 LSB of the VCI value (i.e. channel number) to be looped on upstream
UTOPIA loop
Note: Transparent loop: Data is looped and forwarded.
Non-transparent loop: Data is looped.
Note: For ATM ports with upstream UTOPIA loopback (pcfN[p_atm] = 1 and
pcfN[p_ulp] = 1), all cells are looped regardless of their VCI value. The vci_flt_ulp
and vci_val_ulp[4:0] bits are don’t care.
Data Sheet
164
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.12
Cell Fill Register for Partially Filled Cells (cfil)
Read/write Address 00012H
Reset value: 0000H
15
8
Not used
7
0
cfil[7:0]
cfil
Data Sheet
Dummy fill octet for partially filled cells
165
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.13
Interrupt Mask Register 1 (imr1)
Read/write Address 00013H
Reset value: FFFFH
15
8
imr1[15:8]
7
0
imr1[7:0]
imr1
Data Sheet
Each bit masks the corresponding bit in isr1
0=
Not masked
1=
Masked
166
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.14
Timer Enable Register (time)
Read/write Address 00014H
Reset value: 0000H
15
8
Not used
7
0
Not used
tim_set2
_en
tim_set2_en Timer set 2 enable
Data Sheet
0=
Disabled
1=
Enabled
167
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.15
Cell Delineation FSM Status Register (cdfs)
Read only Address 00015H
Reset value: 0000H
15
8
status_p7[1:0]
status_p6[1:0]
status_p5[1:0]
7
0
status_p3[1:0]
status_pN
status_p4[1:0]
status_p2[1:0]
status_p1[1:0]
status_p0[1:0]
Cell Delineation FSM status of port N
XX = When pcfN[p_atm] = 0
Data Sheet
00 =
Hunt
01 =
Presync
10 =
Sync
168
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.16
Read only
Version Register (vers)
Address 00016H
15
9
Not used
mtypsel
7
ec
mtypsel
ec
e1/t1
version
Data Sheet
8
0
e1/t1
version[5:0]
Microcontroller type select
0=
Microcontroller Interface runs in Intel Mode
1=
Microcontroller Interface runs in Motorola Mode
Status of EC pin
0=
Echo Cancellation mode(EC)
1=
Normal operation mode
Status of E1/T1 pin
0=
T1 mode
1=
E1 mode
Version of IWE8
Value of 011 010B for Version 3.2
169
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.17
Clock Monitor Register (ckmo)
Read only Address 00017H
Reset value: 0000H
15
8
Not used
7
0
frclk_failure[7:0]
frclk_failure FRCLK clock failure on port N
Bit remains active only as long as a clock failure on FRCLK is detected.
Data Sheet
0=
False
1=
True
170
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PXB4219 / PXB4220 / PXB4221
Register Description
7.18
Interrupt Status Register 1 (isr1)
Read only, Address 00018H
Reset value: 0000H
15
iq_ne
8
eis4
eis3
eis2
eis1
eis0
Not used
7
Not used
iq_ne
eis4
eis3
eis2
eis1
eis0
ut_soc
Data Sheet
0
ut_soc
ut_par
ex_par
crv_par
oq_ovf
eq_ovf
ck_eme
Interrupt queue not empty
0=
False
1=
True
A bit is set in eis4
0=
False
1=
True
A bit is set in eis3
0=
False
1=
True
A bit is set in eis2
0=
False
1=
True
A bit is set in eis1
0=
False
1=
True
A bit is set in eis0
0=
False
1=
True
UTOPIA start of cell error,
indicates if SOC is activated too late or twice within one cell cycle.
(corresponds to transmit direction in slave mode and receive direction in
master mode).
0=
False
1=
True
171
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Register Description
ut_par
Parity error on UTOPIA bus
ex_par
Parity error on external RAM
In order to prevent external RAM parity errors, the external RAM should
be written completely during board initialization by the microprocessor.
crv_par
oq_ovf
eq_ovf
ck_eme
0=
False
1=
True
Parity error on clock recovery interface
0=
False
1=
True
Output queue overflow
0=
False
1=
True
Error queue overflow
0=
False
1=
True
Emergency mode state change on one of the emergency mode enabled
ports (see ckmo)
0=
False
1=
True
Note: Bits 6:0 are used for tracing error events. They are set on the occurrence of an
error event and reset by a microprocessor read operation.
Bits 15:10 Bits are reset upon reading of the interrupt generating register.
Data Sheet
172
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PXB4219 / PXB4220 / PXB4221
Register Description
7.19
Extended Interrupt Status 1 Register (eis1)
Destructive read Address 00019H
Reset value: 0000H
15
8
Not used
7
0
Not used
cf_fifo_full
cf_fifo_n_
empty
Data Sheet
cf_fifo_
n_empty
cf_fifo_
full
Cell filter FIFO full
0=
False
1=
True
Cell filter FIFO not empty
0=
False
1=
True
173
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.20
Extended Interrupt Status 2 Register (eis2)
Destructive read Address 0001AH
Reset value: 0000H
15
8
Not used
7
0
rts_overflow[7:0]
rts_overflow RTS buffer overflow of IWE core at port N
Applicable for AAL ports in unstructured CES mode with SRTS.
Data Sheet
X=
When pcfN[p_atm] = 1 or pcfN[p_ces] = 0 or pcfN[p_srts] = 0
0=
False
1=
True
174
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.21
Extended Interrupt Status 3 Register (eis3)
Destructive read Address 0001BH
Reset value: 0000H
15
8
Not used
7
0
tim_set1_exp[7:0]
tim_set1_
exp
Data Sheet
Timer of set 1 expired
Each bit indicates if the corresponding timer expired
0=
False
1=
True
175
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.22
Extended Interrupt Status 4 Register (eis4)
Destructive read Address 0001CH
Reset value: 0000H
15
8
ocd_end[7:0]
7
0
ocd_start[7:0]
ocd_end
ocd_start
Data Sheet
End of OCD (Out of cell delineation) state at port N
X=
When pcfN[p_atm] = 0
0=
False
1=
True
Start of OCD (Out of cell delineation) state at port N
X=
When pcfN[p_atm] = 0
0=
False
1=
True
176
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.23
Interrupt Status Register 2 (isr2)
Destructive read Address 0001DH
Reset value: 0000H
15
8
Not used
7
0
tim_set2_exp[7:0]
t
tim_set2_
exp
Data Sheet
Timer of timer set 2 expired
Each bit indicates if the corresponding timer expired
0=
False
1=
True
177
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.24
Operation Mode Register (opmo)
Read/write Address 0001EH
Reset value 1100H
15
8
Not used
symn
rts_gen
rts_eval
bufthr[3:1]
7
bufthr0
symn
rts_gen
rts_eval
0
tfpp
rfpp
ftri
frri
om[1:0]
cbb
SYMn mode
This bit is relevant only in SYM2 and SYM8
0=
FRMFB[0] is used for frame and multiframe synchronization in
receive and transmit direction of all ports. FRMFB[1:7] are
unused
1=
FRMFB[N] is used for frame and multiframe synchronization in
receive and transmit direction of corresponding ports
RTS generation
0=
Pin SDI is used for RTS
1=
RTS data are generated by ICRC
RTS evaluation
0=
Pins FTCKO are used as transmit clock (FTCKO[0:7] are input
pins)
1=
Clock of ICRC is used as transmit clock and is also switched to
FTCKO pins (FTCKO[0:7] are output pins)
bufthr
Buffer threshold
Determines the threshold for the ATM Transmit Buffer. If the buffer level
remains under the threshold the signal ATBTC will be activated.
tfpp
Transmit frame pulse polarity
valid for GIM
rfpp
0=
FTMFS is active low
1=
FTMFS is active high
Receive frame pulse polarity
valid for GIM, SYM8 and SYM2
0=
Data Sheet
FRMFB is active low
178
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
1=
ftri
frri
FRMFB is active high
Framer transmit rising edge
valid for GIM
0=
FTDAT outputs are clocked with the falling edge of FTCKO
1=
FTDAT outputs are clocked with the rising edge of FTCKO
Framer receive rising edge
valid for GIM:
0=
FRDAT inputs are sampled with the falling edge of FRCLK
1=
FRDAT inputs are sampled with the rising edge of FRCLK
valid for SYM2:
om
cbb
1)
0=
FRDAT inputs are sampled with the falling edge of RFCLK
FTDAT outputs are clocked with the rising edge of RFCLK
1=
FRDAT inputs are sampled with the rising edge of RFCLK
FTDAT outputs are clocked with the falling edge of RFCLK
Operation Mode
00 =
FAM: FALC mode
FTCKO and FRCLK running at 8.192 MHz
01 =
GIM: Generic Interface mode1)
FTCKO and FRCLK running at 2.048 (E1) or 1.544 (T1) MHz
10 =
SYM8: E1 synchronous mode (RFCLK = 8.192 MHz)
11 =
SYM2: E1 synchronous mode (RFCLK = 2.048 MHz)
Clock Boost Bypass
0=
Normal operation: the external clock at RFCLK in internally
doubled to serve as reference clock for the internal DPLL
1=
Clock boost function bypassed
Make sure that no clocks are applied to the transmitter when switching to GIM.
Data Sheet
179
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.25
FT Clock Select Register (ftcs)
Read/write Address 0001FH
Reset value 0000H
15
8
ftck7[1:0]
ftck6[1:0]
ftck5[1:0]
ftck4[1:0]
7
0
ftck3[1:0]
ftcki
ftck2[1:0]
ftck1[1:0]
ftck0[1:0]
Clock Source for framer transmit interface
valid for FAM and GIM
00 =
FTCKOi if opmo[rts_eval]=0
Recovered Clock of ICRC if opmo[rts_eval]=1
01 =
FRCLKi
10 =
Derived from RFCLK
11 =
No clock
Note: Register opmo has to be set before ftcs is configured.
Data Sheet
180
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.26
Cell Filter VCI Pattern 1 Register (cfvp1)
Read/write Address 20H
Reset value: 0000H
15
8
vci_pattern1[15:8]
7
0
vci_pattern1[7:0]
vci_pattern1 First VCI pattern the cell header is compared with.
Data Sheet
181
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.27
Cell Filter VCI Mask 1 Register (cfvm1)
Read/write Address 00021H
Reset value: 0000H
15
8
vci_mask1[15:8]
7
0
vci_mask1[7:0]
vci_mask1
Data Sheet
Each bit masks the corresponding bit in cfvp1
0=
Not masked
1=
Masked
182
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.28
Cell Filter VCI Pattern 2 Register (cfvp2)
Read/write Address 00022H
Reset value: 0000H
15
8
vci_pattern2[15:8]
7
0
vci_pattern2[7:0]
vci_pattern2 Second VCI pattern the cell header is compared with.
Data Sheet
183
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.29
Cell Filter VCI Mask 2 Register (cfvm2)
Read/write Address 00023H
Reset value: 0000H
15
8
vci_mask2[15:8]
7
0
vci_mask2[7:0]
vci_mask2
Data Sheet
Each bit masks the corresponding bit in cfvp2
0=
Not masked
1=
Masked
184
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.30
Cell Filter Payload Type Register (cfpt)
Read/write Address 00024H
Reset value: 0000H
15
8
Not used
pt_pattern2[2:0]
pt_mask
2[2]
7
0
pt_mask2[1:0]
pt_mask1
pt_pattern1[2:0]
pt_mask1[2:0]
Each bit masks the corresponding bit in pt_pattern1.
0=
Not masked
1=
Masked
pt_pattern1
First PT pattern the cell header is compared with.
pt_mask2
Each bit masks the corresponding bit in pt_pattern2.
pt_pattern2
Data Sheet
0=
Not masked
1=
Masked
Second PT pattern the cell header is compared with.
185
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.31
Command Register (cmd)
Read/write Address 00025H
Reset value 0000H
15
8
Not used
7
0
Not used
vci1_comp
vci2_comp
pt1_comp
pt2_comp
insert_cell
Data Sheet
insert_
cell
pt2_
comp
pt1_
comp
vci2_
comp
vci1_
comp
VCI comparison corresponding to register cfvp1 and cfvm1.
0=
Disabled
1=
Enabled
VCI comparison corresponding to register cfvp2 and cfvm2.
0=
Disabled
1=
Enabled
PT comparison corresponding to fields pt_pattern1 and pt_mask1 in
register cfpt.
0=
Disabled
1=
Enabled
PT comparison corresponding to fields pt_pattern2 and pt_mask2 in
register cfpt.
0=
Disabled
1=
Enabled
Cell insertion via microprocessor.
A cell will be inserted in the data stream as soon as possible; when
finished this bit will be reset.
0=
Disabled
1=
Enabled
186
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.32
Cell Filter Read Pointer Register (cfrp)
Read/write Address 00026H
Reset value 0002H
15
8
Not used
7
0
rdptr[7:0]
rdptr
Read Pointer for the Cell Extraction Buffer
02H
to
FFH
Data Sheet
This value is a pointer to the current address, at which the
microprocessor will read the next extracted cell from the Cell
Extraction Buffer
187
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.33
Threshold Register (thrshld)
Read/write Address 00027H
Reset value 00FFH
15
8
Not used
7
0
threshold[7:0]
threshold
Global ATM transmit buffer threshold for discarding cells
00H
to
FFH
Data Sheet
If the amount of cells stored in the ATM transmit buffer crosses
this value cells will be discarded.
188
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.34
UTOPIA Configuration Register (utconf)
Read/write Address 00028H
Reset value 0001H
15
8
Not used
utrange[2:0]
utprtyen
utbaseadr[4:3]
7
0
utbaseadr[2:0]
utrange
utprtyen
utlevel
utmaster
mapping_mode[2:0]
UTOPIA Port Range
Controls the supported port range if the device is configured as UTOPIA
level 2 PHY-Layer (utlevel=0, utmaster=0, mapping_mode=000B)
000 =
Ports 0 to 7 enabled
001 =
Port 0 enabled
010 =
Ports 0 and 1 enabled
011 =
Ports 0 to 2 enabled
100 =
Ports 0 to 3 enabled
101 =
Ports 0 to 4 enabled
110 =
Ports 0 to 5 enabled
111 =
Ports 0 to 6 enabled
UTOPIA parity check enable
0=
Disabled
1=
Enabled
utbaseadr
UTOPIA base address
Defines the base address under which the PHY-Layer is accessible.
Set to 0 if device utlevel = 1.
utlevel
UTOPIA interface level
In Master mode only UTOPIA level 1 is available.
utmaster
Data Sheet
0=
UTOPIA level 2
1=
UTOPIA level 1
UTOPIA Slave/Master configuration
0=
Slave mode (PHY-Layer)
1=
Master mode (ATM-Layer)
189
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
mapping
_mode
Data Sheet
Mapping of the “port_nr” associated with the currently transferred cell
into the UTOPIA datastream
000 =
Disabled
001 =
Mapping to UDF[2:0] field in ATM header
010 =
Mapping toVCI[7:5] field in ATM header
011 =
Mapping toVCI[15:13] field in ATM header
100 =
Mapping toVPI[7:5] field in ATM header
101 =
Mapping toGFC[3:1] field in ATM header
190
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.35
CAS 1 Register (cas1)
Read/write Address 00029H
Reset value: BBBBH
15
8
cas0port3[3:0]
cas0port2[3:0]
7
0
cas0port1[3:0]
cas0port0[3:0]
cas0port0
E1 CAS frame 0 pattern for port 0 (unused in T1 mode)
cas0port1
E1 CAS frame 0 pattern for port 1 (unused in T1 mode)
cas0port2
E1 CAS frame 0 pattern for port 2 (unused in T1 mode)
cas0port3
E1 CAS frame 0 pattern for port 3 (unused in T1 mode)
Data Sheet
191
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.36
CAS 2 Register (cas2)
Read/write Address 0002AH
Reset value: BBBBH
15
8
cas0port7[3:0]
cas0port6[3:0]
7
0
cas0port5[3:0]
cas0port4[3:0]
cas0port4
E1 CAS frame 0 pattern for port 4 (unused in T1 mode)
cas0port5
E1 CAS frame 0 pattern for port 5 (unused in T1 mode)
cas0port6
E1 CAS frame 0 pattern for port 6 (unused in T1 mode)
cas0port7
E1 CAS frame 0 pattern for port 7 (unused in T1 mode)
Data Sheet
192
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.37
CAS 3 Register (cas3)
Read/write Address 0002BH
Reset value: 000DH
15
8
Not used
7
0
Not used
cas_idle
Data Sheet
cas_idle
CAS idle pattern for unused timeslots of the Tx frame
193
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.38
Threshold Register for Ports 0 and 1 (thrsp01)
Read/write Address 0002CH
Reset value: FFFFH
15
8
p_odd[7:0]
7
0
p_even[7:0]
p_odd
Port 1 threshold for backpressure of UTOPIA Tx
p_even
Port 0 threshold for backpressure of UTOPIA Tx
Data Sheet
194
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.39
Threshold Register for Ports 2 and 3 (thrsp23)
Read/write Address 0002DH
Reset value: FFFFH
15
8
p_odd[7:0]
7
0
p_even[7:0]
p_odd
Port 3 threshold for backpressure of UTOPIA Tx
p_even
Port 2 threshold for backpressure of UTOPIA Tx
Data Sheet
195
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.40
Threshold Register for Ports 4 and 5 (thrsp45)
Read/write Address 02EH
Reset value: FFFFH
15
8
p_odd[7:0]
7
0
p_even[7:0]
p_odd
Port 5 threshold for backpressure of UTOPIA Tx
p_even
Port 4 threshold for backpressure of UTOPIA Tx
Data Sheet
196
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.41
Threshold Register for Ports 6 and 7 (thrsp67)
Read/write Address 0002FH
Reset value: FFFFH
15
8
p_odd[7:0]
7
0
p_even[7:0]
p_odd
Port 7 threshold for backpressure of UTOPIA Tx
p_even
Port 6 threshold for backpressure of UTOPIA Tx
Data Sheet
197
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.42
Extended Interrupt Status 0 Register (eis0)
Destructive Read Address 00030H
Reset value: 0000H
15
8
lcd_end[7:0]
7
0
lcd_start[7:0]
lcd_end
lcd_start
Data Sheet
End of LCD detect on port N
0=
False
1=
True
Start of LCD detect on port N
0=
False
1=
True
198
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.43
LCD Timer Register (lcdtimer)
Read/write Address 00031H
Reset value: FFFFH
15
8
lcd_val[14:7]
7
0
lcd_val[6:0]
lcd_dis
lcd_val
LCD timer preload value
The port specific LCD timer is pre-loaded with 128 * lcd_val and clocked
with CLOCK. After expiration an interrupt is issued in eis0.
lcd_dis
LCD timer disable
Data Sheet
0=
Enabled
1=
Disabled
199
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.44
Interrupt Source Register (irs)
Read only Address 00101H
Reset value: 0000H
15
8
Not used
irs7
irs6
7
irs4
irsN
crifo
scri
per
irs5
0
irs3
irs2
irs1
irs0
crifo
scri
per
IRS register of port N
These bits indicate if a bit is set in irsN
0=
False
1=
True
Clock recovery interface FIFO overflow
This bit indicates if a bit is set in crifo
0=
False
1=
True
Synchronization errors at the internal clock recovery interface
This bit indicates if a bit is set in scri
0=
False
1=
True
Parity errors at the clock recovery interface.
This bit indicates if a bit is set in per
0=
False
1=
True
Bits are reset after reading the corresponding registers.
Data Sheet
200
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.45
Interrupt Mask (irm)
Read/Write Address 00102H
Reset value: 07FFH
15
8
Not used
irm7
irm6
7
irm4
irmN
crifo
scri
per
Data Sheet
irm5
0
irm3
irm2
irm1
irm0
crifo
scri
per
Each bit masks the corresponding irsN in irs
0=
Not masked
1=
Masked
This bit masks the bit crifo in irs
0=
Not masked
1=
Masked
This bit masks the bit scri in irs.
0=
Not masked
1=
Masked
This bit masks the bit per in irs
0=
Not masked
1=
Masked
201
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.46
Internal Clock
(icrcconf)
Recovery
Circuit
Configuration
Register
Read/Write Address 00103H
Reset value: 0020H
15
8
Not used
gim
7
ds1
gim
ds1
parc
pdcri
srst
lptd
Data Sheet
0
parc
pdcri
srst
lptd
lptu
lprd
lpru
Generic interface mode
0=
FAM: 8.192 MHz is expected/generated.
1=
GIM: 2.048 MHz (E1) or 1.544 MHz (T1) expected/generated.
DS1 Mode
0=
E1: The receive clocks are divided to 2.048 MHz. Output clocks
are 8.192 MHz in case of FAM or 2.048 MHz in case of GIM.
1=
T1: The receive clocks are divided to 1.544 MHz. Output clocks
are 8.192 MHz in case of FAM or 1.544 MHz in case of GIM.
Parity Check
Inverts all parity bits in the ICRC. All enabled parity checkers will
generate interrupts
0=
Disabled
1=
Enabled
Power Down Clock Recovery Interface
0=
Normal operation
1=
The internal clock recovery interface is put in power down mode.
No data is received, no errors are generated and the parity check
is disabled.
Software Reset
The bit srts is set by the software, but reset by the ICRC. Reading this
bit will always give the Reset value: “0”.
0=
Normal operation
1=
Reset ICRC
Loop back clock recovery interface transmitted data downstream
202
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
lptu
lprd
lpru
Data Sheet
0=
Disabled
1=
Enabled
Loop back clock recovery interface transmitted data upstream
0=
Disabled
1=
Enabled
Loop back clock recovery interface received data downstream
0=
Disabled
1=
Enabled
Loop back clock recovery interface received data upstream
0=
Disabled
1=
Enabled
203
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.47
Configuration Register Downstream of Port N (condN)
Read/Write Address 00104H + N x 32
Reset value: 0840H
15
8
not used
tur[5:1]
7
tur(0]
0
pwd
lgc
lc8
lgs
lpcr
srt
acm
tur
Tuning range select of port N
The tuning range of PLL-ACM is limited to:
(frequency deviation of pin RFCLK in ppm) +/- ((4*tur) +/-5%)ppm.
pwd
Power down of port N
lgc
lc8
lgs
lpcr
srt, acm
0=
Normal operation
1=
Power down mode. No RTS values and no transmit clock are
generated.
Loop back generated clock
0=
Normal operation
1=
The clock generated by the PLL is looped into the RTS generator.
Loop back clock 8.192 MHz
0=
Normal operation
1=
The receive clock is looped to the transmit output of the ICRC.
Loop back generated RTS
0=
Normal operation
1=
Generated RTS values are looped into the SRTS Receive FIFO.
Loop back clock recovery Interface
0=
Normal operation
1=
The clock recovery interface is bypassed. RTS values from the
frame receiver are looped into the SRTS Transmit FIFO.
Selectors for the clock generation algorithm
00 =
Data Sheet
The PLL is put in power down mode, and a free running clock is
generated. In case pwd is set, all circuits of the port, including the
RTS generator are disabled, no output clock is generated and all
error counters are reset.
204
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
Data Sheet
01 =
Transmit clock generation of this port is based on the adaptive
clock algorithm
10 =
Transmit clock generation of this port is based on the SRTS
algorithm.
11 =
Transmit clock generation of this port is based on both
algorithms. The tuning range of PLL-ACM can not be reduced
(tur), because PLL-ACM has to accept the jitter passed through
or generated in PLL-SRTS.
205
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.48
Read only
Interrupt Source of Port N (irsN)
Address 00105H + N x 32
Reset value: 0000H
15
8
not used
7
not used
srrn
tsoutn
srun
sron
srin
atln
ooln
0
srrn
tsoutn
srun
sron
srin
atln
ooln
A bit is set in srrn.
0=
False
1=
True
A bit is set in tsoutN.
0=
False
1=
True
A bit is set in sruN
0=
False
1=
True
A bit is set in sroN.
0=
False
1=
True
A bit is set in sriN.
0=
False
1=
True
A bit is set in atlN.
0=
False
1=
True
A bit is set in oolN.
0=
False
1=
True
Bits are reset upon reading of the interrupt generating register.
Data Sheet
206
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.49
Interrupt Mask of Port N (irmN)
Read/Write Address 00106H + N x 32
Reset value: 007FH
15
8
not used
7
not used
srrn
tsoutn
srun
sron
srin
atln
ooln
Data Sheet
0
srrn
tsoutn
srun
sron
srin
atln
ooln
This bit masks the bit srrN in irsN
0=
Not masked
1=
Masked
This bit masks the bit tsoutN in irsN
0=
Not masked
1=
Masked
This bit masks the bit sruN in irsN.
0=
Not masked
1=
Masked
This bit masks the bit sroN in irsN
0=
Not masked
1=
Masked
This bit masks the bit sriN in irsN
0=
Not masked
1=
Masked
This bit masks the bit atlN in irsN
0=
Not masked
1=
Masked
This bit masks the bit oolN in irsN
0=
Not masked
1=
Masked
207
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.50
Test Input of Port N (tsinN)
Read/Write Address 00107H + N x 32
Reset value: 0000H
15
8
not used
7
0
not used
rtsi[3:0]
ena
rtsi
RTS Input value of port N
ena
Test Input Enable
Disconnect the RTS generator from the transmit FIFO. Each write
command to this register injects the value rtsi into the transmit FIFO.
0=
Disabled
1=
Enabled:
Successive writes to this register should have a minimum distance of 8 x 32 x TCLOCK.
This is the (maximum) time needed to transmit the value rtsi to the clock recovery. In
case bit lgs of register condN is set, this waiting time is not necessary.
Data Sheet
208
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.51
Configuration Register Upstream Direction of Port N (conuN)
Read/Write Address 00108H + N x 32
Reset value: 0000H
15
8
not used
7
0
not used
rtsg
.
rtsg
Data Sheet
RTS generator enable
0=
Disabled
1=
Enabled
209
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.52
Average Buffer Filling of Port N (avbN)
Read/Write Address 0010CH + N x 32
Reset value: 2000H
15
8
not used
avb[13:8]
7
0
avb[7:0]
avb
Data Sheet
Average buffer filling of port N
This field defines the number of bytes ACM should try to keep in the data
buffer of the clock recovery. This value should correspond with the
number of bytes the clock recovery initially stores in the data buffer.
210
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.53
ACM Shift Factor of Port N (asfN)
Read/Write Address 0010DH + N x 32
Reset value: 0000H
15
8
not used
7
0
not used
dir
ampl
Data Sheet
dir
ampl[2:0]
Direction of shifting
0=
shift left = amplification
1=
shift right = attenuation
Amplitude of shifting
This defines the loop-gain of PLL-ACM. It is equivalent to a multiplication
with (or a division by) 2ampl.
211
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.54
Time of Initial Free Run of Port N (tiniN)
Read/Write Address 0010EH + N x 32
Reset value: 0400H
15
8
not used
tini[12:8]
7
0
tini[7:0]
tini[12:0] Time of initial free run of port N
Data Sheet
212
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.55
Threshold Out of Lock Detection of Port N (tresh)
Read/Write Address 0010FH + N x 32
Reset value: 0111H
15
8
not used
tr_filt[3:0]
7
0
tr_srts[3:0]
tr_acm[3:0]
tr_filt
Threshold for out of lock detection of PLL-FILTER
If more than tr_filt out of lock detections during 16 SRTS periods (128
ATM cells) are made, oolN[olf] is set
tr_srts
Threshold for out of lock detection of PLL-SRTS
If more than tr_srts out of lock detections during 16 SRTS periods (128
ATM cells) are made, oolN[ols] is set
tr_acm
Threshold for out of lock detection of PLL-ACM
If more than tr_acm out of lock detections during 16 ATM cells are made,
oolN[ola] is set.
Data Sheet
213
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.56
ICRC Parity Errors at Clock Recovery Interface (per)
Destructive read Address 00110H
Reset value: 0000H
15
8
perd[7:0]
7
0
peru[7:0]
perd
Parity Errors at the Clock Recovery Interface Downstream Pin SDOD
This field counts the amount of parity errors at the internal clock recovery
interface. In case there are more than 255 errors, the value is kept
peru
Parity Errors at the Clock Recovery Interface Upstream Pin SDI
This field counts the amount of parity errors at the internal clock recovery
interface. In case there are more than 255 errors, the value is kept
Note: A synchronization error (scri) generates a random number of parity errors
Data Sheet
214
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.57
ICRC Synchronization Errors at Clock Recovery Interface (scri)
Destructive read Address 00111H
Reset value: 0000H
15
8
not used
7
0
scri[7:0]
scri
Synchronization Error at the Clock Recovery Interface
This field counts the amount of synchronization errors at the internal
clock recovery interface. In case there are more than 255 errors, the
value is kept
Note: A synchronization error (scri) generates a random number of parity errors (per)
Data Sheet
215
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.58
ICRC Clock Recovery Interface FIFO Overflow (crifo)
Destructive read Address 00112H
Reset value: 0000H
15
8
not used
7
0
crifo[7:0]
crifo
Data Sheet
Clock Recovery Interface FIFO Overflow
This field counts the number of times the SRTS transmit FIFO overflows.
In case there are more than 255 errors, the value is kept
216
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.59
ICRC Version Register (icrcv)
Read only Address 00113H
Reset value: 0000H
15
8
not used
7
0
not used
ver
Version Number
rel
Release Number
Data Sheet
ver[2:0]
217
rel[2:0]
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.60
SRTS Receive FIFO Underflow of Port N (sruN)
Destructive read Address 00114H + N x 32
Reset value: 0000H
15
8
not used
7
0
sru[7:0]
sru
Data Sheet
SRTS Receive FIFO underflow of port N
This field counts the amount of underflows of the SRTS Receive FIFO.
Upon reaching FFH it keeps its value.
218
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.61
SRTS Receive FIFO Overflow of Port N (sroN)
Destructive read Address 00115H + N x 32
Reset value: 0000H
15
8
not used
7
0
sro[7:0]
sro
Data Sheet
SRTS Receive FIFO overflow of port N
This field counts the amount of overflows of the SRTS Receive FIFO.
Upon reaching FFH it keeps its value.
219
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.62
SRTS Generator Reset of Port N (srrN)
Destructive read Address 00116H + N x 32
Reset value: 0000H
15
8
not used
7
0
srr[7:0]
srr
Data Sheet
SRTS generator reset command counter of port N
This field counts the number of times the SRTS generator is reset by
frame receiver 1. Upon reaching FFH it keeps its value.
220
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.63
SRTS Invalid Value Processed of Port N (sriN)
Destructive read Address 00117H + N x 32
Reset value: 0000H
15
8
not used
7
0
sri[7:0]
sri
Data Sheet
SRTS invalid value processed counter of port N
This field counts the number of times PLL-SRTS and PLL-FILTER went
in hold over due to invalid RTS values. Upon reaching FFH it keeps its
value.
221
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.64
ACM Data Too Late of Port N (atlN)
Destructive read Address 00118H + N x 32
Reset value: 0000H
15
8
not used
7
0
atl[7:0]
atl
Data Sheet
ACM data too late error counter of port N
This field counts the number of times the next ACM data arrived more
than 10 ms too late. Upon reaching FFH it keeps its value.
222
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.65
Out Of Lock Register of Port N (oolN)
Destructive read Address 00119H + N x 32
Reset value: 0000H
15
8
not used
7
0
not used
olf
ols
ola
Data Sheet
olf
ols
ola
PLL-Filter out of lock at port N
This bit indicates that the number of times PLL-FILTER went out of lock
exceeds treshN[tr_filt].
0=
False
1=
True
PLL-SRTS out of lock at port N
This bit indicates that the number of times PLL-SRTS went out of lock
exceeds treshN[tr_srts].
0=
False
1=
True
PLL-ACM out of lock at port N
This bit indicates that the number of times PLL-ACM went out of lock
exceeds treshN[tr_acm].
0=
False
1=
True
223
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.66
Status Register of Port N (statN)
Destructive read Address 0011AH + N x 32
Reset value: 0001H
15
8
not used
7
0
not used
max
hov
frr
Data Sheet
max
hov
frr
Maximum frequency deviation
Indicates that PLL-ACM is clipped at its maximum frequency deviation.
0=
False
1=
True
Hold over
Indicates that PLL-SRTS is put in hold over because of error conditions
in the SRTS processing.
0=
False
1=
True
Free running clock
Indicates that PLL-SRTS or PLL-ACM is put in free run during start-up.
0=
False
1=
True
224
2002-05-06
PXB4219 / PXB4220 / PXB4221
Register Description
7.67
Test Output Register of Port N (tsoutN)
Destructive read Address 0011BH + N x 32
Reset value: 0000H
15
8
not used
7
0
not used
rtso[3:0]
dav
rtso
RTS test output value of port N
If bit ena from register tsinN is set: RTS value at the output of the SRTS
Receive FIFO of this port.
dav
Data available
SRTS Receive FIFO of this port is not empty
0=
False
1=
True
Note: By verifying bit dav, the SRTS Receive FIFO can be read completely by
successive reads of this register.
Data Sheet
225
2002-05-06
Figure 38
Data Sheet
E1
/
T1
E1
E1
E1
E1
E1
E1
E1
E1
E1
E1
E1
E1
E1
E1
E1
T1
T1
T1
T1
T1
T1
T1
T1
T1
T1
T1
T1
T1
T1
T1
om
00
00
00
00
00
00
01
01
01
01
01
01
10
11
x
00
00
00
00
00
00
01
01
01
01
01
01
10
11
x
rts_
ftcki eval
RFCLK
FRCLK[0:7]
FTCKO[0:7]
00 00
32.768 MHz OEC
8.192 MHz
8.192 MHz
01 01
32.768 MHz OEC
8.192 MHz
FRCLK[0:7]
10 01
32.768 MHz
8.192 MHz
00 01
32.768 MHz +/- 50ppm 8.192 MHz 8.192 MHz from ICRC
00 01 32.768 MHz +/- 130ppm 8.192 MHz 8.192 MHz from ICRC
00 00
32.768 MHz OEC
8.192 MHz 8.192 MHz from ECRC
00 00
32.768 MHz OEC
2.048 MHz
2.048 MHz
01 01
32.768 MHz OEC
2.048 MHz
FRCLK[0:7]
10 01
32.768 MHz
2.048 MHz
RFCLK / 16
00 01
32.768 MHz +/- 50ppm 2.048 MHz 2.048 MHz from ICRC
00 01 32.768 MHz +/- 130ppm 2.048 MHz 2.048 MHz from ICRC
00 00
32.768 MHz OEC
2.048 MHz 2.048 MHz from ECRC
x
x
8.192 MHz FIC
unused
unused
x
x
2.048 MHz FIC
unused
unused
x
x
8.192 MHz FIC
unused
unused
00 00
32.768 MHz OEC
8.192 MHz
8.192 MHz
01 01
32.768 MHz OEC
8.192 MHz
FRCLK[0:7]
10 01
32.768 MHz
8.192 MHz
00 01
32.768 MHz +/- 50ppm 8.192 MHz 8.192 MHz from ICRC
00 01 32.768 MHz +/- 130ppm 8.192 MHz 8.192 MHz from ICRC
00 00
32.768 MHz OEC
8.192 MHz 8.192 MHz from ECRC
00 00
24.704 MHz OEC
1.544 MHz
1.544 MHz
01 01
24.704 MHz OEC
1.544 MHz
FRCLK[0:7]
10 01
24.704 MHz
1.544 MHz
RFCLK / 16
00 01
24.704 MHz +/- 50ppm 1.544 MHz 1.544 MHz from ICRC
00 01 24.704 MHz +/- 130ppm 1.544 MHz 1.544 MHz from ICRC
00 00
24.704 MHz OEC
1.544 MHz 1.544 MHz from ECRC
x
x
unused
unused
unused
x
x
unused
unused
unused
x
x
unused
unused
unused
BITS (cbb=0)
CLK52
unused
unused
unused
51.84 MHz +/- 250ppm
unused
unused
unused
unused
unused
51.84 MHz +/- 250ppm
unused
unused
unused
unused
unused
unused
unused
unused
51.84 MHz +/- 250ppm
unused
unused
unused
unused
unused
51.84 MHz +/- 250ppm
unused
unused
unused
unused
unused
PINS
CLOCK
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
12*FDATA < FCLOCK < 39MHz
unused
unused
unused
RXCLK
TXCLK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
<= CLOCK
unused
unused
unused
8
Application Hints
8.1
Clock Concept
226
FIC = Framer Interface Clock for Rx and Tx; OEC = Optional Emergency Clock; x = Don't care; ECRC = External Clock Recovery Circuit;
Clock
Recovery
none
none
none
SRTS
ACM
ECRC
none
none
none
SRTS
ACM
ECRC
none
none
none
none
none
none
SRTS
ACM
ECRC
none
none
none
SRTS
ACM
ECRC
none
none
none
Mode
Framer
Interface
FAM
FAM
FAM
FAM
FAM
FAM
GIM
GIM
GIM
GIM
GIM
GIM
SYM8
SYM2
EC
FAM
FAM
FAM
FAM
FAM
FAM
GIM
GIM
GIM
GIM
GIM
GIM
SYM8
SYM2
EC
PXB4219 / PXB4220 / PXB4221
Application Hints
Clock Concept
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
The PLLs for SRTS accept RFCLK deviations of at least + and - 50 ppm. However, in
case of switchover to emergency mode, RFCLK will be used to generate the line clock,
which has to fulfill specifications like "maximum 4.6 ppm deviation under ALL
circumstances". In this case RFCLK accuracy has to be 4.6 ppm.
Data Sheet
227
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
8.2
Translating AAL Statistics Counters into the ATM Forum CES
Version 2 MIB
Reset Statistics Counters and µP RAM variables before connection setup
atmfCESReassCells
Accumulated values from IWE8 Statistics Counter #2 destructive read accesses
atmfCESHdrErrors
Accumulated values from IWE8 Statistics Counter #6 destructive read accesses
atmfCESPointerReframes
CES Version 2.0 MIB recommends "This records the count of the number of events in
which the AAL1 reassembler found that an SDT pointer is not where it is expected, and
the pointer must be reacquired.“
"Pointer is not where it is expected" can mean.
a) no pointer occurs within an 8-cell-cycle
b) two pointers occur within an 8-cell-cycle
c) pointer is not in the 2nd byte of ATM cell payload,
Error case a) and b) causes incrementation of Statistics Counter #11.
All error cases a), b) and c) causes loss of synchronization of AtmStartOfStructure (IWE8
reassembly buffer read pointer to structure start in ATM cell) with PortStartOfStructure
(pointer to structure start in framer interface port), so that Statistics Counter #14
increments.
==> Accumulated values from IWE8 Statistics Counter #14 destructive read accesses.
atmfCESPointerParityErrors
Accumulated values from IWE8 Statistics Counter #10 destructive read accesses
atmfCESAal1SeqErrors
Accumulated values from IWE8 Statistics Counter #7 destructive read accesses
atmfCESLostCells
Accumulated values from IWE8 Statistics Counter #15 destructive read accesses
atmfCESMisinsertedCells
Accumulated values from IWE8 Statistics Counter #8 destructive read accesses
Data Sheet
228
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
atmfCESBufUnderflows
Can be derived from IWE8 Statistics Counter #13
atmfCESBufOverflows
Can be derived from IWE8 Statistics Counter #4
atmfCESCellLossStatus
Can be derived from atmfCESBufUnderflows and EndOfUnderflow
"When cells are continuously lost for the number of milliseconds specified by
atmfCESCellLossIntegrationPeriod, the value is set to loss (2). When cells are no longer
lost, the value is set to noLoss (1).“
Data Sheet
229
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
8.3
Jitter Characteristics of the Internal Clock Recovery Circuit
This section shows the results of jitter analysis of the ICRC. The device is intended to be
used with an external jitter attenuator. For this purpose Infineon’s FALC-LH was used.
Results are shown with and without jitter attenuator. Measurements were done using a
Wandel & Goltermann ANT20 for IWE8 in T1 mode with FALC-LH and Wandel &
Goltermann PFJ-8 for the bare IWE8 in E1 or T1 mode.
8.3.1
ACM Jitter Tolerance in E1 Mode
The jitter tolerance falls with 20 dB per decade, It is independent from the PLL gain
("ASF").
For the bare device the jitter tolerance meets the requirements of ITU-T G.823 and I.431
at medium and low frequencies. At frequencies lower than 1 KHz the jitter tolerance is
more than 20 UI. At high frequencies it is lower than the requirements.
In combination with an jitter attenuator the requirements are met. Jitter tolerance at high
frequencies is better than 0.2 UI.
ACM Jitter Tolerance in E1 m ode, CDV=0, ASF=4
100,0
-50 ppm
0 ppm
Jitter [UI]
10,0
+50 ppm
1,0
ITU G.823
and I.431
0,1
1
Figure 39
Data Sheet
10
100
1000
10000
100000 1000000 Frequency [Hz]
ACM Jitter Tolerance in E1 Mode without Jitter Attenuator
230
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
E1, ACM, FALC jitter tolerance, CDV=0, ASF=4
100,0
-50 ppm
0 ppm
Jitter [UI]
10,0
+50 ppm
1,0
ITU G.823
and I.431
0,1
1
Figure 40
8.3.2
10
100
1000
10000
100000 1000000 Frequency [Hz]
ACM Jitter Tolerance in E1 Mode with Jitter Attenuator
ACM Jitter Tolerance in T1 Mode
The jitter tolerance of the bare device in T1 mode exceeds the capabilities of the
measurement equipment. This behavior is independent from frequency offset or PLL
gain.
Using the jitter attenuator slightly reduces the jitter tolerance to a level which can be
measured. All requirements are fulfilled.
Data Sheet
231
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
ACM Jitter Tolerance in T1 m ode, CDV=0, ASF=4
100
ITU G.824 and
I.431
Jitter [UI]
10
TR-NWT-499
1
Measurement
limitation
0,1
1
Figure 41
10
100
1000
10000
100000 1000000
Frequency [Hz]
ACM Jitter Tolerance in T1 Mode without Jitter Attenuator
ACM Jitter Tolerance in T1 Mode, CDV=0, ASF=4
100
-130 ppm
0 ppm
Jitter [UI]
10
+130 ppm
1
ITU G.824 and
I.431
TR-NWT-499
0,1
1
10
100
1000
10000
100000 1000000
Frequency [Hz]
Figure 42
ACM Jitter Tolerance in T1 Mode with Jitter Attenuator
Data Sheet
232
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
8.3.3
SRTS Jitter Tolerance in E1 Mode
The aliasing effect which is inherent to the SRTS algorithm causes the jitter tolerance at
681 Hz and all multiples of 681 Hz to be a copy of the jitter tolerance at 0 Hz.
The jitter tolerance of the bare device meets the requirements of ITU-T G.823 and I.431
only at medium and low frequencies. At high frequencies it is lower than the
requirements.
In combination with an jitter attenuator the tolerance at high frequencies is better than
0.2 UI. All requirements are met.
SRTS Jitter Tolerance in E1 Mode
100,0
-50 ppm
0 ppm
Jitter [UI]
10,0
+50 ppm
1,0
ITU G.823
and I.431
0,1
1
Figure 43
Data Sheet
10
100
1000
10000
100000 1000000
Freqency [Hz]
SRTS Jitter Tolerance in E1 Mode without Jitter Attenuator
233
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
SRTS Jitter Tolerance in E1 Mode
100
-50 ppm
0 ppm
Jitter [UI]
10
+50 ppm
1
ITU G.823
and I.431
0,1
1
Figure 44
8.3.4
10
100
1000
10000
100000 1000000
Frequency [Hz]
SRTS Jitter Tolerance in E1 Mode with Jitter Attenuator
SRTS Jitter Tolerance in T1 Mode
The aliasing effect which is inherent to the SRTS algorithm causes the jitter tolerance at
513 Hz and all multiples of 513 Hz to be a copy of the jitter tolerance at 0 Hz. Jitter
Tolerance at low frequencies violate the requirements.
With jitter attenuator jitter tolerance at low frequencies is increased and all jitter
frequencies above 20 Hz are removed. As a result no aliasing is possible. The jitter
tolerance fulfills the requirements.
Data Sheet
234
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
SRTS Jitter Tolerance in T1 Mode
100
-130 ppm
0 ppm
Jiiter [UI]
10
+130 ppm
1
ITU G.824
and I.431
TR-NWT-499
0,1
1
Figure 45
10
100
1000
10000
100000 1000000
Frequency [Hz]
SRTS Jitter Tolerance in T1 Mode without Jitter Attenuator
SRTS Jitter Tolerance in T1 Mode
100
-130 ppm
0 ppm
Jitter [UI]
10
+130 ppm
ITU G.824
and I.431
1
TR-NWT-499
0,1
1
10
100
1000
10000
100000 1000000
Frequency [Hz]
Figure 46
SRTS Jitter Tolerance in T1 Mode with Jitter Attenuator
Data Sheet
235
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
8.3.5
ACM Jitter Transfer in E1 Mode
The jitter transfer characteristics are much better than the requirements of ITU-T G.735
and I. 432.
The -3dB point of the transfer curve is proportional to the PLL-gain: 0.05 Hz for ASF=4,
0.2 Hz for ASF=16.
No impact of the jitter attenuator on the already very good jitter transfer behavior could
be measured.
ACM Jitter Transfer in E1 mode: ASF=4
10,0
-50 ppm
Transfer [dB]
0,0
0,01
-10,0
0,1
1
10
100
1000
0 ppm
-20,0
+50 ppm
-30,0
-40,0
ITU G.735
and I.431
-50,0
-60,0
Frequency [Hz]
Figure 47
Data Sheet
ACM Jitter Transfer in E1 Mode without Jitter Attenuator
236
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
ACM Jitter Transfer in E1 Mode: ASF=4
10,0
-50 ppm
Transfer [dB]
0,0
0,01
-10,0
0,1
1
10
100
1000
0 ppm
-20,0
+50 ppm
-30,0
-40,0
ITU G.735
and I.431
-50,0
-60,0
Frequency [Hz]
Figure 48
8.3.6
ACM Jitter Transfer in E1 Mode with Jitter Attenuator
ACM Jitter Transfer in T1 Mode
The jitter transfer characteristics are much better than the requirements of ITU-T G.735
and I. 432.
The -3dB point of the transfer curve is proportional to the PLL-gain: 0.075 Hz for ASF=4,
0.3 Hz for ASF=16.
The jitter attenuator improves the already very good jitter transfer behavior. At -130 ppm
all jitter is removed.
Data Sheet
237
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
ACM Jitter Transfer in T1 Mode: ASF=4
10,0
Transfer [dB]
0,0
0,01
-10,0
-130 ppm
0,1
1
10
100
1000
0 ppm
-20,0
-30,0
+130 ppm
-40,0
ITU G.735
and I.431
-50,0
-60,0
Frequency [Hz]
Figure 49
ACM Jitter Transfer in T1 Mode without Jitter Attenuator
ACM Jitter Transfer in T1 m ode: ASF=4
10,0
Transfer [dB]
0,0
0,01
-10,0
0 ppm
0,1
1
10
100
1000
-20,0
+130 ppm
-30,0
-40,0
ITU G.735
and I.431
-50,0
-60,0
Figure 50
Data Sheet
Frequency [Hz]
ACM Jitter Transfer in T1 Mode with Jitter Attenuator
238
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
8.3.7
SRTS Jitter Transfer in E1 Mode
The aliasing effect which is inherent to the SRTS algorithm causes the jitter transfer at
681 Hz and all multiples of 681 Hz to be a copy of the jitter transfer at 0 Hz. This violates
the requirements.
The jitter attenuator removes jitter frequencies above 20 Hz. There is no aliasing and the
requirements are met.
SRTS Jitter Transfer in E1 Mode
10,0
-50 ppm
Transfer [dB]
0,0
0,01
-10,0
0,1
1
10
100
1000
0 ppm
-20,0
-30,0
+50 ppm
-40,0
ITU G.735
and I.431
-50,0
-60,0
Figure 51
Data Sheet
Frequency [Hz]
SRTS Jitter Transfer in E1 Mode without Jitter Attenuator
239
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
SRTS Jitter Transfer
-50 ppm
10,0
Transfer [dB]
0,0
0,01
-10,0
0,1
1
10
100
1000
0 ppm
-20,0
-30,0
+50 ppm
-40,0
-50,0
ITU G.735
and I.431
-60,0
Frequency [Hz]
Figure 52
8.3.8
SRTS Jitter Transfer in E1 Mode with Jitter Attenuator
SRTS Jitter Transfer in T1 Mode
The aliasing effect which is inherent to the SRTS algorithm causes the jitter transfer at
513 Hz and all multiples of 513 Hz to be a copy of the jitter transfer at 0 Hz. This violates
the requirements.
However, the measurement equipment was not able to measure jitter transfer above 100
Hz and the expected peaking is not measured.
The jitter attenuator removes jitter frequencies above 20 Hz. There is no aliasing and the
requirements are met.
Data Sheet
240
2002-05-06
PXB4219 / PXB4220 / PXB4221
Application Hints
SRTS Jitter Transfer
-130 ppm
10,0
Transfer [dB]
0,0
0,01
-10,0
0,1
1
10
100
1000
0 ppm
-20,0
-30,0
+130 ppm
-40,0
-50,0
ITU G.735
and I.431
-60,0
Frequency [Hz]
Figure 53
SRTS Jitter Transfer in T1 Mode without Jitter Attenuator
SRTS Jitter Transfer in T1 Mode
10,0
Transfer [dB]
0,0
0,01
-10,0
0 ppm
0,1
1
10
100
1000
-20,0
+130 ppm
-30,0
-40,0
ITU G.735
and I.431
-50,0
-60,0
Frequency [Hz]
Figure 54
SRTS Jitter Transfer in T1 Mode with Jitter Attenuator
Data Sheet
241
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9
Electrical Characteristics
9.1
Absolute Maximum Ratings
Table 33
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Ambient temperature under bias
TA
-40 to 85
0
Junction temperature under bias
TJ
0 to 125
0
Storage temperature
Tstg
- 65 to 150
0
Supply voltage
VCC
- 0.5 to 3.6
V
Input voltage
(at any signal pin with respect to ground)
VI
- 0.5 to 5.5
V
Output voltage level
(at any signal pin with respect to ground)
VO
- 0.5 to 5.51)
V
ESD robustness2)
HBM: 1.5 kW, 100 pF
VESD,HBM 1000
C
C
C
V
1)
The maximum high output level is limited to VCC. Due to 5V I/O tolerance output signals might be pulled to 5V
level by external pull-up resistors.
2)
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
The RF Pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 V (versus VS or
GND). The high frequency performance prohibits the use of adequate protective structures.
Note: Stresses above those listed under “absolute maximum ratings” may cause
permanent damage to the device. Exposure to “absolute maximum rating”
conditions for extended periods may affect device reliability
Data Sheet
242
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.2
Operating Range
Parameter
Symbol
Limit Values
Min
Max
Unit
Remarks
Ambient temperature
TA
−40
85
°C
Supply voltage
VCC
3.15
3.45
V
3.3V ± 5%
Input voltage
VI
0
5.5
V
Output voltage
VO
0
5.5
V
5V I/O
tolerance
Input low voltage
VIL
0
0.8
V
Input high voltage
VIH
2.1
5.5
V
Data Sheet
243
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.3
Thermal Package Characteristics
Parameter
Symbol
Thermal package
resistance junction to
ambient without airflow
RJA(0,25) 25
Data Sheet
Limit Values
Unit
Test conditions
°C/W TA=25°C
244
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.4
DC Characteristics
Parameter
Symbol
Limit Value
Min
Max
Unit Test Condition
Input low voltage
VIL
0
0.8
V
Input high voltage
VIH
2.1
5.5
V
Output low voltage1)
VOL
0.4
V
IOL = 4 mA, 8 mA
Output high voltage1)
VOH
V
IOH = - 4 mA, - 8 mA
VCC - 0.6
Low-level input leakage ILLI
current
±1
µA
VI = VIL(min) = VSS
High-level input leakage IHLI3.3
IHLI5.5
current
±1
± 10
µA
µA
VI = VIH(VCC) = VCC
VI = VIH(max) = 5.5 V
±1
µA
High-impedance state
output current
IOZ
Pull up current2)
IPUA
1
12
µA
VCC = 3.3V,
VI = VIL(min) = VSS
Pull up current3)
IPUB
40
130
µA
VCC = 3.3V,
VI = VIL(min) = VSS
Pull down current4)
IPDA
1
12
µA
VCC = 3.3V,
VI = VIH(VCC) = VCC
Power supply current
during power-up
ICCPwrUp
700
mA
VCC = 3.3V,
inputs at VSS/VCC,
no output loads,
FCLOCK = 40 MHz
Average power supply
current 5)
ICC Typ.
330
mA
Average Power
dissipation 5)
PTyp.
1.10
W
VCC = 3.3V,
inputs at VSS/VCC,
no output loads,
FCLOCK = 25 MHz
1)
All Utopia output buffers are 8 mA.
2)
The current is applicable for all pins for which an type PUA has been specified in Chapter 2.2
3)
The current is applicable for all pins for which an type PUB has been specified in Chapter 2.2
4)
The current is applicable for all pins for which an type PDA has been specified in Chapter 2.2
5)
Not tested in production.
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
apply at Ta = 25 °C and the given supply voltage.
Data Sheet
245
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.5
Capacitances
Parameter
Symbol
Limit Value
Min
Unit Test Condition
Max
Input capacitance
CIN
10
pF
Output capacitance
COUT
15
pF
Note: The listed characteristics are not tested in production.
Data Sheet
246
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6
AC Characteristics
TA = -40 to 85 °C, VCC = 3.3 V ± 5%, VSS = 0 V
All inputs are driven
to VIH = 2.4 V for a logical “1” and
to VIL = 0.4 V for a logical “0”
All outputs are measured at VH = 2.0 V for a logical “1”and
at VL = 0.8 V for a logical “0”
The AC testing input/output waveforms are shown below.
Test Levels
VTH
Device
under
Test
VTL
CL
Timing Test
Points
Drive Levels
VIH
VIL
Figure 55
9.6.1
Input/Output Waveforms for AC Measurements
Clock and Reset Interface
1
CLOCK
2
CLK52
3
RESET
Figure 56
Clock and Reset Interface Timing Diagram
Table 34
Clock and Reset Interface AC Timing Characteristics
No.
1
1A
Parameter
Limit Values
Unit
Min
Typ
Max
GIM T1:
25,72
40
53,97
ns
others:
25,72
40
40,69
ns
TCLOCK: Period CLOCK
FCLOCK: Frequency CLOCK1)
Data Sheet
247
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 34
No.
Clock and Reset Interface AC Timing Characteristics (cont’d)
Parameter
Limit Values
Unit
Min
Typ
Max
GIM T1:
18,53
25
38,88
MHz
others:
24,58
25
38,88
MHz
2
TCLK52: Period CLK522)
-50 ppm
19.29
+50 ppm ns
2A
FCLK52: Frequency CLK52 2)
-50 ppm
51.84
+50 ppm MHz
3
Pulse width RESET low
3xTCLOCK
1)
The frequency should be equal or higher than RXCLK and TXCLK of the UTOPIA interface
2)
Only required if the Internal Clock Recovery Circuit is used for SRTS
9.6.2
Framer Interface
9.6.2.1
Framer Interface in FAM
Framer Receive Interface
1
RFCLK
2
FRCLK
3
3
FRFRS
4
5
6
7
FRDAT
FRMFB
Figure 57
Data Sheet
Framer Receive Interface Timing in FAM
248
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 35 Framer Receive Interface Timing in FAM
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
TRFCLK: Period RFCLK 1)
30,518
ns
1A
FRFCLK: Frequency RFCLK 1)
32,768
MHz
2
TFRCLK: Period FRCLK
- 130
ppm
122
+130
ppm
ns
2A
FFRCLK: Frequency FRCLK
- 130
ppm
8,192
+130
ppm
MHz
3
Delay FRCLK falling to FRFRS
3
32
ns
4
Setup time FRDAT before FRCLK
falling (center of bit period)
15
ns
5
Hold time FRDAT after FRCLK falling
(center of bit period)
15
ns
6
Setup time FRMFB before FRCLK
falling (center of bit period)
15
ns
7
Hold time FRMFB after FRCLK falling
(center of bit period)
15
ns
1)
In case the Internal Clock Recovery Circuit is used for SRTS, the frequency deviation should be +/- 10 ppm
Data Sheet
249
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Framer Transmit Interface
1
RFCLK
2
FTCKO
3
3
FTFRS
4
FTDAT
5
5
FTMFS
Figure 58
Framer Transmit Interface Timing in FAM
Table 36
Framer Transmit Interface Timing in FAM
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
TRFCLK: Period RFCLK 1)
30,518
ns
1A
FRFCLK: Frequency RFCLK 1)
32,768
MHz
2
TFTCKO: Period FTCKO
-130 ppm 122
+130
ppm
ns
2A
FFTCKO: Frequency FTCKO
-130 ppm 8,192
+130
ppm
MHz
3
Delay FTCKO in falling to FTFRS
3
32
ns
Delay FTCKO out falling to FTFRS
-3
32
ns
Delay FTCKO in falling to FTDAT
3
32
ns
Delay FTCKO out falling to FTDAT
-3
32
ns
Delay FTCKO in falling to FTMFS
3
32
ns
Delay FTCKO out falling to FTMFS
-3
32
ns
4
5
1)
In case the Internal Clock Recovery Circuit is used for SRTS, the frequency deviation should be +/- 10 ppm
Data Sheet
250
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.2.2
Framer Interface in GIM
Framer Receive Interface
1
RFCLK
2
FRCLK
FRFRS
4
5
6
7
FRDAT
FRMFB
Figure 59
Framer Receive Interface Timing in GIM
Table 37 Framer Receive Interface Timing in GIM
No.
Parameter
Limit Values
Min
1
1A
2
2A
TRFCLK: Period RFCLK
Typ
Unit
Max
1)
E1:
30,518
ns
T1:
40,478
ns
E1:
32,768
MHz
T1:
24,704
MHz
E1:
488
ns
T1:
647
ns
E1:
2,048
MHz
T1:
1,544
MHz
FRFCLK: Frequency RFCLK 1)
TFRCLK: Period FRCLK
FFRCLK: Frequency FRCLK
Data Sheet
251
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 37 Framer Receive Interface Timing in GIM (cont’d)
No.
Parameter
Limit Values
Min
Unit
Typ
Max
4
Setup time FRDAT before FRCLK
falling (center of bit period)
15
ns
5
Hold time FRDAT after FRCLK falling
(center of bit period)
15
ns
6
Setup time FRMFB before FRCLK
falling (center of bit period)
15
ns
7
Hold time FRMFB after FRCLK falling
(center of bit period)
15
ns
1)
In case the Internal Clock Recovery Circuit is used for SRTS, the frequency deviation should be +/- 10 ppm
Framer Transmit Interface
1
RFCLK
2
FTCKO
3
3
FTFRS
4
FTDAT
5
5
FTMFS
Figure 60
Framer Transmit Interface Timing in GIM
Table 38
Framer Transmit Interface Timing in GIM
No.
Parameter
Limit Values
Min
1
Typ
Unit
Max
TRFCLK: Period RFCLK1)
E1:
Data Sheet
30,518
252
ns
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 38
No.
Framer Transmit Interface Timing in GIM (cont’d)
Parameter
Limit Values
Min
T1:
1A
2A
4
5
1)
Max
40,478
ns
E1:
32,768
MHz
T1:
24,704
MHz
E1:
488
ns
T1:
647
ns
E1:
2,048
MHz
T1:
1,544
MHz
FRFCLK: Frequency RFCLK 1)
TFTCKO: Period FTCKO
2
3
Typ
Unit
FFTCKO: Frequency FTCKO
Delay FTCKO in falling to FTFRS
3
32
ns
Delay FTCKO out falling to FTFRS
-3
32
ns
Delay FTCKO in falling to FTDAT
3
32
ns
Delay FTCKO out falling to FTDAT
-3
32
ns
Delay FTCKO in falling to FTMFS
3
32
ns
Delay FTCKO out falling to FTMFS
-3
32
ns
In case the Internal Clock Recovery Circuit is used for SRTS, the frequency deviation should be +/- 10 ppm
Data Sheet
253
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.2.3
Framer Interface in SYM Mode
Framer Interface in SYM2
1
RFCLK
opmo.frri = 1
1
RFCLK
opmo.frri = 0
3
4
FRDAT
5
6
FRMFB0
7
FTDAT
Figure 61
Framer Interface Timing for SYM 2.048 MHz
Table 39
Framer Interface AC Timing Characteristics in SYM2 Mode
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
TRFCLK: Period RFCLK
488
ns
1A
FRFCLK: Frequency RFCLK
2,048
MHz
3
Setup time FRDAT before RFCLK
falling/rising (center of bit period)
15
ns
4
Hold time FRDAT after RFCLK falling/ 15
rising (center of bit period)
ns
5
Setup time FRMFBN1) before RFCLK
falling/rising
15
ns
6
Hold time FRMFBN1) after RFCLK
falling
15
ns
7
Delay RFCLK falling/rising to FTDAT
3
1)
32
ns
For usage of FRMFBN in SYM mode see Chapter 7.24
Data Sheet
254
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Framer Interface in SYM8
1
RFCLK
3
4
FRDAT
5
6
FRMFB0
7
FTDAT
Figure 62
Framer Interface Timing in SYM 8.192 MHz
Table 40
Framer Interface Timing in SYM8
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
TRFCLK: Period RFCLK
1A
FRFCLK: Frequency RFCLK
-130 ppm 8,192
3
Setup time FRDAT before RFCLK
falling/rising (center of bit period)
15
ns
4
Hold time FRDAT after RFCLK falling/ 15
rising (center of bit period)
ns
5
Setup time FRMFBN1) before RFCLK 15
falling/rising
ns
6
Hold time FRMFBN1) after RFCLK
falling
15
ns
7
Delay RFCLK falling to FTDAT
3
1)
122
ns
+130ppm MHz
32
ns
For usage of FRMFBN in SYM mode see Chapter 7.24
Data Sheet
255
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.2.4
Framer Interface in EC Mode
I
1
R FC LK
2
2
F R FR S 0
3
TS0.Bit1
FRDAT
4
TS1.Bit8
5
TS0.Bit1
F TD A T
TS1.Bit8
even ports
5
TS1.Bit7
F TD A T
TS1.Bit6
TS1.Bit5
o dd p orts
Figure 63
Framer Interface Timing in EC Mode
Table 41
Framer Interface Timing in EC Mode
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
TRFCLK: Period RFCLK
1A
FRFCLK: Frequency RFCLK
-130 ppm 8,192
+130ppm MHz
2
Delay RFCLK rising to FTFRS0
3
32
3
Setup time FRDAT before RFCLK
falling (center of bit period)
15
ns
4
Hold time FRDAT after RFCLK falling 15
(center of bit period)
ns
5
Delay RFCLK falling to FTDAT
9.6.3
122
3
ns
32
ns
ns
UTOPIA Interface
The AC characteristics of the UTOPIA interface fulfills the ATM Forum “UTOPIA level 2
Specification, Version 1.0" as defined for the interface running at 33 MHz.
The AC characteristics are based on the timing specification for the receiver side of a
signal.
Data Sheet
256
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
The setup and the hold times are defined with regard to a positive clock edge, see
Figure 64.
Taking the actual used clock frequency into account (e.g. up to the max. frequency), the
corresponding (min. and max.) transmit side “clock to output” propagation delay
specifications can be derived. The timing references (tT5 to tT12) are according
toTable 42 to Table 45.
In the following tables, A>P (column DIR, Direction) defines a signal from the ATM layer
(transmitter, driver) to the PHY layer (receiver), A<P defines a signal from the PHY layer
(transmitter, driver) to the ATM layer (receiver).
Clock
Signal
tT5, tT7
tT6, tT8
input setup to clock input hold from clock
Figure 64
Setup and hold time definition (single- and multi PHY)
Clock
tT9
tT10
Signal
tT11
signal going low
impedance from clock
Figure 65
Data Sheet
tT12
signal going low
impedance to clock
signal going high
signal going high
impedance from clock impedance to clock
Tri-state timing (multi-PHY, multiple devices only)
257
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 42
No.
Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single
PHY)
Signal Name DIR
TXCLK1)
t1
Description
Limit Values
A>P TXCLK frequency (nominal)
Unit
Min
Max
0
33
MHz
tT2
TXCLK duty cycle
40
60
%
tT3
TXCLK peak-to-peak jitter
-
5
%
tT4
TXCLK rise/fall time
-
3
ns
8
-
ns
1
-
ns
8
-
ns
1
-
ns
tT5
A>P Input setup to TXCLK
tT6
TXDAT[7:0],
TXPTY,
TXSOC,
TXENB
tT7
TXCLAV
A<P Input setup to TXCLK
Input hold from TXCLK
tT8
1)
Input hold from TXCLK
The frequency should be equal or smaller than the coreclock CLOCK
Table 43
No.
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single
PHY)
Signal Name DIR
RXCLK1)
t1
Description
Limit Values
A>P RXCLK frequency (nominal)
Unit
Min
Max
0
33
MHz
tT2
RXCLK duty cycle
40
60
%
tT3
RXCLK peak-to-peak jitter
-
5
%
tT4
RXCLK rise/fall time
-
3
ns
8
-
ns
tT5
RXENB
A>P Input setup to RXCLK
tT6
Input hold from RXCLK
1
-
ns
tT7
RXDAT[7:0], A<P Input setup to RXCLK
RXPTY,
Input hold from RXCLK
RXSOC,
RXCLAV
8
-
ns
1
-
ns
tT8
1)
The frequency should be equal or smaller than the coreclock CLOCK
Data Sheet
258
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 44
Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY)
No.
Signal Name DIR
t1
TXCLK1)
Description
Limit Values
A>P TXCLK frequency (nominal)
Unit
Min
Max
0
33
MHz
tT2
TXCLK duty cycle
40
60
%
tT3
TXCLK peak-to-peak jitter
-
5
%
tT4
TXCLK rise/fall time
-
3
ns
8
-
ns
1
-
ns
8
-
ns
tT5
tT6
tT7
TXDAT[7:0],
TXPTY,
TXSOC,
TXENB,
TXADR[4:0]
A>P Input setup to TXCLK
TXCLAV
A<P Input setup to TXCLK
Input hold from TXCLK
tT8
Input hold from TXCLK
1
-
ns
tT9
Signal going low impedance
to TXCLK
8
-
ns
tT10
Signal going high impedance
to TXCLK
0
-
ns
tT11
Signal going low impedance
from TXCLK
1
-
ns
tT12
Signal going high impedance
from TXCLK
1
-
ns
1)
The frequency should be equal or smaller than the coreclock CLOCK
Table 45
No.
t1
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY)
Signal Name DIR
RXCLK1)
Description
Limit Values
A>P RXCLK frequency (nominal)
Unit
Min
Max
0
33
MHz
tT2
RXCLK duty cycle
40
60
%
tT3
RXCLK peak-to-peak jitter
-
5
%
tT4
RXCLK rise/fall time
-
3
ns
8
-
ns
1
-
ns
tT5
tT6
RXENB,
RXADR[4:0]
Data Sheet
A>P Input setup to RXCLK
Input hold from RXCLK
259
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 45
No.
tT7
tT8
tT9
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY)
Signal Name DIR
Description
Limit Values
RXDAT[7:0], A<P Input setup to RXCLK
RXPTY,
Input hold from RXCLK
RXSOC,
Signal going low impedance
RXCLAV
to RXCLK
Unit
Min
Max
8
-
ns
1
-
ns
8
-
ns
tT10
Signal going high impedance
to RXCLK
0
-
ns
tT11
Signal going low impedance
from RXCLK
1
-
ns
tT12
Signal going high impedance
from RXCLK
1
-
ns
1)
The frequency should be equal or smaller than the coreclock CLOCK
9.6.4
IMA Interface
At the IMA interface the IWE8 operates in cycles of 12 system clocks. ATBTC can
become active during cycle #3, the UNCHEC can become active during cycle #9. The
Port number is always active for 6 cycles.
C LO C K
1
A TB T C
2
UNCHEC
3
P N 0..2
Figure 66
Data Sheet
Timing of the IMA Interface
260
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 46 IMA Interface AC Timing Characteristics
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
Delay master clock to ATBTC
26
ns
2
Delay master clock to UNCHEC
26
ns
3
Delay master clock to PN[0:2]
26
ns
9.6.5
Clock Recovery Interface
CLOCK
6
SCLK
1
1
SSP
2
SDI
B it1
B it0
3
B it3 1
B it3 0
4
SDOD
B it1
B it0
B it3 1
B it3 0
5
SDOR
B it1
B it0
B it3 1
B it3 0
Figure 67
Clock Recovery Interface Timing Diagram
Table 47
Clock Recovery Interface AC Timing Characteristics
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
Delay SCLK rising to SSP
-1
2
Setup time SDI before SCLK rising
20
ns
3
Hold time SDI after SCLK rising
0
ns
4
Delay SCLK rising to SDOD
0
11
ns
5
Delay SCLK rising to SDOR
0
11
ns
6
Delay CLOCK to SCLK
1
16
ns
Data Sheet
261
11
ns
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.6
Microprocessor Interface
9.6.6.1
Intel Mode
M PADR
1
9
M PCS
2
8
M PW R
10
3
5
6
11
M PRDY
4
7
M PDAT
Figure 68
Intel Mode Write Cycle Timing Diagram
Table 48
Intel Mode Write Cycle AC Characteristics
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
Setup time MPADR before MPCS low
0
ns
2
Setup time MPCS before MPWR low
0
ns
3
Delay MPRDY low after MPWR low
2
4
MPDAT valid after MPWR low
5
Pulse width MPRDY low
2 x Tclock
6
MPRDY high to MPWR high
10
ns
7
Hold time MPDAT after MPWR high
5
ns
8
Hold time MPCS after MPWR high
5
ns
9
Hold time MPADR after MPWR high
5
ns
10
Delay MPCS low to MPRDY high
2
20
ns
11
Delay MPCS high to MPRDY high
impedance
2
20
ns
Data Sheet
20
ns
2 x Tclock ns
262
23xTclock ns
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
M PADR
1
9
M PCS
2
8
M PRD
12
3
4
6
13
M PRDY
10
5
11
7
M PDAT
Figure 69
Intel Mode Read Cycle Timing Diagram
Table 49
Intel Mode Read Cycle AC Timing Characteristics
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
Setup time MPADR before MPCS low
0
ns
2
Setup time MPCS before MPRD low
0
ns
3
Delay MPRDY low after MPRD low
2
20
4
Pulse width MPRDY low
2 x Tclock
23xTclock ns
5
MPDAT valid before MPRDY high
10
ns
6
MPRDY high to MPRD high
10
ns
7
Delay time MPDAT after MPRD high
3
ns
8
Hold time MPCS after MPRD high
5
ns
9
Hold time MPADR after MPRD high
5
ns
10
Delay MPRD low to MPDAT low
impedance
4
20
ns
11
Delay MPRD high to MPDAT high
impedance
5
20
ns
12
Delay MPCS low to MPRDY high
2
20
ns
13
Delay MPCS high to MPRDY high
impedance
2
20
ns
Data Sheet
263
ns
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.6.2
Motorola Mode
MPADR
1
2
MPCS
3
4
MPRW
5
6
MPTS
7
8
10
11
9
MPTA
12
14
15
13
MPDAT
(READ)
16
17
MPDAT
(WRITE)
Figure 70
Motorola Mode Timing Diagram
Table 50
Motorola Mode AC Timing Characteristics
No.
Parameter
Limit Values
Min
Typ
Unit
Max
1
Setup time MPADR before MPCS low
0
ns
2
Hold time MPADR after MPTS high
5
ns
3
Setup time MPCS before MPTS low
0
ns
4
Hold time MPCS after MPTS high
5
ns
5
Setup time MPRW before MPTS low
10
ns
6
Hold time MPRW after MPTS high
0
ns
7
Delay MPCS low to MPTA high
5
15
8
Delay MPTA low after MPTS low
2 x Tclock
23x Tclock ns
9
Pulse width MPTA low
Tclock
Tclock
10
MPTA low to MPTS high
0
11
Delay MPCS high to MPTA high
impedance
5
Data Sheet
264
ns
ns
ns
15
ns
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 50
No.
Motorola Mode AC Timing Characteristics (cont’d)
Parameter
Limit Values
Min
Typ
Unit
Max
12
Delay MPTS low to MPDAT low
impedance
1
13
MPDAT valid before MPTA high
5
ns
14
Delay time MPDAT after MPTS high
2
ns
15
Delay MPTS high to MPDAT high
impedance
2
16
MPDAT valid after MPTS low
17
Hold time MPDAT after MPTS high
9.6.7
15
ns
17
ns
2 x Tclock ns
5
ns
RAM Interface
CLOCK
8
Basic 12 RMCLK cycle
9
RMCLK
1
RMADR
AR1
AR2
AR3
AR4
AR5
AR6
AW1
AW2
AW3
AW4
AW5
AR1
2
RMADC
2
2
RMOE
3 4
RMDAT
R
1
5
R
2
R
3
R
4
R
5
R
6
6
W1
W2
7
W3
2
2
2
2
W4
W5
RMWR
RMCS
Figure 71
Data Sheet
RAM Interface Timing Diagram
265
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 51
No.
RAM Interface AC Timing Characteristics
Parameter
Limit Values
Min
Unit
Typ
Max
1
Delay RMCLK rising to RMADR
1
11
ns
2
Delay RMCLK rising to RMADC
1
7
ns
Delay RMCLK rising to RMOE
1
7
ns
Delay RMCLK rising to RMWR
1
7
ns
Delay RMCLK rising to RMCS
1
7
ns
3
Setup time RMDAT before RMCLK
rising (all read cycles)
11
ns
4
Hold time RMDAT after RMCLK rising
(all read cycles)
0
ns
5
Delay RMCLK falling to RMDAT low
impedance (write cycle W1)
0
8
ns
6
Delay RMCLK rising to RMDAT
(write cycles W2 to W5)
6
12
ns
7
Delay RMCLK falling to RMDAT high
impedance (write cycle W5)
0
8
ns
8
Delay CLOCK to RMCLK
6
12
ns
9
TRMCLK: Period RMCLK
TCLOCK
ns
9A
FRMCLK: Frequency RMCLK
FCLOCK
MHz
9.6.8
Boundary-Scan Test Interface
1
TCK
2
3
TDI
4
5
TDO
6
TRST
Figure 72
Data Sheet
Boundary-Scan Test Interface Timing Diagram
266
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 52
No.
Boundary-Scan Test Interface AC Timing Characteristics
Parameter
Limit Values
Min
Typ
Unit
Max
1
TTCK: Period TCK
1A
FTCK: Frequency TCK
2
Setup time TMS, TDI before TCK rising 10
ns
3
Hold time TMS, TDI after TCK rising
10
ns
4
Delay TCK falling to TDO valid
0
30
ns
5
Delay TCK falling to TDO high
impedance
0
30
ns
6
Pulse width TRST low
2 x TTCK
Data Sheet
160
ns
6,25
267
MHz
ns
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode
10
Testmode
10.1
Device Identification Register
31
28
27
12
11
1
Version(3:0)
Partnumber(15:0)
Manufacturer-ID(10:0)
0010B
0000000001000110B
00001000001B
10.2
0
1
Instruction Register
The following table shows the instruction binary codes for the 4 bit instruction register.
Code
Boundary-Scan Instruction Register Binary Codes
0000 = EXTEST
0001 = IDCODE
0101 = SAMPLE
0101 = INTEST
0111 = CLAMP
1111 = BYPASS
10.3
Boundary-Scan Register
Table 53 describes the Boundary-Scan register. The register contains 299 cells. The
cells of type “control” will disable the corresponding outputs when set. The control cells
are preset to a safe logic-1 during the TEST-LOGIC-RESET state of the TAP controller.
Table 53
Boundary Scan Register
Name
Name
Name
ftcko_4_o
rxdat_2_o
ftcko_0_o
ftcko_4_i
rxdat_3_o
ftcko_0_i
ftcko_4_c
rxdat_4_o
ftcko_0_c
ftcko_5_o
rxdat_5_o
frfrsn_0_o
ftcko_5_i
rxdat_6_o
frfrsn_0_c
ftcko_5_c
rxdat_7_o
ftdat_0_o
rtsen_n
rxprt_o
ftdat_0_c
mpcs_n
rxprt_c
ftmfs_0_o
Data Sheet
268
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode
Table 53
Boundary Scan Register (cont’d)
Name
Name
Name
mpwr_n
rxenb_o
ftmfs_0_c
mprd_n
rxenb_i
ftfrsn_0_o
mpdat_0_o
rxenb_c
ftfrsn_0_c
mpdat_0_i
rxclk
frlos_1
mpdat_c
rmclk
frclk_1
mpdat_1_o
pmt
frdat_1
mpdat_1_i
rmdat_0_o
frmfb_1
mpdat_2_o
rmdat_0_i
ftcko_1_o
mpdat_2_i
rmdat_c
ftcko_1_i
mpdat_3_o
rmdat_1_o
ftcko_1_c
mpdat_3_i
rmdat_1_i
frfrsn_1_o
mpdat_4_o
rmdat_2_o
frfrsn_1_c
mpdat_4_i
rmdat_2_i
ftdat_1_o
mpdat_5_o
rmdat_3_o
ftdat_1_c
mpdat_5_i
rmdat_3_i
ftmfs_1_o
mpdat_6_o
rmdat_4_o
ftmfs_1_c
mpdat_6_i
rmdat_4_i
ftfrsn_1_o
mpdat_7_o
rmdat_5_o
ftfrsn_1_c
mpdat_7_i
rmdat_5_i
frlos_2
mpdat_8_o
rmdat_6_o
frclk_2
mpdat_8_i
rmdat_6_i
frdat_2
mpdat_9_o
rmdat_7_o
frmfb_2
mpdat_9_i
rmdat_7_i
ftcko_2_o
mpdat_10_o
rmdat_8_o
ftcko_2_i
mpdat_10_i
rmdat_8_i
ftcko_2_c
mpdat_11_o
sdi
frfrsn_2_o
mpdat_11_i
rmdat_9_o
frfrsn_2_c
mpdat_12_o
rmdat_9_i
ftdat_2_o
mpdat_12_i
rmdat_10_o
ftdat_2_c
mpdat_13_o
rmdat_10_i
ftmfs_2_o
Data Sheet
269
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode
Table 53
Boundary Scan Register (cont’d)
Name
Name
Name
mpdat_13_i
rmdat_11_o
ftmfs_2_c
mpdat_14_o
rmdat_11_i
ftfrsn_2_o
mpdat_14_i
rmdat_12_o
ftfrsn_2_c
mpdat_15_o
rmdat_12_i
frlos_3
mpdat_15_i
tbus
frclk_3
rfclk
rmdat_13_o
frdat_3
clock
rmdat_13_i
frmfb_3
reset_n
sdod
ftcko_3_o
mprdy_o
sdor
ftcko_3_i
mprdy_c
rmdat_14_o
ftcko_3_c
pn_0
rmdat_14_i
frfrsn_3_o
mpir1_n
rmdat_15_o
frfrsn_3_c
mpir2_n
rmdat_15_i
ftdat_3_o
mpadr_0
rmdat_16_o
ftdat_3_c
mpadr_1
rmdat_16_i
ftmfs_3_o
mpadr_2
ssp
ftmfs_3_c
mpadr_3
rmdat_17_o
ftfrsn_3_o
mpadr_4
rmdat_17_i
ftfrsn_3_c
mpadr_5
rmdat_18_o
frlos_4
mpadr_6
rmdat_18_i
frclk_4
mpadr_7
rmdat_19_o
frdat_4
mpadr_8
rmdat_19_i
frmfb_4
mpadr_9
rmdat_20_o
tscsh
mpadr_10
rmdat_20_i
frfrsn_4_o
mpadr_11
sclk
frfrsn_4_c
mpadr_12
rmdat_21_o
ftdat_4_o
mpadr_13
rmdat_21_i
ftdat_4_c
mpadr_14
rmdat_22_o
ftmfs_4_o
mpadr_15
rmdat_22_i
ftmfs_4_c
mpadr_16
rmdat_23_o
ftfrsn_4_o
Data Sheet
270
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode
Table 53
Boundary Scan Register (cont’d)
Name
Name
Name
mpadr_17
rmdat_23_i
ftfrsn_4_c
licec
rmdat_24_o
frlos_5
clk52
rmdat_24_i
frclk_5
e1ds1
rmdat_25_o
frdat_5
tscen
rmdat_25_i
frmfb_5
txadr_0
rmdat_26_o
frfrsn_5_o
txadr_1
rmdat_26_i
frfrsn_5_c
txadr_2
rmdat_27_o
ftdat_5_o
txadr_3
rmdat_27_i
ftdat_5_c
txadr_4
rmdat_28_o
ftmfs_5_o
rxadr_0
rmdat_28_i
ftmfs_5_c
rxadr_1
rmdat_29_o
ftfrsn_5_o
rxadr_2
rmdat_29_i
ftfrsn_5_c
rxadr_3
rmdat_30_o
frlos_6
rxadr_4
rmdat_30_i
frclk_6
pn_1
rmdat_31_o
frdat_6
pn_2
rmdat_31_i
frmfb_6
txcla_i
rmdat_32_o
frfrsn_6_o
txcla_o
rmdat_32_i
frfrsn_6_c
txcla_c
rmwr_n
ftdat_6_o
txenb_o
rmcs_n
ftdat_6_c
txenb_i
rmoe_n
ftmfs_6_o
txenb_c
rmadc_n
ftmfs_6_c
txsoc
unchec_4
ftfrsn_6_o
txdat_0
rmadr_0
ftfrsn_6_c
txdat_1
rmadr_1
frlos_7
txdat_2
rmadr_2
frclk_7
txdat_3
rmadr_3
frdat_7
txdat_4
rmadr_4
frmfb_7
txdat_5
rmadr_5
ftcko_6_o
Data Sheet
271
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode
Table 53
Boundary Scan Register (cont’d)
Name
Name
Name
txdat_6
rmadr_6
ftcko_6_i
txdat_7
rmadr_7
ftcko_6_c
txprt
rmadr_8
ftcko_7_o
uttr_n
rmadr_9
ftcko_7_i
txclk
rmadr_10
ftcko_7_c
rxsoc_o
rmadr_11
frfrsn_7_o
rxsoc_c
rmadr_12
frfrsn_7_c
rxcla_o
rmadr_13
ftdat_7_o
rxcla_i
rmadr_14
ftdat_7_c
rxcla_c
rmadr_15
ftmfs_7_o
atbtc_3
frlos_0
ftmfs_7_c
rxdat_0_o
frclk_0
ftfrsn_7_o
rxdat_c
frdat_0
ftfrsn_7_c
rxdat_1_o
frmfb_0
Data Sheet
272
2002-05-06
PXB4219 / PXB4220 / PXB4221
Package Outlines
11
Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our Data Book
“Package Information”.
SMD = Surface Mounted Device
Figure 73
Data Sheet
Dimensions in mm
Package Outline: P-BGA-256 (Plastic Metric Quad Flat Package)
273
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
12
Appendix
12.1
ATM Adaptation Layer 1
The ATM Adaptation Layer 1 (AAL1) consists of two sublayers: The Segmentation and
Reassembly Sublayer (SAR), which is responsible for sequence integrity of the
transmitted ATM cell stream and the Convergency Sublayer, responsible for blocking of
user data into 47-octet SAR boundaries.
Figure 74 gives an overview on the AAL1 frame-structure as defined in ITU-T I.363.1
[31].
Parity Pointer
1 bit
AAL user info
7 bit
P format
Dummy Fill
N octets
P
User information
1 octet
46 octets
CS-Sublayer
User information
Non-P format
47 octets
CSI
SC
CRC
Py
1 bit
3 bit
3 bit
1 bit
SAR-Sublayer
SN
SNP
1 octet
Pointer
CSI
SC
CRC
Py
SN
SNP
SAR
SDU
PDU
SAR-SDU
47 octets
ATM Header
ATM-SDU = SAR-PDU
5 octets
48 octets
ATM Layer
= octet offset of data block over 2 cells (111 1111 if not required)
= Convergency Sublayer Indication
Non-P Format: CSI = 0
P format:
CSI = 1 if SC = 0,2,4 or 6, P-field may be inserted
CSI = 0 if SC = 1,3,5 or 7, P-field is unused (Non-P format used)
= Sequence Count
= Cyclic Redundancy Check
= Even Parity bit
= Sequence Number incremented by 1 modulo 8 for each SAR-SDU
= Sequence Number Protection
= Segmentation & Reassembly
= Service Data Unit
= Protocol Data Unit
Figure 74
Data Sheet
Structure of the AAL1 SAR-PDU
274
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
Robust Sequence Count Algorithm
This algorithm is completely described in annex D of the ETSI B-ISDN AAL type 1
Specification [17] and ITU-T I.363.1 [31] and is shown in Figure Figure 75.
The algorithm is described by a state machine of 5 states. A change in states within the
state machine is indicated by an arrow, on which there are two distinct values
represented. The first value refers to the event that originates the state change, and the
second value refers to the action to be taken as a result of that event.
A decision in this algorithm is taken after evaluation of 2 consecutive SN. This means
that when a cell is received it must be temporarily stored, waiting for the next cell before
it is finally passed to the reassembly buffer. In the state machine, an action to be taken
(accept or discard) always refers to the stored cell.
The sequence counting of modulo 8 permits that the algorithm detects a maximum of to
6 consecutive lost cells and 1 misinserted cell, assuming that misinsertion of one cell is
at least as probable as the loss of 7 consecutive cells.
Lost cells are compensated by inserting an appropriate number of dummy cells into the
transmitted data of the channel. This is required to maintain bit count integrity. The
number of octets inserted per dummy cell is equal to the number of user information
octets in the SAR-PDU payload of each cell.
When one misinserted cell is detected, the algorithm is able to delete the misinserted
cell, because of the delay of one cell in taking a decision.
Data Sheet
275
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
invalid SN/discard
Start
Initialization
out of seq/discard
valid SN/discard
invalid SN/discard
Out of
Sync
invalid SN/discard
in seq/accept
out of seq/discard
in seq – 1/discard
in seq – 1+1/accept
invalid SN/accept
Out of
Seq
in seq – 1/discard
Sync
out of seq/accept
out of seq/discard
in seq/insert dummy cell(s) + accept
in seq/accept
in seq – 1+1/accept
invalid SN/discard
Invalid
T1306830-95
Figure 75
Data Sheet
Informative and Example Algorithm State Machine (Fig. III.2/I.363.1)
276
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
Fast Sequence Count Algorithm
The state machines of the robust SC algorithm and the fast SC algorithm are the same.
The only difference is that in the fast algorithm, the action to be taken always refers to
the currently received cell, while in the standard algorithm it refers to the temporarily
stored cell. Therefore the fast SC algorithm does not introduce additional one-cell delay.
In the fast SC algorithm, a misinserted cell is immediately accepted in the reassembly
buffer. Only at the arrival of the next cell, it is detected that the previous cell was
misinserted. Because the misinserted cell was already accepted, the current (in
sequence) cell will be discarded instead. Lost cells are compensated with the insertion
of dummy cells as in the standard algorithm.
Frequency and Value of the Pointer Field
The pointer field contains the binary value of the offset, measured in octets, between the
end of the pointer field and the start of the structured block, in the 93 octet payload. The
payload consists of the remaining 46 octets of this SAR-PDU payload and the 47 octets
of the next SAR-PDU payload.
The frequency of occurrence of the pointer field is according to ITU-T I.363.1 [31]. The
pointer field is used exactly once in every cycle, where a cycle is the sequence of eight
consecutive SAR-PDUs with Sequence Count values 0, 1, to 7. The pointer field is used
at the first available opportunity in a cycle to point to a start of a structured block. If a start
of a structured block is not present in a cycle, then a pointer field containing a dummy
offset value ‘127’ is used at the last opportunity in the cycle.
Data Sheet
277
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
12.2
Synchronous Residual Time Stamp SRTS
This sub chapter contains a short description of the SRTS method, as defined in [12] and
[31].
The SRTS algorithm is used to measure the frequency deviation of a data stream which
is packetized in ATM cells. This frequency is coded in 4 bits and sent to the receiver. At
the receiver, the correct frequency is regenerated.
The 4 RTS bits are spread over 8 ATM cells. These 8 ATM cells contain 8 x 47 byte x 8
bit/byte = 3008 bits of data. In case of an E1 line, the data arrives with 2.048 Mbit/s, thus
after 3008 bit / 2.048 Mbit/s = 1,46875 ms a complete RTS value is received. The
frequency of generated RTS values is 681 Hz.
The RTS value is calculated in the following way:
In N = 3008 cycles of Fdata, we have Mq cycles of the reduced network clock. The
reduced network clock Fnx has to fulfil the following equation: 1 <= Fnx / Fdata < 2. This
defines the value of x in the equation: Fnx = 8 kHz X 19440 / 2^x. For a full E1 line Fdata
= 2.048 MHz, x = 6 and Fnx = 2.43 MHz. The maximum input frequency deviation of 200
ppm (E1 lines: less than 50 ppm) of the data clock translates in a deviation from Mq. At
the receiving side, the same network clock is available and the numbers N and x are
known. As a result, the nominal value Mnom of Mq is known, and only the deviation from
Mnom has to be transmitted. The number of bits to transmit the deviation (p = 4) has to
be sufficient for the maximum frequency deviation.
tolerance
N cycles T seconds
fs
t
Mq
Mmin Mnom
Mmax
fnx
t
y
y
2p
T1817630-92
Figure 76
Data Sheet
The Concept of Synchronous Residual Time Stamp (SRTS) (Fig. 5/
I.363.1)
278
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
RTS values are generated as follows:
T
fs
Counter A
divided by N
fn
1
—
x
Latch
fnx
RTS
P-bit
counter Ct
T1817640-92
Figure 77
Generation of Residual Time Stamp (RTS) (Fig.6/ I.363.1)
The transformation of RTS values in a clock is not specified in the SRTS specifications.
Basically (the implementation is slightly different), the ICRC calculates another RTS
value based on the transmit clock. The difference between received RTS values and
locally calculated RTS values, drives a DCO. This solution can be described as a PLL
with an unusual phase comparator.
Data Sheet
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Appendix
12.3
Adaptive Clock Method ACM
The adaptive clock method does not require information concerning the source clock
transferred over the ATM network. The speed of the transmitter is adjusted to the filling
level of the receive buffer. If the transmit clock is too slow, the buffer filling level will
increase causing the clock recovery circuit to slow down the transmit clock. If the
transmit clock is too fast the buffer filling level will decrease. In this case the clock
recovery circuit will increase the transmit clock.
Data Sheet
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PXB4219 / PXB4220 / PXB4221
Appendix
12.4
Channel Associated Signalling
ITU-T recommendation G.704 [24] defines Channel Associated Signalling (CAS) for
interfaces at 2048 Kbit/s (E1) and 1544 Kbit/s (DS1) interfaces carrying 64 kbit/s
channels. The mapping of E1 or DS1 multiframes containing CAS into ATM cells is
defined in the ATM-Forum “Circuit Emulation Services Specification” [10].
In case of E1 and DS1 circuit emulation, the user information carried via AAL1 consists
of a stream of payload substructures followed by an optional signalling substructure.
Each payload and signalling substructure corresponds to one E1 multiframe / DS1
extended superframe. The payload substructure contains the channel slots and the
optional signalling substructure contains the signalling bits associated with the channels.
The following section gives an overview on this topic.
12.4.1
E1
An E1 multiframe comprises 16 consecutive frames. These are numbered from 0 to15.
The multiframe alignement signal is 0000 and occupies digit time slots 1 to 4 of 64 kbit/
s channel time slot 16 in frame 0.
When 64 kbit/s channel time slot 16 is used for channel-associated signalling, the 64
kbit/s capacity is sub-multiplexed into lower-rate signalling channels using the
multiframe alignement signal as a reference.
Details of the bit allocation are given in Table 54
Table 54
Bit allocation of channel associated 64 kbit/s time slot 16 for channel
associated signalling
E1 Multiframe
Bit allocation of time slot 16
Frame 0 (CasBeginFrame)
0000
xyxx
Frame 1
abcd channel 1
abcd channel 16
Frame 2
abcd channel 2
abcd channel 17
...
...
...
Frame 15
abcd channel 15
abcd channel 30
x = spare bit, to be set to 1 if not used
y = Bit used for alarm indication to the remote end. In undisturbed operation, set to 0; in alarm condition, set to 1.
Data Sheet
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PXB4219 / PXB4220 / PXB4221
Appendix
.
A TM S D U
of 1st ce ll
A A L1 h ead er oc tet
A A L s tru ctu re po inte r = 0
tim es lot x
tim es lot y
tim es lot z
tim es lot x
tim es lot y
tim es lot z
tim es lot
tim es lot
tim es lot
tim es lot
ATM SDU
o f 2 nd ce ll
A A L1 h ead er oc tet
tim es lot y
tim es lot z
A B C D tim e slot x
A B C D tim es lot y
A B C D tim e slot z
u nus ed =0 00 0
tim es lot x
tim es lot y
tim es lot z
tim es lot
tim es lot
tim es lot
tim es lot
Figure 78
12.4.2
x
y
z
x
x
y
z
x
1 st fra m e
2 nd fra m e
1 5th fram e
1st
m ultifram e
1 6th fram e
s igna lling
s ubs tru ctu re
1 st fra m e
2n d
m ultifram e
1 4th fram e
Example Multiframe Structure for 3x64 Kbit/s E1 with CAS
DS1
An DS1 multiframe consists of 24 frames. They are numbered from 1 to 24. In the
multiframe there are four different signalling bits (A, B, C and D) providing four
independent 333 bit/s channels, two independent 667 bit/s channels or one 1333 bit/s
channel. The four signalling bits for each time slot are transported in the last bit of each
time slot of the frames 6, 12, 18, 24. In these frames only 7 bits are available for data
transmission (Robbed Bit Signalling). When mapping DS1 Nx64 Kbit/s frames into ATM
cells the CAS bits may also be transmitted in the payload section. However, only the
signalling bits of the CAS substructure are relevant.
Data Sheet
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2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
Table 55
Allocation of Channel Associated Signalling Bits to 24 Frame
Multiframe
DS1 Multiframe
Digit time slot in each
channel used for
Signalling channel
identifier
Characters Signalling
333
bit/s
667
bit/s
1333
bit/s
Frame 1 (CasBeginFrame) - Frame 5 1-8
-
-
-
-
Frame 6
1-7
8
A
A
A
Frame 7 - Frame 11
1-8
-
-
-
-
Frame 12
1-7
8
B
B
A
Frame 13 - Frame 17
1-8
-
-
-
-
Frame 18
1-7
8
C
A
A
Frame 19 - Frame 23
1-8
-
-
-
-
Frame 24
1-7
8
D
B
A
A A L1 h ead er oc tet
A A L s tru ctu re po inte r = 0
tim es lot x
tim es lot x
tim es lot x
tim es lot x
tim es lot x
tim es lot x
A TM S D U
A B C D ts x
u nus ed =0 00 0
tim es lot x
tim es lot x
tim es lot x
tim es lot x
tim es lot x
tim es lot x
1 st fra m e
2nd fram e
3 rd fra m e
1st
m ultifram
e
22 th fra m e
23 th fra m e
24 th fra m e
sig na lling
1 st fra m e
2nd fram e
3 rd fra m e
2n d
m ultifram e
19 th fra m e
20 th fra m e
2 1st fra m e
Example Multiframe Structure for 1x64 Kbit/s DS1 with CAS
Data Sheet
283
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PXB4219 / PXB4220 / PXB4221
Contacts for SRTS Patent Fee
13
Contacts for SRTS Patent Fee
When using the PXB4220 a patent fee for the SRTS clock recovery needs to be paid to
Telcordia Technologies, Inc.:
Telcordia Technologies, Inc.
331 Newman Springs Road
NVC-3Z375
Red Bank, NJ 07701-5699
Web:
Data Sheet
http://www.telcordia.com
284
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PXB4219 / PXB4220 / PXB4221
Glossary
14
Glossary
AAL
ATM Adaptation Layer
ACM
Adaptive Clock Method
ATM
Asynchronous Transfer Mode
B-ISDN
Broadband - Integrated Services Digital Network
CBR
Constant Bit Rate
CDV
Cell Delay Variation
CES
Circuit Emulation Service
CLP
Cell Loss Priority
CRC
Cyclic Redundancy Check
CS
Convergence Sublayer
CSI
Convergence Sublayer Indication
DCO
Digitally Controlled Oscillator
DS1
Digital Signal 1 (1.544 Mbit/s) (=T1)
EC
Echo Canceller
FALC
Framer And Line Interface Component
FAM
FALC Mode
FIFO
First In, First Out Buffer
FS/DL
Frame Sync/Data Link
FSM
Finite State Machine
GFC
Generic Flow Control
GIM
Generic Interface Mode
HEC
Header Error Control
I/O
Input/Output
ICRC
Internal Clock Recovery Circuit
ITU
International Telecommunications Union
ITU-T
International Telecommunications Union - Telecommunications
Standardization Sector
IWE8
Interworking Element component for 8 channels PXB 4220
IWECORE
IWE8 without ICRC
LCD
Loss of Cell Delineation
LIC
Line Interface Card or Line Interface Circuit
Data Sheet
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PXB4219 / PXB4220 / PXB4221
Glossary
LOS
Loss of Signal
LSB
Least Significant Bit
MSB
Most Significant Bit
NIC
Network Interface Controller or Card
NNI
Network-to-Network Interface
OAM
Operation, Administration, and Maintenance
OCD
Out of Cell Delineation
PDU
Protocol Data Unit
PHY
Physical Layer Device
PTI
Payload Type Identifier
RTS
Residual Time Stamp
SAR
Segmentation And Reassembly
SARE
Segmentation And Reassembly Element, PXB 4110
SC
Sequence Count
SDT
Structured Data Transfer
SN
Sequence Number
SNP
Sequence Number Protection
SRTS
Synchronous Residual Time Stamp
SSRAM
Synchronous Static RAM
SYM
Synchronous Mode
TAP
Test Access Port
TBD
To Be Defined
UDT
Unstructured Data Transfer
UNI
User-to-Network Interface
UTOPIA
Universal Test and Operations Physical Interface for ATM
UTOPIA
Receive
Interface
(Upstream)
Data is transferred from the PHY Layer (in this case the IWE8) to the
ATM Layer.
UTOPIA
Transmit
Interface
(Downstream)
Data is transferred from the ATM Layer to the PHY Layer (in this case
the IWE8).
VC
Virtual Channel
Data Sheet
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PXB4219 / PXB4220 / PXB4221
Glossary
VCI
Virtual Channel Identifier
VP
Virtual Path
VPI
Virtual Path Identifier
Data Sheet
287
2002-05-06
PXB4219 / PXB4220 / PXB4221
Bibliography
15
Bibliography
1. ANSI, American National Standard for Telecommunications. Digital Hierarchy Formats Specification, T1.107-1995.
2. ANSI, B-ISDN Customer Installation Interfaces: Physical Layer Specification, Draft
American National Standard for Telecommunications, T1E1.2/93 020R2.
3. ANSI, B-ISDN Network Node Interfaces and Inter-Network Interfaces: Rates and
Formats Specification, Draft American National Standard for Telecommunications
T1S1.5/94 001R1.
4. ATM Forum, DS1 Physical Layer Specification, Version 1.0, af-phy-0016, September
1994
5. ATM Forum: UTOPIA Specification Level 1, Version 2.01, af-phy-0017.000, March
1994
6. ATM Forum: UTOPIA Level 2 Specification, Version 1.0, ATM Forum Contribution afphy-0039.000, June 1995.
7. ATM Forum, “E1 Physical Interface Specification”, af-phy-0064.000, September, 1996
8. ATM Forum, Inverse Multiplexing for ATM (IMA Specification, Version 1.1, af-phy0086.001, February, 1999
9. ATM Forum, “ATM on Fractional E1/T1”, str-phy-fn64-01.00, July, 1999
10.ATM Forum, Circuit Emulation Service Interoperability Specification Version 2.0, afvtoa-0078.000, January, 1997.
11.ATM Forum, “User-Network Interface Specification”, Version 3.1, 1994
12.Bellcore, Generic requirement, ATM and AAL protocols, GR-1113-CORE, Issue 1,
July 1994
13.Bellcore, Asynchronous Transfer Mode (ATM) and ATM Adaptation Layer (AAL)
Protocols Generic Requirements, GR-1113-CORE, Issue 1, July 1994.
14.Bellcore, “Digital Cross-Connect System - Generic Requirements and Objectives”,
TR-NWT-000170, Issue 2, January, 1993
15.Bellcore, B-ISDN UNI and NNI Physical Layer Generic Criteria, TR-NWT-001112,
Issue 1, June 1993
16.Bellcore, Transport Systems Generic Requirements, TR-TSV-000499, Issue 4,
December 1991
17.ETSI, B-ISDN ATM Adaptation Layer (AAL) Specification Type 1, prI-ETS 300353,
December 1994
18.ETSI, Transmission and Multiplexing (TM); Generic Frame Structures for the
Transport of Various Signals (including ATM cells) at the CCITT Recommendation.
G.702 Hierarchical Rates of 2048-kbit/s, 34368-kbit/s and 139264-kbit/s; prETS 300337, February 1993
19.IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan
Architecture
20.Infineon, Data sheet: Frame and Line Interface Component (FALC), PEB 2254
21.Infineon, Prelininary Product Overview: Smart Integrated Digital Echo Canceller
(SIDEC), PEB 20954
Data Sheet
288
2002-05-06
PXB4219 / PXB4220 / PXB4221
Bibliography
22.ITU-T, Recommendation G.131, Control of talker echo, revised 1996
23.ITU-T, Recommendation G.703, Physical/Electrical Characteristics of Hierarchical
Digital Interfaces, Geneva 1991
24.ITU-T, Recommendation G.704, Synchronous Frame Structures used at 1544, 6312,
2048, 8488 and 44736 kbit/s Hierarchical Levels, 07/95
25.ITU-T, Recommendation G.775, Loss of Signal and Alarm Indication Signal Defect
Detection Criteria for Equipment Interfaces described in Recommendation G.703 and
Operating at Bit Rates described in Recommendation G.702, COM 15-R 9-E, October
1993
26.ITU-T, Recommendation G.804, “ATM Cell Mapping into Plesiochronous Digital
Hierarchy (PDH)”, February 1998
27.ITU-T, Recommendation G.823, The Control of Jitter and Wander within Digital
Networks which are based on the 2048-kbit/s Hierarchy, March 1993
28.ITU-T, Recommendation G.824, The Control of Jitter and Wander within Digital
Networks which are based on the 1544-kbit/s Hierarchy, March 1993
29.ITU-T Recommendation I.231.10, “Circuit-mode Multiple-rate Unrestricted 8 kHz
Structured Bearer Service Category”
30.ITU-T, Recommendation I.361, B-ISDN ATM Layer Specification, 11/95
31.ITU-T, Draft Recommendation I.363.1, B-ISDN ATM Adaptation Layer specification:
Type 1 AAL, 08/96
32.ITU-T Recommendation I.432 “B-ISDN user-network interface - Physical layer
specification”, March, 1993
33.ITU-T Recommendation I.432.1 “B-ISDN user-network interface - Physical layer
specification: General characteristics”, August, 1996
34.ITU-T Recommendation I.432.3 “B-ISDN user-network interface - Physical layer
specification: 1544 kbit/s and 2048 kbit/s operation”, August, 1996
Data Sheet
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2002-05-06
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