100MSPS 12-Bit Track and Hold Amplifier AL1210 FEATURES • 100MSPS Sampling Rate (8-Bit) • 50MSPS Sampling Rate (12-Bit) • 5ns Acquisition Time (8-Bit) • 4ns Output Settling Time (8-Bit) • 0.018% Nonlinearity • 5µ V/°C Hold Offset • 1ps Aperture Jitter • 400MHz Small Signal Bandwidth • Low Power (400mW Max.) • Small Footprint Package (SOIC) APPLICATIONS • Flash A/D Driving • CCD Imaging Systems • Radar and IF Processors • Data Acquisition Systems • Deglitching 50 MSPS GENERAL DESCRIPTION The AL1210 is an extremely fast and accurate monolithic track and hold amplifier. Even at input frequencies of up to 20MHz, and sampling rates of 50MSPS, its outstanding performance allows full 12-bit linearity to be maintained. Under these extremely fast conditions, the TOTAL harmonic distortion introduced by the AL1210 is still only -70dBc. Its primary application is as a track and hold with the new generation high speed flash A/D converters. By using the AL1210 with these converters, it is now possible to obtain meaningful 10-bit performance at input frequencies of up to 40MHz and sampling rates of up to 75MSPS. If the AL1210 were not used, the meaningful resolution would drop down to 6 bits or less. At 50MHz the TOTAL harmonic distortion is only -59dBc. The noise that a track and hold circuit generates must be significantly below the resolution or noise of the A/D converter in order not to limit the dynamic range of the system. The causes of noise in a track and hold are quite complex and come from several sources. In the AL1210 these noise sources are kept very low, for example, an aperture jitter of only 1ps and a total output noise of only 50µV. To obtain this remarkable performance, innovative circuit design and careful layout have been used. It is fabricated in a very fast complementary bipolar process. The AL1210 is packaged in a 16-pin SOIC in order to keep the pin inductances and capacitances to a minimum. 16 15 14 13 12 11 10 9 AL1210 Active Bridge +1 + +1 – 1 2 3 4 5 6 7 8 Block Diagram INPUT 1 16 NC* NC* 2 15 D TRACK NC* 3 14 D HOLD GND 4 13 +5V AMP -5V AMP 5 12 +5V I/P -5V I/P 6 11 +5V O/P -5V O/P 7 10 +I LIMIT -I LIMIT 8 9 OUTPUT AL1210 Pin Out *It is reccomended that the unconnected pins be grounded Acculin supplies information in the belief that it is accurate, but is not responsible for its use; nor for any infringements of patents or other rights of third parties which may result from its use. If it is found not to be accurate, please inform Acculin as soon as possible. No license is granted by implication or otherwise under any patent rights of Acculin. Acculin Inc. 209 West Central Street, Natick Massachusetts 01760 U.S.A. Tel: (508) 650-1012 Fax: (508) 650-1457 Electrical Characteristics Parameter Units Temp Test Level mV mV µV/°C µV/°C V/V V/V ppm/°C V/V V/V ppm/°C % % % % mA mA mA mV/V mV/V +25°C Full Full Full +25°C Full Full +25°C Full Full +25°C Full +25°C Full +25°C Full +25°C Full Full +25°C Full I VI IV IV I VI IV I VI IV I VI I VI IV IV IV VI IV I VI V µA µA kΩ kΩ pF Full +25°C Full +25°C Full Full IV I VI I VI IV -2.5 -65 -90 170 110 V V µA µA µA µA Full Full +25°C Full +25°C Full IV IV I IV I IV -2.9 0.4 MHz MHz MHz MHz µVrms µVrms nV/√ Hz nV/√ Hz pA/√ Hz pA/√ Hz V/µs V/µs V/µs V/µs +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full IV IV IV IV IV IV IV IV IV IV V IV V IV dBc dBc dBc dBc dB dB dB dB +25°C Full +25°C Full +25°C Full +25°C Full V IV V IV V IV V IV Min (VCC=5V, VEE=-5V, RL=1k, CL=20pF, unless otherwise specified) AL1210S Typ Max Min AL1210A Typ Max Min AL1210J Typ Max DC ACCURACY Track Offset Track temperature coefficient1 Hold temperature coefficient1,2 Track Gain (no load) temperature coefficient1 Hold Gain (no load)2 temperature coefficient1 Track Nonlinearity3 Hold Nonlinearity2,3 Output resistance4 Output drive capability without short circuit protection PSRR Ω Ω -15 -20 0.990 0.980 0.990 0.990 -8 20 2 0.993 0.990 20 0.995 0.995 15 0.018 0.015 6 6 20 15 50 8 0 5 40 20 1.000 1.000 30 1.000 1.000 30 0.030 0.035 0.030 0.030 10 11 45 50 -15 -20 0.990 0.980 0.990 0.990 -8 20 2 0.993 0.990 20 0.995 0.995 15 0.018 0.015 6 6 20 15 50 8 4 6 0 5 40 20 1.000 1.000 30 1.000 1.000 30 0.030 0.030 0.030 0.030 10 11 45 50 -15 -20 0.990 0.980 0.990 0.990 -8 20 2 0.993 0.990 20 0.995 0.995 15 0.018 0.015 6 6 20 15 50 8 4 6 0 5 40 20 1.000 1.000 30 1.000 1.000 30 0.030 0.030 0.030 0.030 10 11 45 50 4 6 ANALOG INPUT Voltage range5 Bias current Resistance Capacitance -15 2.5 10 20 300 -2.6 -65 -75 170 140 -15 2.6 10 15 300 2 -2.7 -65 -65 170 170 -15 2.7 10 15 300 2 2 DIGITAL INPUTS Voltage range differential Bias current high Bias current low 10 1.9 5 25 50 -3.0 0.4 10 2.0 5 25 40 -3.1 0.4 10 -85 -170 -40 -85 -130 -40 -85 -110 -40 300 300 350 350 400 300 300 350 350 400 300 300 350 350 400 2.1 5 25 35 TRACK MODE DYNAMICS Bandwidth to output (-3dB) Bandwidth to hold cap. (-3dB) Total noise at output Output noise density Input current noise Capacitor slew rate Output slew rate Total Harmonic Distortion 20MHz 0.5Vpp 50MHz 0.5Vpp PSRR to hold cap. (20MHz) PSRR to output (20MHz) 400 45 5 3.5 55 65 5.5 6.5 5.5 7 400 45 5 3.5 700 55 65 5.5 6 5.5 6.5 5 3.5 550 550 550 475 550 475 -74 475 -74 -68 -54 -74 -68 -54 -48 -34 -48 -32 -48 -34 -32 -26 -24 -68 -54 -34 -26 55 65 5.5 6 5.5 6 700 550 -2- 45 700 550 400 -32 -26 -24 -24 AL1210 Parameter Units Temp Test Level dB dB mV/µs mV/µs ms ms mV√s mV√s dB +25°C Full +25°C Full +25°C Full +25°C Full Full IV IV I VI IV IV V IV IV ps ps rms mV mV µV/°C mV/V mV/V mV mV pVs pVs ns ns ns ns µV µV Full Full +25°C Full Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full IV IV I VI IV IV IV V IV V IV V IV V IV V IV ns ns ns ns ns ns ns ns ns ns mV +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C IV IV IV IV IV IV IV IV IV IV IV dBc dBc Full Full IV IV mA Full VI V V W Full Full Full V V VI Min AL1210S Typ Max Min AL1210A Typ Max Min AL1210J Typ Max HOLD MODE DYNAMICS Feedthrough (10MHz, 2Vpp) Droop rate6 time constant7 Hold noise 8 PSRR (20MHz) -80 2.5 0.5 0.2 -75 -75 5 15 2 -80 2.5 0.5 0.5 50 2 21 -500 -250 1 5 -80 2.5 0.5 0.5 50 150 18 -75 -75 5 10 2 50 150 18 21 -500 -250 1 5 -75 -75 5 15 150 18 21 -500 -250 1 5 TRACK TO HOLD SWITCHING Effective aperture delay9 Aperture jitter Pedestal offset temperature coefficient1 sensitivity to supply voltage Transient amplitude peak-peak10 Glitch impulse10 Settling time to 4mV11 Settling time to 0.5mV11 Total sampled noise (50MSPS)12 20 0.5 0 2 15 20 40 1 2 20 0.5 20 0 2 15 20 40 1 2 20 0.5 20 50 20 50 20 50 20 50 20 50 4 50 4 6 0 2 15 20 40 1 2 4 6 8 6 8 12 8 12 50 12 50 100 50 100 100 HOLD TO TRACK SWITCHING Acquisition time11,13 1% 2V step 0.1% 2V step 0.01% 2V step 1% 200mV step 0.1% 200mV step Output overshoot 2V step 6 8 6 8 6 8 7.5 9 7.5 9 7.5 9 12 14 12 14 12 14 4 6 4 6 4 6 6.5 7 6.5 7 6.5 7 10 20 10 20 10 20 -70 -59 -64 -53 -70 -59 -64 -53 -70 -59 -64 -53 30 36 40 30 36 40 30 36 40 4.75 –5.25 0.3 5 –5 0.36 5.25 –4.75 0.4 4.75 –5.25 0.3 5 –5 0.36 5.25 –4.75 0.4 4.75 –5.25 0.3 5 –5 0.36 5.25 –4.75 0.4 THROUGHPUT DISTORTION Total harmonics 0dBm, 50MSPS14 18.75MHz 43.75MHz15 POWER REQUIREMENTS Total supply current Supply voltages positive negative Power dissipation NOTES 1 End point average 2 Hold mode values include track mode and pedestal errors 3 End point over ± 2V 4 Measured at 5mA output current 5 Voltage range which the output is guaranteed to cover 6 Rate of voltage change in hold mode 7 Decay time constant of the voltage on the hold capacitor 8 Noise accumulated during hold, e.g. at 50mV√ s, holding for 10ns will accumulate a 5 µ Vrms error 9 The delay in the analog signal path is greater than the delay in the digital signal path; therefore the effective aperture delay is negative 10 Excluding pedestal 11 Specified from the time of the digital command 12 Includes all sources of noise above 10kHz in the track and hold, driven from a 50-ohm source, excluding aperture jitter 13 Time for which the track and hold must be kept in track mode to acquire to within the specified precision 14 Includes all sources of distortion in the track and hold, measured by FFT analysis 15 This signal is under sampled, and therefore aliased, which does not present a problem in specifying the distortion -3- Pin Name Pin No. INPUT NC 1 Pin Description Analog input to the track and hold. 2,3,16 These pins have no internal connection, but do perform an important function. They should be grounded to obtain good isolation between the adjacent pins in the lead frame. GND 4 Ground connection for the hold capacitor. This should be connected to a ground plane with the minimum inductance possible. –5V AMP 5 Negative power supply for the amplifier following the hold capacitor. This should be connected to -5V. In order to achieve good isolation from the digital signals and the analog input, it may be desirable to isolate this supply from the input supply. –5V I/P 6 Negative power supply for the input stages of the track and hold should be connected to -5V. This supply is connected to the internal substrate of the circuit, and therefore no pin should be significantly more negative than this one. Since the current drawn from this supply charges the storage capacitor, it has substantial transients during high slew rates, such as acquisition. It is important for optimum operation that these currents do not induce high speed voltage changes, and this pin therefore should be well decoupled to ground. Series resistance on the power supply side of the decoupling capacitor also can be used to prevent any remaining transients from disturbing the other supplies. –5V O/P 7 Negative power supply for the output devices. The nature of the current drawn by this pin is dependent on the load presented to the track and hold output. If the -I LIMIT pin is well decoupled, then the currents drawn will not be subject to large high speed transients. However if a 50-ohm load is driven, then the current drawn by this pin may be correspondingly large. –I LIMIT 8 In normal operation this pin should be decoupled to ground, and will supply transient currents required by the load. The internal output current limit is between this pin and the -5V O/P pin, and therefore these transients will not cause current limiting. If this pin is left unconnected, the current limit will be fast acting, and the -5V O/P should be well decoupled. A large transient of output current will cause current limiting, and consequent serious degradation of output settling time. If current limiting is not required, this pin may be connected to -5V O/P and the pair well decoupled. An output short circuit under these conditions will destroy the device. OUTPUT 9 Output of the track and hold. This pin is capable of directly driving highly capacitive loads, such as flash A/D converters, or 50-ohm line. If it is required to drive more than 20mA continuously, the current limit should be disabled. No more than 50mA should be drawn. +I LIMIT 10 See - I LIMIT, except with respect to +5V O/P. +5V O/P 11 See -5V O/P, except positive supply. +5V I/P 12 See -5V I/P, except positive supply. +5V AMP 13 See -5V AMP, except positive supply. DHOLD 14 One of the digital input pins. It is recommended that these be driven by high speed ECL in a complementary fashion. Particular care should be taken in deriving these signals to keep the edge position jitter to a minimum. This track and hold has very good aperture jitter performance, but can be no better than the jitter on signals presented to the device. High slew rate and fast settling also are desirable attributes for these signals. DTRACK 15 Complementary signal to DHOLD. When DTRACK is higher than DHOLD, the device is in track mode; and when lower, it is in hold mode. Although for optimum performance, high speed ECL is recommended; it is possible to use other levels, subject to the limitations of the common mode and differential voltages in the specification. RECOMMENDED OPERATING CONDITIONS Supply voltages .......... ± 5V Ambient temperature range . . . . . AL1210S -55 to +125°C . . . . . . . . . . AL1210A -25 to +85°C . . . . . . . . . . AL1210J 0 to +70°C Analog input range . . . . . . . . . . ± 2V Digital inputs .......... Balanced ECL ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS -0.5V -3V -5V (-5V I/P) - 0.5V -55°C -65°C I 100% production tested II 100% production tested at +25°C; sample tested at temperature extremes III Sample tested only IV Parameter is guaranteed by design and characterization V Parameter is a typical value only VI 100% production tested at +25°C; military parts 100% tested at temperature extremes -50mA < < < < < < (+5V I/P) - (-5V I/P) INPUT (D TRACK) - (D HOLD) (Any Pin) Ambient temperature Storage temperature Lead temperature (10s) < Continuous output current < 12.5V < 3V < 5V < (+5V I/P) + 0.5V < 125°C < 150°C < 300°C < 50mA Operation of the device beyond these limits may impair performance permanently -4- AL1210 TYPICAL PERFORMANCE CHARACTERISTICS Feedthrough vs Frequency Gain vs Frequency 2 -20 Track Mode -30 0 -4 -6 -8 -60 -70 -80 -90 -10 -100 -12 -14 -50 Gain (dB) Gain (dB) -40 Hold Mode -2 -110 0 100 200 300 400 -120 1M 500 10M 100M 1G Frequency (Hz) Frequency (MHz) Drooprate vs Temperature Offset vs Temperature 5 10 4 6 4 Offset (mV) Drooprate (mV/µs) 8 3 2 Hold Mode 2 0 -2 -4 1 Track Mode -6 -8 0 -50 0 -25 25 50 75 -10 -50 100 125 -25 Temperature (˚C) 0 25 50 75 100 125 Temperature (˚C) Linearity vs Temperature THD vs Input Frequency 0.05 50 50MSPS 0dBm 55 60 THD (-dBc) +2V ENL (%) 0.04 0.03 Track Mode 0.02 Hold Mode 65 70 Hold Mode 75 80 0.01 Track Mode 85 0 -50 -25 0 25 50 75 90 0 100 125 Temperature (˚C) 5 10 15 20 25 30 35 40 45 5 0 Input Frequency (MHz) -5- +1V Analog Input Point Held 0V -1V 1 Acquisition Time Digital Inputs HOLD 0 TRACK Output Acquisition Time Aperture Delay -250ps HOLD Settling Time 5ns Glitch Impulse Pedestal 5mV +1V Output 0V -1V Typical Waveforms 2ns/div GLOSSARY OF TRACK AND HOLD TERMINOLOGY Acquisition Time is the time for which the device has to be switched into track mode in order to acquire the new voltage within a specified percentage of the specified change in voltage. Feedthrough is the effect that a change in the analog input voltage has upon the output voltage when the device is in hold mode. Feedthrough is usually worse at higher frequencies. Aperture Delay is the time delay between the hold Output Acquisition Time is the time from when the command input and the point at which the input is sampled. This can be either positive or negative, depending on the relative delays in the analog and digital signal paths. The exact value is rarely important, but matching between multiple track and holds in a system can be. In some vendors’ specifications this figure is excluded from settling time, in which case its magnitude does become significant. device is switched into track mode, to when the output has settled to within a specified percentage of the specified change in voltage. Some vendors’ specifications call this the acquisition time. Aperture Jitter is the random variation in aperture delay from sample to sample, expressed as an rms time. Aperture jitter will cause an increase in noise in the presence of high slew rate input waveforms. The extra voltage noise on a sample will be the product of the input slew rate and the aperture jitter. Delays are included in the acquisition and settling times, and therefore are not specified. Droop Rate is the rate at which the output voltage changes while the device is in hold mode. For short hold times this is not significant, but over long hold intervals it can cause errors. The estimation of these errors is discussed elsewhere in this data sheet. Output Settling Time is the time from when the device is switched into hold mode, to when the output has settled to within a specified voltage of its final value. Pedestal Offset is the voltage step on the output as the device switches into hold mode, and may be treated as an offset. If it is nonlinear with respect to the input voltage or the slew rate, it will introduce distortion. The pedestal offset of the AL1210 is very linear and stable, and the linearity specification includes pedestal error. Throughput Cycle Time is the total throughput capability of the device while the output is settling to a given level of accuracy. Track to Hold Transient is the glitch on the output voltage when the device is switched into hold mode. This is specified in four ways: 1) peak-to-peak magnitude; 2) glitch impulse, which is the area contained within the glitch in Volt-seconds; 3) pedestal offset, which is where it finally settles; and 4) output settling time. -6- AL1210 GENERAL DISCUSSION OF TRACK AND HOLD PERFORMANCE Noise Considerations 1) The total harmonic distortion is often of interest, and is sometimes specified as a signal-to-noise ratio, which includes the noise contribution. In systems where data from the converter is subject to digital signal processing, it is necessary to know the contributions to error separately. Distortion and noise integrate differently because distortion is correlated to the signal whereas noise is uncorrelated. There are various sources of noise present in any electronic circuit. The AL1210 has been characterized for its noise performance, but many contributions to noise are dependent on the circuit in which it is used. The various sources of noise are uncorrelated, and the total voltage noise is therefore the rms sum of the noise contributions. Low drive impedance is desirable to prevent input current noise from developing extra voltage noise at the input. The contribution to noise will be the product of the input current noise and the driving impedance. The resistive part of the source impedance also will generate thermal noise. Any noise present at the input obviously is included in the sampled signal, and therefore should be minimized. Attention should be given to the bandwidth of the noise source. If the noise density on the input is sufficiently low, then the high bandwidth of the AL1210 will not present a problem; on the other hand, if reduction of amplitude response variation with frequency is important, it will be undesirable to limit the bandwidth. Hold noise is a result of random charges accumulating on the hold capacitor. Voltage error will accumulate in proportion to the square root of the hold time, and normally will not be significant, although it is specified for the AL1210. Noise on the power supplies will couple into the signal path, reduced by the power supply rejection ratio. This noise can be minimized by effective decoupling of the supplies at the pins. Aperture jitter will cause an increase in noise in the presence of high slew rate input waveforms. The extra voltage noise on a sample will be the product of the input slew rate and the aperture jitter. Aperture jitter of 1ps rms is difficult to maintain. The use of balanced high-speed low-impedance logic helps to minimize jitter degradation. Single-ended TTL driving, although convenient, will degrade this aspect of performance. Nonlinearity Considerations Nonlinearity can arise in a variety of ways and is normally measured either as a proportion of the voltage range used (the usual low frequency measurement), or as the harmonic distortion introduced to a sine wave (the usual high frequency measurement). Some caution should be taken in comparing harmonic distortion specifications. Often harmonic distortion will be specified as the ratio of the largest harmonic to the fundamental. Furthermore with track and hold circuits, it is commonly specified in track mode only. While these are useful specifications other factors are significant, in particular: 2) A distortion specified in track mode does not include errors introd uced by the sam pling process. The hold-to-track and track-to-hold settling times place limits on the distortion, but the figures are not readily convertible. There is a nonlinear DC transfer characteristic imposed upon the signal which causes distortion of the signal independent of frequency. This nonlinearity is usually specified as a percentage of the voltage range over which it is measured, either compared to a straight line joining the endpoints (endpoint nonlinearity or ENL), or to a best-fit straight line. The AL1210 specification is endpoint nonlinearity. There is a dynamic contribution to nonlinearity during slew. While the signal is slewing, the output of any circuit will lag behind the change in the input. As the slewrate of the signal changes, this lag changes; and there is some nonlinearity in the change. Typically in flash A/D converters, this nonlinearity results in increased distortion as the input slew rate increases. The AL1210 is of great value in alleviating this problem. The level of dynamic distortion in the AL1210 is much lower than in flash A/D converters. The output of the AL1210 is not slewing when the flash A/D is sampling the signal, which results in the full accuracy of the converter being realized, even at high input frequencies. Thus the harmonic distortion performance of the system is improved dramatically. Further dynamic distortion occurs in flash A/D converters because of a variation in aperture time with input voltage. The distortion associated with this aperture time change is removed when the AL1210 is used to drive the A/D. The output of the AL1210 is not slewing at the time the flash converter samples it; therefore the change in aperture time does not result in a voltage error. The output stage of the AL1210 is capable of driving low impedance loads. While high currents are being drawn from the output, there is an additional contribution to nonlinearity. This does not affect the system performance driving a flash A/D with a high capacitance input. At the time the flash conversion occurs, the voltage on the output of the AL1210 is static, so no capacitive current is drawn. However if a low resistive impedance is presented to the output of the AL1210, the linearity will be reduced. The input resistance of a flash A/D is unlikely to be low enough to cause any significant degradation of linearity. -7- During hold mode, the leakage current to the hold capacitor will cause the voltage on the capacitor to drift. As a result, an offset will develop during the hold interval prior to a flash A/D sampling the output. If this interval is not fixed, and if the hold interval and the signal are uncorrelated, this offset will manifest itself as noise. If the hold interval and signal are correlated, this offset will manifest itself as distortion. The most probable situation is that the flash A/D converter will sample the output of the track and hold at a fixed time after the signal is acquired. The drift will result in an offset error, which will have a temperature coefficient related to the temperature coefficient of the leakage current. If the leakage current contains a resistive component, the amplitude of the signal will change with hold time, thereby causing a gain error. However if the leakage current is nonlinear with voltage, a distortion will be introduced with hold time. In a flash A/D driving circuit, this distortion is unlikely to be significant. Timing Considerations Throughput is the key specification for the performance of a track and hold and is the rate at which the device can sample signals to a given level of accuracy. Unfortunately this is rarely specified, and therefore has to be estimated. The specifications that are given for track and hold devices vary, and the definitions of the same specification figure also vary. The definitions used for the AL1210 are given in the Glossary. The AL1210 timing specifications are all measured from the time of the digital command, which is when the two input logic levels cross. This results in a relatively simple estimation of cycle time as the sum of the acquisition time to the required accuracy; the output settling time to the required accuracy; and any interval for which the output is to be held stable for the benefit of subsequent circuitry. Some specifications do not measure from the digital command, but add delay specifications and then specify times from when the output begins to change. This is not a very satisfactory specification because “begins to change” is not a well-defined point, and the output will probably have a transient upon it at the time the logic levels on the digital input change. This may be satisfactory if the interval is a pure delay, but this is not the case if the output has a transient at the logic switching time. Few designers will be prepared to sample the output of the track and hold during this interval; and therefore this delay adds to the useful acquisition and output settling times and reduces the total throughput. From a designer’s viewpoint, the most useful specification is the throughput rate for the required accuracy, which is usually not specified directly in the data sheet. It is a difficult parameter to test in production, and depends to some extent upon the circuit in which it is used. The AL1210 has a specified throughput harmonic distortion (sometimes called hold mode distortion). Sampling Below Nyquist The AL1210 is quite capable of sampling signals of higher frequencies than can be resolved by the sampling rate unambiguously, subject to the available bandwidth. However it should be recognized that distortion of the input signal is primarily a result of slew rate: the higher the amplitude of a high frequency sine wave, the higher the distortion. The AL1210 has a distortion specification for a 1Vpp 50MHz input. The effect of aperture jitter at high slew rates also will increase the noise level. Circuit Techniques The AL1210 is capable of driving typical capacitive loads with relatively little lengthening of output settling time; however resonant loads can cause more significant settling time increases. The most common way of presenting a resonant load is as a capacitive load at the far end of a length of line. Even a few centimeters of line can be very significant. The AL1210 therefore should be mounted very close to the load it is driving. If this is not possible, then a resistor in series with the output can help to damp the ringing that occurs, and can keep the output settling time reasonably short. The power supplies of the AL1210 are brought out of the package separately. This minimizes the mutual coupling that would occur as a result of the inductance of the package pin. In order to preserve isolation, the tracks from these pins should be kept separate until they are decoupled to ground, which should be as close as possible to the package. Series resistors in the power supplies, as shown in the evaluation board schematic, can help to preserve this isolation. The AL1210 contains current limiting circuitry to prevent destruction of the device under short circuit output conditions. Decoupling the -I limit and +I limit pins will allow larger output currents to flow for short periods. Connecting -I limit to -5V O/P and +I limit to +5V O/P will disable completely the current limiting function. Analog delay is the propagation time for a signal from the input to the output. In some specifications this is excluded from settling time figures; if it is included in settling time, it is of little significance. -8- AL1210 +5V IC2 MC10H116FN C10 .039 ECL LOGIC INPUT SMA J1 R5 10 –5.2V 17 D2 Q2 15 D2 Q2 13 D1 Q1 12 D1 Q1 7 D0 Q0 5 D0 Q0 VBB C2 .039 19 18 9 R6 10 C1 .039 R2 220 8 R3 220 C3 .039 12 +5 14 DH 15 DT 4 3 J4 +5 SJC SJC 14 C4 .039 13 11 +5 J5 2,3,4,16 R1 50 GND AL1210 -5 SMA J2 1 SJC PIN J9 + + C12 4.7 PIN J10 PIN J11 –5V +5V + SMA J3 SJC J7 C8 .039 -5 6 C7 .039 –5.2V C13 4.7 OUTPUT -5 5 R4 50 J6 GND SL1 C9 .039 7 IN C14 22pF 10 9 IL+ IL– OUT 8 IC1 ANALOG INPUT PIN J8 C5 .039 SL1 Solder Bridge Link To Select SMA Output C6 .039 Evaluation Board Schematic Capacitances in µF unless otherwise stated Resistances in Ω unless otherwise stated R7 10 C11 4.7 R8 10 –5V LAYOUT CONSIDERATIONS As with any high speed precision circuit, good printed circuit board layout is necessary. A small package and the use of surface mounting help to reduce the parasitic inductances associated with the pins. The package inductance of pin 4 to ground is already the limiting factor for both acquisition time and output settling time. Therefore pin 4 should be connected directly to an extensive ground plane. Pins 2, 3 and 16 should be grounded; this will minimize capacitive coupling between digital and analog inputs which would otherwise degrade performance. Ground return paths for the input, digital inputs, output and power supply decoupling should not intersect within the ground plane as this would cause mutual coupling of these signals. The input and digital control lines should be transmitted via properly terminated transmission lines, such as microstrip or stripline, if they are longer than 20 or 30mm. The output path should either be kept very short or be properly terminated. The part is capable of driving 50-ohm line, although doing so will reduce the linearity. Unterminated line on the output will adversely affect output settling time. The capacitive load presented by typical flash A/D converters does not present a linearity problem, in spite of its very nonlinear nature, because the output voltage is settled at the time the flash converter is fired. Correct power supply decoupling is very important; typically 0.01µ F surface-mounted multilayer capacitors should be placed as close as possible to the power supply pins of the AL1210. Further isolation of the supplies may be achieved by the use of small series resistors, as in the evaluation board. These resistors and capacitors prevent the high speed transient currents from the track and hold causing voltage transients on the supplies; and also prevent external high frequency transients from reaching the device supplies. It is important that the supplies are stable and contain no lower frequency transients; therefore sharing a supply with logic is not recommended unless thorough supply filtering is employed. The use of sockets is not recommended because of the associated increase in stray inductances. The layout of the evaluation board (AL1210-EVAL) is shown above, and fulfills all of the layout requirements satisfactorily. The schematic of the board is shown above, and illustrates how the part may be used. When the device forms part of a larger circuit, considerable benefit can be gained through the use of a multilayer board. The evaluation board is available to assist the designer in assessing the capabilites of the AL1210 without having to arrange a test fixture. The evaluation board includes an ECL line receiver (IC2) as a convenience to provide balanced logic to the AL1210; other balanced logic sources may be used. In a larger circuit, it may be preferable to terminate the ECL in 50 ohms to -2V depending upon the logic transmission environment. -9- Acculin Inc. 214 N. Main St. Natick, MA 01760 Tel (508)650-1012 Fax (508)650-1457 -5.2 IC2 J9 C13 J4 -5 C12 R2 R3 J10 GND C11 R1 C1 C10 J8 +5 LOG. INPUT J11 C3 C2 C4 C5 C14 J5 R6 R8 R7 J7 R5 IC1 ANA. INPUT AL1210JR R4 C7 C6 C8 C9 OUTPUT J6 AL1210-EVAL Component Side Metal Rev. B Component Layout Back Side Metal Evaluation Board Layout ORDERING INFORMATION Model Temp Range Package AL1210JR 0 to +70°C 16-pin SOIC AL1210AR -25 to +85°C 16-pin SOIC AL1210SE -55 to +125°C 20-terminal LCC AL1210SJ/2 -55 to 125°C 20 J-Lead Ceramic AL1210-DIE Various Unpackaged AL1210-EVAL Evaluation Board PCB PACKAGE DIMENSIONS SOIC-16 PACKAGE (R SUFFIX) MILLIMETERS B DIM MIN INCHES MAX MIN MAX Pin 1 A A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G G P R x 45˚ M˚ C J F D K 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 0.009 K 0.10 0.25 0.004 M 0° 7° 0° 7° P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 NOTES: 1. CONTROLLING DIMENSION: MILLIMETER 2. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION 3. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE - 10 - AL1210 LCC-20 PACKAGE (E SUFFIX) MILLIMETERS Bottom View DIM D1 L Terminal 1 e B1 h x 45˚ D MAX INCHES MIN MAX 0.100 A 1.63 2.54 0.064 B1 0.56 0.71 0.022 0.028 D 8.69 9.09 0.342 0.358 D1 1.91 REF 0.075 REF e 1.27 BSC 0.050 BSC j 0.51 REF 0.020 REF h 1.02 REF 0.040 REF L j x 45˚ MIN 1.14 1.40 0.045 0.055 NOTES: 1. CONTROLLING DIMENSION: INCH 2. DIMENSION A IS OVERALL PACKAGE THICKNESS 3. DIMENSION D APPLIES TO ALL FOUR SIDES A 20 J-LEADED CERAMIC (J/2 SUFFIX) package as LCC-20 with leads attached MILLIMETERS DIM A MIN 2.54 MAX 5.08 INCHES MIN MAX 0.100 0.200 B 0.31 0.46 0.012 0.018 D 8.69 9.34 0.342 0.368 D2 7.16 7.82 0.282 0.308 R 0.64 0.89 0.025 0.035 NOTES: 1. CONTROLLING DIMENSION: INCH 2. DIMENSIONS D AND D2 APPLY TO ALL FOUR SIDES Conversion Table 16-Pin SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20-Term Ceramic 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 20 UNPACKAGED DIE (-DIE SUFFIX) MILLIMETERS 15 14 13 12 11 10 DIM 9 AL1210-DIE B 8 1 4 5 6 MIN MAX INCHES MIN MAX 0.086 A 1.93 2.18 0.076 B 1.27 1.52 0.050 0.060 C 0.28 0.43 0.011 0.017 7 NOTES: 1. CONTROLLING DIMENSION: MILLIMETER 2. DIMENSION C IS OVERALL DIE THICKNESS 3. NUMBERS BY BONDPADS REFER TO SOIC PINS A November 2000 - 11 -