PIC16CR64 PIC16CR64 Rev. A Silicon Errata Sheet The PIC16CR64 (Rev. A) parts you have received conform functionally to the Device Data Sheet (DS30234D), except for the anomalies described below. Work Around To have the I/O pin high until the compare match low occurs, force a compare match high to get the I/O pin into the high state, then reconfigure the compare match to force the I/O low, when the compare condition occurs. All the problems listed here will be addressed in future revisions of the PIC16CR64 silicon. 1. Module: CCP (Compare Mode) The Compare mode may not operate as expected when configuring the compare match to drive the I/O pin low (CCPxM<3:0> = 1001). 2. The special event trigger of the Compare mode may not occur if both of the following conditions exist: • An instruction one cycle (TCY) prior to a Timer1/ Compare register match has literal data equal to the address of a CCP register being used.(1) • An instruction in the same cycle as a Timer1/ Compare register match has an MSb of ‘0’. When the CCP module is changed to compare output low (CCPxM<3:0> = 1001) from any other noncompare CCP mode, the I/O pin will immediately be driven low regardless of the state of the I/O data latch. The pin will remain low when the compare match occurs (see Table 1). The interrupt for the compare event will still be generated, but no special event trigger will occur. However, when the CCP module is changed to compare output high (CCPxM<3:0> = 1000) from any other CCP mode, the I/O pin will immediately be driven low regardless of the state of the I/O data latch. The pin will be driven high when the compare match occurs. Note 1: 15h(CCPR1L), 16h(CCPR1H) or 17h(CCP1CON) for CCP1. Work Around Use the interrupt service routine instead of using the special event trigger to reset Timer1 (and start an A/D conversion, if applicable). Compare Output Low Switching TABLE 1: 3. CCP Mode CCPxM<3:0> = 0xxx 1000 1001 101x 11xx Note: I/O pin State Change CCP to CCPxM<3:0> = 1001 1000 H L L L L L H H — L L — H — L L — L H L L L L L H L L L L L Module: CCP (Compare Mode) Module: SSP Module (I2C™ mode) If the bus is active when the I2C mode is enabled, and the next 8-bits of data on the bus match the address of the device, then the SSP module will generate an acknowledge pulse. Work Around Before enabling the I2C mode, ensure that the bus is not active. As with any windowed EPROM device, please cover the window at all times, except when erasing. 1998 Microchip Technology Inc. DS30234D/CR64/E2A1-page 1 PIC16CR64 4. 6. Module: SSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter-than-expected SCK pulse may occur on the first bit of the transmitted/received data. Example: Write SSPBUF bit0=1 bit1=0 bit2=1 . . . . SD0 SCK Work Around To avoid producing the short pulse, turn off Timer2 and clear the TMR2 register, load the SSPBUF with the data to transmit, and then turn Timer2 back on. Example Code: BSF STATUS, RP0 LOOP BTFSS SSPSTAT, BF GOTO BCF MOVF MOVWF MOVF BCF CLR MOVWF BSF 5. LOOP STATUS, RP0 SSPBUF, W RXDATA TXDATA, W T2CON, TMR2ON TMR2 SSPBUF T2CON, TMR2ON ;Bank 1 ;Data received? ;(Xmit complete?) ;No ;Bank 0 ;W = SSPBUF ;Save in user RAM ;W = TXDATA ;Timer2 off ;Clear Timer2 ;Xmit New data ;Timer2 on Module: Timer0 The TMR0 register may increment when the WDT postscaler is switched to the Timer0 prescaler. If TMR0 = FFh, this will cause TMR0 to overflow (setting T0IF). Work Around a) b) c) d) Module: Timer1 The Timer1 value may unexpectedly increment if either the TMR1H or the TMR1L register is written. If Timer1 is ON, then turned OFF, performing any write instruction with TMR1H as the destination may cause TMR1L to increment. Example 1: BSF T1CON, TMR1ON : BCF T1CON, TMR1ON MOVF TMR1H, 1 TMR1 value before MOVF instruction: TMR1H:TMR1L = 3F:00 TMR1 value after MOVF instruction: TMR1H:TMR1L = 3F:01 Example 2: BSF T1CON, TMR1ON : BCF T1CON, TMR1ON MOVF TMR1H, 1 TMR1 value before MOVF instruction: TMR1H:TMR1L = FF:FF TMR1 value after MOVF instruction: TMR1H:TMR1L = FF:00 If Timer1 is ON, then turned OFF when TMR1H:TMR1L = xx:FF, performing any write instruction with TMR1L as the destination may cause TMR1H to increment. Example 1: BSF T1CON, TMR1ON : BCF T1CON, TMR1ON CLRF TMR1L TMR1 value before CLRF instruction: TMR1H:TMR1L = FF:FF TMR1 value after CLRF instruction: TMR1H:TMR1L = 00:00 (TMR1IF is not set.) Follow the following sequence: Work Around Read the 8-bit TMR0 register into the W register Clear the TMR0 register Assign WDT postscaler to Timer0 Write W register to TMR0 To preserve Timer1 register values: DS30234D/CR64/E2A1-page 2 Read Timer1 register values into “shadow” registers. Perform any write instruction(s) on the shadow registers. Write the shadow register values back into the Timer1 registers. 1998 Microchip Technology Inc. PIC16CR64 Clarifications/Corrections to the Data Sheet: 1. The specification for the High Voltage Open Drain I/O (The RA4 pin on most devices) cannot be met without possible long term reliability issues on that I/O pin. If a high voltage drive is required, use an external transistor that can support the required voltage. In the Device Data Sheet (DS30234D), the following clarifications and corrections should be noted. TABLE 2: DC SPECIFICATION CHANGES FROM DATA SHEET Data Sheet Specification New Specification Param No. Sym. D150 2. a) Module: I/O Ports VOD Characteristic Open-drain High Voltage Units Min Typ Max Min Typ Max Ñ Ñ 10 Ñ Ñ 14 V Module: SSP (SPI Mode Timing Specificatios) The SPI interface timings have been modified to the values shown in Table 3. TABLE 3: Parm No. Data Sheet Specification New Specification Sym. 71 TSCH 71A 72 TSCL 72A 73A DC SPECIFICATION CHANGES FROM DATA SHEET TB2B Characteristic SCK input high time (slave mode) Continuous SCK input low time (slave mode) Continuous Units Min Typ Max Min Typ Max 1.25 TCY + 30 ns — — TCY + 20 ns — — 40 — — 1.25 TCY + 30 ns — — 40 — — N.A. ns 1.5 TCY + 40 ns — — N.A. ns Single Byte (1) Single Byte (1) Last clock edge of the Byte1 to 1st clock edge of the Byte2 (1) N.A. TCY + 20 ns — ns ns — ns * This parameter is characterized but not tested Note 1: Specification 73A is only required if specifications 71A and 72A are used. 3. a) Module: Timer1 The operation of Timer1 needs some clarification when the timer registers are written when the TMR1ON bit is set. The internal clock signal that is the input to the TMR1 presaler affects the incrementing of Timer1 (TMR1H:TMR1L registers and the Timer1 prescaler). When the Timer1 registers are NOT written, the Timer1 will increment on the rising edge of the TMR1 increment clock. When the TMR1H and/or TMR1L registers are written while this clock is high, TMR1 will increment on the next rising edge of this clock. 1998 Microchip Technology Inc. When the TMR1H and/or TMR1L registers are written while this clock is low, TMR1 will not increment on the next rising edge of this clock, but must first have a falling clock and the the rising clock for TMR1 to increment. Figure 1 shows the two cases of writes to the TMR1H and/or TMR1L registers. Due to the VIH and VIL thresholds on the oscillator/clock pins, external Timer1 oscillator components, and external clock frequency, the Timer1 increment clock may not be of a 50% duty cycle. The TMR1 increment clock is out of phase of the T1OSO/T1CKI pin by a small propagation delay. DS30234D/CR64/E2A1-page 3 PIC16CR64 FIGURE 1: WRITES TO TIMER1 (EXTERNAL CLOCK / OSCILLATOR MODE) TMR1 Increment Clock (input to Prescaler) Write to TMR1H and/or TMR1L register(s) TMR1H:TMR1L increments DS30234D/CR64/E2A1-page 4 Write to TMR1H and/or TMR1L register(s) TMR1H:TMR1L increments 1998 Microchip Technology Inc. PIC16CR64 4. Module: RC Oscillator The table for RC Oscillator Frequencies in the Device Characterization section of the Data Sheet is incorrect. The correct characterization information is shown in Table 4. TABLE 4: RC OSCILLATOR FREQUENCIES CHARACTERIZATION CHANGES FROM DATA SHEET Correct Characterization Data Cext 22 pF 100 pF 330 pF Current Data Sheet Values Rext Average % Variation Average % Variation 5.1 K 3.55 MHz ± 9.63% 4.12 MHz ± 1.4% 10 K 1.99 MHz ± 10.53% 2.35 MHz ± 1.4% 100 K 221.9 KHz ± 12.10% 268 KHz ± 1.1% 3.3 K 1.77 MHz ± 10.67% 1.80 MHz ± 1.0% 5.1 K 1.22 MHz ± 10.41% 1.27 MHz ± 1.0% 10 K 669.4 KHz ± 10.92% 688 KHz ± 1.2% 100 K 71.5 KHz ± 11.21% 77.2 KHz ± 1.0% 3.3 K 625.1 KHz ± 10.68% 707 KHz ± 1.4% 5.1 K 428.5 KHz ± 10.96% 501 KHz ± 1.2% 10 K 231.9 KHz ± 11.32% 269 KHz ± 1.6% 100 K 24.4 KHz ± 12.93% 28.3 KHz ± 1.1% The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is ±3 standard deviation from the average value for Vdd = 5V 1998 Microchip Technology Inc. DS30234D/CR64/E2A1-page 5 Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. 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