19-2245; Rev 0; 10/01 KIT ATION EVALU E L B A AVAIL Quad ECL/PECL Differential Buffers/Receivers Features ♦ Differential Double-Swing ECL/PECL Outputs ♦ Input Compatible with LVECL/LVPECL ♦ Guaranteed 900mV Differential Output at 3.0GHz Clock Rate ♦ 365ps Propagation Delay in Asynchronous Mode ♦ 10ps Channel-to-Channel Skew in Synchronous Mode ♦ Integrated 100Ω Input Terminations (MAX9404) ♦ Compatible +3.3V/+5.0V Nominal Supplies ♦ Selectable Synchronous/Asynchronous Operation Ordering Information PART TEMP. RANGE PINPACKAGE MAX9401EGJ* -40°C to +85°C 32 QFN-EP** (5mm x 5mm) Open MAX9401EHJ -40°C to +85°C 32 TQFP (5mm x 5mm) Open MAX9404EGJ* -40°C to +85°C 32 QFN-EP** (5mm x 5mm) 100Ω MAX9404EHJ -40°C to +85°C 32 TQFP (5mm x 5mm) 100Ω Applications Data and Clock Driver and Buffer Central Office Backplane Clock Distribution DSLAM Backplane Base Station ATE INPUT IMPEDANCE *Future product—contact factory for availability. **EP = Exposed paddle Functional Diagram appears at end of data sheet. IN1 IN1 IN1 IN1 25 VEE VEE 26 OUT0 OUT0 27 OUT0 OUT0 28 VCC VCC 29 IN0 IN0 30 * IN0 IN0 31 TOP VIEW 32 Pin Configurations 32 31 30 29 28 27 26 25 * VCC 1 24 VCC VCC 1 24 VCC SEL 2 23 OUT1 SEL 2 23 OUT1 SEL 3 22 OUT1 SEL 3 22 OUT1 CLK 4 21 VEE CLK 4 CLK 5 20 VEE CLK 5 EN 6 19 OUT2 EN 6 19 OUT2 EN 7 18 OUT2 EN 7 18 OUT2 VCC 8 17 VCC VCC 8 17 VCC MAX9401/ MAX9404 * * 21 VEE MAX9401 MAX9404 20 VEE 15 16 IN2 IN2 IN3 14 VEE 16 IN2 13 OUT3 15 IN2 12 OUT3 14 VEE 11 VCC 13 OUT3 QFN-EP* 10 IN3 12 11 VCC 9 OUT3 9 10 IN3 IN3 * TQFP *EXPOSED PAD AND CORNER PINS ARE CONNECTED TO VEE ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9401/MAX9404 General Description The MAX9401/MAX9404 are extremely fast and lowskew quad ECL/PECL differential buffers/receivers for data and clock signals. The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. The MAX9401 has high-impedance (open) input and the MAX9404 has an integrated 100Ω differential input termination, which reduces external component count. Both devices have double amplitude swing open emitter outputs suitable for driving long cables. The MAX9401/MAX9404 operate over a VCC - VEE = +3.0V to +5.5V supply range, and are specified for operation from -40°C to +85°C. These devices are offered in space-saving 32-pin 5mm x 5mm QFN exposed-paddle (EP) and TQFP packages. MAX9401/MAX9404 Quad ECL/PECL Differential Buffers/Receivers ABSOLUTE MAXIMUM RATINGS VCC to VEE .............................................................-0.3V to +6.0V All Other Pins to VEE ...................................-0.3V to (VCC + 0.3V) Differential Input Voltage….................................................±3.0V Continuous Output Current .................................................70mA Surge Output Current….. ..................................................100mA Continuous Power Dissipation (TA = +70°C) 32-Pin 5mm x 5mm TQFP (derate 9.5mW/°C above +70°C)..............................................................761mW 32-Pin 5mm x 5mm QFN-EP (derate 21.3mW/°C above +70°C)..................................................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin TQFP............................................................+105°C/W 32-Pin QFN-EP…. .....................................................+47°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 32-Pin TQFP..............................................................+73°C/W Junction-to-Case Thermal Resistance 32-Pin TQFP..............................................................+25°C/W 32-Pin QFN-EP… ........................................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (Inputs and Outputs) .................>1.25kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = +3.0V to +5.5V, outputs terminated with 50Ω ±1% to VCC - 3.3V, inputs are driven, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL) Differential Input High Voltage VIHD Figure 3 VEE + 2.0 VCC V Differential Input Low Voltage VILD Figure 3 VEE VCC 0.2 V Differential Input Voltage VID Figure 3 0.2 3.0 V Input Current IN to IN Differential Input Resistance MAX9401 EN, EN, SEL, SEL, IN_, IN_, CLK, or CLK = VIHD or VILD -10 25 MAX9404 EN, EN , SEL, SEL, CLK, or CLK = VIHD or VILD -10 25 MAX9404 86 114 VOH - VOL Figure 3 1.2 VOCM Figure 3 VCC 1.8 IEE (Note 4) IIH, IIL RIN µA Ω OUTPUTS (OUT_, OUT_) Differential Output Voltage Output Common-Mode Voltage 1.4 V VCC 1.4 V 118 mA POWER SUPPLY Supply Current 2 84 _______________________________________________________________________________________ Quad ECL/PECL Differential Buffers/Receivers (VCC - VEE = +3.0V to +5.5V, outputs terminated with 50Ω ±1% to VCC - 3.3V, outputs are enabled, input transition time = 125ps (20% to 80%), fCLK = 3.0GHz, fIN = 1.5GHz, VIHD = VEE +2.0V to VCC, VILD = VEE to VCC - 0.2V, VIHD - VILD = 0.2 to 3.0V, unless otherwise noted. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, TA = +25°C, unless otherwise noted.) (Notes 1, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IN to OUT Differential Propagation Delay tPLH1, tPHL1 SEL = high, Figure 4 300 365 550 ps CLK to OUT Differential Propagation Delay tPLH2, tPHL2 SEL = low, Figure 5 580 620 758 ps IN to OUT Channel-to-Channel Skew tSKD1 SEL = high (Note 6) 15 55 ps CLK to OUT Channel-toChannel Skew tSKD2 SEL = low (Note 6) 10 40 ps Maximum Clock Frequency fCLK(MAX) VOH - VOL ≥ 900mV, SEL = low 3.0 GHz Maximum Data Frequency fIN(MAX) SEL = high, VOH - VOL ≥ 900mV 1.5 GHz Added Random Jitter (Note 7) Added Deterministic Jitter (Note 7) IN to CLK Setup Time tRJ tDJ SEL = low, fIN = 1.5GHz, fCLK = 3.0GHz, clock 1.4 2.5 ps (RMS) SEL = high, fIN = 1.5GHz 0.9 2.7 SEL = low, fCLK = 3.0GHz, IN_ = 1.5Gbps, 223-1 PRBS pattern 20 30 SEL = high, IN_ = 1.5Gbps, 223-1 PRBS pattern 36 55 psp-p tS Figure 5 80 CLK to IN Hold Time tH Figure 5 80 Output Rise Time tR Figure 4 116 145 ps Output Fall Time tF Figure 4 115 145 ps 1 ps/°C Propagation Delay Temperature Coefficient ∆tPD/∆T ps ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to VEE except VID and VOD. Note 3: DC parameters are production tested at TA = +25°C. DC limits are guaranteed by design and characterization over the full operating range. Note 4: Outputs are open. Inputs driven high or low. Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Device jitter added to the input signal. _______________________________________________________________________________________ 3 MAX9401/MAX9404 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (Outputs terminated with 50Ω to VCC - 3.3V, VCC - VEE = +3.3V, VIHD = VCC - 0.9V, VILD = VCC - 1.7V, output is enabled, SEL = high, SEL = low, input transition time = 125ps (20% to 80%), fCLK = 3.0GHz, fIN = 1.5GHz, TA = +25°C, unless otherwise noted.) DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. IN_ FREQUENCY SUPPLY CURRENT vs. TEMPERATURE 88 82 76 1.2 0.8 0.4 0 70 -40 -15 10 35 60 0 85 0.5 1.0 1.5 2.0 2.5 TEMPERATURE (°C) IN_ FREQUENCY (GHz) TRANSITION TIME vs. TEMPERATURE PROPAGATION DELAY vs. TEMPERATURE 124 tR 118 tF 112 106 700 PROPAGATION DEALY (ps) MAX9401/04 toc03 130 CLK-TO-OUT DELAY 620 540 460 IN-TO-OUT DELAY 380 100 3.0 MAX9401/04 toc04 SUPPLY CURRENT (mA) 94 1.6 MAX9401/04 toc02 OUTPUTS ARE OPEN; INPUTS ARE HIGH OR LOW DIFFERENTIAL OUTPUT VOLTAGE (mV) MAX9401/04 toc01 100 TRANSITION TIME (ps) MAX9401/MAX9404 Quad ECL/PECL Differential Buffers/Receivers 300 -40 -15 10 35 60 85 -40 -15 TEMPERATURE (°C) 10 35 60 85 TEMPERATURE (°C) Pin Description 4 PIN NAME FUNCTION 1, 8, 11, 17, 24, 30 VCC Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 SEL Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four channels to operate in synchronized mode. 3 SEL Inverting Differential Select Input 4 CLK Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs to the outputs when SEL = low. 5 CLK Noninverting Differential Clock Input _______________________________________________________________________________________ Quad ECL/PECL Differential Buffers/Receivers PIN NAME FUNCTION 6 EN Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables the outputs. Setting EN = low and EN = high (differential low) sets the outputs to logic low. 7 EN Inverting Differential Output Enable Input 9 IN3 Noninverting Differential Input 3 10 IN3 Inverting Differential Input 3 12 OUT3 Inverting Differential Output 3 13 OUT3 Noninverting Differential Output 3 14, 20, 21, 27 VEE Negative Supply Voltage 15 IN2 Noninverting Differential Input 2 16 IN2 Inverting Differential Input 2 18 OUT2 Inverting Differential Output 2 19 OUT2 Noninverting Differential Output 2 22 OUT1 Noninverting Differential Output 1 23 OUT1 Inverting Differential Output 1 25 IN1 Inverting Differential Input 1 26 IN1 Noninverting Differential Input 1 28 OUT0 Noninverting Differential Output 0 29 OUT0 Inverting Differential Output 0 31 IN0 Inverting Differential Input 0 32 IN0 Noninverting Differential Input 0 — EP* Exposed Paddle. EP is electrically connected to VEE. Solder EP to PC board. *QFN-EP package only. Detailed Description The MAX9401/MAX9404 are extremely fast, low-skew quad ECL/PECL buffers/receivers designed for highspeed data and clock driver applications. These devices feature ultra-low propagation delay of 365ps and channel-to-channel skew of 15ps in asynchronous mode with 84mA supply current, making them ideal for driving long cables and double termination applications (Functional Diagram). The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state. Data Input Termination Figure 1 shows the input and output configuration of the MAX9401/MAX9404. The MAX9401 has highimpedance inputs and requires external termination. The MAX9404 has integrated 100Ω differential input termination resistors across each of the four inputs (IN_ to IN_), reducing external component count. Outputs The MAX9401/MAX9404 have double-swing open-emitter outputs as shown in Figure 1. The double-amplitude swing outputs can drive double-terminated links or long _______________________________________________________________________________________ 5 MAX9401/MAX9404 Pin Description (continued) MAX9401/MAX9404 Quad ECL/PECL Differential Buffers/Receivers IN_ nal should be set to either logic low or high state to minimize noise coupling. IN_ Synchronous Operation 100Ω IN_ Setting SEL = low and SEL = high enables all four channels to operate in synchronous mode. In this mode, buffered inputs are clocked into flip-flops simultaneously on every rising edge of the differential clock input (CLK and CLK). IN_ MAX9401 MAX9404 VCC Differential Signal Input Limit The maximum differential input signal magnitude is 3.0V. Supply Voltages OUT_ OUT_ MAX9401 MAX9404 Figure 1. MAX9401/MAX9404 Input and Output Configurations For interfacing to differential PECL signals, the VCC range is from +3.0V to +5.5V (with VEE grounded). For interfacing to differential ECL, the VEE range is -3.0V to -5.5V (with V CC grounded). Output levels are referenced to V CC and are considered PECL or ECL, depending on the level of the VCC supply. Applications Information cables. External termination is required. See the Output Termination section. Enable Setting EN = high and EN = low enables the outputs. Setting EN = low and EN = high forces the outputs to a differential low when disabled. All changes on CLK, SEL, and IN_ are ignored. Asynchronous Operation Setting SEL = high and SEL = low enables four channels to operate independently as a buffer/receiver (CLK is ignored). In asynchronous mode, the CLK sig- Input Bias Unused inputs should be biased to avoid noise coupling that might cause toggling at the unused outputs. See Figure 2 for the biasing network. Output Termination Terminate the outputs through 50Ω to VCC - 3.3V or use an equivalent Thevenin termination. Use identical terminations on each OUT for the lowest skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if OUT_ is used as a single-ended output, terminate both OUT_ and OUT_. VCC VCC IN_ IN_ 100Ω 100Ω IN_ IN_ MAX9401 1kΩ VEE MAX9404 1kΩ VEE Figure 2. Input Bias Circuits for Unused Pins for MAX9401/MAX9404 6 _______________________________________________________________________________________ Quad ECL/PECL Differential Buffers/Receivers VIHD (MAX) VID MAX9401/MAX9404 VCC VCC VID = 0 VOH VILD (MAX) VOH - VOL VOCM VIHD (MIN) VID VOL VID = 0 VEE VEE VILD (MIN) INPUT VOLTAGE DEFINITION OUTPUT VOLTAGE DEFINITION Figure 3. Input and Output Voltage Definitions IN_ VIHD - VILD IN_ tPLH1 tPHL1 OUT_ VOH - VOL OUT_ 80% OUT_ - OUT_ DIFFERENTIAL OUTPUT WAVEFORM VOH - VOL 80% VOH - VOL 20% tR 20% tF (SEL = HIGH, EN = HIGH) Figure 4. IN to OUT Propagation Delay Timing Diagram Ensure that the output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device’s total thermal limits should be observed. possible, with the 0.01µF capacitor closest to the device pins. Use multiple bypass vias for connection to minimize inductance. Power-Supply Bypassing Input and output trace characteristics affect the performance of the MAX9401/MAX9404. Connect each of the inputs and outputs to a 50Ω characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by main- Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors as close to the device as Circuit Board Traces _______________________________________________________________________________________ 7 MAX9401/MAX9404 Quad ECL/PECL Differential Buffers/Receivers CLK VIHD - VILD CLK tH tS tH IN_ VIHD - VILD IN_ tPLH2 tPHL2 OUT_ VOH - VOL OUT_ (SEL = LOW, EN = HIGH) Figure 5. CLK to OUT Propagation Delay Timing Diagram taining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. 8 Chip Information TRANSISTOR COUNT: 748 PROCESS: Bipolar _______________________________________________________________________________________ Quad ECL/PECL Differential Buffers/Receivers IN0 1 IN0 D Q D Q OUT0 0 OUT0 CLK CLK IN1 1 IN1 D Q D Q OUT1 0 OUT1 CLK CLK IN2 1 IN2 D Q D Q OUT2 0 OUT2 CLK CLK IN3 1 IN3 D Q D Q OUT3 0 OUT3 CLK CLK CLK CLK SEL SEL EN EN _______________________________________________________________________________________ 9 MAX9401/MAX9404 Functional Diagram Quad ECL/PECL Differential Buffers/Receivers 32L,TQFP.EPS MAX9401/MAX9404 Package Information 10 ______________________________________________________________________________________ Quad ECL/PECL Differential Buffers/Receivers ______________________________________________________________________________________ 11 MAX9401/MAX9404 Package Information (continued) Quad ECL/PECL Differential Buffers/Receivers MAX9401/MAX9404 Package Information (continued) 12 ______________________________________________________________________________________ Quad ECL/PECL Differential Buffers/Receivers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9401/MAX9404 Package Information (continued)