19-2576; Rev 0; 10/02 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver Applications Precision Clock Distribution Features ♦ 15ps Differential Output-to-Output Skew ♦ 1.7psRMS Added Random Jitter ♦ 150ps (max) Part-to-Part Skew ♦ 450ps Propagation Delay ♦ Synchronous Output Enable/Disable ♦ Single-Ended Monitor Output ♦ Outputs Assert Low when CLK, CLK are Open or at GND ♦ 3.0V to 3.6V Supply Voltage Range ♦ -40°C to +85°C Operating Temperature Range Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9324EUP -40°C to +85°C 20 TSSOP MAX9324ETP* -40°C to +85°C 20 Thin QFN-EP** *Future product—Contact factory for availability. **EP = Exposed paddle. Low-Jitter Data Repeater Data and Clock Driver and Buffer Functional Diagram and Typical Operating Circuit appear at end of data sheet. Central-Office Backplane Clock Distribution DSLAM Backplane Base Station ATE CLK_EN GND Q0 Q0 TOP VIEW N.C. Pin Configurations 20 19 18 17 16 15 VCC SEOUT 1 14 Q1 GND 2 MAX9324 N.C. 3 13 Q1 12 Q2 11 Q2 CLK 5 19 Q0 18 VCC N.C. 3 SEOUT 4 17 Q1 MAX9324 16 Q1 N.C. 6 15 Q2 SEOUT_Z 7 14 Q2 CLK 8 13 VCC CLK 9 12 Q3 VCC 10 11 Q3 10 VCC 9 Q3 8 Q3 7 VCC CLK 6 20 Q0 GND 5 **EXPOSED PADDLE SEOUT_Z 4 GND 1 CLK_EN 2 THIN QFN-EP** (4mm x 4mm) **CONNECT EXPOSED PADDLE TO GND. TSSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9324 General Description The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input to four differential LVPECL outputs and one single-ended LVCMOS output. All outputs default to logic low when the differential inputs equal GND or are left open. The MAX9324 operates from 3.0V to 3.6V, making it ideal for 3.3V systems, and consumes only 25mA (max) of supply current. The MAX9324 features low 150ps (max) part-to-part skew, low 15ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. CLK_EN and SEOUT_Z control the status of the various outputs. Asserting CLK_EN low configures the differential (Q_, Q_) outputs to a differential low condition and SEOUT to a single-ended logic-low state. CLK_EN operation is synchronous with the CLK_ inputs. A logic high on SEOUT_Z places SEOUT in a high-impedance state. SEOUT_Z is asynchronous with the CLK (CLK) inputs. The MAX9324 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN packages and operates over the extended (-40°C to +85°C) temperature range. MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V Q_, Q_, CLK, CLK, SEOUT_Z, CLK_EN, SEOUT to GND.......................................-0.3V to (VCC + 0.3V) CLK to CLK ............................................................................±3V SEOUT Short to GND .................................................Continuous Continuous Output Current (Q_, Q_) ..................................50mA Surge Output Current (Q_, Q_) .........................................100mA Continuous Power Dissipation (TA = +70°C) 20-Pin TSSOP (derate 11mW/°C)..............................879.1mW 20-Pin 4mm ✕ 4mm Thin QFN (derate 16.9mW/°C)..1349.1mW Junction-to-Ambient Thermal Resistance in Still Air 20-Pin TSSOP ............................................................+91°C/W 20-Pin 4mm ✕ 4mm Thin QFN.................................+59.3°C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ............................................................+20°C/W 20-Pin 4mm ✕ 4mm Thin QFN......................................+2°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, differential outputs terminated with 50Ω ±1% to (VCC - 2V), SEOUT_Z = GND, CLK_EN = VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (CLK_EN, SEOUT_Z) Input High Voltage VIH 2 VCC V Input Low Voltage VIL 0 0.8 V Input High Current IIH Input Low Current IIL CLK_EN = VCC -5 +5 SEOUT_Z = VCC CLK_EN = GND 150 -150 SEOUT_Z = GND -5 +5 VIHD Figure 1 1.5 VCC VILD Figure 1 µA µA DIFFERENTIAL INPUT (CLK, CLK) Differential Input High Voltage Differential Input Low Voltage Differential Input Voltage VIHD - VILD 0 VCC - 0.15 V V 0.15 1.5 V -5 +150 µA Input Current ICLK VIHD, VILD DIFFERENTIAL OUTPUTS (Q_, Q_) Single-Ended Output High VOH Figure 1 VCC - 1.4 VCC - 1.0 V Single-Ended Output Low VOL Figure 1 VCC - 2.0 VCC - 1.7 V Differential Output Voltage VOH - VOL Figure 1 0.6 2.4 0.85 V 0.4 V SINGLE-ENDED OUTPUT (SEOUT) Output High Voltage VOH IOH = -4mA Output Low Voltage VOL IOL = 4mA Output High-Impedance Current IOZ SEOUT_Z = VCC, SEOUT = VCC or GND +10 µA Output Short-Circuit Current IOS VCLK = VCC, SEOUT = GND 75 mA ICC (Note 4) 25 mA -10 V SUPPLY Supply Current 2 _______________________________________________________________________________________ One-to-Five LVPECL/LVCMOS Output Clock and Data Driver (VCC = 3.0V to 3.6V, differential outputs terminated with 50Ω ±1% to (VCC - 2V), fCLK ≤ 266MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), VIHD = 1.5V to VCC, VILD = GND to (VCC - 0.15V), VIHD - VILD = 0.15V to 1.5V, CLK_EN = VCC, SEOUT_Z = GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, VIHD = (VCC - 1V), VILD = (VCC 1.5V), TA = +25°C.) (Note 5) PARAMETER Switching Frequency Propagation Delay SYMBOL fMAX tPHL, tPLH MIN TYP VOH - VOL ≥ 0.6V, SEOUT_Z = VCC CONDITIONS 650 800 SEOUT_Z = GND, SEOUT 125 200 CLK, CLK to Q_, Q_, Figure 1 (Note 6) 100 450 MAX UNITS MHz 600 ps Output-to-Output Skew tSKOO (Note 7) 30 ps Part-to-Part Skew tSKPP (Note 8) 150 ps Output Rise Time tR 20% to 80%, Figure 1 100 217 300 ps tF 80% to 20%, Figure 1 100 207 300 ps 48 50 52 % Output Fall Time Output Duty Cycle ODC Added Random Jitter Added Deterministic Jitter tRJ fCLK = 650MHz (Note 9) 1.7 3 ps(RMS) tDJ 2e23 - 1 PRBS pattern, f = 650Mbps (Note 9) 83 100 ps(P-P) Added Jitter tAJ VCC = 3.3V with 25mV superimposed sinusoidal noise at 100kHz (Note 9) 8.5 12 ps(P-P) Single-Ended Output Rise Time tR CL = 15pF, 20% to 80%, Figure 1 1.6 2 ns Single-Ended Output Fall Time tF CL = 15pF, 80% to 20%, Figure 1 1.6 2 ns 52 60 % Single-Ended Output Duty Cycle ODC (Note 10) 40 Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range. All pins open except VCC and GND. Guaranteed by design and characterization. Limits are set at ±6 sigma. Measured from the differential input signal crosspoint to the differential output signal crosspoint. Measured between the differential outputs of the same part at the differential signal crosspoint for a same-edge transition. Measured between the differential outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge transition. Note 9: Jitter added to the input signal. Note 10: Measured at 50% of VCC. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: _______________________________________________________________________________________ 3 MAX9324 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC = 3.3V, outputs terminated to (VCC - 2V) through 50Ω, SEOUT_Z = VCC, CLK_EN = VCC, TA = +25°C.) DIFFERENTIAL OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE 13.0 12.5 12.0 11.5 11.0 600 500 400 300 200 100 10.5 0 10.0 -40 -15 10 35 60 0 85 200 400 600 800 1000 1200 1400 1600 TEMPERATURE (°C) FREQUENCY (MHz) DIFFERENTIAL OUTPUT RISE/FALL TIME vs. TEMPERATURE DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE 230 tR 220 210 200 190 tF 180 170 160 150 510 MAX9324 toc04 240 DIFFERENTIAL PROPAGATION DELAY (ps) MAX9324 toc03 250 500 490 480 tPLH 470 460 450 440 tPHL 430 420 410 -40 -15 10 35 TEMPERATURE (°C) 4 MAX9324 toc02 700 OUTPUT AMPLITUDE (mV) 13.5 SUPPLY CURRENT (mA) 800 MAX9324 toc01 14.0 DIFFERENTIAL OUTPUT RISE/FALL TIME (ps) MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ One-to-Five LVPECL/LVCMOS Output Clock and Data Driver PIN TSSOP QFN 1, 5 2, 18 NAME GND 2 19 CLK_EN 3, 6 3, 20 N.C. FUNCTION Ground. Provide a low-impedance connection to the ground plane. Synchronous Output Enable. Connect CLK_EN to VCC or leave floating to enable the differential outputs. Connect CLK_EN to GND to disable the differential outputs. When disabled, Q_ asserts low, Q_ asserts high, and SEOUT asserts low. A 51kΩ pullup resistor to VCC allows CLK_EN to be left floating. No Connect. Not internally connected. LVCMOS/LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT goes high impedance when SEOUT_Z = VCC. The maximum output frequency of SEOUT is 125MHz. 4 1 SEOUT 7 4 SEOUT_Z Single-Ended Clock Output Enable/Disable. Connect SEOUT_Z to GND to enable the singleended clock output. Connect SEOUT_Z to VCC to disable the single-ended clock output. A 51kΩ pulldown resistor to GND allows SEOUT_Z to be left floating. 8 5 CLK Noninverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or at GND and the outputs are enabled. 9 6 CLK Inverting Differential LVPECL Input. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or at GND and the outputs are enabled. 10, 13, 18 7, 10, 15 VCC Positive Supply Voltage. Bypass VCC to GND with three 0.01µF and one 0.1µF ceramic capacitors. Place the 0.01µF capacitors as close to each VCC input as possible (one per VCC input). Connect all VCC inputs together, and bypass to GND with a 0.1µF ceramic capacitor. 11 8 Q3 Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor. 12 9 Q3 Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor. 14 11 Q2 Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor. 15 12 Q2 Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor. 16 13 Q1 Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor. 17 14 Q1 Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor. 19 16 Q0 Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor. 20 17 Q0 Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor. _______________________________________________________________________________________ 5 MAX9324 Pin Description MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver signal. Terminate CLK and CLK through 50Ω to (VCC 2V) to minimize input signal reflections. Internal 51kΩ pulldown resistors to GND ensure the outputs default to differential low (Q_, Q_) or logic low (SEOUT) when the CLK inputs are left open. Detailed Description The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential LVPECL input signal to four differential LVPECL outputs and a single-ended LVCMOS output. The differential output drivers operate at frequencies up to 800MHz. When SEOUT_Z = GND, the single-ended LVCMOS output driver operates with frequencies as high as 200MHz. The MAX9324 operates from 3.0V to 3.6V, making the device ideal for 3.3V systems. CLK_EN Input CLK_EN enables/disables the differential outputs of the MAX9324. Connect CLK_EN to VCC to enable the differential outputs. The (Q_, Q_) outputs are driven to a differential low condition when CLK_EN = GND. Each differential output pair disables following successive rising and falling edges on CLK (falling and rising edges on CLK), after CLK_EN connects to GND. Both a rising and falling edge on CLK are required to complete the enable/disable function (Figure 2). Data Inputs Differential LVPECL Inputs The MAX9324 accepts a differential LVPECL input. Each differential output duplicates the differential input CLK VIHD VILD CLK Q_ VOH VOH - VOL VOL Q_ tPLH tPHL 80% 80% Q_ - Q_ tR 20% tF 80% 20% 80% SEOUT 20% tR tF Figure 1. MAX9324 Clock Input-to-Output Delay and Rise/Fall Time 6 _______________________________________________________________________________________ 20% One-to-Five LVPECL/LVCMOS Output Clock and Data Driver MAX9324 CLK CLK ENABLED DISABLED CLK_EN Q_ Q_ HIGH IMPEDANCE SEOUT SEOUT_Z Figure 2. MAX9324 CLK_EN Timing Diagram SEOUT_Z SEOUT_Z enables/disables the single-ended LVCMOS output (Table 1). Connect SEOUT_Z to GND to enable the single-ended output. Connect SEOUT_Z to VCC to force the single-ended output to a high-impedance state. SEOUT provides a single-ended monitor for operating frequencies as high as 200MHz. Applications Information Output Termination Terminate both outputs of each differential pair through 50Ω to (VCC - 2V) or use an equivalent Thevenin termination. Use identical termination on each output for the lowest output-to-output skew. Terminate both outputs when deriving a single-ended signal from a differential output. For example, using Q0 as a single-ended output requires termination for both Q0 and Q0. Table 1. Control Input Table INPUTS OUTPUTS CLK_EN SEOUT_Z Q0–Q3 Q0–Q Q3 SEOUT 0 0 Disabled, pulled to logic low Disabled, pulled to logic high Enabled, logic low 0 1 Disabled, pulled to logic low Disabled, pulled to logic high Disabled, high impedance 1 0 Enabled Enabled Enabled 1 1 Enabled Enabled Disabled, high impedance _______________________________________________________________________________________ 7 MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver Circuit Board Traces SEOUT provides a single-ended LVCMOS monitor output. SEOUT operates with a maximum output frequency of 200MHz. Input and output trace characteristics affect the performance of the MAX9324. Connect each input and output to a 50Ω characteristic impedance trace to minimize reflections. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Minimize skew by matching the electrical length of the traces. Ensure that the output currents do not violate the current limits as specified in the Absolute Maximum Ratings table. Observe the device’s total thermal limits under all operating conditions. Power-Supply Bypassing Bypass VCC to GND using three 0.01µF ceramic capacitors and one 0.1µF ceramic capacitor. Place the 0.01µF capacitors (one per VCC input) as close to VCC as possible (see the Typical Operating Circuit). Use multiple bypass vias to minimize parasitic inductance. Chip Information TRANSISTOR COUNT: 4430 PROCESS: BiCMOS Functional Diagram VCC VCC VCC SEOUT_Z MAX9324 SEOUT VCC Q0 Q0 D CLK_EN Q Q1 CLK Q1 CLK CLK Q2 Q2 Q3 Q3 GND 8 GND _______________________________________________________________________________________ One-to-Five LVPECL/LVCMOS Output Clock and Data Driver 3.0V TO 3.6V 0.01µF 0.01µF 0.01µF 0.1µF VCC VCC VCC ZO = 50Ω Q0 Q0 ZO = 50Ω MAX9324 ZO = 50Ω CLK ZO = 50Ω CLK 50Ω 50Ω 50Ω ZO = 50Ω LVPECL RECEIVER Q1 VCC - 2V Q1 ZO = 50Ω 50Ω ZO = 50Ω Q2 VCC - 2V Q2 ZO = 50Ω ZO = 50Ω ON CLK_EN Q3 OFF Q3 OFF ZO = 50Ω SEOUT_Z ON LVCMOS/ LVTTL INPUT SEOUT GND _______________________________________________________________________________________ 9 MAX9324 Typical Operating Circuit MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 10 ______________________________________________________________________________________ A One-to-Five LVPECL/LVCMOS Output Clock and Data Driver PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A ______________________________________________________________________________________ 11 MAX9324 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.