19-2383; Rev 1; 11/03 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver Features ♦ Improved Second Source of the MC10EP11D ♦ +3.0V to +5.5V Differential PECL/LVPECL Operation ♦ -3.0V to -5.5V ECL/LVECL Operation ♦ Low 22mA Supply Current ♦ 20ps Part-to-Part Skew ♦ 6ps Output-to-Output Skew ♦ 208ps Propagation Delay ♦ Minimum 300mV Output at 3GHz ♦ Outputs Low for Open Input ♦ ESD Protection >2kV (Human Body Model) Applications Precision Clock Distribution Ordering Information PART Low-Jitter Data Repeater Protection Switching TEMP RANGE PIN-PACKAGE MAX9320BESA -40°C to +85°C 8 SO MAX9320BEUA -40°C to +85°C 8 TSSOP Pin Configuration D VIHD VIHD - VILD VILD D tPLHD tPHLD Q0 1 Q_ VOH VOH - VOL VOL Q MAX9320B 50kΩ 8 VCC 80kΩ 7 D Q0 2 60kΩ 6 D Q1 3 80% 80% 100kΩ 0V (DIFFERENTIAL) (Q_) - (Q_) 0V (DIFFERENTIAL) 20% 20% tR tF 5 VEE Q1 4 TSSOP/SO Figure 1. Differential Transition Time and Propagation Delay Timing Diagram ________________________________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9320B General Description The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. The MAX9320B features ultra-low propagation delay (208ps), part-to-part skew (20ps), and output-to-output skew (6ps) with 30mA maximum supply current, making this device ideal for clock distribution. For interfacing to differential PECL and LVPECL signals, this device operates over a +3.0V to +5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5V supply. For differential ECL and LVECL operation, this device operates from a -3.0V to -5.5V supply. The MAX9320B is offered in industry-standard 8-pin TSSOP and SO packages. MAX9320B 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS VCC to VEE .............................................................................+6V D or D....................................................VEE - 0.3V to VCC + 0.3V D or D with the Other Floating............. VCC - 5.0V to VCC + 0.3V D to D .................................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Continuous Output Power Dissipation (TA = +70°C) 8-Pin TSSOP (derate 4.5mW/°C above +70°C) .................................362mW 8-Pin SO (derate 5.9mW/°C above +70°C) .................................471mW Junction-to-Ambient Thermal Resistance in Still Air 8-Pin TSSOP ............................................................+221°C/W 8-Pin SO...................................................................+170°C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin TSSOP ............................................................+155°C/W 8-Pin SO.....................................................................+99°C/W Junction-to-Case Thermal Resistance 8-Pin TSSOP ..............................................................+39°C/W 8-Pin SO.....................................................................+40°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (D, D, Q_, Q_) .................................>2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS DIFFERENTIAL INPUT (D, D) High Voltage of Differential Input VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD VEE VCC - 0.1 VEE VCC - 0.1 VEE VCC - 0.1 V VIHD VILD 0.1 3.0 0.1 3.0 0.1 3.0 V 150 µA Differential Input Voltage Input High Current IIH D Input Low Current IILD D Input Low Current IILD 150 150 VCC - VEE ≤ 3.8V -100 +100 -100 +100 -100 +100 VCC - VEE ≥ 3.8V -140 +140 -140 +140 -140 +140 VCC - VEE ≤ 3.8V -150 +150 -150 +150 -150 +150 VCC - VEE ≥ 3.8V -175 +175 -175 +175 -175 +175 VCC - 1.135 VCC - 0.885 VCC - 1.07 VCC - 0.82 VCC - 1.01 VCC - 0.76 µA µA DIFFERENTIAL OUTPUTS (Q_, Q__) Single-Ended Output High Voltage 2 VOH Figure 1 _______________________________________________________________________________________ V 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN Single-Ended Output Low Voltage VOL Figure 1 VCC - 1.935 Differential Output Voltage VOH - VOL Figure 1 550 IEE (Note 4) +25°C TYP MAX MIN TYP VCC VCC - 1.685 - 1.87 +85°C MAX MIN VCC - 1.62 VCC - 1.81 550 TYP MAX VCC - 1.56 550 UNITS V mV POWER SUPPLY Supply Current 20 28 22 28 23 30 mA AC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency ≤ 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Differential Input-toOutput Delay tPLHD, tPHLD Figure 1 tSKOO tSKPP Output-toOutput Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter tRJ tDJ CONDITIONS -40°C +25°C +85°C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX 145 220 265 155 208 265 160 203 270 ps (Note 6) 6 30 6 30 6 30 ps (Note 7) 20 120 20 110 20 110 ps fIN = 1.5GHz, clock pattern (Note 8) 1.7 2.8 1.7 2.8 1.7 2.8 fIN = 3.0GHz, clock pattern (Note 8) 0.6 1.5 0.6 1.5 0.6 1.5 3.0Gbps 223 - 1 PRBS pattern (Note 8) 57 80 57 80 57 80 ps (RMS) ps (P-P) _______________________________________________________________________________________ 3 MAX9320B DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency ≤ 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5) PARAMETER SYMBOL -40°C CONDITIONS MIN VOH - VOL ≥ 300mV, clock pattern, Figure 1 Switching Frequency fMAX Output Rise/Fall Time (20% to 80%) tR, tF TYP +25°C MAX 3.0 MIN TYP +85°C MAX 3.0 MIN TYP MAX UNITS 3.0 GHz VOH - VOL ≥ 550mV, clock pattern, Figure 1 2.0 Figure 1 50 2.0 95 120 2.0 50 98 120 50 105 120 ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25°C. Guaranteed by design and characterization over the full operating temperature range. Note 4: All pins open except VCC and VEE. Note 5: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 8: Device jitter added to the input signal. Typical Operating Characteristics (VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.) 0.7 22 21 20 19 18 17 0.6 0.5 0.4 0.3 15 -15 10 35 TEMPERATURE (°C) 60 85 100 95 tF 90 85 80 0 -40 tR 0.2 0.1 16 105 TRANSITION TIME (ps) OUTPUT AMPLITUDE (V) 23 TRANSITION TIME vs. TEMPERATURE 110 MAX9320B toc02 24 4 0.8 MAX9320B toc01 25 OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY MAX9320B toc03 SUPPLY CURRENT, IEE vs. TEMPERATURE SUPPLY CURRENT (mA) MAX9320B 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver 0 500 1000 1500 2000 2500 3000 3500 FREQUENCY (MHz) -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver PROPAGATION DELAY (ps) tPLHD 210 205 200 195 tPHLD 230 MAX9320B toc05 VIHD - VILD = 0.5V 215 PROPAGATION DELAY vs. TEMPERATURE 240 PROPAGATION DELAY (ps) 220 MAX9320B toc04 PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD tPLHD 220 210 200 tPHLD 190 180 170 160 190 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 -40 -15 10 35 60 85 TEMPERATURE (°C) VIHD (V) Pin Description PIN NAME 1 Q0 FUNCTION 2 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 4 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 5 VEE 6 D Inverting Differential Input. 50kΩ pullup to VCC and 100kΩ pulldown to VEE. 7 D Noninverting Differential Input. 80kΩ pullup to VCC and 60kΩ pulldown to VEE. 8 VCC Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V. Negative Supply Voltage Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. _______________________________________________________________________________________ 5 MAX9320B Typical Operating Characteristics (continued) (VCC = 5V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.) MAX9320B 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver Detailed Description Applications Information The MAX9320B low-skew, 1-to-2 differential driver is designed for clock and data distribution. For interfacing to differential PECL and LVPECL signals, this device operates over a +3.0V to +5.5V supply range, allowing high-performance clock and data distribution in systems with a nominal 3.3V or 5V supply. For differential ECL and LVECL operation, this device operates from a -3.0V to -5.5V supply. Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel ground vias for low inductance. Inputs The maximum magnitude of the differential input from D to D is 3.0V. This limit also applies to the difference between any reference voltage input and a singleended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting input, D, is biased with a 50kΩ pullup to VCC and a 100kΩ pulldown to VEE. The noninverting input, D, is biased with an 80kΩ pullup to VCC and a 60kΩ pulldown to VEE. Specifications for the high and low voltages of the differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). Supply Bypassing Traces Input and output trace characteristics affect the performance of the MAX9320B. Connect each signal of a differential input or output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs through 50Ω to VCC - 2V or use an equivalent Thevenin termination. Terminate both outputs and use the same termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0. Outputs Output levels are referenced to VCC and are considered PECL/LVPECL or ECL/LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are PECL/LVPECL. The outputs are ECL/LVECL when VCC is connected to GND and VEE is connected to a negative supply. A differential input of at least ±100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. 6 Chip Information TRANSISTOR COUNT: 182 _______________________________________________________________________________________ 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver 9LUCSP, 3x3.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9320B Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)