STA510F 44-V, 5.5-A, quad power half bridge Features ! Minimum input output pulse width distortion ! 150 mW Rdson complementary DMOS output stage ! CMOS compatible logic inputs ! Thermal protection ! thermal warning output ! Under-voltage protection ! No power-on, power- off sequence required PowerSO36 with exposed pad (or slug) up The device is particularly designed to make the output stage of a stereo all-digital high-efficiency (FFX) amplifier capable of delivering 100 W + 100 W output power into 8-Ω loads with THD = 10% and Vcc = 39 V. In single BTL configuration the device can deliver 200 W into a 4-Ω load with THD = 10% and Vcc = 39 V. Description STA510F is a monolithic, quad, half-bridge stage in Multipower BCD technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (binary mode) with half current capability. Table 1. The input pins have a threshold proportional to VL pin voltage. Device summary Order code STA510F Figure 1. The device is fully compatible with the DDX® driver device. Operating Temp. range 0° to 70° C Package Packing PowerSO36 (slug up) Tube Typical application Output Filter OUT 1A IN A OUT 1B IN B OUT A OUT B PWM Out 1A IN 1A PWM Out 2A IN 2A SPEAKER STA330 STA510F PWM Out 1B IN1B PWM Out 2B IN 2B Output Filter OUT 2A IN A OUT 2B IN B Vcc OUT A OUT B SPEAKER Vcc PSU GND December 2007 Rev 1 1/11 www.st.com 11 Pin description 1 STA510F Pin description Figure 2. Pin connection (top view) VCCSign 36 1 GND-SUB VCCSign 35 2 OUT2B VSS 34 3 OUT2B VSS 33 4 VCC2B IN2B 32 5 GND2B IN2A 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. D01AU1273 Table 2. Pin 2/11 Pin list Name Description 1 GND-SUB Substrate ground 2, 3 OUT2B Output half bridge 2B 4 Vcc2B Positive Supply 5 GND2B Negative Supply 6 GND2A Negative Supply 7 Vcc2A Positive Supply 8, 9 OUT2A Output half bridge 2A 10, 11 OUT1B Output half bridge 1B 12 Vcc1B Positive Supply 13 GND1B Negative Supply 14 GND1A Negative Supply 15 Vcc1A Positive Supply 16, 17 OUT1A Output half bridge 1A STA510F Pin description Table 2. Pin list (continued) Pin Name Description 18 NC Not connected 19 GND-clean Logical ground 20 GND-Reg Ground for regulator Vdd 21, 22 Vdd 5V Regulator referred to ground 23 VL High logical state setting voltage 24 CONFIG Configuration 25 PWRDN Stand-by 26 TRI-STATE Hi-Z 27 FAULT Fault pin advisor 28 TH-WAR Thermal warning advisor 29 IN1A Input of half bridge 1A 30 IN1B Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 33, 34 Vss 5-V regulator referred to +Vcc 35, 36 VCCSIGN Signal positive supply Table 3. Pin Logical value FAULT (1) Device status 0 Fault detected (short circuit, or thermal) 1 Normal operation 0 All power stages in Hi-Z state 1 Normal operation 0 Low-power mode 1 Normal operation 0 Temperature of the IC =130° C 1 Normal operation 0 Normal Operation 1 OUT1A = OUT1B, OUT2A = OUT2B (IF IN1A = IN1B and IN2A = IN2B) TRI-STATE PWRDN THWAR (1) CONFIG (2) 1. The pin is open collector. To have the high logic value, it needs a pull-up resistor. 2. CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd). 3/11 Electrical specifications STA510F 2 Electrical specifications 2.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol 2.2 Parameter Unit VCC DC supply voltage (Pin 4, 7, 12, 15) 44 V Vmax Maximum voltage on pins 23 to 32 5.5 V ESD Max ESD on pins (HBM) ±1000 V Top Operating temperature range 0 to 70 °C Tstg, Tj Storage and junction temperature -40 to 150 °C Thermal data Table 5. Thermal data Symbol 2.3 Value Parameter Min Typ Max Unit Tj-case Thermal resistance junction to case (thermal pad) 1 TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C 2.5 °C/W Electrical specifications Unless otherwise stated, the results in Table 6 below are given for the conditions: VL = 3.3 V, Vcc = 37 V and T = 25° C unless otherwise specified. Table 6. Symbol 4/11 Electrical specifications Parameter Condition Min Typ Max Unit RdsON Power Pchannel/Nchannel MOSFET RdsON Idss Power Pchannel/Nchannel leakage current gN Power Pchannel RdsON matching Id = 1 A 95 % gP Power Nchannel RdsON matching Id = 1 A 95 % Dt_s Low current dead time (static) see test circuit Figure 3 Dt_d High current dead time (dynamic) L=22µH, C = 470nF, RL = 8 Ω, Id = 4.5 A, see test circuit Figure 4 Id = 1 A 150 10 200 mΩ 100 µA 20 ns 50 ns STA510F Electrical specifications Table 6. Electrical specifications (continued) Symbol Parameter Condition Min Typ Max Unit td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load, as Figure 4 25 ns tf Fall time Resistive load, as Figure 4 25 ns VCC Supply voltage operating voltage 10 40 V VIN-High High level input voltage VL/2 +300 mV VIN-Low Low level input voltage IIN-H High level input current Pin voltage = VL 1 µA IIN-L Low level input current Pin voltage = 0.3V 1 µA IPWRDN-H High level PWRDN pin input current VL= 3.3V 35 µA VLow Low logical state voltage (pins PWRDN, TRISTATE) (see Table 7) VL = 3.3V VHigh High logical state voltage (pins PWRDN, TRISTATE) (see Table 7) VL = 3.3V IVCCPWRDN V VL/2 300m V V 0.8 1.7 V Supply current from Vcc in power PWRDN = 0 down IFAULT Output current pins FAULT -TH-WARN when FAULT CONDITIONS IVCC-hiz V 3 mA Vpin = 3.3V 1 mA Supply current from Vcc in tristate Pin TRI-STATE = 0 22 mA IVCC Supply current from Vcc in operation both channel switching) Input pulse width duty cycle = 50%, switching frequency = 384 kHz, no LC filters; 70 mA IOUT-SH Overcurrent protection threshold Isc (short circuit current limit) (note 2) VUV Undervoltage protection threshold tpw_min Output minimum pulse width 5.5 7 9 7 No Load 25 A V 40 ns 5/11 Electrical specifications Table 7. STA510F Vlow, Vhigh threshold variation with VL VL VLow max VHigh min Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Table 8. Logic truth table TRI-STATE INxA INxB Q1 Q2 Q3 Q4 Output mode 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used Figure 3. Test circuit for low current dead time OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd Figure 4. D03AU1458 Test circuit for high current dead time High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=8Ω OUTxA INxA Iout=4.5A M57 Q3 DTout(B) L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF DTin(B) OUTxB INxB Iout=4.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure 6/11 M64 M63 D00AU1162 STA510F Electrical specifications Figure 5. Typical quad half-bridge configuration giving 200 W per channel into 4 Ω speakers, 10% THD, VCC = 39 V L201 OUT2B 15u C201 330p C203 10n R201 20 R203 20 C205 1u C207 330n R202 20 R204 20 C202 330p C204 10n 4 ohm C206 1u L202 STA510F C8 15u OUT2A 100n PWM Input C7 100n IN 2B IN 2A IN 1B IN 1A TH_W EAPD R2 10K R1 10k 3V3 3V3 C11 C9 100n C10 100n 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VccSig VccSig Vss Vss IN2B IN2A IN1B IN1A TH_WARN FAULT TRISTATE PWRDN CONFIG Ibias Vdd Vdd GNDReg GNDClean GND Sub OUT2B OUT2B Vcc2B GND2B GND2A Vcc2A OUT2A OUT2A OUT1B OUT1B Vcc1B GND1B GND1A Vcc1A OUT1A OUT1A NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Vcc + C2 C3 1u C5 1u OUT1B C4 100n C1 1000u 100n C6 100n L101 100n 15u C101 330p C103 10n R101 20 R103 20 R102 20 R104 20 C102 330p C104 10n C105 1u C107 330n OUT1A C106 1u 4 ohm L102 15u Figure 6. Typical driving configuration with STA330 7/11 Package information 3 STA510F Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 7. PowerSO36 package dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 mm TYP. MAX. 3.43 3.2 1 MIN. 0.128 0.122 0.031 -0.040 0.38 0.32 16 9.8 0.0011 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.2 0.030 0.22 0.23 15.8 9.4 5.8 2.9 0.8 AND data OutlineOUTLINE and mechanical MECHANICAL DATA -0.0015 0.015 0.012 0.630 0.38 0.039 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0 15.5 MAX. 0.135 0.126 0.039 0.008 1 13.9 10.9 inch TYP. 0.026 0.435 0.075 15.9 1.1 1.1 10˚ 8˚ 0 0.61 0.031 0.003 0.625 0.043 0.043 10˚ 8˚ (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. PowerS036 PowerSO36 UP) (exposed pad(SLUG (slug) up) 7183931 D 8/11 STA510F 4 Trademarks and other acknowledgements Trademarks and other acknowledgements FFX is a STMicroelectronics proprietary digital modulation technology. DDX is a registered trademark of Apogee Technology, Inc. ECOPACK is a registered trademark of STMicroelectronics. 9/11 Revision history 5 STA510F Revision history Table 9. 10/11 Document revision history Date Revision 13-Dec-2007 1 Changes Initial release. STA510F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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