SuperLite™ SY55853U FINAL D LATCH FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ 2.5GHz min fmax 2.3V to 5.7V power supply Single bit latch Stores or flows through 1 bit of data Optimized to work with SuperLite™ family Fully differential Source terminated CML outputs for fast edge rates Accepts CML, PECL, LVPECL input logic levels Available in a tiny 10-pin MSOP SuperLite™ DESCRIPTION The SY55853U is a latch. Its differential output will flow through the input while it's enable is high. The output will remain static while the enable is low. In addition, an asynchronous, level sensitive reset is provided. SY55853U inputs can be terminated with a single resistor between the true and the complement pins of a given input. The SY55853U is a member of Micrel's SuperLite™ family of high-speed CML logic. This family features very small packaging and 2.3V to 5.7V operation. PIN CONFIGURATION D 1 10 VCC /D 2 9 /R LE 3 MSOP APPLICATIONS 8 R /LE 4 7 Q GND 5 6 /Q ■ High-speed logic ■ OC-48 communication systems PIN NAMES FUNCTIONAL BLOCK DIAGRAM Pin DATA LATCH ENABLE D Q OUT LE R RESET Function D, /D CML/PECL/LVPECL Data Input LE, /LE CML/PECL/LVPECL Latch Enable Input R, /R CML/PECL/LVPECL Reset Input Q, /Q Data Output GND Ground VCC VCC SuperLite is a trademark of Micrel, Inc. Rev.: B 1 Amendment: /0 Issue Date: March 2003 SuperLite™ SY55853U Micrel PIN DESCRIPTIONS D, /D – CML/PECL/LVPECL Input (Differential) This is the single bit of data that gets latched. R, /R – CML/PECL/LVPECL Input (Differential) This is an asynchronous active high level reset, that forces the latch into a known state, namely zero. It has priority over the LE, /LE input. LE, /LE – CML/PECL/LVPECL Input (Differential) A high on this input causes the D, /D input to flow through to the Q, /Q output. A low on the input causes the Q, /Q output to remain static, except for a possible reset. Q, /Q – CML Output (Differential) This is the output of the latch. FUNCTIONAL DESCRIPTION complement input to V CC and leave the true input unconnected. To make an input static logic one, connect the true input to V CC , leave the complement input unconnected. These are the only ;safe ways to cause inputs to be at a static value. In particular, no input pin should be directly connected to ground. All NC (no connect) pins should be unconnected. Establishing Static Logic Inputs The true pin of an input pair is internally biased to ground through a 75kΩ resistor. The complement pin of an input pair is internally biased halfway between VCC and ground by a voltage divider consisting of two 75kΩ resistors. To keep an input at static logic zero at VCC > 3.0V, leave both inputs unconnected. For V CC ≤ 3.0V, connect the VCC X NC X NC /X NC /X VCC > 3.0V Figure 1. Hard Wiring A Logic “1” (1) Note 1. X is either D, LE, R input. /X is either /D, /LE, /R input. NC X VCC /X VCC ≤ 3.0V TRUTH TABLE Figure 2. Hard Wiring A Logic “0” (1) D LE R Q /Q X 0 0 Latched(1) Latched(1) 0 1 0 0 1 1 1 0 1 0 X X 1 0 1 Note 1. Retains data before LE falling transition. 2 SuperLite™ SY55853U Micrel ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit –0.5 to +6.0 V –0.5 to VCC +0.5 V VCC –1.0 to VCC +0.5 V Operating Temperature Range –40 to +85 °C Storage Temperature Range –65 to +150 °C VCC Power Supply Voltage VIN Input Voltage VOUT CML Output Voltage TA Tstore Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. CML TERMINATION All inputs accept the output from any other member of this family. All outputs are source terminated 100Ω CML differential drivers as shown in Figures 3 and 4. SY55853U expects the inputs to be terminated, and that good high vcc 100Ω speed design practices be adhered to. SY55853U inputs are designed to accept a termination resistor between the true and complement inputs of a differential pair. 0402 form factor chip resistors will fit with some trace fanout. vcc vcc 100Ω 100Ω 100Ω 50Ω 100Ω 100Ω 100Ω 50Ω 100Ω 100Ω 50Ω 50Ω 50Ω 8mA 8mA SY55853U SY55853U Figure 3a. Differentially Terminated (50Ω Load CML Output) Figure 3b. Individually Terminated (50Ω Load CML Output) VCC 100Ω 100Ω 100Ω 200Ω 100Ω 8mA SY55853U Figure 4. 100Ω Load CML Output 3 50Ω SuperLite™ SY55853U Micrel DC ELECTRICAL CHARACTERISTICS(1) VCC = 2.3V to 5.7V; GND = 0V TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Min. Max. Unit VCC Power Supply Voltage 2.3 5.7 2.3 5.7 2.3 5.7 2.3 5.7 V ICC Power Supply Current — 37 — 37 — 37 — 37 mA Note 1. Specification for packaged product only. CML DC ELECTRICAL CHARACTERISTICS(1) VCC = 2.3V to 5.7V; GND = 0V; TA = –40°C to +85°C(2) Symbol VID Parameter Min. Typ. Max. Unit Differential Input Voltage Condition 100 — — mV Input HIGH Voltage(3) 1.6 — VCC V VIL Input LOW Voltage(3) 1.5 — VCC – 0.1 V VOH Output HIGH Voltage VCC – 0.020 VCC – 0.010 VCC V No Load VOL Output LOW Voltage VCC – 0.97 VCC – 0.825 VCC – 0.660 V No Load VOS Output Voltage Swing(4) 0.660 0.800 0.400 0.200 0.950 V No Load 100Ω Environment(5) 50Ω Environment(6) RDRIVE Output Source Impedance 80 100 120 Ω VIH Note 1. Specification for packaged product only. Note 2. Equilibrium temperature. Note 3. Inputs Must be biased to logic LOW or HIGH when VCC is less than 3.0V. Note 4. Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in the 100Ω environment and a 200mV swing in the 50Ω environment. Refer to the “CML Termination” diagram for more details. Note 5. See Figure 4. Note 6. See Figure 3a and 3b. AC ELECTRICAL CHARACTERISTICS(1, 2) VCC = 2.3V to 5.7V; GND = 0V; TA = –40°C to +85°C Symbol Parameter Min. Typ. Max. Unit 2.5 — — GHz fMAX Max. Operating Frequency tPLH tPHL Propagation Delay D to Q LE to Q R to Q — — — — — — 400 400 500 ps tS Set-Up Time D to LE D to R 70 — — — — — ps tH Hold Time LE to D 40 — — ps tRR Reset Recovery 400 — — ps tPW Minimum Pulse Width 160 250 — — — — ps tr tf CML Output Rise/Fall Times (20% to 80%) –40°C to 0°C 0°C to 85°C — 35 — — 175 160 Note 1. Note 2. LE High R High ps Specification for packaged product only. Tested using environment of Figure 3b, 50Ω load CML output. 4 Condition SuperLite™ SY55853U Micrel TIMING DIAGRAMS CLK tH 50% 50% DATA tS tRR RESET 50% Q 50% tPHL tPLH PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY55853UKC K10-1 Commercial 5 SuperLite™ SY55853U Micrel 10 LEAD MSOP (K10-1) Rev. 00 MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 6