TOSHIBA TMPR3907F 32-bit MIPS RISC Microprocessor Peripheral Features Description The TMPR3907F is a 32-bit MIPS RISC microprocessor of the TX39 family. The TMPR3907F uses the TX39/H Processor Core as the CPU, which is a RISC CPU core Toshiba developed based on the MIPS R3000A architecture. The TMPR3907F has built-in peripheral circuits such as a PCI Bus Controller, DRAM and ROM Memory Controllers, Serial Communication Ports, and Timer/Counter implementations. The TX39/H core and added PCI Bus Controller features of this chip allow it to achieve high performance system interfacing. • • Microprocessor Features • • • • Built–in TX39 Processor Core - Developed based on the R3000A architecture - Instruction cache 4KB and Data cache 1KB - Built-in Debug Support Unit (DSU) - Five-stage pipeline: Fetch, Decode, Execute, Memory access, and Register write - Incorporates single cycle DSP function Multiply- • Accumulate (MAC) Power Supply: VDD = 3.3V ± 0.3V • Maximum Operating Frequency: 66MHz Package: 208 pin plastic QFP • R3900 Core Instruction cache Data cache DSU WBU Timer, Debug, SIO0, and Test SIO, Test and Debug • G-Bus Interface IM Bus GBUS RAM Address 3-Channel DRAM Controller Control Signals 5-Channel ROM/Flash Controller Interrupt Controller Host PCI Bridge External Bus Interface (EBIF) Memory Data Bus ROM Address, and Control Signals PCI Bus INT [3:1] DRAM Controller - Supports 3 channels of DRAM memories - Each channel supports two banks of memory - Independent memory size and timing set-up for each channel - Support of 32/16-bit static bus sizing - Supports both fast and hyper page EDO modes ROM Controller - Supports 5 channels of ROM controller with a single chip select per channel - Supports simple-page-mode and interleavedpage-mode ROM - Supports various memory size of 1M/2M/4M/8M/16Mbyte per channel - Supports 32/16-bit static bus sizing and fast page read mode - Supports Mask ROM, EPROM, E2PROM, SRAM, and Flash Memory - Supports 2-way interleaved ROM attachment on Channel 0 Timer/Counter - 3-channel 24-bit up-counter - Interval and Watchdog timer modes Serial I/O Ports - One-channel UART - Baud rate generator and modem flow control Interrupt Controller - Priority process of 8 interrupt sources - Non-maskable Interrupt (NMI) PCI Controller - Full compliance with PCI Local Bus Specification Rev. 2.1 - 32-bit PCI interface at 33MHz - Supports both target and initiator mode - Supports zero-wait-state read and write burst transfer for target and initiator - FIFO to minimize initial latency requirements to and from memory controller - Supports PIO mode transfer between local bus and PCI Core - Supports auto PCI bus to local bus address space mapping Figure 1. TMPR3907F Block Diagram Product Brief TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. TMPR3907F 32-bit MIPS RISC Microprocessor ROM / Flash Control ROM / Flash Clock Generator ROM / Flash Addressing 33 MHz Test & Reset Core Observability 32-Bit Page Mode ROM 32-Bit Page Mode ROM 2-Way Quick-Switches Data Bus TX3907F-66 MHz 208 PQFP DRAM Control Base EDO DRAM DRAM Addressing EDO DRAM SIMM Control/Arb. Address/Data PCI Slot 0 Control/Arb. Address/Data PCI Slot 1 Figure 2. Typical System Block Diagram Product Brief TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 2 TMPR3907F 32-bit MIPS RISC Microprocessor Table 1. Pin Assignment Pin No. Signal Pin No. 1 INT[1] 29 2 INT[0] 30 3 GNT_N[2] 31 4 GNT_N[1] 32 5 GNT_N[0] 33 6 ROMAD[23] 34 7 ROMAD[22] 35 8 SCS[1]*/CE[4]* 36 9 VDD 37 10 VDD 38 11 VSS 39 12 SCS[0]*/CE[3]* 40 13 CE[2]* 41 14 CE[1]* 42 15 VSS 43 16 CE[0]* 44 17 SWE* 45 18 R/W* 46 19 SPADD[0] 47 20 SPADD[1] 48 21 ROMAD[2] 49 22 ROMAD[3] 50 23 ROMAD[4] 51 24 ROMAD[5] 52 25 VDD 53 26 VSS 54 27 VSS 55 28 ROMAD[6] 56 *Active-low signal Product Brief Signal ROMAD[7] ROMAD[8] ROMAD[9] OE* SYSCLK ACK* LAST*/RD* VDD VSS VSS ROMAD[10] ROMAD[11] ROMAD[12] ROMAD[13] VDD ROMAD[14] ROMAD[15] ROMAD[16] ROMAD[17] ROMAD[18] ROMAD[19] VSS ROMAD[20] ROMAD[21] ENLEAFA* ENLEAFB* D[16] D[24] Pin No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal D[17] D[25] D[18] VSS VDD VSS D[26] D[19] D[27] DRAMA[0] DRAMA[1] DRAMA[2] DRAMA[3] DRAMA[4] DRAMA[5] VSS VSS VDD DRAMA[6] DRAMA[10] D[20] D[28] D[21] D[29] D[22] D[30] D[23] D[31] Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Signal VDD VSS DRAMA[7] DRAMA[11] DRAMA[8] DRAMA[9] DRAMA[12] RAS0[0]* RAS0[1]* RAS1[0]* RAS1[1]* VSS VDD RAS2[0]* RAS2[1]* CAS[0]*/BE[0]* CAS[1]*/BE[1]* CAS[3]*/BE[3]* CAS[2]*/BE[2]* WE* D[0] D[8] PLLOFF* PLL_VSS VSS XIN XOUT VDD 3 TMPR3907F 32-bit MIPS RISC Microprocessor Table 1. Pin Assignment (Continued) Pin No. Signal 113 PLL_VDD 114 VDD 115 D[1] 116 D[9] 117 D[2] 118 D[10] 119 VSS 120 D[3] 121 D[11] 122 D[4] 123 D[12] 124 D[13] 125 D[5] 126 D[14] 127 D[6] 128 D[15] 129 D[7] 130 VSS 131 VSS 132 RESET* 133 TEST* 134 NMI* 135 DSA0 136 DRESET* *Active-low signal Pin No. 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal SDI* DBGE* PCST[2] PCST[1] PCST[0] VSS GDCLK PCI_CLK PCIAD[0] PCIAD[1] VDD PCIAD[2] PCIAD[3] PCIAD[4] PCIAD[5] PCIAD[6] PCIAD[7] VDD VSS VSS C_BE[0] PCIAD[8] PCIAD[9] PCIAD[10] Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Signal PCIAD[11] PCIAD[12] PCIAD[13] VSS VDD PCIAD[14] PCIAD[15] C_BE[1] PAR SERR_N PERR_N STOP_N VSS DEVSEL_N TRDY_N IRDY_N FRAME_N C_BE[2] PCIAD[16] PCIAD[17] VDD VSS VSS VDD Pin No. 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal PCIAD[18] PCIAD[19] PCIAD[20] PCIAD[21] PCIAD[22] PCIAD[23] ID_SEL VSS C_BE[3] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] VSS VDD VSS PCIAD[30] PCIAD[31] REQ_N[2] REQ_N[1] REQ_N[0] INT[2] MIPS is a registered trademark R3000A is a trademark of UPS Technologies, Inc. www.toshiba.com/taec 1. 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