TOSHIBA TC5117400BSJ/BST-60/70 PRELIMINARY 4,194,304 WORD X 4 BIT DYNAMIC RAM Description The TC5117400BSJ/BST is the new generation dynamic RAM organized 4,194,304 word by 4 bits. The TC5117400BSJ/BST utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC5117400BSJ/BST to be packaged in a 26/24 pin plastic SOJ (300mil), and 26/24 pin plastic TSOP (300mil). The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V± 10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. Features • 4,194,304 word by 4 bit organization • Fast access time and cycle time • Single power supply of 5V± 10% with a built-in VBB generator • Low Power - 605mW MAX. Operating - (TC5117400BSJ/BST-60) - 523mW MAX. Operating - (TC5117400BSJ/BST-70) - 5.5mW MAX. Standby • Outputs unlatched at cycle end allows twodimensional chip selection • Common I/O capability using “EARLY WRITE” operation • Read-Modify-Write, CAS before RAS refresh, RAS-only refresh, Hidden refresh, Fast Page Mode and Test Mode capability • All inputs and outputs TTL compatible • 2048 refresh cycles/32ms • Package TC5117400BSJ: SOJ26-P-300C TC5117400BST: TSOP26-P-300D Key Parameters TC5117400BSJ/BST ITEM -60 -70 tRAC RAS Access Time 60ns 70ns tAA Column Address Access Time 30ns 35ns tCAC CAS Access Time 15ns 20ns tRC Cycle Time 110ns 130ns tPC Fast Page Mode Cycle Time 40ns 45ns 1. This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited. 2. LIFE SUPPORT POLICY Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this data book is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 1 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Pin Name A0 ~ A10 Address Inputs RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable I/O1~I/O4 Data Input/Output VCC Power (+5V) VSS Ground Pin Connection (Top View) 2 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Block Diagram Absolute Maximum Ratings ITEM SYMBOL RATING UNIT NOTE VIN -0.5~VCC+0.5 V 1 Output Voltage VOUT -0.5~VCC+0.5 V 1 Power Supply Voltage VCC -0.5~7.0 V 1 Operating Temperature TOPR 0~70 °C 1 Storage Temperature TSTG -55~150 °C 1 TSOLDER 260 °C 1 PD 900 mW 1 IOUT 50 mA 1 Input Voltage Soldering Temperature (10s) Power Dissipation Short Circuit Output Current PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 3 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Recommended DC Operating Conditions (Ta = 0 ~ 70°C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTE VCC Power Supply Voltage 4.5 5.0 5.5 V 2 VIH Input High Voltage 2.4 - VCC + 0.5* V 2 VIL Input Low Voltage -0.5** - 0.8 V 2 MIN MAX TC5117400BSJ/BST-60 - 110 TC5117400BSJ/BST-70 - 95 – 2 TC5117400BSJ/BST-60 - 110 TC5117400BSJ/BST-70 - 95 TC5117400BSJ/BST-60 - 70 TC5117400BSJ/BST-70 - 60 – 1 TC5117400BSJ/BST-60 - 110 TC5117400BSJ/BST70 - 95 -10 10 µA -10 10 µA 2.4 - V - 0.4 V *VCC + 2.0V at pulse width ≤ 20ns (pulse width is measured at VCC). **-2.0V at pulse width ≤ 20ns (pulse width is measured at VSS). DC Electrical Characteristics (VCC = 5V ± 10%, Ta = 0 ~ 70°C) SYMBOL |CC1 |CC2 |CC3 |CC4 |CC5 |CC6 |I (L) |O (L) VOH VOL 4 PARAMETER OPERATING CURRENT Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC=tRC MIN) STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VIH) RAS ONLY REFRESH CURRENT Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS=VIH: tRC=tRC MIN.) FAST PAGE MODE CURRENT Average Power Supply Current, Fast Page Mode (RAS =VIL, CAS, Address Cycling: tPC=tPC MIN.) STANDBY CURRENT Power Supply Standby Current (RAS=CAS=VCC-0.2V) CAS BEFORE RAS REFRESH CURRENT Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC=tRC MIN.) INPUT LEAKAGE CURRENT Input Leakage Current, any input (0V<VIN<VCC, All Other Pins Not Under Test=0V) OUTPUT LEAKAGE CURRENT (DOUT is disabled, (0V≤VOUT<VCC) OUTPUT LEVEL Output “H” Level Voltage (IOUT=-5mA) OUTPUT LEVEL Output “L” Level Voltage (IOUT=4.2mA) TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. UNIT NOTE mA 3,4 5 mA mA 3, 5 mA 3,4 5 mA mA 3, 5 PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Electrical Characteristics and Recommended AC Operating Conditions (VCC = 5V ± 10%, Ta = 0~70°C) (Notes 6,7,8) TC5117400BSJ/BST SYMBOL tRC tRMW PARAMETER -60 -70 UNIT MIN MAX. MIN MAX Random Read or Write Cycle Time 110 - 130 - NOTES ns Read-Modify-Write Cycle 155 - 180 - ns Fast Page Mode Cycle Time 40 - 45 - ns Fast Page Mode Read-Modify-Write Cycle Time 85 - 95 - ns Access Time from RAS - 60 - 70 ns 9,14, 15 tCAC Access Time from CAS - 15 - 20 ns 9,14 tAA Access Time from Column Address - 30 - 35 ns 9,15 tPC tPRMW tRAC tCPA Access Time from CAS Precharge - 35 - 40 - 9 tCLZ CAS to Output in Low-Z 0 - 0 - ns 9 tOFF Output Buffer Turn-off Delay 0 15 0 15 ns 10 Transition Time (Rise and Fall) 3 50 3 50 ns 8 tT tRP RAS Precharge Time 40 - 50 - ns tRAS RAS Pulse Width 60 10,000 70 10,000 ns tRASP RAS Pulse Width (Fast Page Mode) 60 200,000 70 200,000 ns tRSH RAS Hold Time 15 - 20 - ns tRHCP RAS Hold Time from CAS Precharge (Fast Page Mode) 35 - 40 - ns tCSH CAS Hold Time 60 - 70 - ns tCAS CAS Pulse Width 15 10,000 20 10,000 ns tRCD RAS to CAS Delay Time 20 45 20 50 ns 14 tRAD RAS to Column Address Delay Time 15 30 15 35 ns 15 tCRP CAS to RAS Precharge Time 5 - 5 tCP CAS Precharge Time 10 - 10 ns - ns tASR Row Address Set-Up Time 0 - 0 - ns tRAH Row Address Hold Time 10 - 10 - ns tASC Column Address Set-Up Time 0 - 0 - ns tCAH Column Address Hold Time 10 - 15 - ns tRAL Column Address to RAS Lead Time 30 - 35 - ns tRCS Read Command Set-Up Time 0 - 0 - ns tRCH Read Command Hold Time 0 - 0 - ns 11 tRRH Read Command Hold Time referenced to RAS 0 - 0 - ns 11 PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 5 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Electrical Characteristics and Recommended AC Operating Conditions (Cont) TC5117400BSJ/BST SYMBOL tWCH 6 PARAMETER Write Command Hold Time -60 -70 UNIT MIN MAX. MIN MAX 10 - 15 - NOTES ns tWP Write Command Pulse Width 10 - 15 - ns tRWL Write Command to RAS Lead Time 15 - 20 - ns tCWL Write Command to CAS Lead Time 15 - 20 - ns tDS Data Set-Up Time 0 - 0 - ns 12 12 tDH Data Hold Time 10 - 15 - ns tREF Refresh Period - 32 - 32 ms tWCS Write Command Set-Up Time 0 - 0 - ns 13 tCWD CAS to WE Delay Time 40 - 45 - ns 13 tRWD RAS to WE Delay Time 85 - 95 - ns 13 tAWD Column Address to WE Delay Time 55 - 60 - ns 13 tCPWD CAS Precharge to WE Delay Time 60 - 65 - ns 13 tCSR CAS Set-Up Time (CAS before RAS Cycle) 5 - 5 - ns tCHR CAS Hold Time (CAS before RAS Cycle) 10 - 15 - ns tRPC RAS to CAS Precharge Time 5 - 5 - ns tCPT CAS Precharge Time (CAS before RAS Counter Test Cycle 20 - 30 - ns tROH RAS Hold Time referenced to OE 10 - 10 - ns tOEA OE Access Time - 15 - 20 ns tOED OE to Data Delay 15 - 15 - ns tOEZ Output buffer turn off Delay Time from OE 0 15 0 15 ns tOEH OE Command Hold Time 10 - 15 - ns tODS Output Disable Setup Time 0 - 0 - ns tWTS Write Command Set-up Time (Test Mode In) 10 - 10 - ns tWTH Write Command Hold Time (Test Mode In) 10 - 10 - ns tWRP WE to RAS Precharge Time (CAS before RAS Cycle) 10 - 10 - ns tWRH WE to RAS Hold Time (CAS before RAS Cycle) 10 - 10 - ns TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 10 PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Electrical Characteristics and Recommended AC Operating Conditions in the Test Mode TC5117400BSJ/BST SYMBOL PARAMETER -60 -70 UNIT MIN MAX. MIN MAX NOTES tRC Random Read or Write Cycle Time 115 - 135 - ns tPC Fast Page Mode Cycle Time 45 - 50 - ns tRAC Access Time from RAS - 65 - 75 ns 9, 14, 15 tCAC Access Time from CAS - 20 - 25 ns 9, 14 tAA Access Time from Column Address - 35 - 40 ns 9, 15 9 tCPA Access Time from CAS Precharge tRAS RAS Pulse Width - 40 - 45 ns 65 10,000 75 10,000 ns tRASP tRSH RAS Pulse Width (Fast Page Mode) 65 200,000 75 200,000 ns RAS Hold Time 20 - 25 - ns tCSH CAS Hold Time 65 - 75 - ns tRHCP CAS Precharge to RAS Hold 40 - 45 - ns tCAS CAS Pulse Width 20 10,000 25 10,000 ns tRAL Column Address to RAS Lead Time 35 - 40 - ns MIN MAX Capacitance (VCC = 5V ± 10%, f = 1MHz, Ta = 0 ~ 70°C) SYMBOL PARAMETER CI1 Input Capacitance (A0~A10) - 5 CI2 Input Capacitance (RAS, CAS, WE, OE) - 7 CO Input Capacitance (I/O1~I/O4) - 7 PRELIMINARY UNIT PF TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 7 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 8 Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are referenced to VSS. ICC1, ICC3, ICC4, ICC6 depend on cycle rate. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed one or less while RAS=VIL. In case of ICC4, it can be changed once or less during a fast page mode cycle (tPC). An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. AC measurements assume tT=5ns. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. Measured with a load equivalent to 2 TTL loads and 100pF. tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; If tRWD≥tRWD (min.), tCWD≥tCWD (min.), tAWD≥tAWD (min.) and tCPWD≥tCPWD (min.), (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. Operation within the tRCD (max.) limit insures that tRAC can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Timing Waveforms Read Cycle PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 9 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Write Cycle (Early Write) 10 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Write Cycle (OE Controlled Write) PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 11 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Read-Modify-Write Cycle 12 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Fast Page Mode Read Cycle PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 13 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Fast Page Mode Write Cycle (Early Write) 14 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Fast Page Mode Read-Modify-Write Cycle PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 15 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 RAS Only Refresh Cycle CAS Before RAS Refresh Cycle 16 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM TC5117400BSJ/BST-60/70 Hidden Refresh Cycle (Read) PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 17 TC5117400BSJ/BST-60/70 Standard DRAM DR16040794 Hidden Refresh Cycle (Write) 18 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. PRELIMINARY DR16040794 Standard DRAM Outline Drawings (SOJ26-P-300C) PRELIMINARY TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. TC5117400BSJ/BST-60/70 Unit in mm 19 TC5117400BSJ/BST-60/70 Standard DRAM Outline Drawings (TSOP26-P-300D) 20 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. DR16040794 Unit in mm PRELIMINARY Back to Memory