W78E58 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78E58 is an 8-bit microcontroller that is functionally compatible with the W78C58, except that the mask ROM is replaced by a flash EEPROM with a size of 32 KB. To facilitate programming and verification, the flash EEPROM inside the W78E58 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E58 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market. It is functionally compatible with the industry-standard 80C52 microcontroller series, except that one extra 4-bit bit-addressable I/O port(Port 4) and two additional external interrupts ( INT2 , INT3 ). The W78E58 contains four 8-bit bi-directional and bit-addressable I/O ports, three 16-bit timer/counters, and a serial port. These peripherals are supported by a eight-source, two-level interrupt capability. There are 256 bytes of RAM and an 32 KB flash EEPROM for application programs. The W78E58 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES • • • • • • • • • • • • • • • • • 8-bit CMOS microcontroller Fully static design Low standby current at full supply voltage DC-40 MHz operation 256 bytes of on-chip scratchpad RAM 32 KB electrically erasable/programmable EPROM 64 KB program memory address space 64 KB data memory address space Four 8-bit bidirectional ports One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC/QFP package) Three 16-bit timer/counters One full duplex serial port Boolean processor Eight-source, two-level interrupt capability Built-in power management Code protection mechanism Packages: − DIP 40: W78E58-16/24/40 − PLCC 44: W78E58P-16/24/40 − QFP 44: W78E58F-16/24/40 − TQFP 44: W78E58M-16/24/40 -1- Publication Release Date: November 1997 Revision A2 W78E58 PIN CONFIGURATIONS 40-Pin DIP (W78E58) T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 44-Pin PLCC (W78E58P) T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 T 2 , P 1 . 0 P 3 . 7 , / R D X T A L 2 / I N T 3 , P 4 V . C 2 C X V P T S 4 A S . L 0 1 P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin QFP/TQFP (W78E58F/W78E58M) A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 T 2 E X , P P P P 1 1 1 1 . . . . 4 3 2 1 A D 3 , P 0 . 3 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R VCC P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE INT0, P3.2 PSEN P2.7, A15 P2.6, A14 P2.5, A13 INT1, P3.3 T0, P3.4 T1, P3.5 P 2 . 4 , A 1 2 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 1 2 P 3 . 6 , / W R -2- / I N T T 2 3 , , P P 1 4 V . . C 0 2 C P 3 . 7 , / R D X T A L 2 X V P P T S 4 2 A S . . L 0 0 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 W78E58 PIN DESCRIPTION The W78E58 has two operating modes, normal and flash. In normal mode, the W78E58 corresponds to the W78C58. In flash mode, the user (the maker of the flash EEPROM writer) can access the flash EEPROM. P0.7−P0.0 Port 0, Bits 7−0 MODE Normal Flash DESCRIPTION Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. This port provides the data bus during access to the flash EEPROM. P1.7−P1.0 Port 1, Bits 7−0 MODE DESCRIPTION Normal Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively. Flash This port provides the low-order address bus during access to the flash EEPROM. P2.7−P2.0 Port 2, Bits 7−0 MODE DESCRIPTION Normal Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.. Flash This port provides the high-order address bus during access to the flash EEPROM. P3.7−P3.0 Port 3, Bits 7−0 MODE Normal Flash DESCRIPTION Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions. P3.3−P3.0 and P3.7−P3.6 are the flash mode configuration pins, Input. P3.3−P3.0 and P3.7−P3.6 are configured to select or execute the flash operations. For details, see Flash Operations. P4.3−P4.0 Port 4, Bits 3−0 (available on 44-pin PLCC/QFP package) MODE Normal DESCRIPTION Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 / INT3 ). -3- Publication Release Date: November 1997 Revision A2 W78E58 Flash No function in this mode. EA/VPP MODE Normal DESCRIPTION EA , External Access, Input, active low. This pin forces the processor to execute a program from the external ROM. When the internal flash EEPROM is accessed as in the W78C58, this pin should be kept high. Flash VPP, Program Power supply pin, Input. This pin accepts the high voltage (12V) needed for programming the flash EEPROM. RST MODE Normal DESCRIPTION RST, Reset, Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor. Flash Flash mode configuration pin, Input, active high. RST is used to configure the flash operations. For details, see Flash Operations. ALE MODE Normal Flash DESCRIPTION ALE, Address Latch Enable, Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high impedance state with a weak pull-up during reset state. Flash mode configuration pin, Input, active low. ALE is used to configure the flash operations. For details, see Flash Operations. PSEN MODE Normal DESCRIPTION PSEN , Program Store Enable, Output, active low. This pin enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state with a weak pull-up during reset state Flash Flash mode configuration pin, Input, active high. PSEN is used to configure the flash operations. For details, see Flash Operations. XTAL1 MODE DESCRIPTION -4- W78E58 Normal Flash Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock. Connect to VSS. XTAL2 MODE Normal Flash DESCRIPTION Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1. No function in this mode. VSS, VCC Power Supplies. These are the chip ground and positive supplies. -5- Publication Release Date: November 1997 Revision A2 W78E58 BLOCK DIAGRAM P1.0 ~ P1.7 Port 1 Port 1 Latch B ACC INT2 Port 0 Interrupt INT3 Latch T1 T2 Timer 2 Timer 0 Port 0 P0.0 ~ P0.7 DPTR Stack Pointer PSW ALU Temp Reg. Timer 1 PC Incrementor UART Addr. Reg. P3.0 ~ P3.7 Port 3 Port 3 Latch SFR RAM Address Instruction Decoder & Sequencer 256 bytes RAM & SFR Port 2 Latch Bus & Clock Controller P4.0 ~ P4.3 Port 4 Port 4 Latch Oscillator Reset Block XTAL1 XTAL2 ALE PSEN RST -6- Power Control Vcc Vss Port 2 P2.0 ~ P2.7 W78E58 FUNCTIONAL DESCRIPTION The W78E58 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78E58: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. Clock The W78E58 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78E58 relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78E58 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a reset. -7- Publication Release Date: November 1997 Revision A2 W78E58 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E58 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. Option Setting Users write programs into the W78E58 by using the Winbond proprietary writer. The writer programs the data into an internal 32 KB region and reads the data back for verification. After confirming that the program is correct, the user can lock the data so that they can no longer be read. Lock Bit This bit is used to protect the customer data in the W78E58. It may be turned on after the programmer finishes the programming and verify sequence. Once this bit is set to logic 0, no flash data can be accessed again. MOVC Execute This bit is used to restrict the region accessible to the MOVC instruction. It can prevent the program from being downloaded using this instruction if the program needs to jump outside to get data. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code in the external memory, but it will not be able to access code in the internal memory. A MOVC instruction in internal program memory space will always be able to access code in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. New Defined Peripheral In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows: 1. INT2/INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. ***XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 PX3: External interrupt 3 priority high if set -8- EX2 IE2 IT2 W78E58 EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt informations: INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 - External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 - Serial Port 23H 4 IE.4 - Timer/Counter 2 2BH 5 IE.5 - External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3 2. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 / INT3 ). Example: P4 REG 0D8H MOV P4, #0AH ; Output data "A" through P4.0−P4.3. MOV A, P4 ; Read P4 status to Accumulator. SETB P4.0 ; Set bit P4.0 CLR P4.1 ; Clear bit P4.1 3. Reduce EMI Emission Because of the large on-chip flash EEPROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI -9- Publication Release Date: November 1997 Revision A2 W78E58 emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space.. The AO bit in the AUXR register, when set, disables the ALE output. ***AUXR - Auxiliary register (8EH) - - - - - - - AO POF GF1 GF0 PD IDL AO: Turn off ALE output. 4. Power-off Flag ***PCON - Power control (87H) SMOD - - SMOD: Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2, 3. POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software to determine chip reset is a warm boot or cold boot. GF1, GF0: These two bits are general-purpose flag bits for the user. PD: Power down mode bit. Set it to enter power down mode. IDL: Idle mode bit. Set it to enter idle mode. The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. Flash Operations In normal operation, the W78E58 is functionally compatible with the W78C58. In the flash operating mode, the flash EEPROM can be programmed and verified repeatedly. Once the code inside the flash EEPROM is confirmed, the code can be protected. The flash EEPROM and the operations on it are described below. All of the operations are configured by the pins RST, ALE, PSEN, A9CTRL (P3.0), A13CTRL (P3.1), A14CTRL (P3.2), OECTRL (P3.3), CE (P3.6), OE (P3.7), A0 (P1.0) and VPP ( EA ). In these operations, A15 to A0 (P2.7 to P2.0, P1.7 to P1.0) and D7 to D0 (P0.7 to P0.0) serve as the address and data bus, respectively. Read Operation This operation enables customers to read their codes and the option bits. The data will not be valid if the lock bit is programmed to low. - 10 - W78E58 Program Operation This operation is used to program data to the flash EEPROM and the option bits. Programming is initiated when VPP reaches VCP (12.5V) level, CE is set to low, and OE is set to high. Program Verify Operation All data must be checked after programming. This operation should be performed after each byte is programmed, and it will ensure a substantial program margin. P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 (A9 CTRL) (A13 CTRL) (A14 CTRL) (OE CTRL) ( CE ) ( OE ) Read VIL VIL VIL VIL VIL VIL Program VIL VIL VIL VIL VIL VIH Program Verify VIL VIL VIL VIL VIH VIL VCP OPERATION P2, P1 P0 (A15 TO A0) (D7 TO D0) VIH Address Data Out 1, 2 VCP Address Data In 1, 2 Address Data Out EA (VPP) NOTES 3 Notes: 1. During all of these operations, RST = VIH, ALE = VIL, and PSEN = VIH. 2. VCP = 12V, VIH = VDD, VIL = Vss. 3. The program verify operation should follow the programming operaion. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT VDD−VSS -0.3 +7.0 V Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability the device. +5V +5V V DD V DD A0 to A7 P1 V IL P3.0 V IL P3.1 V IL P3.2 V IL V IL V IH P0 EA/Vpp PGM DATA V IL P3.3 P3.6 RST V IH P3.7 PSEN V IH P2 A0 to A7 V CP ALE X'tal1 of P1 V IL P3.0 V IL P3.1 V IL V IL P3.2 P3.3 V IH P3.6 V IL P3.7 X'tal1 A8 to A15 X'tal2 X'tal2 Vss Vss Programming Configuration P0 EA/Vpp PGM DATA V CP ALE V IL RST V IH PSEN V IH P2 A8 to A15 Programming Verification - 11 - Publication Release Date: November 1997 Revision A2 W78E58 DC CHARACTERISTICS (VDD-VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SYM. SPECIFICATION MIN. MAX. UNIT Operating Voltage VDD 4.5 5.5 V Operating Current IDD - 20 mA TEST CONDITIONS No load VDD = 5.5V Idle Current IIDLE - 6 mA Idle mode VDD = 5.5V Power Down Current IPWDN - 50 µA Power-down mode VDD = 5.5V Input Current IIN1 -50 +10 µA P1, P2, P3, P4 Input Current VIN = 0V or VDD IIN2 -10 +300 µA RST Input Leakage Current VDD = 5.5V 0 < VIN < VDD ILK -10 +10 µA VDD = 5.5V 0V <VIN < VDD P0, EA Logic 1 to 0 Transition Current VDD = 5.5V ITL [*4] -500 -200 µA VDD = 5.5V VIN =2.0V P1, P2, P3, P4 Input Low Voltage VIL1 0 0.8 V VDD = 4.5V VIL2 0 0.8 V VDD = 4.5V VIL3 0 0.8 V VDD = 4.5V VIH1 2.4 VDD +0.2 V VDD = 5.5V VIH2 3.5 VDD +0.2 V VDD = 5.5V VIH3 3.5 VDD +0.2 V VDD = 5.5V VOL1 - 0.45 V VDD = 4.5V P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4] Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3, P4 IOL = +2 mA - 12 - W78E58 DC Characteristics, continued PARAMETER Output Low Voltage SYM. VOL2 SPECIFICATION MIN. MAX. - 0.45 UNIT V ISK1 4 12 mA P1, P2, P3, P4 Sink Current ISK2 10 20 mA VOH1 2.4 - V VOH2 2.4 - V VDD = 4.5V IOH = -400 µA ISR1 -120 -250 µA P1, P2, P3, P4 Source Current VDD = 4.5V IOH = -100 µA P0, ALE, PSEN [*3] Source Current VDD = 4.5V Vs = 0.45V P1, P2, P3, P4 Output High Voltage VDD = 4.5V Vs = 0.45V P0, ALE, PSEN Output High Voltage VDD = 4.5V IOL = +4mA P0, ALE, PSEN [*3] Sink Current TEST CONDITIONS VDD = 4.5V Vs = 2.4V ISR2 -8 -14 mA VDD = 4.5V Vs = 2.4V P0, ALE, PSEN Notes: *1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 KΩ. *3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V. AC CHARACTERISTICS The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.8 micron CMOS process when using 2 and 4 mA output buffers. Clock Input Waveform - 13 - Publication Release Date: November 1997 Revision A2 W78E58 XTAL1 T CH TCL F OP, PARAMETER TCP SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP -∆ - - nS 4 Address Hold from ALE Low TAAH 1 TCP -∆ - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP -∆ - - nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP -∆ 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP -∆ 3 TCP - nS 4 Notes: 1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "∆" (due to buffer driving delay and wire loading) is 20 nS. Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to RD Low TDAR 3 TCP -∆ - 3 TCP +∆ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 - 14 - NOTE S W78E58 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP -∆ 6 TCP - nS 2 Notes: 1. Data memory access time is 8 TCP. 2. "∆" (due to buffer driving delay and wire loading) is 20 nS. Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP -∆ - 3 TCP +∆ nS Data Valid to WR Low TDAD 1 TCP -∆ - - nS Data Hold from WR High TDWD 1 TCP -∆ - - nS WR Pulse Width TDWR 6 TCP -∆ 6 TCP - nS SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: "∆" (due to buffer driving delay and wire loading) is 20 nS. Port Access Cycle PARAMETER Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. Program Operation PARAMETER SYMBOL MIN. TYP. MAX. UNIT VPP Setup Time TVPS 2.0 - - µS Data Setup Time TDS 2.0 - - µS Data Hold Time TDH 2.0 - - µS Address Setup Time TAS 2.0 - - µS Address Hold Time TAH 0 - - µS CE Program Pulse Width for Program Operation TPWP 295 300 305 µS CE Program Pulse Width for Program Operation TOPWP 295 300 305 µS OECTRL Setup Time TOCS 2.0 - - µS OECTRL Hold Time TOCH 2.0 - - µS - 15 - Publication Release Date: November 1997 Revision A2 W78E58 OE Setup Time TOES 2.0 - - µS OE High to Output Float TDFP 0 - 130 nS Data Valid from OE TOEV - - 150 nS Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and the PSEN pin must pull in VIH status. - 16 - W78E58 TIMING WAVEFORMS Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TPDA TAAH TPDH, TPDZ PORT 0 A0-A7 Code Data A0-A7 A0-A7 Code Data A0-A7 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 A8-A15 DATA A0-A7 PORT 0 T DAR T DDA T DDH, T DDZ RD T DRD - 17 - Publication Release Date: November 1997 Revision A2 W78E58 Timing Waveforms, continued Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 XTAL1 ALE PSEN A8-A15 PORT 2 PORT 0 A0-A7 DATA OUT T DWD TDAD WR T DWR T DAW Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS T PDA T PDH DATA OUT PORT INPUT SAMPLE - 18 - S3 W78E58 Timing Waveforms, continued Program Operation Program P2, P1 VIH (A15... A0) VIL P3.6 VIH (CE) VIL P3.3 (OECTRL) VIH P3.7 VIH (OE) VIL P0 (A7... A0) Program Verify Address Stable TPWP TAH TOCS TOCH TOES TDFP TDH VIH DOUT Data In Data Out TDS Vcp TOEV Vpp VIH Address Valid TAS VIL VIL Read Verify TVPS - 19 - Publication Release Date: November 1997 Revision A2 W78E58 TYPICAL APPLICATION CIRCUITS Expanded External Program Memory and Crystal VCC VCC 31 19 10 u EA XTAL1 R 18 XTAL2 CRYSTAL 8.2 K 9 C1 RST C2 12 13 14 15 INT0 INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 A15 GND 1 RD WR PSEN ALE TXD RXD 17 16 29 30 11 10 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 11 G 74LS373 2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 GND 20 CE 22 OE 27512 W78E58 Figure A CRYSTAL C1 C2 R 16 MHz 30P 30P - 24 MHz 15P 15P - 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 4.7K Above table shows the reference values for crystal applications. Note: C1, C2, R components refer to Figure A. - 20 - O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 W78E58 Typical Application Circuits, continued Expanded External Data Memory and Oscillator VCC VCC 31 10 u EA 19 XTAL1 18 XTAL2 9 RST 12 13 14 15 INT0 OSCILLATOR 8.2 K INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 38 37 36 35 34 33 32 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 RD 17 16 29 30 11 10 WR PSEN ALE TXD RXD AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1 11 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 20 22 27 CE OE WR A0 A1 A2 A3 A4 A5 A6 A7 OC G 74LS373 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 20256 W78E58 Figure B PACKAGE DIMENSIONS 40-pin DIP Symbol Dimension in inches Min. A A1 A2 B B1 c D E E1 e1 L D 40 21 E1 a eA S 20 1 Nom. Dimension in mm Max. Min. Nom. 0.210 0.010 Max. 5.334 0.254 0.150 0.155 0.160 3.81 3.937 0.016 0.018 0.022 0.406 0.457 4.064 0.048 0.050 0.054 1.219 1.27 1.372 0.008 0.010 0.014 0.203 0.254 0.356 2.055 2.070 52.20 52.58 15.494 0.559 0.610 14.986 15.24 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794 0.120 0.130 0.140 3.048 3.302 3.556 16.51 17.01 0.590 0.600 0 0.630 15 0.650 0.670 0 16.00 0.090 15 2.286 Notes: E S c A A2 A1 L Base Plane Seating Plane B B e1 a 1 - 21 - eA 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. Publication Release Date: November 1997 Revision A2 W78E58 Package Dimensions, continued 44-pin PLCC H D D 6 1 44 40 Symbol 7 39 HE E 17 GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inches Nom. Min. Dimension in mm Max. Min. Nom. Max. 0.185 4.699 0.020 0.508 0.145 0.150 0.155 3.683 3.81 0.026 0.028 0.032 0.66 0.711 0.016 0.018 0.022 0.406 0.457 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.050 0.590 16.46 0.658 BSC 0.610 0.813 0.559 16.59 1.27 0.630 3.937 16.71 BSC 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 0.10 L A2 Notes: A 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ e b b Seating Plane G A1 y 1 D 44-pin QFP HD Symbol 34 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e Dimension in mm Dimension in inch D 44 b 22 Min. Nom. Max. Min. Nom. --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 13.45 0.520 0.530 12.95 13.2 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 0.08 0.003 0 7 0 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. A2 A Seating Plane See Detail F A1 y θ L L1 Detail F - 22 - --- 0.510 Notes: c Max. --- --- 7 W78E58 Timing Waveforms, continued 44-pin TQFP HD D Symbol 34 44 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e b 22 Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. --- --- 0.047 --- --- Max. 1.20 0.002 0.004 0.006 0.05 0.10 0.15 0.037 0.039 0.041 0.95 1.00 1.05 0.0039 0.38 0.013 0.015 0.22 0.32 0.004 --- 0.008 0.090 --- 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.025 0.031 0.036 0.635 0.80 0.952 0.468 0.472 0.476 11.90 12.00 12.10 0.200 0.468 0.472 0.476 11.90 12.00 12.10 0.018 0.024 0.030 0.45 0.60 0.75 --- 0.039 --- --- 1.00 0.003 0 7 --0.08 0 7 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. c A2 A θ A1 Seating Plane See Detail F L y L Headquarters Detail F 1 Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792697 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice & Fax-on-demand: 886-2-27197006 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 23 - Publication Release Date: November 1997 Revision A2