19-2713; Rev 1; 11/03 KIT ATION EVALU E L B AVAILA 12.5Gbps Settable Receive Equalizer Features ♦ Compensates Up to 30in (0.75m) of 6-mil FR-4 Transmission Line Loss ♦ 115mW Operating Power ♦ Up to 12.5Gbps Data Rate ♦ Compatible with 8B10B, 64B66B, and PRBS Data ♦ Less than 30psP-P Residual Jitter After Equalization ♦ 3-Bit Equalization Level Select Input ♦ 3mm x 3mm Thin QFN Package ♦ DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O ♦ -40°C to +85°C Operation ♦ +3.3V Core Supply Voltage Ordering Information PART Applications OC-192 and 10Gb Ethernet Switches and Routers PINPACKAGE TEMP RANGE MAX3804ETE -40°C to +85°C PACKAGE CODE 16 Thin QFN T1633F-3 (3mm x 3mm) Pin Configuration appears at end of data sheet. OC-192 and 10Gb Ethernet Serial Modules High-Speed Signal Distribution Typical Operating Circuit +1.8V +2.5V +3.3V VCC 10Gbps SERIAL OPTICAL MODULE SDO+ IN 30in OF FR-4 STRIPLINE OR MICROSTRIP TRANSMISSION LINE VCC1 SDI+ SDO- SDI- VCC MAX3804 VCC VCC2 10Gbps SERDES SDO+ SDI+ SDO- SDI- EQ1 EQ2 EQ3 GND +3.3V ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3804 General Description The MAX3804 driver with integrated analog equalizer compensates up to 20dB of loss at 5GHz. It is designed to ensure PC board signal integrity up to 12.5Gbps, where frequency-dependent skin effect and dielectric losses typically produce unacceptable amounts of intersymbol interference. The MAX3804 can extend the practical chip-to-chip transmission distance for 10Gbps NRZ serial data up to 30in (0.75m) on FR-4, and it significantly decreases deterministic jitter. Residual jitter after equalization for 10.7Gbps signals is typically 24psP-P on the maximum path length. The MAX3804 is ideal for 10Gbps chip-to-chip serial interconnections on inexpensive FR-4 material. Its 3mm ✕ 3mm package affords optimal placement and routing flexibility. It has separate VCC connections for internal logic and current-mode logic (CML) I/O. This allows the CML input and output to be referenced to isolated supplies, providing independent DC-coupled interfacing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of input equalization can be selected through a digital control input, enabling the equalizer to be matched to a range of transmission line path loss. When correctly set to match the path loss, the MAX3804 provides optimal performance over a wide range of data rates and formats. MAX3804 12.5Gbps Settable Receive Equalizer ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ............................................-0.5V to +4.0V CML Supply Voltage (VCC1, VCC2) ............-0.5V to (VCC + 0.5V) Current at Serial Output (SDO+, SDO-) ............................±25mA Input Voltage (SDI+, SDI-, EQ1, EQ2, EQ3) ..............................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 16-Lead Thin QFN-EP (derate 17.5mW/°C above +85°C) ........................................................1398mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, VCC1 = VCC2 = +1.65V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = VCC1 = VCC2 = +3.3V, and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Supply Current ICC CML Input Differential VIN CONDITIONS AC-coupled or DC-coupled (Note 1) MIN TYP MAX UNITS 35 50 mA 400 1200 mVP-P VCC1 + 0.1 V CML Input Common Mode DC-coupled VCC1 - 0.4 CML Input Termination Single ended 42.5 CML Input Return Loss Up to 5GHz CML Output Differential VOUT CML Output Impedance CML Output Transition Time Single ended tR, tF Residual Jitter Output (Total RJ, PWD, and PDJ) LVTTL Input Current IIH, IIL LVTTL Input Low VIL LVTTL Input High VIH 50 57.5 10 Ω dB 400 500 600 42.5 50 57.5 Ω 35 ps 20% to 80% (Notes 2, 6) At 10.7Gbps (Notes 3, 4, 5, 6) 24 30 At 12.5Gbps (Notes 3, 4, 5, 6) 17 30 -30 2.0 mVP-P psP-P +30 µA 0.8 V V Note 1: Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z0 = 100Ω, 6-mil microstrip in FR-4, εr = 4.5, and tan δ = 0.02, VIN = (SDI+ - SDI-). Note 2: Measured with 0000011111 pattern at 12.5Gbps. Note 3: Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmission line) and equalizer output. Total residual jitter is DJP-P + 14.2 x RJRMS. Note 4: Measured at 10.7Gbps using a pattern of 100 ones, 27PRBS, 100 zeros, 27PRBS, and at 12.5Gbps using a K28.5 pattern. Deterministic jitter at the input is from frequency-dependent, media-induced loss only. Note 5: VIN = 400mVP-P to 1200mVP-P, input path is 0 to 30in, 6-mil microstrip in FR-4, εr = 4.5, and tan δ = 0.02. Note 6: Guaranteed by design and characterization. 2 _______________________________________________________________________________________ 12.5Gbps Settable Receive Equalizer 40 27PRBS WITH 100 CIDs AT 9.953Gbps 25 20 15 K28.5 AT 12.5Gbps 10 35 400mVP-P INPUT AMPLITUDE 30 RESIDUAL JITTER (psP-P) 55 30in OF FR-4 TRANSMISSION LINE 30 RESIDUAL JITTER (psP-P) SUPPLY CURRENT (mA) 70 35 MAX3804 toc02 VCC = VCC1 = VCC2 = 3.3V MAX3804 toc01 85 RESIDUAL JITTER vs. FR-4 PATH LENGTH 27PRBS WITH 100 MAX3804 toc03 RESIDUAL JITTER vs. INPUT AMPLITUDE SUPPLY CURRENT vs. TEMPERATURE CIDs AT 9.953Gbps 25 20 15 10 K28.5 AT 12.5Gbps 25 5 10 0 -15 10 35 60 85 600 800 1000 1200 3 9 15 21 27 FR-4 PATH LENGTH (in) RESIDUAL JITTER vs. EQUALIZATION SETTING EQUALIZER OUTPUT EYE AFTER 18in OF FR-4 (27PRBS WITH 100 CIDs AT 10.7Gbps) EQUALIZER OUTPUT EYE AFTER 18in OF FR-4 (K28.5 AT 12.5Gbps) 31 24in MAX3804 toc06 RESIDUAL JITTER DJP-P + 14.2RJRMS 18in MAX3804 toc05 INPUT AMPLITUDE (mVP-P) 35 RESIDUAL JITTER (psP-P) 400 RESIDUAL JITTER = DJP-P + 14.2RJRMS 0 TEMPERATURE (°C) MAX3804 toc04 -40 5 RESIDUAL JITTER = DJP-P + 14.2RJRMS 30in 27 60mV/ div 60mV/ div 6in 23 19 3in 15 000 001 400mVP-P, FR-4, 27 PRBS WITH 100 CIDs AT 10.7Gbps 12in 010 011 100 101 110 111 16ps/div 16ps/div EQUALIZATION SETTING (EQ3, EQ2, EQ1) _______________________________________________________________________________________ 3 MAX3804 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) 60mV/ div EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (K28.5 AT 12.5Gbps) MAX3804 toc09 EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (27PRBS WITH 100 CIDs AT 10.7Gbps) MAX3804 toc08 EQUALIZER INPUT EYE AFTER 30in OF FR-4 (27PRBS WITH 100 CIDs AT 10.7Gbps) MAX3804 toc07 60mV/ div 60mV/ div 16ps/div 16ps/div EQUALIZER OUTPUT EYE AFTER 30in OF FR-4 (27PRBS WITH 100 CIDs AT 3.2Gbps) MAX3804 toc11 EQUALIZER OUTPUT EYE AFTER 24ft OF RG-188/U COAXIAL CABLE, SINGLE ENDED (27PRBS WITH 100 CIDs, 9.953Gbps) 16ps/div MAX3804 toc10 MAX3804 12.5Gbps Settable Receive Equalizer 60mV/ div 60mV/ div 20ps/div 4 60ps/div _______________________________________________________________________________________ 12.5Gbps Settable Receive Equalizer PIN NAME FUNCTION 1, 4 VCC1 CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be AC-coupled. 2 SDI+ Positive Serial Data Input, CML 3 SDI- Negative Serial Data Input, CML 5 EQ1 Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1. 6 EQ2 Equalizer Boost Control Logic Input, LVTTL. See Table 1. 7 EQ3 Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1. 8, 16 GND Supply Ground 9, 12 VCC2 CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be AC-coupled. 10 SDO- Negative Serial Data Output, CML 11 SDO+ Positive Serial Data Output, CML 13, 14 N.C. No Connection. Leave unconnected. 15 VCC +3.3V Core Supply Voltage EP Exposed Pad Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance (see the Package and Layout Considerations section). Detailed Description General Theory of Operation The MAX3804’s low-noise linear input stage includes two amplifiers, one with flat-frequency response, and one with response that compensates for the loss characteristic of an FR-4 PC board transmission line. A current-steering network allows the designer to control the amount of equalization to match the path loss for specific applications. This network consists of a pair of variable attenuators feeding into a summing node. Equalization is set by a 3-bit LVTTL-compatible input (EQ3, EQ2, and EQ1). By employing fixed control of the equalization level, the MAX3804 provides optimal performance for a specific path loss. A high-speed limiting amplifier follows the equalizer circuitry to shape the output signal (see Figure 1). CML Input and Output Buffers The MAX3804 input and output CML buffers are terminated with 50Ω to VCC1 and VCC2, respectively. The equivalent circuit for the output is shown in Figure 2. Separate supply voltage connections are provided for the core (VCC), input (VCC1), and output (VCC2) circuitry to control noise coupling, and to allow DC-coupling to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs and outputs can also be AC-coupled. Use AC-coupling for single-ended cable applications. The unused CML input must be connected through an AC-coupling capacitor to a 50Ω termination. The low-frequency cutoff of the input-stage offset-cancellation circuit is nominally 21kHz. _______________________________________________________________________________________ 5 MAX3804 Pin Description MAX3804 12.5Gbps Settable Receive Equalizer VCC2 VCC1 FLATRESPONSE AMPLIFIER 50Ω VARIABLE ATTENUATOR 50Ω 50Ω SDI+ ∑ CML SDIBOOSTRESPONSE AMPLIFIER 50Ω SDO+ LIMITING AMP CML SDO- VARIABLE ATTENUATOR MAX3804 EQ1 EQ2 EQ3 DIGITALTO-ANALOG CONVERTER Figure 1. Functional Diagram Applications Information Equalizer Boost Level Control The MAX3804 equalizer is intended for use at the receive end of an FR-4 PC board transmission line, typically up to 30in of differential 6-mil stripline or microstrip. It is specifically designed to mitigate intersymbol interference caused by the frequencydependent path loss of FR-4 transmission lines. It can also be used with a variety of other transmission-line materials and geometries, including coaxial cable, or PC board paths that include well-engineered connectors. Table 1 shows the relationship between nominal 6-mil FR-4 transmission line length and equalization setting. VCC2 50Ω VCC 50Ω SDO+ MAX3804 ESD DIODES SDO- Supply Voltage Connections The CML input and output supplies (VCC1, VCC2) can be connected to +1.8V to +3.3V. VCC1 and VCC2 need not be connected to the same supply voltage; however, the core supply (VCC) must be connected to +3.3V. Package and Layout Considerations The MAX3804 is packaged in a 3mm x 3mm plasticencapsulated 16-lead thin QFN package. The package has an exposed pad that provides thermal and electrical connectivity to the IC and must be soldered to a high-frequency ground. Use good layout techniques for the SDI± and SDO± PC board transmission lines, and configure the trace geometry near the IC 6 Figure 2. Simplified Output Structure package to minimize impedance discontinuities. Power-supply decoupling capacitors should be as close as possible to the IC. _______________________________________________________________________________________ 12.5Gbps Settable Receive Equalizer GND VCC N.C. N.C. 16 15 14 13 EQ3 EQ2 EQ1 NOMINAL 6-mil FR-4 MICROSTRIP LENGTH (in) 0 0 0 2 VCC1 1 12 VCC2 0 0 1 6 SDI+ 2 11 SDO+ 10 SDI- 3 10 SDO- VCC1 4 9 VCC2 0 0 18 1 0 1 22 1 1 0 26 1 1 1 30 8 1 GND 14 7 1 EQ3 1 6 0 5 0 EQ2 1 EQ1 0 MAX3804 Thin QFN* (3mm x 3mm) *THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT BOARD GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE. Chip Information TRANSISTOR COUNT: 1007 PROCESS: SiGe bipolar _______________________________________________________________________________________ 7 MAX3804 Pin Configuration Table 1. Nominal 6-mil FR-4 Transmission Line Length and Equalization Settings Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12x16L QFN THIN.EPS MAX3804 12.5Gbps Settable Receive Equalizer D2 0.10 M C A B b D D2/2 D/2 E/2 E2/2 CL -A- (NE - 1) X e E E2 L -B- k e CL (ND - 1) X e CL CL 0.10 C 0.08 C A A2 A1 L L e e PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0136 8 _______________________________________________________________________________________ REV. C 1 2 12.5Gbps Settable Receive Equalizer EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0136 REV. C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3804 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)