ETC CPU16RM

Freescale Semiconductor, Inc.
M68HC16 Family
CPU16
Freescale Semiconductor, Inc...
Reference Manual
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TABLE OF CONTENTS
Paragraph
Title
Page
SECTION 1OVERVIEW
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SECTION 2NOTATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Register Notation ....................................................................................... 2-1
Condition Code Register Bits .................................................................... 2-2
Condition Code Register Activity ............................................................... 2-2
Condition Code Expressions ..................................................................... 2-2
Memory Addressing .................................................................................. 2-2
Addressing Modes ..................................................................................... 2-3
Instruction Format ..................................................................................... 2-3
Symbols and Operators ............................................................................. 2-4
Conventions .............................................................................................. 2-4
SECTION 3 SYSTEM RESOURCES
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.3.1
3.3.2
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
3.3.2.5
3.3.3
3.3.3.1
3.3.3.2
3.3.4
3.4
3.5
3.5.1
3.5.1.1
3.5.1.2
General ...................................................................................................... 3-1
Register Model .......................................................................................... 3-1
Accumulators ..................................................................................... 3-2
Index Registers ................................................................................. 3-3
Stack Pointer ..................................................................................... 3-3
Program Counter ............................................................................... 3-3
Condition Code Register ................................................................... 3-4
Address Extension Register and Address Extension Fields ............. 3-5
Multiply and Accumulate Registers ................................................... 3-5
Memory Management ............................................................................... 3-5
Address Extension ............................................................................ 3-5
Extension Fields ................................................................................ 3-6
Using Accumulator B to Modify Extension Fields ...................... 3-6
Using Stack Pointer Transfer to Modify Extension Fields ......... 3-6
Using Index Register Exchange to Modify Extension Fields ..... 3-6
Stacking Extension Field Values ............................................... 3-6
Adding Immediate Data to Registers ........................................ 3-7
Program Counter Address Extension ................................................ 3-7
Effect of Jump Instructions on PK : PC ..................................... 3-7
Effect of Branch Instructions on PK : PC .................................. 3-7
Effective Addresses and Extension Fields ........................................ 3-7
Intermodule Bus ........................................................................................ 3-8
External Bus Interface ............................................................................... 3-8
Bus Control Signals ........................................................................... 3-9
Function Codes ......................................................................... 3-9
Size Signals .............................................................................. 3-9
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3.5.1.3
3.5.2
3.5.3
3.5.4
3.5.5
3.5.5.1
3.5.5.2
3.5.5.3
Read/Write Signal ................................................................... 3-10
Address Bus .................................................................................... 3-10
Data Bus .......................................................................................... 3-10
Bus Cycle Termination Signals ....................................................... 3-10
Data Transfer Mechanism ............................................................... 3-11
Dynamic Bus Sizing ................................................................ 3-11
Operand Alignment ................................................................. 3-12
Misaligned Operands .............................................................. 3-13
SECTION 4 DATA TYPES AND ADDRESSING MODES
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
Data Types ................................................................................................ 4-1
Memory Organization ................................................................................ 4-2
Addressing Modes ..................................................................................... 4-3
Immediate Addressing Modes ........................................................... 4-4
Extended Addressing Modes ............................................................ 4-5
Indexed Addressing Modes ............................................................... 4-5
Inherent Addressing Mode ................................................................ 4-5
Accumulator Offset Addressing Mode ............................................... 4-5
Relative Addressing Modes ............................................................... 4-5
Post-Modified Index Addressing Mode .............................................. 4-5
Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode .... 4-6
SECTION 5 INSTRUCTION SET
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.4
5.5
General ...................................................................................................... 5-1
Data Movement Instructions ...................................................................... 5-1
Load Instructions ............................................................................... 5-1
Move Instructions .............................................................................. 5-2
Store Instructions .............................................................................. 5-2
Transfer Instructions .......................................................................... 5-2
Exchange Instructions ....................................................................... 5-3
Mathematic Instructions ............................................................................ 5-3
Addition and Subtraction Instructions ................................................ 5-3
Binary Coded Decimal Instructions ................................................... 5-5
Compare and Test Instructions ......................................................... 5-5
Multiplication and Division Instructions .............................................. 5-6
Decrement and Increment Instructions ............................................. 5-7
Clear, Complement, and Negate Instructions ................................... 5-7
Boolean Logic Instructions ................................................................ 5-8
Bit Test and Manipulation Instructions ...................................................... 5-8
Shift and Rotate Instructions ..................................................................... 5-8
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5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.7
5.7.1
5.7.2
5.8
5.9
5.10
5.11
5.12
5.13
Program Control Instructions ................................................................... 5-11
Short Branch Instructions ................................................................ 5-12
Long Branch Instructions ................................................................. 5-13
Bit Condition Branch Instructions .................................................... 5-15
Jump Instruction .............................................................................. 5-16
Subroutine Instructions .................................................................... 5-16
Interrupt Instructions ........................................................................ 5-17
Indexing and Address Extension Instructions ......................................... 5-18
Indexing Instructions ....................................................................... 5-18
Address Extension Instructions ....................................................... 5-19
Stacking Instructions ............................................................................... 5-20
Condition Code Instructions .................................................................... 5-21
Digital Signal Processing Instructions ..................................................... 5-21
Stop and Wait Instructions ...................................................................... 5-22
Background Mode and Null Operations .................................................. 5-23
Comparison of CPU16 and M68HC11 Instruction Sets .......................... 5-23
SECTION 6 INSTRUCTION GLOSSARY
6.1
6.2
6.3
6.4
Assembler Syntax ..................................................................................... 6-1
Instructions ................................................................................................ 6-1
Condition Code Evaluation .................................................................... 6-265
Instruction Set Summary ....................................................................... 6-270
SECTION 7 INSTRUCTION PROCESS
7.1
Instruction Format ..................................................................................... 7-1
7.2
Execution Model ........................................................................................ 7-2
7.2.1
Microsequencer ................................................................................. 7-3
7.2.2
Instruction Pipeline ............................................................................ 7-3
7.2.3
Execution Unit ................................................................................... 7-3
7.3
Execution Process ..................................................................................... 7-4
7.3.1
Detailed Process ............................................................................... 7-4
7.3.2
Changes in Program Flow ................................................................. 7-5
7.3.2.1
Jumps ........................................................................................ 7-6
7.3.2.2
Branches ................................................................................... 7-6
7.3.2.3
Subroutines ............................................................................... 7-6
7.3.2.4
Interrupts ................................................................................... 7-7
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SECTION 8 INSTRUCTION TIMING
8.2
8.2.1
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.2.4
8.2.2.5
8.2.2.6
8.2.2.7
8.3
8.4
8.5
8.5.1
8.5.1.1
8.5.1.2
8.5.1.3
8.5.2
8.5.2.1
8.5.2.2
8.5.2.3
8.5.3
8.5.3.1
8.5.3.2
Program and Operand Access Time ......................................................... 8-2
Program Accesses ............................................................................ 8-2
Operand Accesses ............................................................................ 8-2
Regular Instructions .................................................................. 8-2
Read-Modify-Write Instructions ................................................. 8-2
Change-of-Flow Instructions ..................................................... 8-3
Stack Manipulation Instructions ................................................ 8-4
Stop and Wait Instructions ........................................................ 8-4
Move Instructions ...................................................................... 8-4
Multiply and Accumulate Instructions ........................................ 8-5
Internal Operation Time ............................................................................. 8-5
Calculating Execution Times for Slower Accesses ................................... 8-5
Examples ................................................................................................... 8-6
LDD (Load D) Instruction ................................................................... 8-6
LDD IND8, X ............................................................................. 8-6
LDD IND8, X ............................................................................. 8-6
LDD IND8, X ............................................................................. 8-6
NEG (Negate) Instruction .................................................................. 8-7
NEG EXT .................................................................................. 8-7
NEG EXT .................................................................................. 8-7
NEG EXT .................................................................................. 8-7
STED (Store Accumulators E and D) Instruction .............................. 8-8
STED EXT ................................................................................. 8-8
STED EXT ................................................................................. 8-8
SECTION 9 EXCEPTION PROCESSING
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.7.1
9.7.1.1
9.7.1.2
9.7.1.3
9.7.1.4
9.7.2
Definition of Exception ............................................................................... 9-1
Exception Vectors ..................................................................................... 9-1
Types of Exceptions .................................................................................. 9-2
Exception Stack Frame ............................................................................. 9-2
Exception Processing Sequence ............................................................... 9-3
Multiple Exceptions ................................................................................... 9-8
Processing of Specific Exceptions ............................................................ 9-9
Asynchronous Exceptions ................................................................. 9-9
Processor Reset (RESET) ........................................................ 9-9
Bus Error (BERR) .................................................................... 9-11
Breakpoint Exception (BKPT) ................................................. 9-12
Interrupts ................................................................................. 9-13
Synchronous Exceptions ................................................................. 9-14
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9.7.2.1
Illegal Instructions ................................................................... 9-14
9.7.2.2
Division By Zero ...................................................................... 9-15
9.7.2.3
BGND Instruction .................................................................... 9-15
9.7.2.4
SWI Instruction ........................................................................ 9-15
9.8
Return from Interrupt (RTI) ...................................................................... 9-15
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SECTION 10 DEVELOPMENT SUPPORT
10.1
Deterministic Opcode Tracking ............................................................... 10-1
10.1.1
Instruction Pipeline .......................................................................... 10-1
10.1.2
IPIPE0/IPIPE1 Multiplexing ............................................................. 10-2
10.1.3
Pipeline State Signals ..................................................................... 10-3
10.1.3.1
NULL — No Instruction Pipeline Activity ................................. 10-3
10.1.3.2
START — Instruction Start ...................................................... 10-3
10.1.3.3
ADVANCE — Instruction Pipeline Advance ............................ 10-4
10.1.3.4
FETCH — Instruction Fetch .................................................... 10-4
10.1.3.5
EXCEPTION — Exception Processing in Progress ................ 10-4
10.1.3.6
INVALID — PHASE1/PHASE2 Signal Invalid ......................... 10-4
10.1.4
Combining Opcode Tracking with Other Capabilities ...................... 10-5
10.1.5
CPU16 Instruction Pipeline State Signal Flow ................................ 10-5
10.2
Breakpoints ............................................................................................. 10-5
10.3
Opcode Tracking and Breakpoints .......................................................... 10-8
10.4
Background Debugging Mode (BDM) ..................................................... 10-8
10.4.1
Enabling BDM ............................................................................... 10-10
10.4.2
BDM Sources ................................................................................ 10-11
10.4.2.1
BKPT Signal .......................................................................... 10-11
10.4.2.2
BGND Instruction .................................................................. 10-11
10.4.2.3
Microcontroller Module Breakpoints ...................................... 10-11
10.4.2.4
Double Bus Fault ................................................................... 10-11
10.4.3
BDM Signals .................................................................................. 10-11
10.4.4
Entering BDM ................................................................................ 10-12
10.4.5
Command Execution ..................................................................... 10-12
10.4.6
Returning from BDM ...................................................................... 10-13
10.4.7
BDM Serial Interface ..................................................................... 10-13
10.4.7.1
CPU Serial Logic ................................................................... 10-15
10.4.7.2
Development System Serial Logic ........................................ 10-16
10.4.8
BDM Command Format ................................................................ 10-18
10.4.9
Command Sequence Diagram ...................................................... 10-18
10.4.10
BDM Command Set ...................................................................... 10-20
10.4.10.1
BDM Memory Commands and Bus Errors ............................ 10-20
10.4.11
Future Commands ......................................................................... 10-37
10.4.12
Recommended BDM Connection .................................................. 10-37
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SECTION 11 DIGITAL SIGNAL PROCESSING
11.1
General .................................................................................................... 11-1
11.2
Digital Signal Processing Hardware ........................................................ 11-1
11.3
Modulo Addressing .................................................................................. 11-2
11.4
MAC Data Types ..................................................................................... 11-2
11.5
MAC Accumulator Overflow .................................................................... 11-3
11.5.1
Extension Bit Overflow .................................................................... 11-4
11.5.2
Sign Bit Overflow ............................................................................. 11-4
11.6
Data Saturation ....................................................................................... 11-5
11.7
DSP Instructions ...................................................................................... 11-5
11.7.1
Initialization Instructions .................................................................. 11-5
11.7.1.1
LDHI — Load Registers H and I .............................................. 11-5
11.7.1.2
TDMSK — Transfer D to XMSK:YMSK ................................... 11-5
11.7.1.3
TEDM — Transfer E and D to AM ........................................... 11-5
11.7.1.4
TEM — Transfer E to AM ........................................................ 11-6
11.7.2
Transfer Instructions ........................................................................ 11-6
11.7.2.1
TMER — Transfer AM to E Rounded ...................................... 11-6
11.7.2.2
TMET — Transfer AM to E Truncated .................................... 11-6
11.7.2.3
TMXED — Transfer AM to IX : E : D ....................................... 11-6
11.7.2.4
LDED/STED — Long Word Load and Store Instructions ........ 11-7
11.7.3
Multiplication and Accumulation Instructions ................................... 11-7
11.7.3.1
MAC — Multiply and Accumulate ............................................ 11-7
11.7.3.2
RMAC — Repeating Multiply and Accumulate ........................ 11-7
11.7.3.3
FMULS — Signed Fractional Multiply ..................................... 11-8
11.7.3.4
ACED — Add E: D to AM ........................................................ 11-8
11.7.3.5
ACE — Add E to AM ............................................................... 11-9
11.7.4
Bit Manipulation Instructions ........................................................... 11-9
11.7.4.1
ASLM — Arithmetic Shift Left AM ........................................... 11-9
11.7.4.2
ASRM — Arithmetic Shift Right AM ........................................ 11-9
11.7.4.3
CLRM — Clear AM ................................................................. 11-9
11.7.5
Stacking Instructions ..................................................................... 11-10
11.7.5.1
PSHMAC — Push MAC Registers ........................................ 11-10
11.7.5.2
PULMAC — Pull MAC Registers .......................................... 11-10
11.7.6
Branch Instructions ........................................................................ 11-10
11.7.6.1
LBEV — Long Branch if EV Set ............................................ 11-10
11.7.6.2
LBMV — Long Branch if MV Set ........................................... 11-11
APPENDIX A COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY LANGUAGE
A.1
A.2
Introduction ............................................................................................... A-1
Register Models ....................................................................................... A-2
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A.3
CPU16 Instruction Formats and Pipelining Mechanism ........................... A-4
A.3.1
Instruction Format ............................................................................ A-4
A.3.2
Execution Model ............................................................................... A-4
A.3.2.1
Microsequencer ........................................................................ A-4
A.3.2.2
Instruction Pipeline ................................................................... A-4
A.3.2.3
Execution Unit .......................................................................... A-5
A.3.3
Execution Process ............................................................................ A-5
A.3.4
Changes in Program Flow ................................................................ A-5
A.3.4.1
Jumps ....................................................................................... A-5
A.3.4.2
Branches .................................................................................. A-5
A.3.4.3
Subroutines .............................................................................. A-6
A.3.4.4
Interrupts .................................................................................. A-6
A.3.4.5
Interrupt Priority ........................................................................ A-7
A.3.5
Stack Frame ..................................................................................... A-7
A.4
Functionally Equivalent Instructions ......................................................... A-7
A.4.1
BHS .................................................................................................. A-7
A.4.2
BLO .................................................................................................. A-7
A.4.3
CLC .................................................................................................. A-7
A.4.4
CLI .................................................................................................... A-8
A.4.6
DES .................................................................................................. A-8
A.4.7
DEX .................................................................................................. A-8
A.4.8
DEY .................................................................................................. A-9
A.4.9
INS ................................................................................................... A-9
A.4.10
INX ................................................................................................... A-9
A.4.11
INY ................................................................................................... A-9
A.4.12
PSHX ................................................................................................ A-9
A.4.13
PSHY .............................................................................................. A-10
A.4.14
PULX .............................................................................................. A-10
A.4.15
PULY .............................................................................................. A-10
A.4.16
SEC ................................................................................................ A-10
A.4.17
SEI .................................................................................................. A-11
A.4.18
SEV ................................................................................................ A-11
A.4.19
STOP (LPSTOP) ............................................................................ A-11
A.5
Instructions that Operate Differently ....................................................... A-11
A.5.1
BSR ................................................................................................ A-11
A.5.2
JSR ................................................................................................. A-11
A.5.3
PSHA, PSHB .................................................................................. A-12
A.5.4
PULA, PULB ................................................................................... A-12
A.5.5
RTI .................................................................................................. A-12
A.5.6
SWI ................................................................................................ A-12
A.5.7
TAP ............................................................................................... A-12
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A.5.7.1
M68HC11 CPU Implementation: ........................................... A-12
A.5.7.2
CPU16 Implementation: ........................................................ A-12
A.5.8
TPA ............................................................................................... A-13
A.5.8.1
M68HC11 CPU Implementation: ........................................... A-13
A.5.8.2
CPU16 Implementation: ........................................................ A-13
A.5.9
WAI ................................................................................................. A-13
A.6
Instructions With Transparent Changes ................................................. A-13
A.6.1
RTS ................................................................................................ A-13
A.6.2
TSX ................................................................................................ A-13
A.6.3
TSY ................................................................................................ A-13
A.6.4
TXS ................................................................................................ A-14
A.6.5
TYS ................................................................................................ A-14
A.7
Unimplemented Instructions ................................................................... A-14
A.7.1
TEST .............................................................................................. A-14
A.8
Addressing Mode Differences ................................................................ A-14
A.8.1
Extended Addressing Mode ........................................................... A-14
A.8.2
Indexed Addressing Mode .............................................................. A-14
A.8.3
Post-Modified Index Addressing Mode ........................................... A-14
A.8.4
CPU16 Indexed Mode to Replace M68HC11 CPU Direct Mode .... A-14
APPENDIX B MOTOROLA ASSEMBLER SYNTAX
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LIST OF ILLUSTRATIONS
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Figure
3-1
3-2
3-3
4-1
6-1
7-1
9-1
9-2
9-2
9-2
9-2
9-2
9-3
10-1
10-2
10-3
10-3
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
11-1
11-2
A-1
A-2
A-3
A-4
A-5
Title
Page
CPU16 Register Model ................................................................................... 3-2
Condition Code Register ................................................................................ 3-4
Operand Byte Order ..................................................................................... 3-12
Data Types and Memory Organization ........................................................... 4-3
Typical Instruction Glossary Entry .................................................................. 6-2
Instruction Execution Model ........................................................................... 7-3
Exception Stack Frame Format ...................................................................... 9-2
(Sheet 1 of 5) Exception Processing Flow Diagram ....................................... 9-4
(Sheet 2 of 5) Exception Processing Flow Diagram ....................................... 9-5
(Sheet 3 of 5) Exception Processing Flow Diagram ....................................... 9-6
(Sheet 4 of 5) Exception Processing Flow Diagram ....................................... 9-7
(Sheet 5 of 5) Exception Processing Flow Diagram ....................................... 9-8
RESET Vector ................................................................................................ 9-9
Instruction Execution Model ......................................................................... 10-2
IPIPE DEMUX Logic ..................................................................................... 10-3
(Sheet 1 of 3) Instruction Pipeline Flow ........................................................ 10-6
(Sheet 2 of 3) Instruction Pipeline Flow ........................................................ 10-7
(Sheet 3 of 3) Instruction Pipeline Flow ........................................................ 10-8
In-Circuit Emulator Configuration ................................................................. 10-9
Bus State Analyzer Configuration ................................................................ 10-9
Sample BDM Enable Circuit ....................................................................... 10-10
BDM Enable Waveforms ............................................................................ 10-10
BDM Command Flow Diagram ................................................................... 10-13
BDM Serial I/O Block Diagram ................................................................... 10-14
Serial Data Word Format ............................................................................ 10-14
Serial Interface Timing Diagram ................................................................. 10-16
BKPT Timing for Single Bus Cycle ............................................................. 10-17
BKPT Timing for Forcing BDM ................................................................... 10-17
BKPT/DSCLK Logic Diagram ..................................................................... 10-18
Command Sequence Diagram Example .................................................... 10-19
BDM Connector Pinout ............................................................................... 10-37
MAC Unit Register Model ............................................................................. 11-2
MAC Data Types .......................................................................................... 11-3
M68HC11 CPU Registers .............................................................................. A-2
M68HC11 CPU Condition Code Register ...................................................... A-2
CPU16 Registers ............................................................................................ A-3
CPU16 Condition Code Register .................................................................... A-3
CPU16 Stack Frame Format .......................................................................... A-7
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LIST OF ILLUSTRATIONS
(Continued)
Title
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LIST OF TABLES
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Table
3-1
3-2
3-3
3-4
3-5
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
6-1
6-2
Title
Page
Operations that Cross Bank Boundaries ......................................................... 3-8
Address Space Encoding ................................................................................ 3-9
Size Signal Encoding ...................................................................................... 3-9
Effect of DSACK Signals ............................................................................... 3-11
Operand Alignment ....................................................................................... 3-12
Addressing Modes........................................................................................... 4-4
Load Summary ................................................................................................ 5-2
Move Summary ............................................................................................... 5-2
Store Summary ............................................................................................... 5-2
Transfer Summary........................................................................................... 5-3
Exchange Summary ........................................................................................ 5-3
Addition Summary ........................................................................................... 5-3
Subtraction Summary...................................................................................... 5-4
Arithmetic Operations...................................................................................... 5-4
BCD Summary ................................................................................................ 5-5
DAA Function Summary.................................................................................. 5-5
Compare and Test Summary .......................................................................... 5-6
Multiplication and Division Summary............................................................... 5-6
Decrement and Increment Summary .............................................................. 5-7
Clear, Complement, and Negate Summary .................................................... 5-7
Boolean Logic Summary ................................................................................. 5-8
Bit Test and Manipulation Summary ............................................................... 5-8
Logic Shift Summary ....................................................................................... 5-9
Arithmetic Shift Summary.............................................................................. 5-10
Rotate Summary ........................................................................................... 5-11
Short Branch Summary ................................................................................. 5-12
Long Branch Instructions............................................................................... 5-14
Bit Condition Branch Summary ..................................................................... 5-15
Jump Summary ............................................................................................. 5-16
Subroutine Summary..................................................................................... 5-16
Interrupt Summary......................................................................................... 5-17
Indexing Summary ........................................................................................ 5-18
Address Extension Summary ........................................................................ 5-19
Stacking Summary ........................................................................................ 5-20
Condition Code Summary ............................................................................. 5-21
DSP Summary............................................................................................... 5-21
Stop and Wait Summary ............................................................................... 5-23
Background Mode and Null Operations ........................................................ 5-23
CPU16 Implementation of M68HC11 Instructions......................................... 5-24
Standard Assembler Formats.......................................................................... 6-1
Branch Instruction Summary (8-Bit Offset).................................................... 6-47
CPU16
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Table
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
7-1
7-2
7-3
7-4
7-5
8-1
8-2
Page
Branch Instruction Summary (8-Bit Offset).................................................... 6-50
Branch Instruction Summary (8-Bit Offset).................................................... 6-51
Branch Instruction Summary (8-Bit Offset).................................................... 6-52
Branch Instruction Summary (8-Bit Offset).................................................... 6-54
Branch Instruction Summary (8-Bit Offset).................................................... 6-55
Branch Instruction Summary (8-Bit Offset).................................................... 6-58
Branch Instruction Summary (8-Bit Offset).................................................... 6-59
Branch Instruction Summary (8-Bit Offset).................................................... 6-60
Branch Instruction Summary (8-Bit Offset).................................................... 6-61
Branch Instruction Summary (8-Bit Offset).................................................... 6-62
Branch Instruction Summary (8-Bit Offset).................................................... 6-63
Branch Instruction Summary (8-Bit Offset).................................................... 6-64
Branch Instruction Summary (8-Bit Offset).................................................... 6-66
Branch Instruction Summary (8-Bit Offset).................................................... 6-71
Branch Instruction Summary (8-Bit Offset).................................................... 6-72
DAA Function Summary................................................................................ 6-96
Branch Instruction Summary (16-Bit Offset)................................................ 6-118
Branch Instruction Summary (16-Bit Offset)................................................ 6-119
Branch Instruction Summary (16-Bit Offset)................................................ 6-120
Branch Instruction Summary (16-Bit Offset)................................................ 6-122
Branch Instruction Summary (16-Bit Offset)................................................ 6-123
Branch Instruction Summary (16-Bit Offset)................................................ 6-124
Branch Instruction Summary (16-Bit Offset)................................................ 6-125
Branch Instruction Summary (16-Bit Offset)................................................ 6-126
Branch Instruction Summary (16-Bit Offset)................................................ 6-127
Branch Instruction Summary (16-Bit Offset)................................................ 6-128
Branch Instruction Summary (16-Bit Offset)................................................ 6-130
Branch Instruction Summary (16-Bit Offset)................................................ 6-131
Branch Instruction Summary (16-Bit Offset)................................................ 6-132
Branch Instruction Summary (16-Bit Offset)................................................ 6-133
Branch Instruction Summary (16-Bit Offset)................................................ 6-135
Branch Instruction Summary (16-Bit Offset)................................................ 6-136
Condition Code Evaluation.......................................................................... 6-265
Instruction Set Summary ............................................................................. 6-270
Basic Instruction Formats................................................................................ 7-2
Page 0 Opcodes.............................................................................................. 7-8
Page 1 Opcodes............................................................................................ 7-11
Page 2 Opcodes............................................................................................ 7-14
Page 3 Opcodes............................................................................................ 7-17
Access Bus Cycles.......................................................................................... 8-2
Change-of-Flow Instruction Timing ................................................................. 8-3
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Title
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Table
8-3
8-4
8-5
8-6
9-1
10-1
10-2
10-3
10-4
10-5
11-1
11-2
A-1
Page
Stack Manipulation Timing .............................................................................. 8-4
Stop and Wait Timing ...................................................................................... 8-4
Move Timing.................................................................................................... 8-4
MAC Timing..................................................................................................... 8-5
Exception Vector Table ................................................................................... 9-2
IPIPE0/IPIPE1 Encoding ............................................................................... 10-2
BDM Source Summary................................................................................ 10-11
BDM Signals................................................................................................ 10-12
CPU Generated Message Encoding ........................................................... 10-15
Command Summary ................................................................................... 10-20
AM Values and Effect on EV ......................................................................... 11-4
Saturation Values .......................................................................................... 11-5
M68HC16 Implementation of M68HC11 Instructions .................................... A-15
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Table
LIST OF TABLES
(Continued)
Title
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SECTION 1OVERVIEW
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The CPU16 is a high-speed 16-bit central processing unit used in the M68HC16 family
of modular microcontrollers. The CPU16 uses a prefetch mechanism and a three-instruction pipeline to reduce instruction execution time. The CPU16 instruction set has
been optimized for high performance and high-level language support. Program diagnosis is enhanced by a background debugging mode.
The CPU16 has two 16-bit general-purpose accumulators and three 16-bit index registers. It supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and store operations, as well as 16-bit and 32-bit signed fractional operations.
CPU16 memory space includes a 1 Mbyte data space and a 1 Mbyte program space.
Twenty-bit addressing and transparent bank switching are used to implement extended memory. In addition, most instructions automatically handle bank boundaries.
The CPU16 provides M68HC11 users a migration path to higher performance. CPU16
architecture is a superset of M68HC11 CPU architecture — all M68HC11 CPU resources are available in the CPU16. The CPU16 and M68HC11 CPU instruction sets
are source code compatible. M68HC11 CPU instructions are either directly implemented in the CPU16 instruction set, or have been replaced by equivalent instructions.
The CPU16 includes instructions and hardware to implement control-oriented digital
signal processing functions with a minimum of interfacing. A multiply and accumulate
unit provides the capability to multiply signed 16-bit fractional numbers and store the
resulting 32-bit fixed point product in a 36-bit accumulator. Modulo addressing supports finite impulse response filters.
Documentation for the M68HC16 family follows the modular design concept. There is
a comprehensive user's manual for each device in the product line, and a detailed reference manual for each of the individual on-chip modules.
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SECTION 2NOTATION
The following notation, symbols, and conventions are used throughout the manual.
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2.1 Register Notation
A
AM
B
CCR
D
E
EK
IR
HR
IX
IY
IZ
K
PC
PK
SK
SL
SP
XK
YK
ZK
XMSK
YMSK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Accumulator A
Accumulator M
Accumulator B
Condition code register
Accumulator D
Accumulator E
Extended addressing extension field
Multiply and accumulate multiplicand register
Multiply and accumulate multiplier register
Index register X
Index register Y
Index register Z
Address extension register
Program counter
Program counter extension field
Stack pointer extension field
Multiply and accumulate sign latch
Stack pointer
Index register X extension field
Index register Y extension field
Index register Z extension field
Modulo addressing index register X mask
Modulo addressing index register Y mask
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2.2 Condition Code Register Bits
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
—
—
—
—
—
—
Stop disable control bit
AM overflow indicator
Half carry indicator
AM extended overflow indicator
Negative indicator
Zero indicator
Two’s complement overflow indicator
Carry/borrow indicator
Interrupt priority field
Saturation mode control bit
Program counter extension field
2.3 Condition Code Register Activity
—
∆
0
1
—
—
—
—
Bit not affected
Bit changes according to specified conditions
Bit cleared
Bit set
2.4 Condition Code Expressions
M
R
S
X
—
—
—
—
Memory location used in operation
Result of operation
Source data
Register used in operation
2.5 Memory Addressing
M
M+1
M:M+1
(...)X
(...)Y
(...)Z
—
—
—
—
—
—
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Address of one memory byte
Address of byte at M + $0001
Address of one memory word
Contents of address pointed to by IX
Contents of address pointed to by IY
Contents of address pointed to by IZ
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2.6 Addressing Modes
E, X
E, Y
E, Z
EXT
EXT20
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
IND20, X
IND20, Y
IND20, Z
INH
IXP
REL8
REL16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IX with E offset
IY with E offset
IZ with E offset
Extended
20-bit extended
8-bit immediate
16-bit immediate
IX with unsigned 8-bit offset
IY with unsigned 8-bit offset
IZ with unsigned 8-bit offset
IX with signed 16-bit offset
IY with signed 16-bit offset
IZ with signed 16-bit offset
IX with signed 20-bit offset
IY with signed 20-bit offset
IZ with signed 20-bit offset
Inherent
Post-modified indexed
8-bit relative
16-bit relative
2.7 Instruction Format
b
ii
jj
kk
hh
ll
gggg
ff
mm
mmmm
rr
rrrr
xo
yo
z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4-bit address extension
8-bit immediate data sign-extended to 16 bits
High-order byte of 16-bit immediate data
Low-order byte of 16-bit immediate data
High-order byte of 16-bit extended address
Low-order byte of 16-bit extended address
16-bit signed offset
8-bit unsigned offset
8-bit mask
16-bit mask
8-bit unsigned relative offset
16-bit signed relative offset
MAC index register X offset
MAC index register Y offset
4-bit zero extension
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2.8 Symbols and Operators
+
*
/
>
<
=
≥
≤
≠
•
;
⊕
NOT
:
⇒
⇔
±
«
%
$
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addition
Subtraction or negation (twos complement)
Multiplication
Division
Greater
Less
Equal
Equal or greater
Equal or less
Not equal
AND
Inclusive OR (OR)
Exclusive OR (EOR)
Complementation
Concatenation
Transferred
Exchanged
Sign bit; also used to show tolerance
Sign extension
Binary value
Hexadecimal value
2.9 Conventions
Logic level one is the voltage that corresponds to Boolean true (1) state.
Logic level zero is the voltage that corresponds to Boolean false (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
Cleared refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.
ADDR is the mnemonic for address bus. DATA is the mnemonic for data bus.
LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out.
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LSW means least significant word or words. MSW means most significant word or
words.
A specific mnemonic within a range is referred to by mnemonic and number. A35 is
bit 35 of accumulator A; ADDR[7:0] form the low byte of the address bus. A range of
mnemonics is referred to by mnemonic and the numbers that define the range.
AM[35:30] are bits 35 to 30 of accumulator M; DATA[15:8] form the high byte of the
data bus.
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Parentheses are used to indicate the content of a register or memory location, rather
than the register or memory location itself. (A) is the content of accumulator A. (M : M
+ 1) is the content of the word at address M.
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SECTION 3 SYSTEM RESOURCES
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This section provides information concerning CPU16 register organization, memory
management, and bus interfacing. The CPU16 is a subcomponent of a modular microcontroller. Due to the diversity of modular microcontrollers, detailed information concerning interaction with other modules and external devices is contained in the
microcontroller user's manual.
3.1 General
The CPU16 was designed to provide compatibility with the M68HC11 and to provide
additional capabilities associated with 16- and 32-bit data sizes, 20-bit addressing,
and digital signal processing. CPU16 registers are an integral part of the CPU and are
not addressed as memory locations. The CPU16 register model contains all the resources of the M68HC11, plus additional resources.
The CPU16 treats all peripheral, I/O, and memory locations as parts of a pseudolinear
1 Megabyte address space. There are no special instructions for I/O that are separate
from instructions for addressing memory. Address space is made up of 16 64-Kbyte
banks. Specialized bank addressing techniques and support registers provide transparent access across bank boundaries.
The CPU16 interacts with external devices and with other modules within the microcontroller via a standardized bus and bus interface. There are bus protocols for memory and peripheral accesses, as well as for managing an hierarchy of interrupt
priorities.
3.2 Register Model
Figure 3-1 shows the CPU16 register model. Registers are discussed in detail in the
following paragraphs.
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20
16 15
8 7
0 BIT POSITION
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A
D
B
ACCUMULATORS A AND B
ACCUMULATOR D (A : B)
E
ACCUMULATOR E
XK
IX
INDEX REGISTER X
YK
IY
INDEX REGISTER Y
ZK
IZ
INDEX REGISTER Z
SK
SP
STACK POINTER
PK
PC
PROGRAM COUNTER
CCR
EK
XK
XMSK
YK
PK
CONDITION CODE REGISTER/
PC EXTENSION REGISTER
ZK
ADDRESS EXTENSION REGISTER
SK
STACK EXTENSION REGISTER
HR
MAC MULTIPLIER REGISTER
IR
MAC MULTIPLICAND REGISTER
AM
AM
MAC ACCUMULATOR MSB [35:16]
MAC ACCUMULATOR LSB [15:0]
YMSK
MAC XY MASK REGISTER
Figure 3-1 CPU16 Register Model
3.2.1 Accumulators
The CPU16 has two 8-bit accumulators (A and B) and one 16-bit accumulator (E). In
addition, accumulators A and B can be concatenated into a second 16-bit “double” accumulator (D).
Accumulators A, B, and D are general-purpose registers used to hold operands and
results during mathematic and data manipulation operations.
Accumulator E can be used in the same way as accumulator D, and also extends
CPU16 capabilities. It allows more data to be held within the CPU16 during operations,
simplifies 32-bit arithmetic and digital signal processing, and provides a practical 16bit accumulator offset indexed addressing mode.
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The CPU16 accumulators can perform the same operations as M68HC11 accumulators of the same names, but the CPU16 instruction set provides additional 8-bit, 16bit, and 32-bit accumulator operations. See SECTION 5 INSTRUCTION SET for more
information.
3.2.2 Index Registers
The CPU16 has three 16-bit index registers (IX, IY, and IZ). Each index register has
an associated 4-bit extension field (XK, YK, and ZK).
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Concatenated registers and extension fields provide 20-bit indexed addressing and
support data structure functions anywhere in the CPU16 address space.
IX and IY can perform the same operations as M68HC11 registers of the same names,
but the CPU16 instruction set provides additional indexed operations.
IZ can perform the same operations as IX and IY, and also provides an additional indexed addressing capability that replaces M68HC11 direct addressing mode. Initial IZ
and ZK extension field values are included in the RESET exception vector, so that ZK
: IZ can be used as a direct page pointer out of reset. See SECTION 4 DATA TYPES
AND ADDRESSING MODES and SECTION 9 EXCEPTION PROCESSING for more
information.
3.2.3 Stack Pointer
The CPU16 stack pointer (SP) is 16 bits wide. An associated 4-bit extension field (SK)
provides 20-bit stack addressing.
Stack implementation in the CPU16 is from high to low memory. The stack grows
downward as it is filled. SK : SP are decremented each time data is pushed on the
stack, and incremented each time data is pulled from the stack.
SK : SP point to the next available stack address, rather than to the address of the latest stack entry. Although the stack pointer is normally incremented or decremented by
word address, it is possible to push and pull byte-sized data; however, setting the
stack pointer to an odd value causes misalignment, which affects performance. See
SECTION 4 DATA TYPES AND ADDRESSING MODES and SECTION 5 INSTRUCTION SET for more information.
3.2.4 Program Counter
The CPU16 program counter (PC) is 16 bits wide. An associated 4-bit extension field
(PK) provides 20-bit program addressing.
CPU16 instructions are fetched from even word boundaries. Bit 0 of the PC always has
a value of zero, to assure that instruction fetches are made from word-aligned addresses. See SECTION 7 INSTRUCTION PROCESS for more information.
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3.2.5 Condition Code Register
The 16-bit condition code register can be divided into two functional blocks. The eight
MSB, which correspond to the CCR in the M68HC11, contain the low-power stop control bit and processor status flags. The eight LSB contain the interrupt priority field, the
DSP saturation mode control bit, and the program counter address extension field.
Management of interrupt priority in the CPU16 differs considerably from that of the
M68HC11. See SECTION 9 EXCEPTION PROCESSING for complete information.
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Figure 3-2 shows the condition code register. Detailed descriptions of each status indicator and field in the register follow the figure.
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
7
6
5
IP
4
3
SM
2
1
0
PK
Figure 3-2 Condition Code Register
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed
1 = Perform NOP when LPSTOP instruction is executed
MV — Accumulator M Overflow Flag
Set when overflow into AM35 has occurred.
H — Half Carry Flag
Set when a carry from bit 3 in A or B occurs during BCD addition.
EV — Extension Bit Overflow Flag
Set when an overflow into AM31 has occurred.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when two’s complement overflow occurs as the result of an operation.
C — Carry Flag
Set when carry or borrow occurs during arithmetic operation. Also used during shift
and rotate to facilitate multiple word operations.
IP[2:0] — Interrupt Priority Field
The priority value in this field (0 to 7) is used to mask interrupts.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from AM using TMER or TMET
will be given maximum positive or negative value, depending on the state of the AM
sign bit before overflow.
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PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit address.
3.2.6 Address Extension Register and Address Extension Fields
There are six 4-bit address extension fields. EK, XK, YK, and ZK are contained by the
address extension register, PK is part of the CCR, and SK stands alone.
Extension fields are the bank portions of 20-bit concatenated bank : byte addresses
used in the CPU16 pseudolinear memory management scheme.
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All extension fields except EK correspond directly to a register. XK, YK, and ZK extend
registers IX, IY, and IZ; PK extends the PC; and SK extends the SP. EK holds the four
MSB of the 20-bit address used by extended addressing mode.
The function of extension fields is discussed in 3.3 Memory Management.
3.2.7 Multiply and Accumulate Registers
The multiply and accumulate (MAC) registers are part of a CPU submodule that performs repetitive signed fractional multiplication and stores the cumulative result. These
operations are part of control-oriented digital signal processing.
There are four MAC registers. Register H contains the 16-bit signed fractional multiplier. Register I contains the 16-bit signed fractional multiplicand. Accumulator M is a
specialized 36-bit product accumulation register. XMSK and YMSK contain 8-bit mask
values used in modulo addressing.
The CPU16 has a special subset of signal processing instructions that manipulate the
MAC registers and perform signal processing calculation. See SECTION 5 INSTRUCTION SET and SECTION 11 DIGITAL SIGNAL PROCESSING for more information.
3.3 Memory Management
The CPU16 uses bank switching to provide a 1 Megabyte address space. There are
16 banks within the address space. Each bank is made up of 64 Kbytes addressed
from $0000 to $FFFF. Banks are selected by means of address extension fields associated with individual CPU16 registers.
In addition, address space can be split into discrete 1 Megabyte program and data
spaces by externally decoding the outputs described in 3.5.1.1 Function Codes.
When this technique is used, instruction fetches and RESET vector fetches access
program space, while exception vector fetches (other than RESET), data accesses,
and stack accesses are made in data space.
3.3.1 Address Extension
All CPU16 resources that are used to generate addresses are effectively 20 bits wide.
These resources include extended index registers, program counter, and stack pointer. All addressing modes use 20-bit addresses.
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Twenty-bit addresses are formed from a 16-bit byte address generated by an individual CPU16 register and a 4-bit bank address contained in an associated extension
field. The byte address corresponds to ADDR[15:0] and the bank address corresponds to ADDR[19:16].
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3.3.2 Extension Fields
The six address extension fields are each used in a different type of access. As shown
in 3.2 Register Model, all but EK are associated with particular CPU16 registers.
There are a number of ways to manipulate extension fields and the address map.
3.3.2.1 Using Accumulator B to Modify Extension Fields
EK, XK, YK, ZK, and SK can be examined and modified by using the transfer extension field to B and transfer B to extension field instructions.
Transfer extension field to B instructions (TEKB, TXKB, TYKB, TZKB, and TSKB) copy
the designated extension field into the four LSB of accumulator B, where it can be
modified. Transfer B to extension field instructions (TBEK, TBXK, TBYK, TBZK, and
TBSK) replace the designated extension field with the contents of the four LSB of accumulator B.
3.3.2.2 Using Stack Pointer Transfer to Modify Extension Fields
XK, YK, ZK, and SK can be modified by using the transfer index register to stack pointer and transfer stack pointer to index register instructions.
When the SP is transferred to (TSX, TSY, and TSZ) or from (TXS, TYS, and TZS) an
index register, the corresponding address extension field is also transferred. Before
the extension field is transferred, it is incremented or decremented if bank overflow occurred as a result of the instruction.
3.3.2.3 Using Index Register Exchange to Modify Extension Fields
XK, YK, and ZK can be modified by using the transfer index register to index register
instructions.
When index registers are exchanged (TXY, TXZ, TYX, TYZ, TZX, and TZY), the corresponding address extension field is also exchanged.
3.3.2.4 Stacking Extension Field Values
The push multiple registers (PSHM) instruction can be used to store alternate extension field values on the stack. When bit 5 of the PSHM mask operand is set, the entire
address extension register (EK, XK, YK, and ZK values) is pushed onto the stack.
The pull multiple registers (PULM) instruction can be used to replace extension field
values. When bit 1 of the PULM mask operand is set, the entire address extension register (EK, XK, YK, and ZK) will be replaced with stacked values.
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3.3.2.5 Adding Immediate Data to Registers
XK, YK, ZK, and SK are automatically modified when an AIX, AIY, AIZ, or AIS instruction causes an overflow from the corresponding register. The byte addresses contained in the registers have a range of $0000 to $FFFF. If the operation results in a
value below $0000 or above $FFFF, the associated extension field is decremented or
incremented by the amount of overflow.
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3.3.3 Program Counter Address Extension
The PK field cannot be altered by direct transfer or exchange like other address extension fields, but a number of instructions and addressing modes affect the program
counter and its associated extension field.
PK is automatically modified when an operation causes an overflow from the PC. The
PC has a range of $0000 to $FFFF. If it is decremented below $0000 or incremented
above $FFFF, PK is also incremented or decremented.
3.3.3.1 Effect of Jump Instructions on PK : PC
There are two forms of jump instruction in the CPU16 instruction set. Both use special
addressing modes that replace PK : PC with a 20-bit effective address, but do not affect other address extension fields.
JMP causes an unconditional change in program execution. The effective address is
placed in PK : PC and execution continues at the new address.
JSR causes a branch to a subroutine. After the contents of the program counter and
the condition code register are stacked, the effective address is placed in PK : PC and
execution continues at the new address.
See SECTION 5 INSTRUCTION SET for detailed information about jump instructions.
3.3.3.2 Effect of Branch Instructions on PK : PC
The CPU16 instruction set includes a number of branch instructions. All add an offset
to the program counter when a branch is taken. The size of offset differs, but in all cases, PK is automatically modified when addition of the offset causes PC overflow. The
PC has a range of $0000 to $FFFF. If it is decremented below $0000 or incremented
above $FFFF, PK is also decremented or incremented. Pipelining affects the actual
offset from the instruction. See SECTION 5 INSTRUCTION SET for detailed information about branch instructions.
3.3.4 Effective Addresses and Extension Fields
It is important to distinguish address extension field values from effective address values. Effective address calculation is a part of addressing mode operation. Indexed and
accumulator offset addressing modes can generate effective addresses that cross
bank boundaries — ADDR[19:16] are changed to make an access, but extension field
values do not change as a result of the operation. See SECTION 4 DATA TYPES
AND ADDRESSING MODES for more information. Table 3-1 summarizes the effects
of various operations on address lines and address extension fields.
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Table 3-1 Operations that Cross Bank Boundaries
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Type of Operation
Normal PC Increments
Operand Read Using
Indexed Addressing Mode
Operand Write Using
Indexed Addressing Mode
Operand Read Using
Extended Addressing Mode
Operand Write Using
Extended Addressing Mode
Post-modified Indexed Addressing
(XK is modified after use as effective
address)
JMP, JSR Instruction
Branch Instructions
(Including BSR and LBSR)
Stack Access
AIX, AIY, AIZ, or AIS Instruction
TSX, TSY, or TSZ Instruction
TXS, TYS, or TZS Instruction
TXY or TXZ Instruction
TYX or TYZ Instruction
TZX or TZY Instruction
Extension Field Used
PK
XK, YK, ZK
Extension Field
Affected
PK
None
Effect on
ADDR[19:16]
Equals new PK
Used for
Effective Address
Used for
Effective Address
Used for
Effective Address
Used for
Effective Address
Used for
Effective Address
XK, YK, ZK
None
EK
None
EK
None
XK
XK
None
PK
PK
PK
Equals new PK
Equals new PK
SK
XK, YK, ZK, or SK
SK
XK, YK, or ZK
XK
YK
ZK
SK
XK, YK, ZK, or SK
XK, YK, or ZK
SK
YK, ZK
XK, ZK
XK, YK
Stack at new SK
None
None
None
None
None
None
3.4 Intermodule Bus
The intermodule bus is a standardized bus developed to facilitate design of modular
microcontrollers. Bus protocols are based on the MC68020 bus. The IMB contains circuitry to support exception processing, address space partitioning, multiple interrupt
levels, and vectored interrupts.
Modular microcontroller family modules communicate with one another via the IMB.
Although the full IMB supports 24 address and 16 data lines, CPU16 uses only 16 data
lines and 20 address lines — ADDR[23:20] are tied to ADDR19 when processor driven.
3.5 External Bus Interface
The external bus interface (EBI) is contained in the system integration module of the
modular microcontroller. This section provides a general discussion of EBI capabilities. Refer to the appropriate microcontroller user's manual for detailed information
about the bus interface.
The external bus is essentially an extension of the IMB. There are 24 address lines
and 16 data lines. ADDR[19:0] are normal address outputs, ADDR[23:20] follow the
output state of ADDR19. It provides dynamic sizing between 8- and 16-bit data accesses. A three-line handshaking interface performs bus arbitration.
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The EBI transfers information between the MCU and external devices. It supports
byte, word, and long-word transfers. Data ports of 8 and 16 bits can be accessed
through the use of asynchronous cycles controlled by the data transfer (SIZ1 and
SIZ0) and data size acknowledge pins (DSACK1 andDSACK0). Multiple bus cycles
may be required for an operand transfer to an 8-bit port, due to misalignment or to port
width smaller than the operand size.
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Port width is defined as the maximum number of bits accepted or provided during a
bus transfer. External devices must follow the handshake protocol described below.
3.5.1 Bus Control Signals
Control signals indicate the beginning of the cycle, the address space and size of the
transfer, and the type of cycle. The selected device controls the length of the cycle.
Strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. The EBI operates asynchronously for all port widths. A bus cycle is initiated by driving the address, size,
function code, and read/write outputs.
3.5.1.1 Function Codes
Function codes are automatically generated by the CPU16. Since the CPU16 always
operates in supervisor mode (FC2 = 1) FC1 and FC0 are encoded to select one of four
address spaces. One encoding (%00) is reserved. The remaining three spaces are
called program space, data space and CPU space. Program and data space are used
for instruction and operand accesses. CPU space is used for control information not
normally associated with read or write bus cycles, such as interrupt acknowledge cycles, breakpoint acknowledge cycles, and low power stop broadcast cycles. Function
codes are valid while address strobe AS is asserted. The following table shows address space encoding.
Table 3-2 Address Space Encoding
FC2
1
1
1
1
FC1
0
0
1
1
FC0
0
1
0
1
Address Space
Reserved
Data Space
Program Space
CPU Space
3.5.1.2 Size Signals
SIZ0 and SIZ1 indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while the AS is asserted. The following table shows SIZ0
and SIZ1 encoding.
Table 3-3 Size Signal Encoding
SIZ1
0
1
1
0
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SIZ0
1
0
1
0
Transfer Size
Byte
Word
3 Byte
Long Word
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3.5.1.3 Read/Write Signal
R/W determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted.
The signal may remain low for two consecutive write cycles.
3.5.2 Address Bus
Bus signals ADDR[19:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while address strobe (AS) is asserted.
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AS is a timing signal that indicates the validity of an address on the address bus and
of many control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.5.3 Data Bus
Bus signals DATA[15:0] comprise a bidirectional, nonmultiplexed parallel bus that
transfers data to or from the MCU. A read or write operation can transfer 8 or 16 bits
of data in one bus cycle. During a read cycle, the data is latched by the MCU on the
last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data
bus are driven, regardless of the port width or operand size. The EBI places the data
on the data bus one-half clock cycle after AS is asserted in a write cycle.
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid. The EBI asserts DS one full clock cycle after the assertion of AS during a write
cycle.
3.5.4 Bus Cycle Termination Signals
During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1 and/or DSACK0). During a read cycle, the signals tell the EBI to terminate the bus cycle and to latch data. During a write cycle, the signals indicate that an
external device has successfully stored data and that the cycle may terminate. These
signals also indicate to the EBI the size of the port for the bus cycle just completed.
The bus error signal (BERR) is also a bus cycle termination indicator and can be used
in the absence of DSACK to indicate a bus error condition. It can also be asserted in
conjunction with DSACKx to indicate a bus error condition, provided it meets the appropriate timing requirements. Simultaneous assertion of BERR and HALT is treated
in the same way as assertion of BERR alone.
An internal bus monitor can be used to generate the BERR signal for internal and internal-to-external transfers. An external bus master must provide its own BERR generation and drive the BERR pin, since the internal BERR monitor has no information
about transfers initiated by an external bus master.
Finally, autovector signal (AVEC) can be used to terminate external IRQ pin interrupt
acknowledge cycles. AVEC indicates to the EBI that it must internally generate a vecMOTOROLA
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tor number to locate an interrupt handler routine. If AVEC is continuously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored during
all other bus cycles.
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3.5.5 Data Transfer Mechanism
EBI architecture supports byte, word, and long-word operands, allowing access to 8and 16-bit data ports through the use of asynchronous cycles controlled by the data
transfer and size acknowledge inputs (DSACK1and DSACK0).
3.5.5.1 Dynamic Bus Sizing
The EBI dynamically interprets the port size of the addressed device during each bus
cycle, allowing operand transfers to or from 8- and 16-bit ports. During an operand
transfer cycle, the slave device signals its port size and indicates completion of the bus
cycle to the EBI through the use of the DSACKx inputs, as shown in the following table.
Table 3-4 Effect of DSACK Signals
DSACK1
1
1
0
0
DSACK0
1
0
1
0
Result
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
For example, if the CPU16 is executing an instruction that reads a long-word operand
from a 16-bit port, the EBI latches the 16 bits of valid data and runs another bus cycle
to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four
read cycles. The addressed device uses the DSACK signals to indicate the port width.
For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of
whether the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the EBI transfers valid data.
The EBI always attempts to transfer a maximum amount of data during each bus cycle.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle
begins. Operand bytes are designated as shown in Figure 3-2. OP0 is the most significant byte of a long-word operand, and OP3 is the least significant byte. The two
bytes of a word-length operand are OP0 (most significant) and OP1. The single byte
of a byte-length operand is OP0.
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Operand
31
Long Word
Three Byte
Word
Byte
24 23
OP0
Byte Order
16 15
OP1
OP2
OP0
OP1
OP0
8 7
0
OP3
OP2
OP1
OP0
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Figure 3-3 Operand Byte Order
3.5.5.2 Operand Alignment
Refer to Table 3-5 for required organization of 8- and 16-bit data ports. A data multiplexer establishes the necessary connections for different combinations of address
and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them
to their required positions. Positioning of bytes is determined by the size and address
outputs. SIZ1 and SIZ0 indicate the remaining number of bytes to be transferred during the current bus cycle. The number of bytes transferred is equal to or less than the
size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects data multiplexer operation. During an operand transfer, ADDR[23:1] indicate the word base address of the portion of the operand to be accessed,
and ADDR0 indicates the byte offset from the base. Table 3-5 shows the number of
bytes required on the data bus for read cycles. OPn entries are portions of the requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0,
and ADDR0 for that bus cycle.
Table 3-5 Operand Alignment
Transfer Case
Byte to Byte
Byte to Word (Even)
Byte to Word (Odd)
Word to Byte (Aligned)
Word to Byte (Misaligned)
Word to Word (Aligned)
Word to Word (Misaligned)
3 Byte to Byte (Aligned)†
3 Byte to Byte (Misaligned)†
3 Byte to Word (Aligned)†
3 Byte to Word (Misaligned)†
Long Word to Byte (Aligned)
Long Word to Byte (Misaligned)*
Long Word to Word (Aligned)
Long Word to Word (Misaligned)*
SIZ1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
SIZ0 ADDR0 DSACK1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DSACK0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
X
X
0
0
X
X
0
0
X
X
0
0
X
X
DATA
15
8
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
DATA
7
0
(OP0)
(OP0)
OP0
(OP1)
(OP0)
OP1
OP0
(OP1)
(OP0)
OP1
OP0
(OP1)
(OP0)
OP1
OP0
NOTES:
Operands in parentheses are ignored by the CPU16 during read cycles.
*The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
†Three-byte transfer cases occur only as a result of a long word to byte transfer.
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3.5.5.3 Misaligned Operands
The value of ADDR0 determines alignment. When ADDR0 = 0, the address is a word
and byte boundary. When ADDR0 = 1, the address is a byte boundary only. A byte
operand is properly aligned at any address; a word or long-word operand is misaligned
at an odd address.
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The basic CPU16 operand size is a 16-bit word. The CPU16 fetches instruction words
and operands from word boundaries only. The CPU16 performs misaligned data word
and long-word transfers. This capability is provided in order to make the CPU16 compatible with the M68HC11.
At most, a bus cycle can transfer a word of data aligned on a word boundary. If data
words are misaligned, each byte of the misaligned word is treated as a separate word
transfer. If a long-word operand is transferred via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word
on a following bus cycle.
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SECTION 4 DATA TYPES AND ADDRESSING MODES
This section contains information about CPU16 data types and addressing modes. It
is intended to familiarize users with basic processor capabilities.
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4.1 Data Types
The CPU16 uses the following types of data:
• Bits
• 4-bit signed integers
• 8-bit (byte) signed and unsigned integers
• 8-bit, 2-digit binary coded decimal numbers
• 16-bit (word) signed and unsigned integers
• 32-bit (long word) signed and unsigned integers
• 16-bit signed fractions
• 32-bit signed fractions
• 36-bit signed fixed-point numbers
• 20-bit effective addresses
• There are 8 bits in a byte, 16 bits in a word. Bit set and clear instructions use both
byte and word operands. Bit test instructions use byte operands.
Negative integers are represented in two’s-complement form. Four-bit signed integers,
packed two to a byte, are used only as X and Y offsets in MAC and RMAC operations.
Integers of 32 bits are used only by extended multiply and divide instructions, and by
the associated LDED and STED instructions.
Binary coded decimal numbers are packed, two digits per byte. BCD operations use
byte operands.
16-bit fractions are used in both fractional multiplication and division, and as multiplicand and multiplier operands in the MAC unit. Bit 15 is the sign bit. An implied radix
point lies between bits 15 and 14. There are 15 bits of magnitude — the range of values is –1 ($8000) to 1 – 2-15 ($7FFF).
Signed 32-bit fractions are used only by fractional multiplication and division instructions. Bit 31 is the sign bit. An implied radix point lies between bits 31 and 30. There
are 31 bits of magnitude — the range of values is –1 ($80000000) to 1 – 2-31
($7FFFFFFF).
Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit.
Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and
30. There are 31 bits of magnitude, but use of the extension bits allows representation
of numbers in the range –16 ($800000000) to 15.999999999 ($7FFFFFFFF).
20-bit effective addresses are formed by combining a 16-bit byte address with a 4-bit
address extension. See 4.3 Addressing Modes for more information.
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4.2 Memory Organization
Both program and data memory are divided into sixteen 64-Kbyte banks. Addressing
is pseudolinear — a 20-bit extended address can access any byte location in the appropriate address space.
A word is composed of two consecutive bytes. A word address is normally an even
byte address. Byte 0 of a word has a lower 16-bit address than byte 1. Long words and
32-bit signed fractions consist of two consecutive words, and are normally accessed
at the address of byte 0 in the word 0.
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Instruction fetches always access word addresses. Word operands are normally accessed at even byte addresses, but may be accessed at odd byte addresses, with a
substantial performance penalty.
To be compatible with the M68HC11, misaligned word transfers and misaligned stack
accesses are allowed. Transferring a misaligned word requires two successive byte
transfer operations.
Figure 4-1 shows how each CPU16 data type is organized in memory. Consecutive
even addresses show size and alignment.
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Memory/Register Data Types
Type
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
15 14 13 12 11 10
9
8
7
6
5
4
3
BYTE0
BYTE1
±
X OFFSET
±
Y OFFSET
±
X OFFSET
±
BCD1
BCD0
BCD1
WORD 0
WORD1
MSW LONG WORD 0
LSW LONG WORD 0
MSW LONG WORD 1
LSW LONG WORD 1
± ⇐ (Radix Point)
16-BIT SIGNED FRACTION 0
± ⇐ (Radix Point)
16-BIT SIGNED FRACTION 1
± ⇐ (Radix Point)
MSW 32-BIT SIGNED FRACTION 0
LSW 32-BIT SIGNED FRACTION 0
± ⇐ (Radix Point)
MSW 32-BIT SIGNED FRACTION 1
LSW 32-BIT SIGNED FRACTION 1
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Address
$0000
$0002
$0004
$0006
$0008
$000A
$000C
$000E
$0010
$0012
$0014
$0016
$0018
$001A
$001C
$001E
BIT
2
BIT
1
BIT
0
Y OFFSET
BCD0
0
0
MAC Data Types
35
±
«
«
32
«
31
«
15
±
16
⇐ (Radix Point)
MSW 32-BIT SIGNED FRACTION
0
⇐ (Radix Point)
LSW 32-BIT SIGNED FRACTION
16-BIT SIGNED FRACTION
Address Data Type
19
16
4-Bit Extension
15
0
16-Bit Address
Figure 4-1 Data Types and Memory Organization
4.3 Addressing Modes
The CPU16 uses nine basic types of addressing. There are one or more addressing
modes within each type. Table 4-1 shows the addressing modes.
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Table 4-1 Addressing Modes
Addressing
Type
Accumulator Offset
Extended
Immediate
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Indexed 8-Bit
Indexed 16-Bit
Indexed 20-Bit
Inherent
Post-modified Index
Relative
Mode
Mnemonic
E, X
E, Y
E, Z
EXT
EXT20
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
IND20, X
IND20, Y
IND20, Z
INH
IXP
REL8
REL16
Description
Index Register X with Accumulator E offset
Index Register Y with Accumulator E offset
Index Register Z with Accumulator E offset
Extended
20-bit Extended
8-bit Immediate
16-bit Immediate
Index Register X with unsigned 8-bit offset
Index Register Y with unsigned 8-bit offset
Index Register Z with unsigned 8-bit offset
Index Register X with signed 16-bit offset
Index Register Y with signed 16-bit offset
Index Register Z with signed 16-bit offset
Index Register X with signed 20-bit offset
Index Register Y with signed 20-bit offset
Index Register Z with signed 20-bit offset
Inherent
Signed 8-bit offset added to Index Register X
after effective address is used
8-bit relative
16-bit relative
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an
operand or an extension field to form a 20-bit effective address.
Note
Bank switching is transparent to most instructions. ADDR[19:16] of
the effective address are changed to make an access across a page
boundary. However, extension field values do not change as a result
of effective address computation.
4.3.1 Immediate Addressing Modes
In the immediate modes, an argument is contained in a byte or word immediately following the instruction. For IMM8 and IMM16 modes, the effective address is the address of the argument.
There are three specialized forms of IMM8 addressing.
The AIS, AIX/Y/Z, ADDD and ADDE instructions decrease execution time by signextending the 8-bit immediate operand to 16 bits, then adding it to an appropriate
register.
The MAC and RMAC instructions use an 8-bit immediate operand to specify two
signed 4-bit index register offsets.
The PSHM and PULM instructions use an 8-bit immediate operand to indicate
which registers must be pushed to or pulled from the stack.
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4.3.2 Extended Addressing Modes
Regular extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective address is formed by concatenating the EK field and the 16-bit byte
address. EXT20 mode is used only by JMP and JSR instructions. JMP and JSR instructions contain a complete 20-bit effective address —the operand is zero-extended
to 24 bits so that the instruction has an even number of bytes.
4.3.3 Indexed Addressing Modes
In the indexed modes, registers IX, IY, and IZ, together with their associated extension
fields, are used to calculate the effective address.
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For 8-bit indexed modes an 8-bit unsigned offset contained in the instruction is added
to the value contained in an index register and its extension field.
For 16-bit modes, a 16-bit signed offset contained in the instruction is added to the value contained in an index register and its extension field.
For 20-bit modes, a 20-bit signed offset (zero-extended to 24 bits) is added to the value contained in an index register. These modes are used for JMP and JSR instructions
only.
4.3.4 Inherent Addressing Mode
Inherent mode instructions use information directly available to the processor to determine the effective address. Operands (if any) are system resources and are thus not
fetched from memory.
4.3.5 Accumulator Offset Addressing Mode
Accumulator offset modes form an effective address by sign-extending the content accumulator E to 20 bits, then adding the result to an index register and its associated
extension field. This mode allows use of an index register and an accumulator within
a loop without corrupting accumulator D.
4.3.6 Relative Addressing Modes
Relative modes are used for branch and long branch instructions. If a branch condition
is satisfied, a byte or word signed twos complement offset is added to the concatenated PK field and program counter. The new PK : PC value is the effective address.
4.3.7 Post-Modified Index Addressing Mode
Post-modified index mode is used only by the MOVB and MOVW instructions. A
signed 8-bit offset is added to index register X after the effective address formed by
XK : IX is used. Post-modified mode provides enhanced block-move capabilities —
programmers should carefully consider its effect on pointers.
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4.3.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode
In M68HC11 systems, the direct addressing mode can be used to perform rapid accesses to RAM or I/O mapped into bank 0 ($0000 to $00FF), but the CPU16 uses the
first 512 bytes of bank 0 for exception vectors. To provide an enhanced replacement
for direct mode, the ZK field and index register Z have been assigned reset initialization vectors — by resetting the ZK field to a chosen page, and using indexed mode
addressing, a programmer can access useful data structures anywhere in the address
map.
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SECTION 5 INSTRUCTION SET
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This section contains general information about the instruction set. It is organized into
instruction summaries grouped by function. If an instruction has a special purpose,
such as aiding indexed operations, it appears in the summary for that function, rather
than in a general summary. An instruction that is used for more than one purpose appears in more than one summary. SECTION 6 INSTRUCTION GLOSSARY contains
detailed information about individual instructions.
5.1 General
The instruction set is based upon that of the M68HC11, but the opcode map has been
rearranged to maximize performance with a 16-bit data bus. Most M68HC11 instructions are supported by the CPU16, although they may be executed differently. Much
M68HC11 code will run on the CPU16 following reassembly. The user must take into
account changed instruction times, the interrupt mask, and the new interrupt stack
frame. See 5.13 Comparison of CPU16 and M68HC11 Instruction Sets for more information.
The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed
and unsigned multiplication and division. A number of instructions support extended
addressing and expanded memory space. In addition, there are special instructions
related to digital signal processing.
5.2 Data Movement Instructions
The CPU16 has a complete set of 8- and 16-bit data movement instructions, as well
as instructions to support 32-bit intermodule bus (IMB) operations. General-purpose
load, store, transfer and move instructions facilitate movement of data to and from
memory and peripherals. Special purpose instructions enhance indexing, extended
addressing, stacking, and digital signal processing.
5.2.1 Load Instructions
Load instructions copy memory content into an accumulator or register. Memory content is not changed by the operation.
There are specialized load instructions for stacking, indexing, extended addressing,
and digital signal processing. Refer to the appropriate summary for more information.
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Table 5-1 Load Summary
Mnemonic
Function
Operation
LDAA
Load A
(M) ⇒ A
LDAB
Load B
(M) ⇒ B
LDD
Load D
(M : M + 1) ⇒ D
LDE
Load E
(M : M + 1) ⇒ E
LDED
Load Concatenated E and D
(M : M + 1) ⇒ E
(M + 2 : M + 3) ⇒ D
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5.2.2 Move Instructions
These instructions move data bytes or words from one location to another in memory.
Table 5-2 Move Summary
Mnemonic
Function
Operation
MOVB
Move Byte
(M1) ⇒ M2
MOVW
Move Word
(M : M + 11) ⇒ M : M + 12
5.2.3 Store Instructions
Store instructions copy the content of an accumulator or register to memory. Register/
accumulator content is not changed by the operation.
There are specialized store instructions for indexing, extended addressing, and CCR
manipulation. Refer to the appropriate summary for more information.
Table 5-3 Store Summary
Mnemonic
Function
Operation
STAA
Store A
(A) ⇒ M
STAB
Store B
(B) ⇒ M
STD
Store D
(D) ⇒ M : M + 1
STE
Store E
(E) ⇒ M : M + 1
STED
Store Concatenated D and E
(E) ⇒ M : M + 1
(D) ⇒ M + 2 : M + 3
5.2.4 Transfer Instructions
These instructions transfer the content of a register or accumulator to another register
or accumulator. Content of the source is not changed by the operation.
There are specialized transfer instructions for stacking, indexing, extended addressing, CCR manipulation, and digital signal processing. Refer to the appropriate summary for more information.
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Table 5-4 Transfer Summary
Mnemonic
Function
Operation
TAB
Transfer A to B
(A) ⇒ B
TBA
Transfer B to A
(B) ⇒ A
TDE
Transfer D to E
(D)⇒ E
TED
Transfer E to D
(E) ⇒ D
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5.2.5 Exchange Instructions
These instructions exchange the contents of pairs of registers or accumulators. There
are specialized exchange instructions for indexing. Refer to the appropriate summary
for more information.
Table 5-5 Exchange Summary
Mnemonic
Function
Operation
XGAB
Exchange A with B
(A) ⇔ (B)
XGDE
Exchange D with E
(D) ⇔ (E)
5.3 Mathematic Instructions
The CPU16 has a full set of 8- and 16-bit mathematic instructions. There are instructions for signed and unsigned arithmetic, division and multiplication, as well as a complete set of 8- and 16-bit Boolean operators.
Special arithmetic and logic instructions aid stacking operations, indexing, extended
addressing, BCD calculation, and condition code register manipulation. There are also
dedicated multiply and accumulate unit instructions. Refer to the appropriate instruction summary for more information.
5.3.1 Addition and Subtraction Instructions
Signed and unsigned 8- and 16-bit arithmetic instructions can be performed between
registers or between registers and memory. Instructions that also add or subtract the
value of the CCR carry bit facilitate multiple precision computation.
Table 5-6 Addition Summary
Mnemonic
ABA
ADCA
ADCB
ADCD
ADCE
ADDA
ADDB
ADDD
ADDE
ADE
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Function
Add B to A
Add with Carry to A
Add with Carry to B
Add with Carry to D
Add with Carry to E
Add to A
Add to B
Add to D
Add to E
Add D to E
Operation
(A) + (B) ⇒ A
(A) + (M) + C ⇒ A
(B) + (M) + C ⇒ B
(D) + (M : M + 1) + C ⇒ D
(E) + (M : M + 1) + C ⇒ E
(A) + (M) ⇒ A
(B) + (M) ⇒ B
(D) + (M : M + 1) ⇒ D
(E) + (M : M + 1) ⇒ E
(E) + (D) ⇒ E
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Table 5-7 Subtraction Summary
Mnemonic
Function
Operation
SBA
Subtract B from A
(A) – (B) ⇒ A
SBCA
Subtract with Carry from A
(A) – (M) – C ⇒ A
SBCB
Subtract with Carry from B
(B) – (M) – C ⇒ B
SBCD
Subtract with Carry from D
(D) – (M : M + 1) – C ⇒ D
SBCE
Subtract with Carry from E
(E) – (M : M + 1) – C ⇒ E
SDE
Subtract D from E
(E) – (D)⇒ E
SUBA
Subtract from A
(A) – (M) ⇒ A
SUBB
Subtract from B
(B) – (M) ⇒ B
SUBD
Subtract from D
(D) – (M : M + 1) ⇒ D
SUBE
Subtract from E
(E) – (M : M + 1) ⇒ E
The following table shows the type of arithmetic operation performed by each addition
and subtraction instruction.
Table 5-8 Arithmetic Operations
Mnemonic
8-Bit
ABA
x
ADCA
x
ADCB
x
16-Bit
X±X
X±M
X±M±C
x
x
x
ADCD
x
x
ADCE
x
x
ADDA
x
ADDB
x
x
x
ADDD
x
x
ADDE
x
x
ADE
x
x
SBA
x
SBCA
x
x
SBCB
x
x
SBCD
x
x
SBCE
x
SDE
x
x
x
x
SUBA
x
x
SUBB
x
x
SUBD
x
x
SUBE
x
x
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5.3.2 Binary Coded Decimal Instructions
To add binary coded decimal operands, use addition instructions that set the half-carry
bit in the CCR, then adjust the result with the DAA instruction.
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Table 5-9 BCD Summary
Mnemonic
Function
Operation
ABA
Add B to A
(A) + (B) ⇒ A
ADCA
Add with Carry to A
(A) + (M) + C ⇒ A
ADCB
Add with Carry to B
(B) + (M) + C ⇒ B
ADDA
Add to A
(A) + (M) ⇒ A
ADDB
Add to B
(B) + (M) ⇒ B
DAA
Decimal Adjust A
(A)10
SXT
Sign Extend B into A
If B7 = 1
then A = $FF
else A = $00
The following table shows DAA operation for all legal combinations of input operands.
Columns 1 through 4 represent the results of addition operations on BCD operands.
The correction factor in column 5 is added to the accumulator to restore the result of
an operation on two BCD operands to a valid BCD value, and to set or clear the C bit.
All values are hexadecimal.
Table 5-10 DAA Function Summary
1
2
3
4
5
6
Initial
C Bit Value
Value of
A[7:4]
Initial
H Bit Value
Value of
A[3:0]
Correction
Factor
Corrected
C Bit Value
0
0–9
0
0–9
00
0
0
0–8
0
A–F
06
0
0
0–9
1
0–3
06
0
0
A–F
0
0–9
60
1
0
9–F
0
A–F
66
1
0
A–F
1
0–3
66
1
1
0–2
0
0–9
60
1
1
0–2
0
A–F
66
1
1
0–3
1
0–3
66
1
5.3.3 Compare and Test Instructions
Compare and test instructions perform subtraction between a pair of registers or between a register and memory. The result is not stored, but condition codes are set by
the operation. These instructions are generally used to establish conditions for branch
instructions.
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Table 5-11 Compare and Test Summary
Mnemonic
Function
Operation
CBA
Compare A to B
(A) – (B)
CMPA
Compare A to Memory
(A) – (M)
CMPB
Compare B to Memory
(B) – (M)
CPD
Compare D to Memory
(D) – (M : M + 1)
CPE
Compare E to Memory
(E) – (M : M + 1)
TST
Test for Zero or Minus
(M) – $00
TSTA
Test A for Zero or Minus
(A) – $00
TSTB
Test B for Zero or Minus
(B) – $00
TSTD
Test D for Zero or Minus
(D) – $0000
TSTE
Test E for Zero or Minus
(E) – $0000
TSTW
Test for Zero or Minus Word
(M : M + 1) – $0000
5.3.4 Multiplication and Division Instructions
There are instructions for signed and unsigned 8- and 16-bit multiplication, as well as
for signed 16-bit fractional multiplication. Eight-bit multiplication operations have a 16bit product. Sixteen-bit multiplication operations can have either 16- or 32-bit products.
All division operations have 16-bit divisors, but dividends can be either 16- or 32-bit
numbers. Quotients and remainders of all division operations are 16-bit numbers.
There are instructions for signed and unsigned division, as well as for fractional division.
Fractional multiplication uses 16-bit operands. Bit 15 is the sign bit. There is an implied
radix point between bits 15 and 14. The range of values is –1 ($8000) to 0.999969482
($7FFF). The MSB of the result is its sign bit, and there is an implied radix point between the sign bit and the rest of the result.
There are special 36-bit signed fractional multiply and accumulate unit instructions to
support digital signal processing operations. Refer to the appropriate summary for
more information.
Table 5-12 Multiplication and Division Summary
Mnemonic
EDIV
Function
Extended Unsigned Divide
EDIVS
Extended Signed Divide
EMUL
EMULS
FDIV
Extended Unsigned Multiply
Extended Signed Multiply
Unsigned Fractional Divide
FMULS
IDIV
Signed Fractional Multiply
Integer Divide
MUL
Multiply
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Operation
(E : D) / (IX)
Quotient ⇒ IX
Remainder ⇒ D
(E : D) / (IX)
Quotient ⇒ IX
Remainder ⇒ D
(E) ∗ (D) ⇒ E : D
(E) ∗ (D) ⇒ E : D
(D) / (IX) ⇒ IX
remainder ⇒ D
(E) ∗ (D) ⇒ E : D
(D) / (IX) ⇒ IX
remainder ⇒ D
(A) ∗ (B) ⇒ D
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5.3.5 Decrement and Increment Instructions
These instructions are optimized 8- and 16-bit addition and subtraction operations.
They are generally used to implement counters. Because they do not affect the carry
bit in the CCR, they are particularly well suited for loop counters in multiple-precision
computation routines.
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Table 5-13 Decrement and Increment Summary
Mnemonic
Function
Operation
DEC
Decrement Memory
(M) – $01 ⇒ M
DECA
Decrement A
(A) – $01 ⇒ A
DECB
Decrement B
(B) – $01 ⇒ B
DECW
Decrement Memory Word
(M : M + 1) – $0001 ⇒ M : M + 1
INC
Increment Memory
(M) + $01 ⇒ M
INCA
Increment A
(A) + $01 ⇒ A
INCB
Increment B
(B) + $01 ⇒ B
INCW
Increment Memory Word
(M : M + 1) + $0001 ⇒ M : M + 1
5.3.6 Clear, Complement, and Negate Instructions
Each of these instructions performs a specific binary operation on a value in an accumulator or in memory. Clear operations set the value to zero, complement operations
replace the value with its one’s complement, and negate operations replace the value
with its two’s complement.
Table 5-14 Clear, Complement, and Negate Summary
Mnemonic
Function
Operation
CLR
Clear Memory
$00 ⇒ M
CLRA
Clear A
$00 ⇒ A
CLRB
Clear B
$00 ⇒ B
CLRD
Clear D
$0000 ⇒ D
CLRE
Clear E
$0000 ⇒ E
CLRW
Clear Memory Word
$0000 ⇒ M : M + 1
COM
One’s Complement Byte
$FF – (M) ⇒ M
COMA
One’s Complement A
$FF – (A) ⇒ A
COMB
One’s Complement B
$FF – (B) ⇒ B
COMD
One’s Complement D
$FFFF – (D) ⇒ D
COME
One’s Complement E
$FFFF – (E) ⇒ E
COMW
One’s Complement Word
$FFFF – M : M + 1 ⇒ M : M + 1
NEG
Two’s Complement Byte
$00 – (M) ⇒ M
NEGA
Two’s Complement A
$00 – (A) ⇒ A
NEGB
Two’s Complement B
$00 – (B) ⇒ B
NEGD
Two’s Complement D
$0000 – (D) ⇒ D
NEGE
Two’s Complement E
$0000 – (E) ⇒ E
NEGW
Two’s Complement Word
$0000 – (M : M + 1) ⇒ M : M + 1
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5.3.7 Boolean Logic Instructions
Each of these instructions performs the Boolean logic operation represented by the
mnemonic. There are 8- and 16-bit versions of each instruction.
There are special forms of logic instructions for stack pointer, program counter, index
register, and address extension field manipulation. Refer to the appropriate summary
for more information.
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Table 5-15 Boolean Logic Summary
Mnemonic
Function
Operation
ANDA
AND A
(A) × (M) ⇒ A
ANDB
AND B
(B) × (M) ⇒ B
ANDD
AND D
(D) × (M : M + 1) ⇒ D
ANDE
AND E
(E) × (M : M + 1) ⇒ E
EORA
Exclusive OR A
(A) ⊕ (M) ⇒ A
EORB
Exclusive OR B
(B) ⊕ (M) ⇒ B
EORD
Exclusive OR D
(D) ⊕ (M : M + 1) ⇒ D
EORE
Exclusive OR E
(E) ⊕ (M : M + 1) ⇒ E
ORAA
OR A
(A) ✛ (M) ⇒ A
ORAB
OR B
(B) ✛ (M) ⇒ B
ORD
OR D
(D) ✛ (M : M + 1) ⇒ D
ORE
OR E
(E) ✛ (M : M + 1) ⇒ E
5.4 Bit Test and Manipulation Instructions
These operations use a mask value to test or change the value of individual bits in an
accumulator or in memory. BITA and BITB provide a convenient means of setting condition codes without altering the value of either operand.
Table 5-16 Bit Test and Manipulation Summary
Mnemonic
Function
Operation
BITA
Bit Test A
(A) × (M)
BITB
Bit Test B
(B) × (M)
BCLR
Clear Bit(s)
(M) × (Mask) ⇒ M
BCLRW
Clear Bit(s) Word
(M : M + 1) × (Mask) ⇒ M : M + 1
BSET
Set Bit(s)
(M) ✛ (Mask) ⇒ M
BSETW
Set Bit(s) Word
(M : M + 1) ✛ (Mask) ⇒ M : M + 1
5.5 Shift and Rotate Instructions
There are shift and rotate commands for all accumulators, for memory bytes, and for
memory words. All shift and rotate operations pass the shifted-out bit through the carry
bit in the CCR in order to facilitate multiple-byte and multiple-word operations. There
are no separate logical left shift operations. Use arithmetic shift left (ASL) for logic shift
left (LSL) functions — LSL mnemonics will be assembled as ASL operations.
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Special shift commands move multiply and accumulate unit accumulator bits. See
5.10 Digital Signal Processing Instructions for more information.
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Table 5-17 Logic Shift Summary
Mnemonic
Function
LSR
Logic Shift Right
LSRA
Logic Shift Right A
LSRB
Logic Shift Right B
LSRD
Logic Shift Right D
LSRE
Logic Shift Right E
LSRW
Logic Shift Right Word
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Table 5-18 Arithmetic Shift Summary
Mnemonic
Function
ASL
(LSL)
Arithmetic Shift Left
ASLA
(LSLA)
Arithmetic Shift Left A
ASLB
(LSLB)
Arithmetic Shift Left B
ASLD
(LSLD)
Arithmetic Shift Left D
ASLE
(LSLE)
Arithmetic Shift Left E
ASLW
(LSLW)
Arithmetic Shift Left Word
ASR
Arithmetic Shift Right
ASRA
Arithmetic Shift Right A
ASRB
Arithmetic Shift Right B
ASRD
Arithmetic Shift Right D
ASRE
Arithmetic Shift Right E
ASRW
Arithmetic Shift Right Word
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Table 5-19 Rotate Summary
Mnemonic
Function
ROL
Rotate Left
ROLA
Rotate Left A
ROLB
Rotate Left B
ROLD
Rotate Left D
ROLE
Rotate Left E
ROLW
Rotate Left Word
ROR
Rotate Right
RORA
Rotate Right A
RORB
Rotate Right B
RORD
Rotate Right D
RORE
Rotate Right E
RORW
Rotate Right Word
Operation
5.6 Program Control Instructions
Program control instructions affect the sequence of instruction execution.
Branch instructions cause sequence to change when specific conditions exist. The
CPU16 has short, long, and bit-condition branches.
Jump instructions cause immediate changes in sequence. The CPU16 has a true 20bit address jump instruction.
Subroutine instructions optimize the process of temporarily transferring control to a
segment of code that performs a particular task. The CPU16 can branch or jump to
subroutines.
Interrupt instructions handle immediate transfer of control to a routine that performs a
critical task. Software interrupts are a type of exception. SECTION 9 EXCEPTION
PROCESSING covers interrupt exception processing in detail.
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5.6.1 Short Branch Instructions
Short branch instructions operate as follows. When a specified condition is met, a
signed 8-bit offset is added to the value in the program counter. If addition causes the
value in the PC to be greater than $FFFF or less than $0000, the PK extension field is
incremented or decremented. Program execution continues at the new extended address.
Short branch instructions can be classified by the type of condition that must be satisfied in order for a branch to be taken. Some instructions belong to more than one classification.
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Unary branch instructions always execute.
Simple branches are taken when a specific bit in the condition code register is in a specific state as a result of a previous operation.
Unsigned conditional branches are taken when comparison or test of unsigned quantities results in a specific combination of condition code register bits.
Signed branches are taken when comparison or test of signed quantities results in a
specific combination of condition code register bits.
Table 5-20 Short Branch Summary
Mnemonic
Opcode
Equation
Condition
BRA
B0
1=1
True
BRN
B1
1=0
False
Simple Branches
Mnemonic
Opcode
Equation
Condition
BCC
B4
C=0
Equation
BCS
B5
C=1
Equation
BEQ
B7
Z=1
Equation
BMI
BB
N=1
Equation
BNE
B6
Z=0
Equation
BPL
BA
N=0
Equation
BVC
B8
V=0
Equation
BVS
B9
V=1
Equation
Unsigned Branches
Mnemonic
Opcode
Equation
Condition
BCC
B4
C=0
(X) ≥ (M)
BCS
B5
C=1
(X) < (M)
BEQ
B7
Z=1
(X) = (M)
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BHI
B2
C✛Z=0
(X) > (M)
BLS
B3
C✛Z=1
(X) ≤ (M)
BNE
B6
Z=0
(X) ≠ (M)
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Table 5-20 Short Branch Summary (Continued)
Signed Branches
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Mnemonic
Opcode
Equation
Condition
BEQ
B7
Z=1
(X) = (M)
BGE
BC
N⊕V=0
(X) ≥ (M)
BGT
BE
Z ✛ (N ⊕ V) = 0
(X) > (M)
BLE
BF
Z ✛ (N ⊕ V) = 1
(X) ≤ (M)
BLT
BD
N⊕V=1
(X) < (M)
BNE
B6
Z=0
(X) ≠ (M)
Note
The numeric range of short branch offset values is $80 (–128) to $7F
(127), but actual displacement from the instruction differs from the
range for two reasons.
First, PC values are automatically aligned to word boundaries. Only
even offsets are valid — an odd offset value is rounded down. Maximum positive offset is $7E.
Second, instruction pipelining affects the value in the PC at the time
an instruction executes. The value to which the offset is added is the
address of the instruction plus $0006. At maximum positive offset
($7E), displacement from the branch instruction is 132. At maximum
negative offset ($80), displacement is –122.
5.6.2 Long Branch Instructions
Long branch instructions operate as follows. When a specified condition is met, a
signed 16-bit offset is added to the value in the program counter. If addition causes the
value in the PC to be greater than $FFFF or less than $0000, the PK extension field is
incremented or decremented. Program execution continues at the new extended address. Long branches are used when large displacements between decision-making
steps are necessary.
Long branch instructions can be classified by the type of condition that must be satisfied in order for a branch to be taken. Some instructions belong to more than one classification.
Unary branch instructions always execute.
Simple branches are taken when a specific bit in the condition code register is in a specific state as a result of a previous operation.
Unsigned branches are taken when comparison or test of unsigned quantities results
in a specific combination of condition code register bits.
Signed branches are taken when comparison or test of signed quantities results in a
specific combination of condition code register bits.
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Table 5-21 Long Branch Instructions
Unary Branches
Mnemonic
Opcode
Equation
Condition
LBRA
3780
1=1
True
LBRN
3781
1=0
False
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Simple Branches
Mnemonic
Opcode
Equation
Condition
LBCC
3784
C=0
Equation
LBCS
3785
C=1
Equation
LBEQ
3787
Z=1
Equation
LBEV
3791
EV = 1
Equation
LBMI
378B
N=1
Equation
LBMV
3790
MV = 1
Equation
LBNE
3786
Z=0
Equation
LBPL
378A
N=0
Equation
LBVC
3788
V=0
Equation
LBVS
3789
V=1
Equation
Unsigned Branches
Mnemonic
Opcode
Equation
Condition
LBCC
3784
C=0
(X) ≥ (M)
LBCS
3785
C=1
(X) < (M)
LBEQ
3787
Z=1
(X) = (M)
LBHI
3782
C✛Z=0
(X) > (M)
LBLS
3783
C✛Z=1
(X) ≤ (M)
LBNE
3786
Z=0
(X) ≠ (M)
Equation
Condition
Signed Branches
Mnemonic
Opcode
LBEQ
3787
Z=1
(X) = (M)
LBGE
378C
N⊕V=0
(X) ≥ (M)
LBGT
378E
Z ✛ (N ⊕ V) = 0
(X) > (M)
LBLE
378F
Z ✛ (N ⊕ V) = 1
(X) ≤ (M)
LBLT
378D
N⊕V=1
(X) < (M)
LBNE
3786
Z=0
(X) ≠ (M)
Note
The numeric range of long branch offset values is $8000 (–32768) to
$7FFF (32767), but actual displacement from the instruction differs
from the range for two reasons.
First, PC values are automatically aligned to word boundaries. Only
even offsets are valid — an odd offset value will be rounded down.
Maximum positive offset is $7FFE.
Second, instruction pipelining affects the value in the PC at the time
an instruction executes. The value to which the offset is added is the
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address of the instruction plus $0006. At maximum positive offset
($7FFE), displacement from the instruction is 32772. At maximum
negative offset ($8000), displacement is –32762.
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5.6.3 Bit Condition Branch Instructions
Bit condition branches are taken when specific bits in a memory byte are in a specific
state. A mask operand is used to test a memory location pointed to by a 20-bit indexed
or extended effective address. If the bits in memory match the mask, an 8- or 16-bit
signed relative offset is added to the current value of the program counter. If addition
causes the value in the PC to be greater than $FFFF or less than $0000, the PK extension field is incremented or decremented. Program execution continues at the new
extended address.
Table 5-22 Bit Condition Branch Summary
Mnemonic
Addressing Mode
Opcode
Equation
BRCLR
IND8, X
CB
(M) • (Mask) = 0
IND8, Y
DB
IND8, Z
EB
IND16, X
0A
IND16, Y
1A
IND16, Z
2A
EXT
3A
BRSET
IND8, X
8B
IND8, Y
9B
IND8, Z
AB
IND16, X
0B
IND16, Y
1B
IND16, Z
2B
EXT
3B
(M) • (Mask) = 0
Note
The numeric range of 8-bit offset values is $80 (–128) to $7F (127),
and the numeric range of 16-bit offset values is $8000 (–32768) to
$7FFF (32767), but actual displacement from the branch instruction
differs from the range, for two reasons.
First, PC values are automatically aligned to word boundaries. Only
even offsets are valid — an odd offset value is rounded down. Maximum positive 8-bit offset is $7E; maximum positive 16-bit offset is
$7FFE.
Second, instruction pipelining affects the value in the PC at the time
an instruction executes. The value to which the offset is added is the
address of the instruction plus $0006. Maximum positive ($7E) and
negative ($80) 8-bit offsets correspond to displacements of 132 and
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–122 from the branch instruction. Maximum positive ($7FFE) and
negative ($8000) 16-bit offsets correspond to displacements of
32772 and –32762.
5.6.4 Jump Instruction
The CPU16 JMP instruction uses 20-bit addressing, so that control can be passed to
any address in the memory map. It should be noted that BRA and LBRA execute in
fewer cycles than the indexed forms of JMP.
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Table 5-23 Jump Summary
Mnemonic
Function
Operation
JMP
Jump
20-bit Address ⇒ PK : PC
5.6.5 Subroutine Instructions
Subroutines can be called by short (BSR) or long (LBSR) branches, or by a jump
(JSR). A single instruction, RTS returns control to the calling routine.
All three types of calling instructions stack return PC and CCR values prior to transferring control to a subroutine. Stacking the CCR also saves the PK extension field. Other
resources can be saved by means of the PSHM instruction, if necessary.
Table 5-24 Subroutine Summary
Mnemonic
Function
Operation
BSR
Branch to Subroutine
(PK : PC) − 2 ⇒ PK : PC
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
(PK : PC) + Offset ⇒ PK : PC
JSR
Jump to Subroutine
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
20-bit Address ⇒ PK : PC
LBSR
Long Branch to Subroutine
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
(PK : PC) + Offset ⇒ PK : PC
RTS
Return from Subroutine
(SK : SP) + 2 ⇒ SK : SP
Pull PK
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) – 2 ⇒ PK : PC
Note
Instruction pipelining affects the operation of BSR. When a subroutine is called, PK : PC contain the address of the calling instruction
plus $0006. LBSR and JSR stack this value, but BSR must adjust it
prior to stacking.
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LBSR and JSR are 4-byte instructions. For program execution to resume at the instruction immediately following them, RTS must subtract $0002 from the stacked PK : PC value.
BSR is a 2-byte instruction. BSR subtracts $0002 from the stacked
value prior to stacking so that RTS will work correctly.
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5.6.6 Interrupt Instructions
The SWI instruction initiates synchronous exception processing. First, return PC and
CCR values are stacked (stacking the CCR saves the PK extension field). After return
values are stacked, the PK field is cleared, and the PC is loaded with exception vector
6 (content of address $000C).
The RTI instruction is used to terminate all exception handlers, including interrupt service routines. It causes normal execution to resume with the instruction following the
last instruction that executed prior to interrupt. See SECTION 9 EXCEPTION PROCESSING for more information.
Table 5-25 Interrupt Summary
Mnemonic
Function
Operation
RTI
Return from Interrupt
(SK : SP) + 2 ⇒ SK : SP
Pull CCR
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) – 6 ⇒ PK : PC
SWI
Software Interrupt
(PK : PC) + 2 ⇒ PK : PC
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
$0 ⇒ PK
SWI Vector ⇒ PC
Note
Instruction pipelining affects the operation of SWI. When an interrupt
occurs, PK : PC contain the address of the interrupted instruction
plus $0006. This value is stacked during asynchronous exception
processing, but synchronous exceptions, such as SWI, must adjust
the stacked value so that RTI can work correctly.
For program execution to resume with the interrupted instruction following an asynchronous interrupt, RTI must subtract $0006 from the
stacked PK : PC value.
Synchronous interrupts allow an interrupted instruction to finish execution before exception processing begins. The SWI instruction must
add $0002 prior to stacking in order for execution to resume correctly.
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5.7 Indexing and Address Extension Instructions
The CPU16 has a complete set of instructions that enable a user to take full advantage
of 20-bit pseudolinear addressing. These instructions use specialized forms of mathematic and data transfer instructions to perform index register manipulation and extension field manipulation.
5.7.1 Indexing Instructions
Indexing instructions perform 8- and 16-bit operations on the three index registers and
accumulators, other registers, or memory. Index addition and transfer instructions also
affect the associated extension field.
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Table 5-26 Indexing Summary
Addition Instructions
Mnemonic
Function
Operation
ABX
Add B to IX
(XK : IX) + (000 : B) ⇒ XK : IX
ABY
Add B to IY
(YK : IY) + (000 : B) ⇒ YK : IY
ABZ
Add B to IZ
(ZK : Z) + (000 : B) ⇒ ZK : IZ
ADX
Add D to IX
(XK : IX) + ( « D) ⇒ XK : IX
ADY
Add D to IY
(YK : IY) + ( « D) ⇒ YK : IY
ADZ
Add D to IZ
(ZK : IZ) + ( « D) ⇒ ZK : IZ
AEX
Add E to IX
(XK : IX) + ( « D)⇒ XK : IX
AEY
Add E to IY
(YK : IY) + ( « E) ⇒ YK : IY
AEZ
Add E to IZ
(ZK : IZ) + ( « E) ⇒ ZK : IZ
AIX
Add Immediate Value to IX
XK : IX + ( « IMM8/16) ⇒ XK : IX
AIY
Add Immediate Value to IY
YK : IY + ( « IMM8/16) ⇒ YK : IY
AIZ
Add Immediate Value to IZ
ZK : IZ + ( « IMM8/16) ⇒ ZK : IZ
Compare Instructions
Mnemonic
Function
Operation
CPX
Compare IX to Memory
(IX) – (M : M + 1)
CPY
Compare IY to Memory
(IY) – (M : M + 1)
CPZ
Compare IZ to Memory
(IZ) – (M : M + 1)
Load Instructions
Mnemonic
Function
Operation
LDX
Load IX
(M : M + 1) ⇒ IX
LDY
Load IY
(M : M + 1) ⇒ IY
LDZ
Load IZ
(M : M + 1) ⇒ IZ
Store Instructions
Mnemonic
Function
Operation
STX
Store IX
(IX) ⇒ M : M + 1
STY
Store IY
(IY) ⇒ M : M + 1
STZ
Store IZ
(IZ) ⇒ M : M + 1
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Table 5-26 Indexing Summary (Continued)
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Transfer Instructions
Mnemonic
Function
Operation
TSX
Transfer SP to IX
(SK : SP) + 2 ⇒ XK : IX
TSY
Transfer SP to IY
(SK : SP) + 2 ⇒ YK : IY
TSZ
Transfer SP to IZ
(SK : SP) + 2 ⇒ ZK : IZ
TXS
Transfer IX to SP
(XK : IX) – 2 ⇒ SK : SP
TXY
Transfer IX to IY
(XK : IX) ⇒ YK : IY
TXZ
Transfer IX to IZ
(XK : IX) ⇒ ZK : IZ
TYS
Transfer IY to SP
(YK : IY) – 2 ⇒ SK : SP
TYX
Transfer IY to IX
(YK : IY) ⇒ XK : IX
TYZ
Transfer IY to IZ
(YK : IY) ⇒ ZK : IZ
TZS
Transfer IZ to SP
(ZK : IZ) – 2 ⇒ SK : SP
TZX
Transfer IZ to IX
(ZK : IZ) ⇒ XK : IX
TZY
Transfer IZ to IY
(ZK : IZ) ⇒ ZK : IY
Exchange Instructions
Mnemonic
Function
Operation
XGDX
Exchange D with IX
(D) ⇔ (IX)
XGDY
Exchange D with IY
(D) ⇔ (IY)
XGDZ
Exchange D with IZ
(D) ⇔ (IZ)
XGEX
Exchange E with IX
(E) ⇔ (IX)
XGEY
Exchange E with IY
(E) ⇔ (IY)
XGEZ
Exchange E with IZ
(E) ⇔ (IZ)
5.7.2 Address Extension Instructions
Address extension instructions transfer extension field contents to or from accumulator B. Other types of operations can be performed on the extension field value while it
is in the accumulator.
Table 5-27 Address Extension Summary
Mnemonic
TBEK
TBSK
TBXK
TBYK
TBZK
TEKB
Function
Transfer B to EK
Transfer B to SK
Transfer B to XK
Transfer B to YK
Transfer B to ZK
Transfer EK to B
TSKB
Transfer SK to B
TXKB
Transfer XK to B
TYKB
Transfer YK to B
TZKB
Transfer ZK to B
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Operation
(B) ⇒ EK
(B) ⇒ SK
(B) ⇒ XK
(B) ⇒ YK
(B) ⇒ ZK
$0 ⇒ B[7:4]
(EK) ⇒ B[3:0]
(SK) ⇒ B[3:0]
$0 ⇒ B[7:4]
$0 ⇒ B[7:4]
(XK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(YK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(ZK) ⇒ B[3:0]
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5.8 Stacking Instructions
There are two types of stacking instructions. Stack pointer instructions use specialized
forms of mathematic and data transfer instructions to perform stack pointer manipulation. Stack operation instructions save information on and retrieve information from the
system stack.
Table 5-28 Stacking Summary
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Stack Pointer Instructions
Mnemonic
Function
Operation
AIS
Add Immediate Data to SP
SK : SP + ( « IMM16) ⇒ SK : SP
CPS
Compare SP to Memory
(SP) – (M : M + 1)
LDS
Load SP
(M : M + 1) ⇒ SP
STS
Store SP
(SP) ⇒ M : M + 1
TSX
Transfer SP to IX
(SK : SP) + 2 ⇒ XK : IX
TSY
Transfer SP to IY
(SK : SP) + 2 ⇒ YK : IY
TSZ
Transfer SP to IZ
(SK : SP) + 2 ⇒ ZK : IZ
TXS
Transfer IX to SP
(XK : IX) – 2 ⇒ SK : SP
TYS
Transfer IY to SP
(YK : IY) – 2 ⇒ SK : SP
TZS
Transfer IZ to SP
(ZK : IZ) – 2 ⇒ SK : SP
Stack Operation Instructions
Mnemonic
Function
Operation
PSHA
Push A
(SK : SP) + 1 ⇒ SK : SP
Push (A)
(SK : SP) – 2 ⇒ SK : SP
PSHB
Push B
(SK : SP) + 1 ⇒ SK : SP
Push (B)
(SK : SP) – 2 ⇒ SK : SP
PSHM
Push Multiple Registers
Mask bits:
0=D
1=E
2 = IX
3 = IY
4 = IZ
5=K
6 = CCR
7 = (reserved)
For mask bits 0 to 6 :
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If mask bit set
Push register
(SK : SP) – 2 ⇒ SK : SP
PULA
Pull A
(SK : SP) + 2 ⇒ SK : SP
Pull (A)
(SK : SP) – 1 ⇒ SK : SP
PULB
Pull B
(SK : SP) + 2 ⇒ SK : SP
Pull (B)
(SK : SP) – 1 ⇒ SK : SP
PULM
Pull Multiple Registers
Mask bits:
0 = CCR[15:4]
1=K
2 = IZ
3 = IY
4 = IX
5=E
6=D
7 = (reserved)
For mask bits 0 to 7:
If mask bit set
(SK : SP) + 2 ⇒ SK : SP
Pull register
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5.9 Condition Code Instructions
Condition code instructions use specialized forms of mathematic and data transfer instructions to perform condition code register manipulation. Interrupts are not acknowledged until after the instruction following ANDP, ORP, TAP, and TDP has executed.
Refer to 5.11 Stop and Wait Instructions for more information.
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Table 5-29 Condition Code Summary
Mnemonic
Function
Operation
ANDP
AND CCR
(CCR) ¥ IMM16 ⇒ CCR[15:4]
ORP
OR CCR
(CCR) ; IMM16 ⇒ CCR[15:4]
TAP
Transfer A to CCR
(A[7:0]) ⇒ CCR[15:8]
TDP
Transfer D to CCR
(D) ⇒ CCR[15:4]
TPA
Transfer CCR MSB to A
(CCR[15:8]) ⇒ A
TPD
Transfer CCR to D
(CCR) ⇒ D
5.10 Digital Signal Processing Instructions
DSP instructions use the CPU16 multiply and accumulate unit to implement digital filters and other signal processing functions. Other instructions, notably those that operate on concatenated E and D accumulators, are also used. See SECTION 11
DIGITAL SIGNAL PROCESSING for more information.
Table 5-30 DSP Summary
Mnemonic
Function
Operation
ACE
Add E to AM[31:15]
(AM[31:15]) + (E) ⇒ AM
ACED
Add concatenated E and D to AM
(E : D) + (AM) ⇒ AM
ASLM
Arithmetic Shift Left AM
ASRM
Arithmetic Shift Right AM
CLRM
Clear AM
$000000000 ⇒ AM[35:0]
LDHI
Initialize HR and IR
(M : M + 1)X ⇒ HR
(M : M + 1)Y ⇒ IR
MAC
Multiply and Accumulate
Signed 16-Bit Fractions
(HR) ∗ (IR) ⇒ E : D
(AM) + (E : D) ⇒ AM
Qualified (IX) ⇒ IX
Qualified (IY) ⇒ IY
(HR) ⇒ IZ
(M : M + 1)X ⇒ HR
(M : M + 1)Y ⇒ IR
PSHMAC
Push MAC State
MAC Registers ⇒ Stack
PULMAC
Pull MAC State
Stack ⇒ MAC Registers
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Table 5-30 DSP Summary (Continued)
Mnemonic
Function
Operation
RMAC
Repeating
Multiply and Accumulate
Signed 16-Bit Fractions
Repeat until (E) < 0
(AM) + (H) ∗ (I) ⇒ AM
Qualified (IX) ⇒ IX;
Qualified (IY) ⇒ IY;
(M : M + 1)X ⇒ H;
(M : M + 1)Y ⇒ I
(E) – 1 ⇒ E
TDMSK
Transfer D to XMSK : YMSK
(D[15:8]) ⇒ X MASK
(D[7:0]) ⇒ Y MASK
TEDM
Transfer E and D to AM[31:0]
Sign Extend AM
(D) ⇒ AM[15:0]
(E) ⇒ AM[31:16]
AM[32:35] = AM31
TEM
Transfer E to AM[31:16]
Sign Extend AM
Clear AM LSB
(E) ⇒ AM[31:16]
$00 ⇒ AM[15:0]
AM[32:35] = AM31
TMER
Transfer AM to E Rounded
Rounded (AM) ⇒ Temp
If (SM • (EV ; MV))
then Saturation ⇒ E
else Temp[31:16] ⇒ E
TMET
Transfer AM to E Truncated
If (SM • (EV ; MV))
then Saturation ⇒ E
else AM[31:16] ⇒ E
TMXED
Transfer AM to IX : E : D
AM[35:32] ⇒ IX[3:0]
AM35 ⇒ IX[15:4]
AM[31:16] ⇒ E
AM[15:0] ⇒ D
5.11 Stop and Wait Instructions
There are two instructions that put the CPU16 in an inactive state. Both require that
either an interrupt or a reset exception occurs before normal execution of instructions
resumes. However, each operates differently.
LPSTOP minimizes microcontroller power consumption. The CPU16 initiates a stop,
but it and other controller modules are deactivated by the microcontroller system integration module. Reactivation is also handled by the integration module. The interrupt
priority field from the CPU16 condition code register is copied into the integration module external bus interface, then the system clock to the processor is stopped. When a
reset or an interrupt of higher priority than the IP value occurs, the integration module
activates the CPU16, and the appropriate exception processing sequence begins.
WAI idles the CPU16, but does not affect operation of other microcontroller modules.
The IP field is not copied to the integration module. System clocks continue to run. The
processor waits until a reset or an interrupt of higher priority than the IP value occurs,
then begins the appropriate exception processing sequence.
Because the system integration module does not restart the CPU16, interrupts are acknowledged more quickly following WAI than following LPSTOP. See SECTION 9 EXCEPTION PROCESSING for more information.
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To make certain that conditions for termination of LPSTOP and WAI are correct, interrupts are not recognized until after the instruction following ANDP, ORP, TAP, and
TDP executes. This prevents interrupt exception processing during the period after the
mask changes but before the following instruction executes.
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Table 5-31 Stop and Wait Summary
Mnemonic
Function
Operation
LPSTOP
Low Power Stop
If S
then STOP
else NOP
WAI
Wait for Interrupt
WAIT
5.12 Background Mode and Null Operations
Background debug mode is a special CPU16 operating mode that is used for system
development and debugging. Executing BGND when BDM is enabled puts the CPU16
in this mode. For complete information refer to SECTION 10 DEVELOPMENT SUPPORT.
Null operations are often used to replace other instructions during software debugging.
Replacing conditional branch instructions with BRN, for instance, permits testing a decision-making routine without actually taking the branches.
Table 5-32 Background Mode and Null Operations
Mnemonic
Function
Operation
BGND
Enter Background Debugging Mode
If BDM enabled
enter BDM;
else, illegal instruction
BRN
Branch Never
If 1 = 0, branch
LBRN
Long Branch Never
If 1 = 0, branch
NOP
Null operation
—
5.13 Comparison of CPU16 and M68HC11 Instruction Sets
Most M68HC11 instructions are a source-code compatible subset of the CPU16
instruction set. However, certain M68HC11 instructions have been replaced by functionally equivalent CPU16 instructions, and some M68HC11 instructions operate differently in the CPU16. APPENDIX A COMPARISON OF CPU16/M68HC11 CPU
ASSEMBLY LANGUAGE gives detailed information.
Table 5-33 shows M68HC11 instructions that have either been replaced by CPU16 instructions or that operate differently in the CPU16. Replacement instructions are not
identical to M68HC11 instructions; M68HC11 code must be altered to establish proper
preconditions.
All CPU16 instruction cycle counts and execution times differ from those of the
M68HC11. SECTION 6 INSTRUCTION GLOSSARY gives information on instruction
cycles. See SECTION 8 INSTRUCTION TIMING for information regarding calculation
of instruction cycle times.
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Table 5-33 CPU16 Implementation of M68HC11 Instructions
M68HC16 Implementation
BHS
Replaced by BCC
BLO
Replaced by BCS
BSR
Generates a different stack frame
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M68HC11 Instruction
CLC
Replaced by ANDP
CLI
Replaced by ANDP
CLV
Replaced by ANDP
DES
Replaced by AIS
DEX
Replaced by AIX
DEY
Replaced by AIY
INS
Replaced by AIS
INX
Replaced by AIX
INY
Replaced by AIY
JMP
IND8 addressing modes replaced by IND20 and EXT modes
JSR
IND8 addressing modes replaced by IND20 and EXT modes
Generates a different stack frame
LSL, LSLD
Use ASL instructions*
PSHX
Replaced by PSHM
PSHY
Replaced by PSHM
PULX
Replaced by PULM
PULY
Replaced by PULM
RTI
Reloads PC and CCR only
RTS
Uses two-word stack frame
SEC
Replaced by ORP
SEI
Replaced by ORP
SEV
Replaced by ORP
STOP
Replaced by LPSTOP
TAP
CPU16 CCR bits differ from M68HC11
CPU16 interrupt priority scheme differs from M68HC11
TPA
CPU16 CCR bits differ from M68HC11
CPU16 interrupt priority scheme differs from M68HC11
TSX
Adds two to SK : SP before transfer to XK : IX
TSY
Adds two to SK : SP before transfer to YK : IY
TXS
Subtracts two from XK : IX before transfer to SK : SP
TXY
Transfers XK field to YK field
TYS
Subtracts two from YK : IY before transfer to SK : SP
TYX
Transfers YK field to XK field
WAI
Waits indefinitely for interrupt or reset
Generates a different stack frame
*Motorola assemblers will automatically translate LSL mnemonics
MOTOROLA
5-24
INSTRUCTION SET
For More Information On This Product,
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CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SECTION 6 INSTRUCTION GLOSSARY
Freescale Semiconductor, Inc...
The instruction glossary presents detailed information concerning each CPU16 instruction in concise form. 6.1 Assembler Syntax shows standard assembler syntax
formats. 6.2 Instructions contains the glossary pages. 6.3 Condition Code Evaluation lists Boolean expressions used to determine the effect of instructions on condition
codes. 6.4 Instruction Set Summary is a quick reference to the instruction set.
6.1 Assembler Syntax
Addressing mode determines standard assembler syntax. Table 6-1 shows the standard formats. Bit set and clear instructions, bit condition branch instructions, jump
instructions, multiply and accumulate instructions, move instructions and register
stacking instructions have special syntax. Information on syntax is given on the appropriate glossary page. APPENDIX B MOTOROLA ASSEMBLER SYNTAX is a detailed syntax reference.
Table 6-1 Standard Assembler Formats
Addressing Mode
Instruction Mnemonic
E,Index Register Symbol
Extended
Instruction Mnemonic
Address Extension Operand
Immediate
Instruction Mnemonic
#Operand
Offset Operand,Index Register Symbol
Indexed
Instruction Mnemonic
Inherent
Instruction Mnemonic
Relative
Instruction Mnemonic
Displacement
6.2 Instructions
Each instruction is listed alphabetically by mnemonic. Each listing contains complete
information about instruction format, operation, and the effect an operation has on the
condition code register.
The number of system clock cycles required to execute each instruction is also shown.
Cycle counts are based on bus accesses that require two system clock cycles each,
a 16-bit data bus, and aligned access. Cycle counts include system clock cycles required for prefetch, operand access, and internal operation. See SECTION 8 INSTRUCTION TIMING for more information.
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
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MOTOROLA
6-1
Freescale Semiconductor, Inc.
LDX
MNEMONIC
Load Inde
Operation:
(M : M + 1) ⇒ X
SYMBOLIC DESCRIPTION
OF OPERATION
Description:
Loads the most significa
memory at the addres
DETAILED DESCRIPTION
OF OPERATION
Condition Codes and Boolean Form
S
X
H
—
—
∆
N: Set if MSB of resu
Freescale Semiconductor, Inc...
Z: Set if result is $00
EFFECT ON
CONDITION CODE REGISTER
STATUS BITS
V: 0; Cleared.
Addressing Modes, Machine Code, an
DETAILED SYNTAX
AND
CYCLE-BY-CYCLE
OPERATION
Source Form
Address Mode
Obje
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]
IMM
DIR
EXT
ID X
IDX1
IDX2
[D,IDX]
[IDX2]
CE jj
DE d
FE h
EE
E
E
EX GLO PG
Figure 6-1 Typical Instruction Glossary Entry
MOTOROLA
6-2
INSTRUCTION GLOSSARY
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CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ABA
Add B to A
ABA
Operation:
(A) + (B) ⇒ A
Description:
Adds the content of accumulator B to the content of accumulator A,
then places the result in accumulator A. Content of accumulator B
does not change. The ABA operation affects the CCR H bit, which
makes it useful for BCD arithmetic (see DAA for more information).
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
5
4
3
0
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
—
∆
∆
∆
∆
—
—
—
Not affected.
Not affected.
Set if there is a carry from bit 3 during addition; else cleared.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from A during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
370B
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
MOTOROLA
6-3
Freescale Semiconductor, Inc.
ABX
ABX
Add B to IX
Operation:
(XK : IX) + (000 : B) ⇒ XK : IX
Description:
Adds the zero-extended content of accumulator B to the content of
index register X, then places the result in index register X. Content
of accumulator B does not change. If IX overflows as a result of the
operation, the XK is incremented or decremented.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
—
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-4
Opcode
374F
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ABY
ABY
Add B to IY
Operation:
(YK : IY) + (000 : B) ⇒ YK : IY
Description:
Adds the zero-extended content of accumulator B to the content of
index register Y, then places the result in index register Y. Content of
accumulator B does not change. If IY overflows as a result of the operation, the YK is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
375F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-5
Freescale Semiconductor, Inc.
ABZ
ABZ
Add B to IZ
Operation:
(ZK : IZ) + (000 : B) ⇒ ZK : IZ
Description:
Adds the zero-extended content of accumulator B to the content of
index register Z, then places the result in index register Z. Content of
accumulator B does not change. If IZ overflows as a result of the operation, the ZK is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-6
Opcode
376F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ACE
ACE
Add E to AM
Operation:
(AM[31:16]) + (E) ⇒ AM
Description:
Adds the content of accumulator E to bits 31 to 16 of accumulator M,
then places the result in accumulator M. Bits 15 to 0 of accumulator
M are not affected. The value in E is assumed to be a 16-bit signed
fraction. See SECTION 11 DIGITAL SIGNAL PROCESSING for
more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
—
∆
—
—
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Set if overflow into AM35 occurs during addition; else not affected.
Not affected.
Set if overflow into AM[34:31] occurs during addition; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3722
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
MOTOROLA
6-7
Freescale Semiconductor, Inc.
ACED
Add E : D to AM
ACED
Operation:
(AM) + (E : D) ⇒ AM
Description:
The concatenated contents of accumulators E and D are added to
accumulator M. The value in the concatenated registers is assumed
to be a 32-bit signed fraction. See SECTION 11 DIGITAL SIGNAL
PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
5
4
3
0
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
—
∆
—
—
—
—
—
—
—
Not affected.
Set if overflow into AM35 occurs as a result of addition; else cleared.
Not affected.
Set if overflow into AM[34:31] occurs as a result of addition; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-8
Opcode
3723
Operand
—
INSTRUCTION GLOSSARY
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Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ADCA
ADCA
Add with Carry to A
Operation:
(A) + (M) + C ⇒ A
Description:
Adds the value of the CCR carry bit to the sum of the content of accumulator A and a memory byte, then places the result in accumulator A. Memory content is not affected. ADCA operation affects the
CCR H bit, which makes it useful for BCD arithmetic.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Set if there is a carry from bit 3 during addition; else cleared.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from A during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
43
53
63
73
1743
1753
1763
1773
2743
2753
2763
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
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Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-9
Freescale Semiconductor, Inc.
ADCB
ADCB
Add with Carry to B
Operation:
(B) + (M) + C ⇒ B
Description:
Adds the value of the CCR carry bit to the sum of the content of accumulator B and a memory byte, then places the result in accumulator B. Memory content is not affected. ADCB operation affects the
CCR H bit, which makes it useful for BCD arithmetic.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Set if there is a carry from bit 3 during addition; else cleared.
Not affected.
Set if B7 is set by operation; else cleared.
Set if B = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from B during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-10
Opcode
C3
D3
E3
F3
17C3
17D3
17E3
17F3
27C3
27D3
27E3
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
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Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ADCD
ADCD
Add with Carry to D
Operation:
(D) + (M : M + 1) + C ⇒ D
Description:
Adds the value of the CCR carry bit to the sum of the content of accumulator D and a memory word, then places the result in accumulator D. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from D during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
83
93
A3
37B3
37C3
37D3
37E3
37F3
2783
2793
27A3
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
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Cycles
6
6
6
4
6
6
6
6
6
6
6
MOTOROLA
6-11
Freescale Semiconductor, Inc.
ADCE
ADCE
Add with Carry to E
Operation:
(E) + (M : M + 1) + C ⇒ E
Description:
Adds the value of the CCR carry bit to the sum of the content of accumulator E and a memory word, then places the result in accumulator E. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from E during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-12
Opcode
3733
3743
3753
3763
3773
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
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Cycles
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ADDA
ADDA
Add to A
Operation:
(A) + (M) ⇒ A
Description:
Adds a memory byte to the content of accumulator A, then places
the result in accumulator A. Memory content is not affected. ADDA
affects the CCR H bit . It is used for BCD arithmetic.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
∆
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Set if operation requires a carry from A3; else cleared.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from A during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
41
51
61
71
1741
1751
1761
1771
2741
2751
2761
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-13
Freescale Semiconductor, Inc.
ADDB
ADDB
Add to B
Operation:
(B) + (M) ⇒ B
Description:
Adds a memory byte to the content of accumulator B, then places
the result in accumulator B. Memory content is not affected. ADDB
affects the CCR H bit — it is used for BCD arithmetic.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
∆
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Set if operation requires a carry from B3; else cleared.
Not affected.
Set if B7 is set by operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from B during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-14
Opcode
C1
D1
E1
F1
17C1
17D1
17E1
17F1
27C1
27D1
27E1
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ADDD
ADDD
Add to D
Operation:
(D) + (M : M + 1) ⇒ D
Description:
Adds a memory word to the content of accumulator D, then places
the result in accumulator D. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from D during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
81
91
A1
FC
37B1
37C1
37D1
37E1
37F1
2781
2791
27A1
Operand
ff
ff
ff
ii
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
4
6
6
6
6
6
6
6
MOTOROLA
6-15
Freescale Semiconductor, Inc.
ADDE
ADDE
Add to E
Operation:
(E) + (M : M + 1) ⇒ E
Description:
Adds a memory word to the content of accumulator E, then places
the result in accumulator E. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from E during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-16
Opcode
7C
3731
3741
3751
3761
3771
Operand
ii
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ADE
Add D to E
ADE
Operation:
(E) + (D) ⇒ E
Description:
Adds the content of accumulator D to the content of accumulator E,
then places the result in accumulator E. Content of accumulator D is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
5
4
3
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if there is a carry from E during operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
2778
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-17
Freescale Semiconductor, Inc.
ADX
Add D to IX
ADX
Operation:
(XK : IX) + (20 « D) ⇒ XK : IX
Description:
Sign-extends the content of accumulator D to 20 bits, then adds it to
the content of concatenated XK and IX. Content of accumulator D
does not change.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-18
Opcode
37CD
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ADY
Add D to IY
ADY
Operation:
(YK : IY) + (20 « D) ⇒ YK : IY
Description:
Sign-extends the content of accumulator D to 20 bits, then adds it to
the content of concatenated YK and IY. Content of accumulator D
does not change.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
37DD
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-19
Freescale Semiconductor, Inc.
ADZ
Add D to IZ
ADZ
Operation:
(ZK : IZ) + (20 « D) ⇒ ZK : IZ
Description:
Sign-extends the content of accumulator D to 20 bits, then adds it to
the content of concatenated ZK and IZ. Content of accumulator D
does not change.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-20
Opcode
37ED
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
AEX
Add E to IX
AEX
Operation:
(XK : IX) + (20 « E) ⇒ XK : IX
Description:
Sign-extends the content of accumulator E to 20 bits, then adds it to
the content of concatenated XK and IX. Content of accumulator E
does not change.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
374D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-21
Freescale Semiconductor, Inc.
AEY
Add E to IY
AEY
Operation:
(YK : IY) + (20 « E) ⇒ YK : IY
Description:
Sign-extends the content of accumulator E to 20 bits, then adds it to
the content of concatenated YK and IY. Content of accumulator E
does not change.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-22
Opcode
375D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
AEZ
Add E to IZ
AEZ
Operation:
(ZK : IZ) + (20 « E) ⇒ ZK : IZ
Description:
Sign-extends the content of accumulator E to 20 bits, then adds it to
the content of concatenated ZK and IZ. Content of accumulator E
does not change.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
376D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-23
Freescale Semiconductor, Inc.
AIS
AIS
Add Immediate Value to Stack Pointer
Operation:
(SK : SP) + (20 « IMM)⇒ SK : SP
Description:
Adds a 20-bit value to concatenated SK and SP. The 20-bit value is
formed by sign-extending an 8-bit or 16-bit signed immediate operand.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
IMM8
IMM16
MOTOROLA
6-24
Opcode
3F
373F
Operand
ii
jjkk
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
AIX
AIX
Add Immediate Value to IX
Operation:
(XK : IX) + (20 « IMM) ⇒ XK : IX
Description:
Adds a 20-bit value to the concatenated XK and IX. The 20-bit value
is formed by sign-extending an 8-bit or 16-bit signed immediate operand.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
∆
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set if (IX) = $0000 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM8
IMM16
CPU16
REFERENCE MANUAL
Opcode
3C
373C
Operand
ii
jjkk
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
4
MOTOROLA
6-25
Freescale Semiconductor, Inc.
AIY
AIY
Add Immediate Value to IY
Operation:
(YK : IY) + (20 « IMM) ⇒ YK : IY
Description:
Adds a 20-bit value to the concatenated YK and IY. The 20-bit value
is formed by sign-extending an 8-bit or 16-bit signed immediate operand.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
∆
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set if (IY) = $0000 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM8
IMM16
MOTOROLA
6-26
Opcode
3D
373D
Operand
ii
jjkk
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
AIZ
AIZ
Add Immediate Value to IZ
Operation:
(ZK : IZ) + (20 « IMM) ⇒ ZK : IZ
Description:
Adds a 20-bit value to the concatenated ZK and IZ. The 20-bit value
is formed by sign-extending an 8-bit or 16-bit signed immediate operand.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
∆
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set if (IZ) = $0000 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM8
IMM16
CPU16
REFERENCE MANUAL
Opcode
3E
373E
Operand
ii
jjkk
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
4
MOTOROLA
6-27
Freescale Semiconductor, Inc.
ANDA
ANDA
AND A
Operation:
(A) ≤ (M) ⇒ A
Description:
Performs AND between the content of accumulator A and a memory
byte, then places the result in accumulator A. Memory content is not
affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-28
Opcode
46
56
66
76
1746
1756
1766
1776
2746
2756
2766
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ANDB
ANDB
AND B
Operation:
(B) ≤ (M) ⇒ B
Description:
Performs AND between the content of accumulator B and a memory
byte, then places the result in accumulator B. Memory content is not
affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 is set by operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
C6
D6
E6
F6
17C6
17D6
17E6
17F6
27C6
27D6
27E6
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-29
Freescale Semiconductor, Inc.
ANDD
ANDD
AND D
Operation:
(D) ≤ (M : M + 1) ⇒ D
Description:
Performs AND between the content of accumulator D and a memory
word, then places the result in accumulator D. Memory content is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-30
Opcode
86
96
A6
37B6
37C6
37D6
37E6
37F6
2786
2796
27A6
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ANDE
ANDE
AND E
Operation:
(E) ≤ (M : M + 1) ⇒ E
Description:
Performs AND between the content of accumulator E and a memory
word, then places the result in accumulator E. Memory content is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
3736
3746
3756
3766
3776
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
6
6
6
6
MOTOROLA
6-31
Freescale Semiconductor, Inc.
ANDP
ANDP
AND Condition Code Register
Operation:
(CCR) ≤ IMM16 ⇒ CCR
Description:
Performs AND between the content of the condition code register
and an unsigned immediate operand, then replaces the content of
the CCR with the result.
Freescale Semiconductor, Inc...
To make certain that conditions for termination of LPSTOP and WAI
are correct, interrupts are not recognized until after the instruction
following ANDP executes. This prevents interrupt exception processing during the period after the mask changes but before the following instruction executes.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Cleared if bit 15 of operand = 0; else unchanged.
Cleared if bit 14 of operand = 0; else unchanged.
Cleared if bit 13 of operand = 0; else unchanged.
Cleared if bit 12 of operand = 0; else unchanged.
Cleared if bit 11 of operand = 0; else unchanged.
Cleared if bit 10 of operand = 0; else unchanged.
Cleared if bit 9 of operand = 0; else unchanged.
Cleared if bit 8 of operand = 0; else unchanged.
Each bit in field cleared if corresponding bit [7:5] of operand = 0; else unchanged.
Cleared if bit 4 of operand = 0; else unchanged.
Not affected.
Instruction Format:
Addressing Mode
IMM16
MOTOROLA
6-32
Opcode
373A
Operand
jjkk
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASL
ASL
Arithmetic Shift Left
Operation:
Description:
Shifts all eight bits of a memory byte one place to the left. Bit 7 is
transferred to the CCR C bit. Bit 0 is loaded with a zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M7 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
04
14
24
1704
1714
1724
1734
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
MOTOROLA
6-33
Freescale Semiconductor, Inc.
ASLA
ASLA
Arithmetic Shift Left A
Operation:
Description:
Shifts all eight bits of accumulator A one place to the left. Bit 7 is
transferred to the CCR C bit. Bit 0 is loaded with a zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if A7 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-34
Opcode
3704
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASLB
ASLB
Arithmetic Shift Left B
Operation:
Description:
Shifts all eight bits of accumulator B one place to the left. Bit 7 is
transferred to the CCR C bit. Bit 0 is loaded with a zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if B7 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3714
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-35
Freescale Semiconductor, Inc.
ASLD
ASLD
Arithmetic Shift Left D
Operation:
Description:
Shifts all sixteen bits of accumulator D one place to the left. Bit 15 is
transferred to the CCR C bit. Bit 0 is loaded with a zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if D15 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-36
Opcode
27F4
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASLE
ASLE
Arithmetic Shift Left E
Operation:
Description:
Shifts all sixteen bits of accumulator E one place to the left. Bit 15 is
transferred to the CCR C bit. Bit 0 is loaded with a zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if E15 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
2774
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-37
Freescale Semiconductor, Inc.
ASLM
ASLM
Arithmetic Shift Left AM
Operation:
Description:
Shifts all 36 bits of accumulator M one place to the left. Bit 35 is
transferred to the CCR C bit. Bit 0 is loaded with a zero. See SECTION 11 DIGITAL SIGNAL PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
—
∆
∆
—
—
∆
—
—
—
0
Not affected.
Set if AM[35] has changed state as a result of operation; else unchanged.
Not affected.
Cleared if AM[34:31] = $0000 or $1111 as a result of operation; else set.
Set if M35 = 1 as a result of operation; else cleared.
Not affected.
Not affected.
Set if AM35 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-38
Opcode
27B6
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASLW
ASLW
Arithmetic Shift Left Word
Operation:
Description:
Shifts all sixteen bits of memory word one place to the left. Bit 15 is
transferred to the CCR C bit. Bit 0 is loaded with a zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M : M + 1[15] = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
2704
2714
2724
2734
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
MOTOROLA
6-39
Freescale Semiconductor, Inc.
ASR
ASR
Arithmetic Shift Right
Operation:
Description:
Shifts all eight bits of a memory byte one place to the right. Bit 7 is
held constant. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 set as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-40
Opcode
0D
1D
2D
170D
171D
172D
173D
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASRA
ASRA
Arithmetic Shift Right A
Operation:
Description:
Shifts all eight bits of accumulator A one place to the right. Bit 7 is
held constant. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if A0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
370D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-41
Freescale Semiconductor, Inc.
ASRB
ASRB
Arithmetic Shift Right B
Operation:
Description:
Shifts all eight bits of accumulator B one place to the right. Bit 7 is
held constant. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if B0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-42
Opcode
371D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASRD
ASRD
Arithmetic Shift Right D
Operation:
Description:
Shifts all sixteen bits of accumulator D one place to the right. Bit 15
is held constant. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if D0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27FD
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-43
Freescale Semiconductor, Inc.
ASRE
ASRE
Arithmetic Shift Right E
Operation:
Description:
Shifts all sixteen bits of accumulator E one place to the right. Bit 15
is held constant. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if E0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-44
Opcode
277D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ASRM
ASRM
Arithmetic Shift Right AM
Operation:
Description:
Shifts all 36 bits of accumulator M one place to the right. Bit 35 is
held constant. Bit 0 is transferred to the CCR C bit. See SECTION
11 DIGITAL SIGNAL PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
∆
∆
—
—
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Cleared if AM[34:31] = $0000 or $1111 as a result of operation; else set.
Set if AM35 = 1 as a result of operation; else cleared.
Not affected.
Not affected.
Set if AM0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27BA
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
MOTOROLA
6-45
Freescale Semiconductor, Inc.
ASRW
ASRW
Arithmetic Shift Right Word
Operation:
Description:
Shifts all sixteen bits of a memory word one place to the right. Bit 15
is held constant. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M : M + 1[0] = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-46
Opcode
270D
271D
272D
273D
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BCC
Branch If Carry Clear
BCC
Operation:
If C = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR carry bit has a value of zero.
An 8-bit signed relative offset is added to the current value of the
program counter. When the operation causes PC overflow, the PK
field is incremented or decremented. Used to implement simple or
unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B4
Operand
rr
Cycles
6, 2
Table 6-2 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-47
Freescale Semiconductor, Inc.
BCLR
BCLR
Clear Bits
Operation:
(M) ≤ (Mask) ⇒ M
Description:
Performs AND between a memory byte and the complement of a
mask byte. Bits in the mask are set to clear corresponding bits in
memory. Other bits in the memory byte are unchanged. The location
of the mask differs for 8- and 16-bit addressing modes.
Syntax:
BCLR address operand, [register symbol,] #mask
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-48
Opcode
1708
1718
1728
08
18
28
38
Mask
mm
mm
mm
mm
mm
mm
mm
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BCLRW
BCLRW
Clear Bits in a Word
Operation:
(M : M + 1) ≤ (Mask) ⇒ M : M + 1
Description:
Performs AND between a memory word and the complement of a
mask word. Bits in the mask are set to clear corresponding bits in
memory. Other bits in the memory word are unchanged.
Syntax:
BCLRW Address Operand, [Index Register Symbol,] #Mask
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M15 = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
2708
2718
2728
2738
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Mask
mmmm
mmmm
mmmm
mmmm
Cycles
10
10
10
10
MOTOROLA
6-49
Freescale Semiconductor, Inc.
BCS
BCS
Branch If Carry Set
Operation:
If C = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR carry bit has a value of one.
An 8-bit signed relative offset is added to the current value of the
program counter. When the operation causes PC overflow, the PK
field is incremented or decremented. Used to implement simple or
unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B5
Operand
rr
Cycles
6, 2
Table 6-3 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-50
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BEQ
Branch If Equal to Zero
BEQ
Operation:
If Z = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR zero bit has a value of one. An
8-bit signed relative offset is added to the current value of the program counter. When the operation causes PC overflow, the PK field
is incremented or decremented. Used to implement simple, signed,
or unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B7
Operand
rr
Cycles
6, 2
Table 6-4 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-51
Freescale Semiconductor, Inc.
BGE
BGE
Branch If Greater than or Equal to Zero
Operation:
If N ⊕ V = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR negative and overflow bits
both have a value of zero or both have a value of one. An 8-bit
signed relative offset is added to the current value of the program
counter. When the operation causes PC overflow, the PK field is incremented or decremented. Used to implement signed conditional
branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
BC
Operand
rr
Cycles
6, 2
Table 6-5 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-52
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BGND
Enter Background Debug Mode
BGND
Operation:
If background debug mode is enabled, begin debug; else, illegal instruction trap
Description:
Background debug mode is an operating mode in which the CPU16
microcode performs debugging functions. To prevent accidental entry, a specific method of enabling BDM is used. If BDM has been
correctly enabled, executing BGND will cause the CPU16 to suspend normal operation. If BDM has not been correctly enabled, an
illegal instruction exception is generated. See SECTION 9 EXCEPTION PROCESSING for more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
37A6
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
N/A
MOTOROLA
6-53
Freescale Semiconductor, Inc.
BGT
BGT
Branch If Greater than Zero
Operation:
If Z ✛ (N ⊕ V) = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR negative and overflow bits
both have a value of zero or both have a value of one, and the CCR
zero bit has a value of zero. An 8-bit signed relative offset is added
to the current value of the program counter. When the operation
causes PC overflow, the PK field is incremented or decremented.
Used to implement signed conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
BE
Operand
rr
Cycles
6, 2
Table 6-6 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-54
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BHI
BHI
Branch If Higher
Operation:
If C ✛ Z = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR carry and zero bits both have
a value of zero. An 8-bit signed relative offset is added to the current
value of the program counter. When the operation causes PC overflow, the PK field is incremented or decremented. Used to implement unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B2
Operand
rr
Cycles
6, 2
Table 6-7 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-55
Freescale Semiconductor, Inc.
BITA
BITA
Bit Test A
Operation:
(A) ≤ (M)
Description:
Performs AND between the content of accumulator A and corresponding bits in a memory byte. Condition codes are set, but neither
accumulator content nor memory content is changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 ≤ M7 = 1; else cleared.
Set if (A) ≤ (M) = $00; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-56
Opcode
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BITB
BITB
Bit Test B
Operation:
(B) ≤ (M)
Description:
Performs AND between the content of accumulator B and corresponding bits in a memory byte. Condition codes are set, but neither
accumulator content nor memory content is changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 ≤ M7 = 1; else cleared.
Set if (B) ≤ (M) = $00; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
C9
D9
E9
F9
17C9
17D9
17E9
17F9
27C9
27D9
27E9
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-57
Freescale Semiconductor, Inc.
BLE
BLE
Branch If Less than or Equal to Zero
Operation:
If Z ✛ (N ⊕ V) = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if either the CCR negative bit or overflow
bit has a value of one, or the CCR zero bit has a value of one. An 8bit signed relative offset is added to the current value of the program
counter. When the operation causes PC overflow, the PK field is incremented or decremented. Used to implement signed conditional
branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
BF
Operand
rr
Cycles
6, 2
Table 6-8 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-58
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BLS
Branch If Lower or Same
BLS
Operation:
If C ✛ Z = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if either or both the CCR carry and zero
bits have a value of one. An 8-bit signed relative offset is added to
the current value of the program counter. When the operation causes PC overflow, the PK field is incremented or decremented. Used
to implement unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B3
Operand
rr
Cycles
6, 2
Table 6-9 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-59
Freescale Semiconductor, Inc.
BLT
BLT
Branch If Less than Zero
Operation:
If N ⊕ V = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if either of the CCR negative or overflow
bits has a value of one. An 8-bit signed relative offset is added to the
current value of the program counter. When the operation causes
PC overflow, the PK field is incremented or decremented. Used to
implement signed conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
BD
Operand
rr
Cycles
6, 2
Table 6-10 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-60
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BMI
Branch If Minus
BMI
Operation:
If N = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR negative bit has a value of
one. An 8-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple
conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
BB
Operand
rr
Cycles
6, 2
Table 6-11 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-61
Freescale Semiconductor, Inc.
BNE
BNE
Branch If Not Equal to Zero
Operation:
If Z = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR zero bit has a value of zero. An
8-bit signed relative offset is added to the current value of the program counter. When the operation causes PC overflow, the PK field
is incremented or decremented. Used to implement simple, signed,
and unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B6
Operand
rr
Cycles
6, 2
Table 6-12 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-62
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BPL
BPL
Branch If Plus
Operation:
If N = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR negative bit has a value of zero. An 8-bit signed relative offset is added to the current value of the
program counter. When the operation causes PC overflow, the PK
field is incremented or decremented. Used to implement simple conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
BA
Operand
rr
Cycles
6, 2
Table 6-13 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-63
Freescale Semiconductor, Inc.
BRA
BRA
Branch Always
Operation:
(PK : PC) + Offset ⇒ PK : PC
Description:
Always branches. An 8-bit signed relative offset is added to the current value of the program counter. When the operation causes PC
overflow, the PK field is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
REL8
Opcode
B0
Operand
rr
Cycles
6
Table 6-14 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-64
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BRCLR
BRCLR
Branch if Bits Clear
Operation:
If (M) ≤ (Mask) = 0, (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch when specified bits in memory have values of zero. Performs AND between a memory byte and a mask
byte. The memory byte is pointed to by a 20-bit indexed or extended
effective address.
If a mask bit has a value of one, the corresponding memory bit must
have a value of zero. When the result of the operation is zero, an 8or 16-bit signed relative offset is added to the current value of the
program counter. When the operation causes PC overflow, the PK
field is incremented or decremented.
Syntax:
BRCLR address operand, [register symbol,] #mask, displacement
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
CB
DB
EB
0A
1A
2A
3A
Mask
mm
mm
mm
mm
mm
mm
mm
Addr Operand
ff
ff
ff
gggg
gggg
gggg
hhll
Branch Offset
rr
rr
rr
rrrr
rrrr
rrrr
rrrr
INSTRUCTION GLOSSARY
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Cycles
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
MOTOROLA
6-65
Freescale Semiconductor, Inc.
BRN
BRN
Branch Never
Operation:
(PK : PC) + 2 ⇒ PK : PC
Description:
Never branches. This instruction is effectively a NOP that requires
two cycles to execute. When the operation causes PC overflow, the
PK field is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
REL8
Opcode
B1
Operand
rr
Cycles
2
Table 6-15 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-66
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BRSET
BRSET
Branch if Bits Set
Operation:
If (M) ≤ (Mask) = 0, (PC) + Offset ⇒ PK : PC
Description:
Causes a program branch when specified bits in memory have values of one. Performs AND between the complement of memory byte
and a mask byte. The memory byte is pointed to by a 20-bit indexed
or extended effective address.
If a mask bit has a value of one, the corresponding (uncomplemented) memory bit must have a value of one. When the result of the operation is zero, an 8- or 16-bit signed relative offset is added to the
current value of the program counter. When the operation causes
PC overflow, the PK field is incremented or decremented.
Syntax:
BRSET address operand, [register symbol,] #mask, displacement
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
8B
9B
AB
0B
1B
2B
3B
Mask
mm
mm
mm
mm
mm
mm
mm
Addr Operand
ff
ff
ff
gggg
gggg
gggg
hhll
Branch Offset
rr
rr
rr
rrrr
rrrr
rrrr
rrrr
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
MOTOROLA
6-67
Freescale Semiconductor, Inc.
BSET
BSET
Set Bits in a Byte
Operation:
(M) ✛ (MASK) ⇒ M
Description:
Performs OR between a memory byte and a mask byte. Bits in the
mask are set to set corresponding bits in memory. Other bits in the
memory word are unchanged. The location of the mask differs for 8and 16-bit addressing modes.
Syntax:
BSET address operand, [register symbol,] #mask
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-68
Opcode
1709
1719
1729
09
19
29
39
Mask
mm
mm
mm
mm
mm
mm
mm
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BSETW
BSETW
Set Bits in a Word
Operation:
(M : M + 1) ✛ (Mask) ⇒ M : M + 1
Description:
Performs OR between a memory word and a mask word. Set bits in
the mask to set corresponding bits in memory. Other bits in the
memory word are unchanged.
Syntax:
BSETW address operand, [register symbol,] #mask
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M15 = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
2709
2719
2729
2739
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Mask
mmmm
mmmm
mmmm
mmmm
Cycles
10
10
10
10
MOTOROLA
6-69
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
BSR
Branch to Subroutine
BSR
Operation:
(PK : PC) − $0002 ⇒ PK : PC
Push (PC)
(SK : SP) − $0002 ⇒ SK : SP
Push (CCR)
(SK : SP) − $0002 ⇒ SK : SP
(PK : PC) + Offset ⇒ PK : PC
Description:
Saves current program address and status, then branches to a subroutine. PK : PC are adjusted so that program execution will resume
correctly after return from subroutine.
The program counter is stacked, then the condition code register is
stacked (PK field as well as condition code bits and interrupt priority
mask). An 8-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
MOTOROLA
6-70
Opcode
36
Operand
rr
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
10
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
BVC
Branch If Overflow Clear
BVC
Operation:
If V = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR overflow bit has a value of zero. An 8-bit signed relative offset is added to the current value of the
program counter. When the operation causes PC overflow, the PK
field is incremented or decremented. Used to implement simple,
signed, and unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B8
Operand
rr
Cycles
6, 2
Table 6-16 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
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Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
MOTOROLA
6-71
Freescale Semiconductor, Inc.
BVS
BVS
Branch If Overflow Set
Operation:
If V = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a program branch if the CCR overflow bit has a value of
one. An 8-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple,
signed, and unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL8
Opcode
B9
Operand
rr
Cycles
6, 2
Table 6-17 Branch Instruction Summary (8-Bit Offset)
Mnemonic
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BVC
BVS
MOTOROLA
6-72
Opcode
B4
B5
B7
BC
BE
B2
BF
B3
BD
BB
B6
BA
B0
B1
B8
B9
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
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Complement
BCS
BCC
BNE
BLT
BLE
BLS
BGT
BHI
BGE
BPL
BEQ
BMI
BRN
BRA
BVS
BVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CBA
CBA
Compare B to A
Operation:
(A) − (B)
Description:
Subtracts the content of accumulator B from the content of accumulator A and sets appropriate condition code register bits. The contents of the accumulators are not changed by the operation, and no
result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R7 = 1 as a result of operation; else cleared.
Set if (A) − (B) = $00; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
371B
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-73
Freescale Semiconductor, Inc.
CLR
CLR
Clear a Byte in Memory
Operation:
$00 ⇒ M
Description:
Content of a memory byte is cleared to zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
0
1
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-74
Opcode
05
15
25
1705
1715
1725
1735
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CLRA
CLRA
Clear A
Operation:
$00 ⇒ A
Description:
Content of accumulator A is cleared to zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
0
1
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3705
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-75
Freescale Semiconductor, Inc.
CLRB
CLRB
Clear B
Operation:
$00 ⇒ B
Description:
Content of accumulator B is cleared to zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
0
1
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-76
Opcode
3715
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CLRD
CLRD
Clear D
Operation:
$0000 ⇒ D
Description:
Content of accumulator D is cleared to zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
0
1
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27F5
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-77
Freescale Semiconductor, Inc.
CLRE
CLRE
Clear E
Operation:
$0000 ⇒ E
Description:
Content of accumulator E is cleared to zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
0
1
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-78
Opcode
2775
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CLRM
CLRM
Clear AM
Operation:
$000000000 ⇒ AM[35:0]
Description:
Content of MAC accumulator is cleared to zero. See SECTION 11
DIGITAL SIGNAL PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
0
—
0
—
—
—
—
—
—
—
0
Not affected.
Cleared.
Not affected.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27B7
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-79
Freescale Semiconductor, Inc.
CLRW
CLRW
Clear a Word in Memory
Operation:
$0000 ⇒ M : M + 1
Description:
Content of a memory word is cleared to zero.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
0
1
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-80
Opcode
2705
2715
2725
2735
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CMPA
CMPA
Compare A
Operation:
(A) − (M)
Description:
Subtracts content of a memory byte from content of accumulator A
and sets condition code register bits. Accumulator and memory contents are not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R7 = 1 as a result of operation; else cleared.
Set if (A) − (M) = $00; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
48
58
68
78
1748
1758
1768
1778
2748
2758
2768
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-81
Freescale Semiconductor, Inc.
CMPB
CMPB
Compare B
Operation:
(B) − (M)
Description:
Subtracts content of a memory byte from content of accumulator B
and sets condition code register bits. Accumulator and memory contents are not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R7 = 1 as a result of operation; else cleared.
Set if (B) − (M) = $00; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-82
Opcode
C8
D8
E8
F8
17C8
17D8
17E8
17F8
27C8
27D8
27E8
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
COM
COM
One’s Complement Byte
Operation:
$FF − (M) ⇒ M, or M ⇒ M
Description:
Replaces content of a memory byte with its one’s complement. Only
BEQ and BNE branches will perform consistently immediately after
COM on unsigned values. All signed branches are available after
COM on two’s complement values.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
1
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 is set; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Cleared.
Set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
00
10
20
1700
1710
1720
1730
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
MOTOROLA
6-83
Freescale Semiconductor, Inc.
COMA
COMA
One’s Complement A
Operation:
$FF − (A) ⇒ A, or M ⇒ A
Description:
Replaces content of accumulator A with its one’s complement. Only
BEQ and BNE branches will perform consistently immediately after
COMA on an unsigned value. All signed branches are available after
COMA on a two’s complement value.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
1
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-84
Opcode
3700
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
COMB
COMB
One’s Complement B
Operation:
$FF − (B) ⇒ B, or B ⇒ B
Description:
Replaces content of accumulator B with its one’s complement. Only
BEQ and BNE branches will perform consistently immediately after
COMB on an unsigned value. All signed branches are available after
COMB on a two’s complement value.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
1
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3710
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-85
Freescale Semiconductor, Inc.
COMD
COMD
One’s Complement D
Operation:
$FFFF − (D) ⇒ D, or D ⇒ D
Description:
Replaces content of accumulator D with its one’s complement. Only
BEQ and BNE branches will perform consistently immediately after
COMD on an unsigned value. All signed branches are available after
COMD on a two’s complement value.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
1
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-86
Opcode
27F0
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
COME
COME
One’s Complement E
Operation:
$FFFF − (E) ⇒ E, or E ⇒ E
Description:
Replaces content of accumulator E with its one’s complement. Only
BEQ and BNE branches will perform consistently immediately after
COME on an unsigned value. All signed branches are available after
COME on a two’s complement value.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
1
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
2770
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-87
Freescale Semiconductor, Inc.
COMW
COMW
One’s Complement Word
Operation:
$FFFF − (M : M + 1) ⇒ M : M + 1, or
(M : M + 1) ⇒ M : M + 1
Description:
Replaces content of a memory word with its one’s complement.
Only BEQ and BNE branches will perform consistently immediately
after COMW on unsigned values. All signed branches are available
after COMW on two’s complement values.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
1
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M15 is set; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Cleared.
Set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-88
Opcode
2700
2710
2720
2730
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CPD
CPD
Compare D
Operation:
(D) − (M : M + 1)
Description:
Subtracts content of a memory word from content of accumulator D
and sets condition code register bits. Accumulator and memory contents are not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R15 = 1 as a result of operation; else cleared.
Set if (D) − (M) = $0000; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
88
98
A8
37B8
37C8
37D8
37E8
37F8
2788
2798
27A8
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
6
6
6
MOTOROLA
6-89
Freescale Semiconductor, Inc.
CPE
CPE
Compare E
Operation:
(E) − (M : M + 1)
Description:
Subtracts content of a memory word from content of accumulator E
and sets condition code register bits. Accumulator and memory contents are not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R15 = 1 as a result of operation; else cleared.
Set if (E) − (M) = $0000; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-90
Opcode
3738
3748
3758
3768
3778
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CPS
CPS
Compare Stack Pointer
Operation:
(SP) − (M : M + 1)
Description:
Subtracts content of a memory word from content of the stack pointer and sets condition code register bits. SP and memory contents
are not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R15 = 1 as a result of operation; else cleared.
Set if (SP) − (M) = $0000; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
4F
5F
6F
377F
174F
175F
176F
177F
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
MOTOROLA
6-91
Freescale Semiconductor, Inc.
CPX
CPX
Compare IX
Operation:
(IX) − (M : M + 1)
Description:
Subtracts content of a memory word from content of index register X
and sets condition code register bits. IX and memory contents are
not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R15 = 1 as a result of operation; else cleared.
Set if (IX) − (M) = $0000; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-92
Opcode
4C
5C
6C
377C
174C
175C
176C
177C
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
CPY
CPY
Compare IY
Operation:
(IY) − (M : M + 1)
Description:
Subtracts content of a memory word from content of index register Y
and sets condition code register bits. IY and memory contents are
not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R15 = 1 as a result of operation; else cleared.
Set if (IY) − (M) = $0000; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
4D
5D
6D
377D
174D
175D
176D
177D
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
MOTOROLA
6-93
Freescale Semiconductor, Inc.
CPZ
CPZ
Compare IZ
Operation:
(IZ) − (M : M + 1)
Description:
Subtracts content of a memory word from content of index register Z
and sets condition code register bits. IZ and memory contents are
not changed, and no result is stored.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if R15 = 1 as a result of operation; else cleared.
Set if (IZ) − (M) = $0000; else cleared.
Set if operation causes two’s complement overflow; else cleared.
Set if operation requires a borrow; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-94
Opcode
4E
5E
6E
377E
174E
175E
176E
177E
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
DAA
DAA
Decimal Adjust A
Operation:
(A)10
Description:
Adjusts the content of accumulator A and the state of the CCR carry
bit after binary-coded decimal operations, so that there is a correct
BCD sum and an accurate carry indication. The state of the CCR
half carry bit affects operation. Table 6-18 shows details of operation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
U
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Undefined.
See Table 6-18.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3721
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-95
Freescale Semiconductor, Inc.
DAA
DAA
Decimal Adjust A
Freescale Semiconductor, Inc...
Table 6-18 DAA Function Summary
1
Initial
C Bit Value
0
0
0
0
0
0
1
1
1
2
Value of
A[7:4]
0–9
0–8
0–9
A–F
9–F
A–F
0–2
0–2
0–3
3
Initial
H Bit Value
0
0
1
0
0
1
0
0
1
4
Value of
A[3:0]
0–9
A–F
0–3
0–9
A–F
0–3
0–9
A–F
0–3
5
Correction
Factor
00
06
06
60
66
66
60
66
66
6
Corrected
C Bit Value
0
0
0
1
1
1
1
1
1
The table shows DAA operation for all legal combinations of input operands. Columns
1 through 4 represent the results of ABA, ADC, or ADD operations on BCD operands.
The correction factor in column 5 is added to the accumulator to restore the result of
an operation on two BCD operands to a valid BCD value, and to set or clear the C bit.
All values are in hexadecimal.
MOTOROLA
6-96
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
DEC
DEC
Decrement Byte
Operation:
(M) − $01 ⇒ M
Description:
Subtracts $01 from the content of a memory byte. Only BEQ and
BNE branches will perform consistently immediately after DEC on
unsigned values. All signed branches are available after DEC on
two’s complement values. Because DEC does not affect the C bit in
the condition code register, it can be used to implement a loop
counter in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (M) = $80 before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
01
11
21
1701
1711
1721
1731
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
MOTOROLA
6-97
Freescale Semiconductor, Inc.
DECA
DECA
Decrement A
Operation:
(A) − $01 ⇒ A
Description:
Subtracts $01 from the content of accumulator A. Only BEQ and
BNE branches will perform consistently immediately after DECA on
unsigned values. All signed branches are available after DECA on
two’s complement values. Because DECA does not affect the C bit
in the condition code register, it can be used to implement a loop
counter in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if (A) = $80 before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-98
Opcode
3701
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
DECB
DECB
Decrement B
Operation:
(B) − $01 ⇒ B
Description:
Subtracts $01 from the content of accumulator B. Only BEQ and
BNE branches will perform consistently immediately after DECB on
unsigned values. All signed branches are available after DECB on
two’s complement values. Because DECB does not affect the C bit
in the condition code register, it can be used to implement a loop
counter in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (B) = $80 before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3711
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-99
Freescale Semiconductor, Inc.
DECW
DECW
Decrement Word
Operation:
(M : M + 1) − $0001 ⇒ M : M + 1
Description:
Subtracts $0001 from the content of a memory word. Only BEQ and
BNE branches will perform consistently immediately after DECW on
unsigned values. All signed branches are available after DECW on
two’s complement values. Because DECW does not affect the C bit
in the condition code register, it can be used to implement a loop
counter in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (M : M + 1) = $8000 before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-100
Opcode
2701
2711
2721
2731
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
EDIV
EDIV
Extended Unsigned Integer Divide
Operation:
(E : D) / (IX) ⇒ IX
Remainder ⇒ D
Description:
Divides a 32-bit unsigned dividend contained in concatenated accumulators E and D by a 16-bit divisor contained in index register X.
The quotient is placed in IX and the remainder in D. There is an implied radix point to the right of the quotient (IX0). An implied radix
point is assumed to occupy the same position in both dividend and
divisor.
The states of condition code register bits N, Z, V, and C are undefined after division by zero, but accumulator contents are not
changed. Division by zero causes an exception. See SECTION 9
EXCEPTION PROCESSING for more information. The states of the
N, Z, and C bits are also undefined after overflow.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if IX15 = 1 as a result of operation; else cleared. Undefined after overflow or division by zero.
Set if (IX) = $0000 as a result of operation; else cleared. Undefined after overflow or division by zero.
Set if (IX) > $FFFF as a result of operation; else cleared. Undefined after division by zero.
Set if 2 ∗ Remainder ≥ Divisor; else cleared. Undefined after overflow or division by zero.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3728
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
24
MOTOROLA
6-101
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
EDIVS
EDIVS
Extended Signed Integer Divide
Operation:
(E : D) / (IX) ⇒ IX
Remainder ⇒ D
Description:
Divides a 32-bit signed dividend contained in concatenated accumulators E and D by a 16-bit divisor contained in index register X. The
quotient is placed in IX and the remainder in D. There is an implied
radix point to the right of IX0. Implied radix points in dividend and divisor must occupy the same bit position.
The states of condition code register bits N, Z, and C are undefined
after overflow. The states of bits N, Z, V, and C are undefined after
division by zero, but accumulator contents are not changed. Division
by zero causes an exception. See SECTION 9 EXCEPTION PROCESSING for more information.
Syntax:
Standard
Condition Code Register:
15
14
13
12
S
—
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
S:
Not affected.
MV:
Not affected.
H:
Not affected.
EV:
Not affected.
N:
Set if IX15 = 1 as a result of operation; else cleared. Undefined after overflow or division by zero.
Z:
Set if (IX) = $0000 as a result of operation; else cleared. Undefined after overflow or division by zero.
V:
Set if (IX) > $7FFF for a positive quotient or if (IX) > $8000 for a negative quotient as a result of operation;
else cleared. Undefined after division by zero.
C:
Set if 2 ∗ Remainder ≥ Divisor; else cleared. Undefined after overflow or division by zero.
IP:
Not affected.
SM:
Not affected.
PK:
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-102
Opcode
3729
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
38
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
EMUL
EMUL
Extended Unsigned Multiply
Operation:
(E) ∗ (D) ⇒ E : D
Description:
Multiplies a 16-bit unsigned multiplicand contained in accumulator E
by a 16-bit unsigned multiplier contained in accumulator D, then
places the product in concatenated accumulators E and D. The CCR
carry bit can be used to round the high word of the product — execute EMUL, then ADCE #0.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
—
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E : D) = $00000000 as a result of operation; else cleared.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3725
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
10
MOTOROLA
6-103
Freescale Semiconductor, Inc.
EMULS
EMULS
Extended Signed Multiply
Operation:
(E) ∗ (D) ⇒ E : D
Description:
Multiplies a 16-bit signed multiplicand contained in accumulator E by
a 16-bit signed multiplier contained in accumulator D, then places
the product in concatenated accumulators E and D. The CCR carry
bit can be used to round the high word of the product — execute
EMULS, then ADCE #0.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
—
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E : D) = $00000000 as a result of operation; else cleared.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-104
Opcode
3726
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
EORA
EORA
Exclusive OR A
Operation:
(A) ⊕ (M) ⇒ A
Description:
Performs EOR between the content of accumulator A and a memory
byte, then places the result in accumulator A. Memory content is not
affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
44
54
64
74
1744
1754
1764
1774
2744
2754
2764
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-105
Freescale Semiconductor, Inc.
EORB
EORB
Exclusive OR B
Operation:
(B) ⊕ (M) ⇒ B
Description:
Performs EOR between the content of accumulator B and a memory
byte, then places the result in accumulator B. Memory content is not
affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 is set by operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-106
Opcode
C4
D4
E4
F4
17C4
17D4
17E4
17F4
27C4
27D4
27E4
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
EORD
EORD
Exclusive OR D
Operation:
(D) ⊕ (M : M + 1) ⇒ D
Description:
Performs EOR between the content of accumulator D and a memory
word, then places the result in accumulator D. Memory content is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
84
94
A4
37B4
37C4
37D4
37E4
37F4
2784
2794
27A4
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
6
6
6
MOTOROLA
6-107
Freescale Semiconductor, Inc.
EORE
EORE
Exclusive OR E
Operation:
(E) ⊕ (M : M + 1) ⇒ E
Description:
Performs EOR between the content of accumulator E and a memory
word, then places the result in accumulator E. Memory content is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-108
Opcode
3734
3744
3754
3764
3774
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
FDIV
FDIV
Unsigned Fractional Divide
Operation:
(D) / (IX) ⇒ IX
Remainder ⇒ D
Description:
Divides a 16-bit unsigned dividend contained in accumulator D by a
16-bit unsigned divisor contained in index register X. The quotient is
placed in IX and the remainder is placed in D.
There is an implied radix point to the left of the quotient (IX15). An
implied radix point is assumed to occupy the same position in both
dividend and divisor. If the dividend is greater than or equal to the divisor, or if the divisor is equal to zero, (IX) is set to $FFFF and (D) is
indeterminate. To maintain compatibility with the M68HC11, no exception is generated on overflow or division by zero.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set if (IX) = $0000 as a result of operation; else cleared.
Set if (IX) ≤ (D) before operation; else cleared.
Set if (IX) = $0000 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
372B
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
22
MOTOROLA
6-109
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
FMULS
FMULS
Signed Fractional Multiply
Operation:
(E) ∗ (D) ⇒ E : D[31:1]
0 ⇒ E : D[0]
Description:
Multiplies a 16-bit signed fractional multiplicand contained in accumulator E by a 16-bit signed fractional multiplier contained in accumulator D. The implied radix points are between bits 15 and 14 of
the accumulators. The product is left-shifted one place to align the
radix point between bits 31 and 30, then placed in bits 31 to 1 of
concatenated accumulators E and D. D0 is cleared. The CCR carry
bit can be used to round the high word of the product — execute
FMULS, then ADCE #0.
When both accumulators contain $8000 (–1), the product is
$80000000 (–1.0) and the CCR V bit is set.
Syntax:
Standard
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E : D) = $00000000 as a result of operation; else cleared.
Set when operation is (–1)2; else cleared.
Set if D15 = 1 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-110
Opcode
3727
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
IDIV
IDIV
Integer Divide
Operation:
(D) / (IX) ⇒ IX
Remainder ⇒ D
Description:
Divides a 16-bit unsigned dividend contained in accumulator D by a
16-bit unsigned divisor contained in index register X. The quotient is
placed in IX and the remainder is placed in D.
There is an implied radix point to the right of the quotient (IX0). An
implied radix point is assumed to occupy the same position in both
dividend and divisor. If the divisor is equal to zero, (IX) is set to
$FFFF and (D) is indeterminate. To maintain compatibility with the
M68HC11, no exception is generated on division by zero.
Syntax:
Standard
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
—
∆
0
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set if (IX) = $0000 as a result of operation; else cleared.
Cleared.
Set if (IX) = $0000 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
372A
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
22
MOTOROLA
6-111
Freescale Semiconductor, Inc.
INC
INC
Increment Byte
Operation:
(M) + $01 ⇒ M
Description:
Adds $01 to the content of a memory byte. Only BEQ and BNE
branches will perform consistently immediately after INC on unsigned values. All signed branches are available after INC on two’s
complement values. Because INC does not affect the C bit in the
condition code register, it can be used to implement a loop counter
in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (M) = $7F before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-112
Opcode
03
13
23
1703
1713
1723
1733
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
INCA
INCA
Increment A
Operation:
(A) + $01 ⇒ A
Description:
Adds $01 to the content of accumulator A. Only BEQ and BNE
branches will perform consistently immediately after INCA on unsigned values. All signed branches are available after INCA on two’s
complement values. Because INCA does not affect the C bit in the
condition code register, it can be used to implement a loop counter
in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if (A) = $7F before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3703
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-113
Freescale Semiconductor, Inc.
INCB
INCB
Increment B
Operation:
(B) + $01 ⇒ B
Description:
Adds $01 to the content of accumulator B. Only BEQ and BNE
branches will perform consistently immediately after INCB on unsigned values. All signed branches are available after INCB on two’s
complement values. Because INCB does not affect the C bit in the
condition code register, it can be used to implement a loop counter
in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (B) = $7F before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-114
Opcode
3713
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
INCW
Increment Word
INCW
Operation:
(M : M + 1) + $0001 ⇒ M : M + 1
Description:
Adds $0001 to the content of a memory word. Only BEQ and BNE
branches will perform consistently immediately after INCW on unsigned values. All signed branches are available after INCW on
two’s complement values. Because INCW does not affect the C bit
in the condition code register, it can be used to implement a loop
counter in multiple-precision computation.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (M : M + 1) = $7FFF before operation (operation causes two’s complement overflow); else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
2703
2713
2723
2733
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
MOTOROLA
6-115
Freescale Semiconductor, Inc.
JMP
JMP
Jump
Operation:
Effective Address ⇒ PK : PC
Description:
Causes an unconditional change in program execution. A 20-bit effective address is placed in the concatenated program counter extension field and program counter. The next instruction is fetched
from the new address. The effective address can be generated in
two ways:
Freescale Semiconductor, Inc...
1. Effective Address = Extension: 16-bit Extended Address
When extended addressing mode is employed, the effective address is formed by a zero-extended 4-bit right-justified address
extension and a 16-bit byte address that are both contained in
the instruction. The EK field is not changed.
2. Effective Address = $0: (index register) + 20-bit Offset
When indexed addressing mode is employed, the effective address is calculated by adding a zero-extended 20-bit signed offset to the zero-extended content of an index register. The
associated extension field is not changed.
Syntax:
JMP (effective address)
JMP (offset)
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
EXT20
IND20, X
IND20, Y
IND20, Z
MOTOROLA
6-116
Opcode
7A
4B
5B
6B
Operand
zb hhll
zg gggg
zg gggg
zg gggg
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
JSR
Jump to Subroutine
JSR
Operation:
Push (PC)
(SK : SP) − $0002 ⇒ SK : SP
Push (CCR)
(SK : SP) − $0002 ⇒ SK : SP
Effective Address ⇒ PK : PC
Description:
Causes a branch to a subroutine. After the current content of the
program counter and the condition code register are stacked, a 20bit effective address is placed in the concatenated program counter
extension field and program counter. The next instruction is fetched
from the new address. The effective address can be generated in
two ways:
1. Effective Address = Extension: 16-bit Extended Address
When extended addressing mode is employed, the effective address is formed by a zero-extended 4-bit right-justified address
extension and a 16-bit extended address that are both contained
in the instruction. The EK field is not changed.
2. Effective Address = $0 : (index register) + 0 : 20-bit Offset
When indexed addressing mode is employed, the effective address is calculated by adding a zero-extended 20-bit signed offset to the zero-extended content of an index register. The
associated extension field is not changed.
Syntax:
JSR (effective address)
JSR (offset)
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
EXT20
IND20, X
IND20, Y
IND20, Z
CPU16
REFERENCE MANUAL
Opcode
FA
89
99
A9
Operand
zb hh ll
zg gggg
zg gggg
zg gggg
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
10
12
12
12
MOTOROLA
6-117
Freescale Semiconductor, Inc.
LBCC
LBCC
Long Branch If Carry Clear
Operation:
If C = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR carry bit has a value of
zero. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple
or unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3784
Operand
rrrr
Cycles
6, 4
Table 6-19 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-118
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBCS
Long Branch If Carry Set
LBCS
Operation:
If C = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR carry bit has a value of
one. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple
or unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3785
Operand
rrrr
Cycles
6, 4
Table 6-20 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-119
Freescale Semiconductor, Inc.
LBEQ
LBEQ
Long Branch If Equal to Zero
Operation:
If Z = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR zero bit has a value of
one. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple,
signed, or unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3787
Operand
rrrr
Cycles
6, 4
Table 6-21 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-120
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBEV
Long Branch If EV Set
LBEV
Operation:
If EV = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the EV bit in the condition code
register has a value of one. A 16-bit signed relative offset is added to
the current value of the program counter. When the operation causes PC overflow, the PK field is incremented or decremented. See
SECTION 11 DIGITAL SIGNAL PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
CPU16
REFERENCE MANUAL
Opcode
3791
Operand
rrrr
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6, 4
MOTOROLA
6-121
Freescale Semiconductor, Inc.
LBGE
Long Branch If Greater than or Equal to Zero
LBGE
Operation:
If N ⊕ V = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR negative and overflow
bits both have a value of zero or both have a value of one. A 16-bit
signed relative offset is added to the current value of the program
counter. When the operation causes PC overflow, the PK field is incremented or decremented. Used to implement signed conditional
branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
378C
Operand
rrrr
Cycles
6, 4
Table 6-22 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-122
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBGT
Long Branch If Greater than Zero
LBGT
Operation:
If Z ✛ (N ⊕ V) = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR negative and overflow
bits both have a value of zero or both have a value of one, and the
CCR zero bit has a value of zero. A 16-bit signed relative offset is
added to the current value of the program counter. When the operation causes PC overflow, the PK field is incremented or decremented. Used to implement signed conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
378E
Operand
rrrr
Cycles
6, 4
Table 6-23 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-123
Freescale Semiconductor, Inc.
LBHI
Long Branch If Higher
LBHI
Operation:
If C ✛ Z = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR carry and zero bits both
have a value of zero. A 16-bit signed relative offset is added to the
current value of the program counter. When the operation causes
PC overflow, the PK field is incremented or decremented. Used to
implement unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3782
Operand
rrrr
Cycles
6, 4
Table 6-24 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-124
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBLE
Long Branch If Less than or Equal to Zero
LBLE
Operation:
If Z ✛ (N ⊕ V) = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if either the CCR negative bit or
overflow bit has a value of one, or the CCR zero bit has a value of
one. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement signed
conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
378F
Operand
rrrr
Cycles
6, 4
Table 6-25 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-125
Freescale Semiconductor, Inc.
LBLS
Long Branch If Lower or Same
LBLS
Operation:
If C ✛ Z = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if either or both the CCR carry and
zero bits have a value of one. A 16-bit signed relative offset is added
to the current value of the program counter. When the operation
causes PC overflow, the PK field is incremented or decremented.
Used to implement unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3783
Operand
rrrr
Cycles
6, 4
Table 6-26 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-126
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBLT
Long Branch If Less than Zero
LBLT
Operation:
If N ⊕ V = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if either the CCR negative or overflow bits has a value of one. A 16-bit signed relative offset is added
to the current value of the program counter. When the operation
causes PC overflow, the PK field is incremented or decremented.
Used to implement signed conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
378D
Operand
rrrr
Cycles
6, 4
Table 6-27 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-127
Freescale Semiconductor, Inc.
LBMI
LBMI
Long Branch If Minus
Operation:
If N = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR negative bit has a value
of one. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple
conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
378B
Operand
rrrr
Cycles
6, 4
Table 6-28 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-128
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBMV
Long Branch If MV Set
LBMV
Operation:
If MV = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the MV bit in the condition code
register has a value of one. A 16-bit signed relative offset is added to
the current value of the program counter. When the operation causes PC overflow, the PK field is incremented or decremented. See
SECTION 11 DIGITAL SIGNAL PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
CPU16
REFERENCE MANUAL
Opcode
3790
Operand
rrrr
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6, 4
MOTOROLA
6-129
Freescale Semiconductor, Inc.
LBNE
LBNE
Long Branch If Not Equal to Zero
Operation:
If Z = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR zero bit has a value of zero. A 16-bit signed relative offset is added to the current value of the
program counter. When the operation causes PC overflow, the PK
field is incremented or decremented. Used to implement simple,
signed, and unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3786
Operand
rrrr
Cycles
6, 4
Table 6-29 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-130
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBPL
Long Branch If Plus
LBPL
Operation:
If N = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR negative bit has a value
of zero. A 16-bit signed relative offset is added to the current value
of the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple
conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
378A
Operand
rrrr
Cycles
6, 4
Table 6-30 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-131
Freescale Semiconductor, Inc.
LBRA
LBRA
Long Branch Always
Operation:
(PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch. A 16-bit signed relative offset is
added to the current value of the program counter. When the operation causes PC overflow, the PK field is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
REL16
Opcode
3780
Operand
rrrr
Cycles
6
Table 6-31 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-132
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBRN
Long Branch Never
LBRN
Operation:
(PK : PC) + 4 ⇒ PK : PC
Description:
Never branches. This instruction is effectively a NOP that requires
three cycles to execute. When the operation causes PC overflow,
the PK field is incremented or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
REL16
Opcode
3781
Operand
rrrr
Cycles
6
Table 6-32 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-133
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
LBSR
Long Branch to Subroutine
LBSR
Operation:
Push (PC)
(SK : SP) − $0002 ⇒ SK : SP
Push (CCR)
(SK : SP) − $0002 ⇒ SK : SP
(PK : PC) + Offset ⇒ PK : PC
Description:
Saves current address and flags, then branches to a subroutine. The
current value of the program counter is stacked, then the condition
code register is stacked (which preserves the PK field as well as
condition code bits and the interrupt priority mask). A 16-bit signed
relative offset is added to the current value of the program counter.
When the operation causes PC overflow, the PK field is incremented
or decremented.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
MOTOROLA
6-134
Opcode
27F9
Operand
rrrr
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
10
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LBVC
Long Branch If Overflow Clear
LBVC
Operation:
If V = 0, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR overflow bit has a value of
zero. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple,
signed, and unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3788
Operand
rrrr
Cycles
6, 4
Table 6-33 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
CPU16
REFERENCE MANUAL
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
MOTOROLA
6-135
Freescale Semiconductor, Inc.
LBVS
LBVS
Long Branch If Overflow Set
Operation:
If V = 1, then (PK : PC) + Offset ⇒ PK : PC
Description:
Causes a long program branch if the CCR overflow bit has a value of
one. A 16-bit signed relative offset is added to the current value of
the program counter. When the operation causes PC overflow, the
PK field is incremented or decremented. Used to implement simple,
signed, and unsigned conditional branches.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
REL16
Opcode
3789
Operand
rrrr
Cycles
6, 4
Table 6-34 Branch Instruction Summary (16-Bit Offset)
Mnemonic
LBCC
LBCS
LBEQ
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBNE
LBPL
LBRA
LBRN
LBVC
LBVS
MOTOROLA
6-136
Opcode
3784
3785
3787
378C
378E
3782
378F
3783
378D
378B
3786
378A
3780
3781
3788
3789
Equation
C=0
C=1
Z=1
N⊕V=0
Z ✛ (N ⊕ V) = 0
C✛Z=0
Z ✛ (N ⊕ V) = 1
C✛Z=1
N⊕V=1
N=1
Z=0
N=0
1
0
V=0
V=1
Type
Simple, Unsigned
Simple, Unsigned
Simple, Unsigned, Signed
Signed
Signed
Unsigned
Signed
Unsigned
Signed
Simple
Simple, Unsigned, Signed
Simple
Unary
Unary
Simple
Simple
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Complement
LBCS
LBCC
LBNE
LBLT
LBLE
LBLS
LBGT
LBHI
LBGE
LBPL
LBEQ
LBMI
LBRN
LBRA
LBVS
LBVC
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LDAA
LDAA
Load A
Operation:
(M) ⇒ A
Description:
Loads the content of a memory byte into accumulator A. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
45
55
65
75
1745
1755
1765
1775
2745
2755
2765
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-137
Freescale Semiconductor, Inc.
LDAB
LDAB
Load B
Operation:
(M) ⇒ B
Description:
Loads the content of a memory byte into accumulator B. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-138
Opcode
C5
D5
E5
F5
17C5
17D5
17E5
17F5
27C5
27D5
27E5
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LDD
LDD
Load D
Operation:
(M : M + 1) ⇒ D
Description:
Loads the content of a memory word into accumulator D. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
85
95
A5
37B5
37C5
37D5
37E5
37F5
2785
2795
27A5
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
6
6
6
MOTOROLA
6-139
Freescale Semiconductor, Inc.
LDE
LDE
Load E
Operation:
(M : M + 1) ⇒ E
Description:
Loads the content of a memory word into accumulator E. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-140
Opcode
3735
3745
3755
3765
3775
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LDED
Load Concatenated E and D
LDED
Operation:
(M : M + 1) ⇒ E
(M + 2 : M + 3) ⇒ D
Description:
Loads four successive bytes of memory into concatenated accumulators E and D. Used to transfer long word operands and 32-bit
signed fractions from memory. Can also be used to transfer 32-bit
words from IMB peripherals. Misaligned long transfers are converted
into two misaligned word transfers.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
EXT
CPU16
REFERENCE MANUAL
Opcode
2771
Operand
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
MOTOROLA
6-141
Freescale Semiconductor, Inc.
LDHI
Load MAC Registers H and I
LDHI
Operation:
(M : M + 1)X ⇒ HR
(M : M + 1)Y ⇒ IR
Description:
Initializes MAC registers H and I. HR is loaded with a memory word
located at address (XK : IX). IR is loaded with a memory word located at address (YK : IY). Memory content is not changed by the operation. See SECTION 11 DIGITAL SIGNAL PROCESSING for more
information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
EXT
MOTOROLA
6-142
Opcode
27B0
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LDS
LDS
Load Stack Pointer
Operation:
(M : M + 1) ⇒ SP
Description:
Loads the content of a memory word into the stack pointer. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if SP15 = 1 as a result of operation; else cleared.
Set if (SP) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
CF
DF
EF
37BF
17CF
17DF
17EF
17FF
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
MOTOROLA
6-143
Freescale Semiconductor, Inc.
LDX
LDX
Load IX
Operation:
(M : M + 1) ⇒ IX
Description:
Loads the content of a memory word into index register X. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if IX15 = 1 as a result of operation; else cleared.
Set if (IX) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-144
Opcode
CC
DC
EC
37BC
17CC
17DC
17EC
17FC
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LDY
LDY
Load IY
Operation:
(M : M + 1) ⇒ IY
Description:
Loads the content of a memory word into index register Y. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if IY15 = 1 as a result of operation; else cleared.
Set if (IY) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
CD
DD
ED
37BD
17CD
17DD
17ED
17FD
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
MOTOROLA
6-145
Freescale Semiconductor, Inc.
LDZ
LDZ
Load IZ
Operation:
(M : M + 1) ⇒ IZ
Description:
Loads the content of a memory word into index register Z. Memory
content is not changed by the operation.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if IZ15 = 1 as a result of operation; else cleared.
Set if (IZ) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-146
Opcode
CE
DE
EE
37BE
17CE
17DE
17EE
17FE
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
LPSTOP
Low Power Stop
LPSTOP
Operation:
If S, then enter low-power mode
Else NOP
Description:
Operation is controlled by the S bit in the CCR. If S = 0 when LPSTOP is executed, the IP field from the condition code register is
copied into an external bus interface, and the system clock input to
the CPU is disabled. If S = 1, LPSTOP operates in the same way as
a 4-cycle NOP.
Normal execution of instructions can resume in one of two ways. If a
reset occurs, a reset exception is generated. If an interrupt request
of higher priority than the copied IP value is received, an interrupt
exception is generated. See SECTION 9 EXCEPTION PROCESSING for more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
Opcode
27F1
Operand
—
Cycles
4, 20
Cycle times are for S = 1, S = 0 respectively.
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-147
Freescale Semiconductor, Inc.
LSR
LSR
Logic Shift Right
Operation:
Description:
Shifts all eight bits of a memory byte one place to the right. Bit 7 is
cleared. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
0
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-148
Opcode
0F
1F
2F
170F
171F
172F
173F
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LSRA
LSRA
Logic Shift Right A
Operation:
Description:
Shifts all eight bits of accumulator A one place to the right. Bit 7 is
cleared. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
0
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set if (A) = $00; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if A0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
370F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-149
Freescale Semiconductor, Inc.
LSRB
LSRB
Logic Shift Right B
Operation:
Description:
Shifts all eight bits of accumulator B one place to the right. Bit 7 is
cleared. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
0
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if B0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-150
Opcode
371F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LSRD
LSRD
Logic Shift Right D
Operation:
Description:
Shifts all sixteen bits of accumulator D one place to the right. Bit 15
is cleared. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
0
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if D0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27FF
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-151
Freescale Semiconductor, Inc.
LSRE
LSRE
Logic Shift Right E
Operation:
Description:
Shifts all sixteen bits of accumulator E one place to the right. Bit 15
is cleared. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
0
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if E0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-152
Opcode
277F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
LSRW
LSRW
Logic Shift Right Word
Operation:
Description:
Shifts all sixteen bits of a memory word one place to the right. Bit 15
is cleared. Bit 0 is transferred to the CCR C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
0
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M : M + 1[0] = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
270F
271F
272F
273F
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
MOTOROLA
6-153
Freescale Semiconductor, Inc.
MAC
Multiply and Accumulate
MAC
(HR) ∗ (IR) ⇒ E : D
(AM) + (E : D) ⇒ AM
((IX) ≤ X MASK) ✛ ((IX) + xo) ≤ X MASK)⇒ IX
((IY) ≤ Y MASK) ✛ ((IY) + yo) ≤ Y MASK)⇒ IY
(HR) ⇒ IZ
(M : M + 1)X ⇒ HR
(M : M + 1)Y ⇒ IR
Description:
Multiplies a 16-bit signed fractional multiplicand in MAC register I by
a 16-bit signed fractional multiplier in MAC register H. There are implied radix points between bits 15 and 14 of the registers. The product is left-shifted one place to align the radix point between bits 31
and 30, then placed in bits 31:1 of concatenated accumulators E
and D. D0 is cleared. The aligned product is then added to the content of AM.
Freescale Semiconductor, Inc...
Operation:
As multiply and accumulate operations take place, 4-bit offsets xo
and yo are sign-extended to 16 bits and used with X and Y masks to
qualify the X and Y index registers.
Writing a non-zero value into a mask register prior to MAC execution
enables modulo addressing. The TDMSK instruction writes mask
values. When a mask contains $0, modulo addressing is disabled,
and the sign-extended offset is added to the content of the corresponding index register.
After accumulation, the content of HR is transferred to IZ, then a
word at the address pointed to by XK : IX is loaded into HR, and a
word at the address pointed to by YK : IY is loaded into IR. The fractional product remains in concatenated E and D.
When both registers contain $8000 (–1), a value of $80000000 (1.0
in 36-bit format) is accumulated, (E : D) is $80000000 (–1 in 32-bit
format), and the V bit in the condition code register is set. See SECTION 11 DIGITAL SIGNAL PROCESSING for more information.
MOTOROLA
6-154
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
MAC
MAC
Multiply and Accumulate
Syntax:
MAC xo, yo
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
∆
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
∆
11
N
—
10
Z
—
9
V
∆
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Set if overflow into AM35 occurs as a result of addition; else not affected.
Not affected.
Set if overflow into AM[34:31] occurs as a result of addition; else cleared.
Not affected.
Not affected.
Set if operation is (–1)2; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM8
CPU16
REFERENCE MANUAL
Opcode
7B
Offset
xoyo
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
12
MOTOROLA
6-155
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MOVB
MOVB
Move Byte
Operation:
(M1) ⇒ M2
Description:
Moves a byte of data from a source address to a destination address. Data is examined as it is moved, and condition codes are set.
Source data is not changed. A combination of source and destination addressing modes is used. Extended addressing can be used
to specify source, destination, or both. A special form of indexed addressing, in which an 8-bit signed offset is added to the content of
index register X after the move is complete, can be used to specify
source or destination. If addition causes IX to overflow, the XK field
is incremented or decremented.
Syntax:
MOVB Source Offset Operand, X, Destination Address Operand
MOVB Source Address Operand, Destination Offset Operand,
XMOVB Source Address Operand, Destination Address Operand
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if MSB of source data = 1; else cleared.
Set if source data = $00; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IXP to EXT
EXT to IXP
EXT to EXT
MOTOROLA
6-156
Opcode
30
32
37FE
Offset
ff
ff
—
Addr Operand
hh ll
hh ll
hhll hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
10
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MOVW
MOVW
Move Word
Operation:
(M : M + 11) ⇒ M : M + 12
Description:
Moves a data word from a source address to a destination address.
Data is examined as it is moved, and condition codes are set.
Source data is not changed. A combination of source and destination addressing modes is used. Extended addressing can be used
to specify source, destination, or both. A special form of indexed addressing, in which an 8-bit signed offset is added to the content of
index register X after the move is complete, can be used to specify
source or destination only. If addition causes IX to overflow, the XK
field is incremented or decremented.
Syntax:
MOVB Source Offset Operand, X, Destination Address Operand
MOVB Source Address Operand, Destination Offset Operand,
XMOVB Source Address Operand, Destination Address Operand
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
0
8
C
—
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if MSB of source data = 1; else cleared.
Set if source data = $0000; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IXP to EXT
EXT to IXP
EXT to EXT
CPU16
REFERENCE MANUAL
Opcode
31
33
37FF
Offset
ff
ff
—
Operand
hhll
hhll
hhll hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
8
8
10
MOTOROLA
6-157
Freescale Semiconductor, Inc.
MUL
MUL
Unsigned Multiply
Operation:
(A) ∗ (B) ⇒ D
Description:
Multiplies an 8-bit unsigned multiplicand contained in accumulator A
by an 8-bit unsigned multiplier contained in accumulator B, then
places the product in accumulator D. Unsigned multiply can be used
to perform multiple-precision operations. The CCR Carry bit can be
used to round the high byte of the product — execute MUL, then
ADCA #0.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
—
10
Z
—
9
V
—
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Set if D7 = 1 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-158
Opcode
3724
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
10
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
NEG
NEG
Negate Byte
Operation:
$00 − (M) ⇒ M
Description:
Replaces the content of a memory byte with its two’s complement. A
value of $80 will not be changed.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (M) = $80 after operation (two’s complement overflow); else cleared.
Cleared if (M) = $00 before operation; else set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
02
12
22
1702
1712
1722
1732
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
8
8
8
8
8
8
8
MOTOROLA
6-159
Freescale Semiconductor, Inc.
NEGA
NEGA
Negate A
Operation:
$00 − (A) ⇒ A
Description:
Replaces the content of accumulator A with its two’s complement. A
value of $80 will not be changed.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if (A) = $80 after operation (two’s complement overflow); else cleared.
Cleared if (A) = $00 before operation; else set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-160
Opcode
3702
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
NEGB
NEGB
Negate B
Operation:
$00 − (B) ⇒ B
Description:
Replaces the content of accumulator B with its two’s complement. A
value of $80 will not be changed.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (B) = $80 after operation (two’s complement overflow); else cleared.
Cleared if (B) = $00 before operation; else set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3712
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
MOTOROLA
6-161
Freescale Semiconductor, Inc.
NEGD
NEGD
Negate D
Operation:
$0000 − (D) ⇒ D
Description:
Replaces the content of accumulator D with its two’s complement. A
value of $8000 will not be changed.
Syntax:
Standard
Condition Code Register:
Freescale Semiconductor, Inc...
15
S
—
14
MV
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
H
—
12
EV
—
11
N
∆
10
Z
∆
9
V
∆
8
C
∆
7
6
IP
—
5
4
SM
—
3
2
1
0
PK
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if (D) = $8000 after operation (two’s complement overflow); else cleared.
Cleared if (D) = $0000 before operation; else set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-162
Opcode
27F2
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
NEGE
NEGE
Negate E
Operation:
$0000 − (E) ⇒ E
Description:
Replaces the content of accumulator E with its two’s complement. A
value of $8000 will not be changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if (E) = $8000 after operation (two’s complement overflow); else cleared.
Cleared if (E) = $0000 before operation; else set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
2772
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-163
Freescale Semiconductor, Inc.
NEGW
NEGW
Negate Word
Operation:
$0000 − (M : M + 1) ⇒ M : M + 1
Description:
Replaces the content of a memory word with its two’s complement.
A value of $8000 will not be changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (M : M + 1) = $8000 after operation (two’s complement overflow); else cleared.
Cleared if (M : M + 1) = $0000 before operation; else set.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-164
Opcode
2702
2712
2722
2732
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
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Cycles
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
NOP
NOP
Null Operation
Operation:
None
Description:
Causes program counter to be incremented, but has no other effect.
Often used to temporarily replace other instructions during debug,
so that execution continues with a routine disabled. Can be used to
produce a time delay based on CPU clock frequency, although this
practice makes programs system-specific.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
274C
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
MOTOROLA
6-165
Freescale Semiconductor, Inc.
ORAA
ORAA
OR A
Operation:
(A) ✛ (M) ⇒ A
Description:
Performs inclusive OR between the content of accumulator A and a
memory byte, then places the result in accumulator A. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-166
Opcode
47
57
67
77
1747
1757
1767
1777
2747
2757
2767
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ORAB
ORAB
OR B
Operation:
(B) ✛ (M) ⇒ B
Description:
Performs inclusive OR between the content of accumulator B and a
memory byte, then places the result in accumulator B. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 is set by operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
C7
D7
E7
F7
17C7
17D7
17E7
17F7
27C7
27D7
27E7
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-167
Freescale Semiconductor, Inc.
ORD
ORD
OR D
Operation:
(D) ✛ (M : M + 1) ⇒ D
Description:
Performs inclusive OR between the content of accumulator D and a
memory word, then places the result in accumulator D. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-168
Opcode
87
97
A7
37B7
37C7
37D7
37E7
37F7
2787
2797
27A7
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
6
6
4
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ORE
ORE
OR E
Operation:
(E) ✛ (M : M + 1) ⇒ E
Description:
Performs inclusive OR between the content of accumulator E and a
memory word, then places the result in accumulator E. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
3737
3747
3757
3767
3777
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
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Cycles
4
6
6
6
6
MOTOROLA
6-169
Freescale Semiconductor, Inc.
ORP
ORP
OR Condition Code Register
Operation:
(CCR) ✛ IMM16 ⇒ CCR
Description:
Performs inclusive OR between the content of the condition code
register and a 16-bit unsigned immediate operand, then replaces
the content of the CCR with the result.
Freescale Semiconductor, Inc...
To make certain that conditions for termination of LPSTOP and WAI
are correct, interrupts are not recognized until after the instruction
following ORP executes. This prevents interrupt exception processing during the period after the mask changes but before the following instruction executes.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Set if bit 15 of operand = 1; else unchanged.
Set if bit 14 of operand = 1; else unchanged.
Set if bit 13 of operand = 1; else unchanged.
Set if bit 12 of operand = 1; else unchanged.
Set if bit 11 of operand = 1; else unchanged.
Set if bit 10 of operand = 1; else unchanged.
Set if bit 9 of operand = 1; else unchanged.
Set if bit 8 of operand = 1; else unchanged.
Each bit in field set if corresponding bit [7:5] of operand = 1; else unchanged.
Set if bit 4 of operand = 1; else unchanged.
Not affected.
Instruction Format:
Addressing Mode
IMM16
MOTOROLA
6-170
Opcode
373B
Operand
jjkk
INSTRUCTION GLOSSARY
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Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PSHA
PSHA
Push A
Operation:
(SK : SP) + $0001 ⇒ SK : SP
Push (A)
(SK : SP) − $0002 ⇒ SK : SP
Description:
Increments (SK : SP) by one, stores the content of accumulator A at
that address, then decrements (SK : SP) by two. If the SP overflows
as a result of the operation, the SK field is incremented or decremented.
Pushing byte data to the stack can misalign the stack pointer and
degrade performance. See SECTION 8 INSTRUCTION TIMING for
more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3708
Operand
—
INSTRUCTION GLOSSARY
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Cycles
4
MOTOROLA
6-171
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PSHB
PSHB
Push B
Operation:
(SK : SP) + $0001 ⇒ SK : SP
Push (B)
(SK : SP) − $0002 ⇒ SK : SP
Description:
Increments (SK : SP) by one, stores the content of accumulator B at
that address, then decrements (SK : SP) by two. If the SP overflows
as a result of the operation, the SK field is incremented or decremented.
Pushing byte data to the stack can misalign the stack pointer and
degrade performance. See SECTION 8 INSTRUCTION TIMING for
more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-172
Opcode
3718
Operand
—
INSTRUCTION GLOSSARY
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Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
PSHM
Freescale Semiconductor, Inc...
Operation:
Push Multiple Registers
PSHM
For mask bits 0 to 7
If bit set
push corresponding register
(SK : SP) − $0002 ⇒ SK : SP
Next
Mask bits:
0 = accumulator D
1 = accumulator E
2 = index register X
3 = index register Y
4 = index register Z
5 = extension register
6 = condition code register
7 = (Reserved)
Description:
Stores contents of selected registers on the system stack. Registers
are designated by setting bits in a mask byte. The PULM instruction
restores registers from the stack. PUSHM mask order is the reverse
of PULM mask order. If SP overflow occurs as a result of operation,
the SK field is decremented.
Stacking into the highest available memory address causes the
PULM instruction to attempt a prefetch from inaccessible memory.
Pushing to an odd SK : SP can degrade performance. See SECTION 8 INSTRUCTION TIMING for more information.
Syntax:
PSHM (mask)
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
IMM8
Opcode
34
Mask
ii
Cycles
4 + 2N*
*N = Number of registers to be pushed.
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
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MOTOROLA
6-173
Freescale Semiconductor, Inc.
PSHMAC
Operation:
Start
Freescale Semiconductor, Inc...
End
Push MAC Registers
PSHMAC
Stack registers in sequence shown, beginning at address pointed to
by stack pointer.
15 14
8 7
3
0
(SP)
H REGISTER
(SP) + $0002
I REGISTER
(SP) + $0004
ACCUMULATOR M[15:0]
(SP) + $0006
ACCUMULATOR M[31:16]
(SP) + $0008 SL
RESERVED
AM[35:32]
(SP) + $000A
IX ADDRESS MASK
IY ADDRESS MASK
Description:
Stores multiply and accumulate unit internal state on the system
stack. The SP is decremented after each save operation (stack
grows downward in memory). If SP overflow occurs as a result of
operation, the SK field is decremented. See SECTION 11 DIGITAL
SIGNAL PROCESSING for more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-174
Opcode
27B8
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
14
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PULA
PULA
Pull A
Operation:
(SK : SP) + $0002 ⇒ SK : SP
Pull (A)
(SK : SP) − $0001 ⇒ SK : SP
Description:
Increments (SK : SP) by two, restores the content of accumulator A
from that address, then decrements (SK : SP) by one. If the SP overflows as a result of the operation, the SK field is incremented or decremented.
Pulling byte data from the stack can misalign the stack pointer and
degrade performance. See SECTION 8 INSTRUCTION TIMING for
more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3709
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
MOTOROLA
6-175
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PULB
PULB
Pull B
Operation:
(SK : SP) + $0002 ⇒ SK : SP
Pull (B)
(SK : SP) − $0001 ⇒ SK : SP
Description:
Increments (SK : SP) by two, restores the content of accumulator B
from that address, then decrements (SK : SP) by one. If the SP overflows as a result of the operation, the SK field is incremented or decremented.
Pulling byte data from the stack can misalign the stack pointer and
degrade performance. See SECTION 8 INSTRUCTION TIMING for
more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-176
Opcode
3719
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
PULM
Operation:
Pull Multiple Registers
PULM
For mask bits 0 to 7
If bit set
(SK : SP) + $0002 ⇒ SK : SP
Pull corresponding register
Next
Freescale Semiconductor, Inc...
Mask bits:
0 = condition code register
1 = extension register
2 = index register Z
3 = index register Y
4 = index register X
5 = accumulator E
6 = accumulator D
7 = (Reserved)
Description:
Restores contents of registers stacked by a PSHM instruction. Registers are designated by setting bits in a mask byte. PULM mask order is the reverse of PSHM mask order. If SP overflow occurs as a
result of operation, the SK field is incremented.
PULM prefetches a stacked word on each iteration. If SP points to
the highest available stack address after the last register has been
restored, the prefetch will attempt to read inaccessible memory. Pulling from an odd SK : SP can degrade performance. See SECTION 8
INSTRUCTION TIMING for more information.
Syntax:
PULM (mask)
Condition Code Register:
Set according to CCR pulled from stack. Not affected unless CCR is
pulled.
Instruction Format:
Addressing Mode
IMM8
Opcode
35
Mask
ii
Cycles
4+ 2 (N + 1)*
*N = Number of registers to be pulled.
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
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MOTOROLA
6-177
Freescale Semiconductor, Inc.
PULMAC
Operation:
End
Freescale Semiconductor, Inc...
Start
Pull MAC Registers
PULMAC
Restore registers in sequence shown, beginning at address pointed
to by stack pointer.
15 14
8 7
3
0
(SP) + $000C
IX ADDRESS MASK
IY ADDRESS MASK
(SP) + $000A SL
RESERVED
AM[35:32]
(SP) + $0008
ACCUMULATOR M[31:16]
(SP) + $0006
ACCUMULATOR M[15:0]
(SP) + $0004
I REGISTER
(SP) + $0002
H REGISTER
(SP)
(Top of Stack)
Description:
Restores multiply and accumulate unit internal state from the system stack. The SP is incremented after each restoration (stack
shrinks upward in memory). If SP overflow occurs as a result of operation, the SK field is incremented. See SECTION 11 DIGITAL
SIGNAL PROCESSING for more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-178
Opcode
27B9
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
16
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
RMAC
Repeating Multiply and Accumulate
RMAC
Repeat:
(AM) + ((HR) ∗ (IR)) ⇒ AM
((IX) ≤ X MASK) ✛ ((IX) + xo) ≤ X MASK) ⇒ IX
((IY) ≤ Y MASK) ✛ ((IY) + yo) ≤ Y MASK) ⇒ IY
(M : M + 1)X ⇒ HR
(M : M + 1)Y ⇒ IR
(E) − $0001 ⇒ EUntil (E) < $0000
Description:
Performs repeated multiplication of 16-bit signed fractional multiplicands in MAC register I by 16-bit signed fractional multipliers in MAC
register H. Each product is added to the content of accumulator M.
Accumulator D is used for temporary storage during multiplication. A
16-bit signed integer in accumulator E determines the number of
repetitions.
Freescale Semiconductor, Inc...
Operation:
There are implied radix points between bits 15 and 14 of HR and IR.
Each product is left-shifted one place to align the radix point between bits 31 and 30 before addition to AM.
As multiply and accumulate operations take place, 4-bit offsets xo
and yo are sign-extended to 16 bits and used with X and Y masks to
qualify the X and Y index registers.
Writing a non-zero value into a mask register prior to RMAC execution enables modulo addressing. The TDMSK instruction writes
mask values. When a mask contains $0, modulo addressing is disabled, and the sign-extended offset is added to the content of the
corresponding index register.
After accumulation, a word pointed to by XK : IX is loaded into HR,
and a word pointed to by YK : IY is loaded into IR, then the value in
E is decremented and tested. After execution, content of E is indeterminate.
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-179
Freescale Semiconductor, Inc.
RMAC
RMAC
Repeating Multiply and Accumulate
RMAC always iterates at least once, even when executed with a
zero or negative value in E. Since the value in E is decremented,
then tested, loading E with $8000 results in 32,769 iterations.
If HR and IR both contain $8000 (–1), a value of $80000000 (1.0 in
36-bit format) is accumulated, but no condition code is set.
Freescale Semiconductor, Inc...
RMAC execution is suspended during asynchronous exceptions.
Operation resumes when RTI is executed. All registers used by
RMAC must be restored prior to RTI. See SECTION 11 DIGITAL
SIGNAL PROCESSING for more information.
Syntax:
RMAC xo, yo
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
—
∆
—
—
—
—
—
—
—
0
Not affected.
Set if overflow into AM35 occurs as a result of addition; else not affected.
Not affected.
Set if overflow into AM[34:31] occurs as a result of addition; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM8
MOTOROLA
6-180
Opcode
FB
Offset
xoyo
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
6 + 12 per iteration
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ROL
ROL
Rotate Left Byte
Operation:
Description:
Rotates all eight bits of a memory byte one place to the left. Bit 0 is
loaded from the CCR carry bit. Bit 7 is transferred to the C bit.
Rotation through the C bit aids shifting and rotating multiple bytes.
For example, use the sequence ASL Byte0, ROL Byte1, ROL Byte2
to shift a 24-bit value contained in bytes 0 to 2 left one bit.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
—
∆
—
—
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M7 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
0C
1C
2C
170C
171C
172C
173C
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
8
8
8
8
8
8
8
MOTOROLA
6-181
Freescale Semiconductor, Inc.
ROLA
ROLA
Rotate Left A
Operation:
Description:
Rotates all eight bits of accumulator A one place to the left. Bit 0 is
loaded from the CCR carry bit. Bit 7 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if A7 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-182
Opcode
370C
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ROLB
ROLB
Rotate Left B
Operation:
Description:
Rotates all eight bits of accumulator B one place to the left. Bit 0 is
loaded from the CCR carry bit. Bit 7 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if B7 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
371C
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-183
Freescale Semiconductor, Inc.
ROLD
ROLD
Rotate Left D
Operation:
Description:
Rotates all sixteen bits of accumulator D one place to the left. Bit 0 is
loaded from the CCR carry bit. Bit 15 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if D15 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-184
Opcode
27FC
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ROLE
ROLE
Rotate Left E
Operation:
Description:
Rotates all sixteen bits of accumulator E one place to the left. Bit 0 is
loaded from the CCR carry bit. Bit 15 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if E15 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
277C
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-185
Freescale Semiconductor, Inc.
ROLW
ROLW
Rotate Left Word
Operation:
Description:
Rotates all sixteen bits of a memory word one place to the left. Bit 0
is loaded from the CCR carry bit. Bit 15 is transferred to the C bit.
Rotation through the C bit aids shifting and rotating multiple words.
For example, use the sequence ASLW Word0, ROLW Word1, ROLW
Word2 to shift a 48-bit value contained in words 0 to 2 left one bit.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M : M + 1[15] = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-186
Opcode
270C
271C
272C
273C
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
ROR
ROR
Rotate Right Byte
Operation:
Description:
Rotates all eight bits of a memory byte one place to the right. Bit 7 is
loaded from the CCR C bit. Bit 0 is transferred to the C bit.
Freescale Semiconductor, Inc...
Rotation through the C bit aids shifting and rotating multiple words.
For example, use the sequence LSR Byte2, ROR Byte1, ROR Byte0
to shift a 24-bit value contained in bytes 0 to 2 right one bit. Replace
LSR with ASR to maintain the value of a sign bit.
Syntax:
Standard
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 set as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
0E
1E
2E
170E
171E
172E
173E
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
8
8
8
8
8
8
8
MOTOROLA
6-187
Freescale Semiconductor, Inc.
RORA
RORA
Rotate Right A
Operation:
Description:
Rotates all eight bits of accumulator A one place to the right. Bit 7 is
loaded from the CCR C bit. Bit 0 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if A0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-188
Opcode
370E
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
RORB
RORB
Rotate Right B
Operation:
Description:
Rotates all eight bits of accumulator B one place to the right. Bit 7 is
loaded from the CCR C bit. Bit 0 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if B0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
371E
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-189
Freescale Semiconductor, Inc.
RORD
RORD
Rotate Right D
Operation:
Description:
Rotates all sixteen bits of accumulator D one place to the right. Bit
15 is loaded from the CCR C bit. Bit 0 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if D0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-190
Opcode
27FE
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
RORE
RORE
Rotate Right E
Operation:
Description:
Rotates all sixteen bits of accumulator E one place to the right. Bit
15 is loaded from the CCR C bit. Bit 0 is transferred to the C bit.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if E0 = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
277E
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-191
Freescale Semiconductor, Inc.
RORW
RORW
Rotate Right Word
Operation:
Description:
Rotates all sixteen bits of a memory word one place to the right. Bit
15 is loaded from the CCR C bit. Bit 0 is transferred to the C bit.
Freescale Semiconductor, Inc...
Rotation through the C bit aids shifting and rotating multiple words.
For example, use the sequence LSRW Word2, RORW Word1,
RORW Word0 to shift a 48-bit value contained in words 0 to 2 right
one bit. Replace LSRW with ASRW to maintain value of a sign bit.
Syntax:
Standard
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Set if (N is set and C is clear) or (N is clear and C is set) as a result of operation; else cleared.
Set if M : M + 1[0] = 1 before operation; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-192
Opcode
270E
271E
272E
273E
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
8
8
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
RTI
RTI
Return From Interrupt
Operation:
(SK : SP) + 2 ⇒ SK : SP
Pull CCR
(SK : SP) + 2 ⇒ SK : SP
Pull PC(PK : PC) − 6 ⇒ PK : PC
Description:
Causes normal program execution to resume after an interrupt, or
any exception other than reset. The condition code register and program counter are restored from the system stack. When the CCR is
pulled, the PK field is restored, so that execution resumes on the
proper page after the PC is pulled.
Syntax:
Standard
Condition Code Register:
15
14
S
∆
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
0
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Value changes according to CCR restored from stack.
Set or cleared according to CCR restored from stack.
Value changes according to CCR restored from stack.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
2777
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
12
MOTOROLA
6-193
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
RTS
RTS
Return From Subroutine
Operation:
(SK : SP) + 2 ⇒ SK : SP
Pull PK
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) − 2 ⇒ PK : PC
Description:
Returns control to a routine that executed JSR. The PK field and
program counter are restored from the system stack, so that execution resumes on the proper page. Use PSHM/PULM to conserve
other program resources.
Syntax:
Standard
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
—
—
—
—
∆
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Value changes to that of PK restored from stack.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-194
Opcode
27F7
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
12
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SBA
Subtract B from A
SBA
Operation:
(A) − (B) ⇒ A
Description:
Subtracts the content of accumulator B from the content of accumulator A, then places the result in accumulator A. Content of accumulator B does not change. The CCR C bit represents a borrow for
subtraction.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
5
4
3
0
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
∆
∆
—
—
—
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if (A) < (B); else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
370A
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-195
Freescale Semiconductor, Inc.
SBCA
SBCA
Subtract with Carry from A
Operation:
(A) − (M) − C ⇒ A
Description:
Subtracts the content of a memory byte minus the value of the C bit
from the content of accumulator A, then places the result in accumulator A. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
5
4
3
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if (A) < (M) + C; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-196
Opcode
42
52
62
72
1742
1752
1762
1772
2742
2752
2762
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SBCB
SBCB
Subtract with Carry from B
Operation:
(B) − (M) − C ⇒ B
Description:
Subtracts the content of a memory byte minus the value of the C bit
from the content of accumulator B, then places the result in accumulator B. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
5
4
3
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 is set by operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if (B) < (M) + C; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
C2
D2
E2
F2
17C2
17D2
17E2
17F2
27C2
27D2
27E2
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-197
Freescale Semiconductor, Inc.
SBCD
SBCD
Subtract with Carry from D
Operation:
(D) − (M : M + 1) − C ⇒ D
Description:
Subtracts the content of a memory word minus the value of the C bit
from the content of accumulator D, then places the result in accumulator D. Memory content is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of operation; else cleared.
Set if (D) < (M : M + 1) + C; else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-198
Opcode
82
92
A2
37B2
37C2
37D2
37E2
37F2
2782
2792
27A2
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
STAA
STAA
Store A
Operation:
(A) ⇒ M
Description:
Stores content of accumulator A in a memory byte. Content of accumulator is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 is set as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
4A
5A
6A
174A
175A
176A
177A
274A
275A
276A
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
4
4
4
MOTOROLA
6-199
Freescale Semiconductor, Inc.
STAB
STAB
Store B
Operation:
(B) ⇒ M
Description:
Stores content of accumulator B in a memory byte. Content of accumulator is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 is set as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-200
Opcode
CA
DA
EA
17CA
17DA
17EA
17FA
27CA
27DA
27EA
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
4
4
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
STD
STD
Store D
Operation:
(D) ⇒ M : M + 1
Description:
Stores content of accumulator D in a memory word. Content of accumulator is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] is set as a result of operation; else cleared.
Set if (M : M + 1) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
8A
9A
AA
37CA
37DA
37EA
37FA
278A
279A
27AA
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
6
6
6
MOTOROLA
6-201
Freescale Semiconductor, Inc.
STE
STE
Store E
Operation:
(E) ⇒ M : M + 1
Description:
Stores content of accumulator E in a memory word. Content of accumulator is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] is set as a result of operation; else cleared.
Set if (M : M + 1) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-202
Opcode
374A
375A
376A
377A
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
STED
Store Concatenated E and D
STED
Operation:
(E) ⇒ (M : M + 1)
(D) ⇒ (M + 2 : M + 3)
Description:
Stores concatenated accumulators E and D into four successive
bytes of memory. Used to transfer long-word and 32-bit fractional
operands to memory. Can also be used to perform coherent long
word transfers to IMB peripherals. Misaligned long word transfers
are converted into two misaligned word transfers.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
EXT
CPU16
REFERENCE MANUAL
Opcode
2773
Operand
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
8
MOTOROLA
6-203
Freescale Semiconductor, Inc.
STS
STS
Store Stack Pointer
Operation:
(SP) ⇒ M : M + 1
Description:
Stores content of stack pointer in a memory word. Content of pointer
is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] is set as a result of operation; else cleared.
Set if (M : M + 1) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-204
Opcode
8F
9F
AF
178F
179F
17AF
17BF
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
STX
STX
Store IX
Operation:
(IX) ⇒ M : M + 1
Description:
Stores content of index register X in a memory word. Content of register is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] is set as a result of operation; else cleared.
Set if (M : M + 1) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
8C
9C
AC
178C
179C
17AC
17BC
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
MOTOROLA
6-205
Freescale Semiconductor, Inc.
STY
STY
Store IY
Operation:
(IY) ⇒ M : M + 1
Description:
Stores content of index register Y in a memory word. Content of register is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] is set as a result of operation; else cleared.
Set if (M : M + 1) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-206
Opcode
8D
9D
AD
178D
179D
17AD
17BD
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
STZ
STZ
Store IZ
Operation:
(IZ) ⇒ M : M + 1
Description:
Stores content of index register Z in a memory word. Content of register is unchanged.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] is set as a result of operation; else cleared.
Set if (M : M + 1) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
8E
9E
AE
178E
179E
17AE
17BE
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
4
4
6
6
6
6
MOTOROLA
6-207
Freescale Semiconductor, Inc.
SUBA
SUBA
Subtract from A
Operation:
(A) − (M) ⇒ A
Description:
Subtracts the content of a memory byte from the content of accumulator A, then places the result in accumulator A. Memory content is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
5
4
3
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 is set by operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if (A) < (M); else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-208
Opcode
40
50
60
70
1740
1750
1760
1770
2740
2750
2760
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SUBB
SUBB
Subtract from B
Operation:
(B) − (M) ⇒ B
Description:
Subtracts the content of a memory byte from the content of accumulator B, then places the result in accumulator B. Memory content is
not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
5
4
3
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 is set by operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if (B) < (M); else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Opcode
C0
D0
E0
F0
17C0
17D0
17E0
17F0
27C0
27D0
27E0
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
2
6
6
6
6
6
6
6
MOTOROLA
6-209
Freescale Semiconductor, Inc.
SUBD
SUBD
Subtract from D
Operation:
(D) − (M : M + 1) ⇒ D
Description:
Subtracts the content of a memory word from the content of accumulator D, then places the result in accumulator D. Memory content
is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 is set by operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of operation; else cleared.
Set if (D) < (M : M + 1); else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA
6-210
Opcode
80
90
A0
37B0
37C0
37D0
37E0
37F0
2780
2790
27A0
Operand
ff
ff
ff
jjkk
gggg
gggg
gggg
hhll
—
—
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
4
6
6
6
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SUBE
SUBE
Subtract from E
Operation:
(E) − (M : M + 1) ⇒ E
Description:
Subtracts the content of a memory word from the content of accumulator E, then places the result in accumulator E. Memory content
is not affected.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
∆
∆
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 is set by operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Set if two’s complement overflow occurs as a result of the operation; else cleared.
Set if (E) < (M : M + 1); else cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
3730
3740
3750
3760
3770
Operand
jjkk
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
6
6
6
6
MOTOROLA
6-211
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
SWI
SWI
Software Interrupt
Operation:
(PK : PC) + $0002 ⇒ PK : PC
Push (PC)
(SK : SP) – $0002 ⇒ SK : SP
Push (CCR)
(SK : SP) – $0002 ⇒ SK : SP
$0 ⇒ PK
(SWI Vector) ⇒ PC
Description:
Causes an internally generated interrupt exception. Current program counter and condition code register (including the PK field) are
saved on the system stack, then PK is cleared and the PC is loaded
with exception vector 6 (content of address $000C). See SECTION
9 EXCEPTION PROCESSING for more information.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
—
—
—
—
—
0
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Cleared.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-212
Opcode
3720
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
16
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SXT
SXT
Sign Extend B into A
Operation:
If B7 = 1
then $FF ⇒ A
else $00 ⇒ A
Description:
Extends an 8-bit two’s complement value contained in accumulator
B into a 16-bit two’s complement value in accumulator D.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
∆
∆
—
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27F8
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-213
Freescale Semiconductor, Inc.
TAB
TAB
Transfer A to B
Operation:
(A) ⇒ B
Description:
Replaces the content of accumulator B with the content of accumulator A. Content of A is not changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-214
Opcode
3717
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TAP
TAP
Transfer A to Condition Code Register
Operation:
(A) ⇒ CCR[15:8]
Description:
Replaces bits 15 to 8 of the condition code register with the content
of accumulator A. Content of A is not changed.
To make certain that conditions for termination of LPSTOP and WAI
are correct, interrupts are not recognized until after the instruction
following TAP executes. This prevents interrupt exception processing
during the period after the mask changes but before the following instruction executes.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
S
∆
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
∆
∆
∆
∆
∆
∆
—
—
—
0
Set or cleared according to content of A.
Set or cleared according to content of A.
Set or cleared according to content of A.
Set or cleared according to content of A.
Set or cleared according to content of A.
Set or cleared according to content of A.
Set or cleared according to content of A.
Set or cleared according to content of A.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
37FD
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
MOTOROLA
6-215
Freescale Semiconductor, Inc.
TBA
TBA
Transfer B to A
Operation:
(B) ⇒ A
Description:
Replaces the content of accumulator A with the content of accumulator B. Content of B is not changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-216
Opcode
3707
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TBEK
Transfer B to EK
TBEK
Operation:
(B[3:0]) ⇒ EK
Description:
Replaces the content of the EK field with the content of bits 0 to 3 of
accumulator B. Bits 4 to 7 are ignored. Content of B is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
27FA
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-217
Freescale Semiconductor, Inc.
TBSK
Transfer B to SK
TBSK
Operation:
(B[3:0]) ⇒ SK
Description:
Replaces the content of the SK field with the content of bits 0 to 3 of
accumulator B. Bits 4 to 7 are ignored. Content of B is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
379F
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-218
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TBXK
Transfer B to XK
TBXK
Operation:
(B[3:0]) ⇒ XK
Description:
Replaces the content of the XK field with the content of bits 0 to 3 of
accumulator B. Bits 4 to 7 are ignored. Content of B is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
379C
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-219
Freescale Semiconductor, Inc.
TBYK
Transfer B to YK
TBYK
Operation:
(B[3:0]) ⇒ YK
Description:
Replaces the content of the YK field with the content of bits 0 to 3 of
accumulator B. Bits 4 to 7 are ignored. Content of B is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
379D
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-220
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TBZK
Transfer B to ZK
TBZK
Operation:
(B[3:0]) ⇒ ZK
Description:
Replaces the content of the ZK field with the content of bits 0 to 3 of
accumulator B. Bits 4 to 7 are ignored. Content of B is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
379E
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-221
Freescale Semiconductor, Inc.
TDE
TDE
Transfer D to E
Operation:
(D) ⇒ E
Description:
Replaces the content of accumulator E with the content of accumulator D. Content of D is not changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-222
Opcode
277B
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TDMSK
Transfer D to XMSK:YMSK
TDMSK
Operation:
(D[15:8]) ⇒ XMSK
(D[7:0]) ⇒ YMSK
Description:
Replaces the content of the MAC X and Y masks with the content of
accumulator D. Content of D is not changed. Masks are used to implement modulo buffers. See SECTION 11 DIGITAL SIGNAL PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
372F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-223
Freescale Semiconductor, Inc.
TDP
TDP
Transfer D to Condition Code Register
Operation:
(D) ⇒ CCR[15:4]
Description:
Replaces bits 15 to 4 of the condition code register with the content
of accumulator D. Content of D is not changed.
To make certain that conditions for termination of LPSTOP and WAI
are correct, interrupts are not recognized until after the instruction
following TDP executes. This prevents interrupt exception processing during the period after the mask changes but before the following instruction executes.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
S
∆
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
0
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Set or cleared according to content of D.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-224
Opcode
372D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TED
TED
Transfer E to D
Operation:
(E) ⇒ D
Description:
Replaces the content of accumulator D with the content of accumulator E. Content of E is not changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
MV
H
EV
—
—
—
11
10
9
8
7
6
5
4
3
2
1
N
Z
V
C
IP
SM
PK
∆
∆
0
—
—
—
—
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27FB
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
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Cycles
2
MOTOROLA
6-225
Freescale Semiconductor, Inc.
TEDM
TEDM
Transfer E and D to AM
Operation:
(E) ⇒ AM[31:16]
(D) ⇒ AM[15:0]
AM[32:35] = AM31
Description:
Replaces bits 31 to 16 of the MAC accumulator with the content of
accumulator E, then replaces bits 15 to 0 of the MAC accumulator
with the content of accumulator D. AM[35:32] reflect the state of
AM31. Content of E and D are not changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
S
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
13
12
11
10
9
8
7
6
5
4
3
2
1
MV
H
EV
N
Z
V
C
IP
SM
PK
0
—
0
—
—
—
—
—
—
—
0
Not affected.
Cleared.
Not affected.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-226
Opcode
27B1
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TEKB
Transfer EK to B
TEKB
Operation:
(EK) ⇒ B[3:0]
$0 ⇒ B[7:4]
Description:
Replaces bits 0 to 3 of accumulator B with the content of the EK
field. Bits 4 to 7 of B are cleared. Content of EK is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27BB
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-227
Freescale Semiconductor, Inc.
TEM
TEM
Transfer E to AM
Operation:
(E) ⇒ AM[31:16]
$00 ⇒ AM[15:0]
AM[35:32] = AM31
Description:
Replaces bits 31 to 16 of the MAC accumulator with the content of
accumulator E. AM[15:0] are cleared. AM[35:32] reflect the state of
bit 31. Content of E is not changed.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
0
—
0
—
—
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Cleared.
Not affected.
Cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-228
Opcode
27B2
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
4
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
TMER
TMER
Transfer Rounded AM to E
Operation:
Rounded (AM) ⇒ Temp
If (SM • (EV ÷ MV))
then Saturation Value ⇒ E
else Temp ⇒ E
Description:
The content of the MAC accumulator is rounded and transferred to
temporary storage. If the saturation mode bit in the CCR is set and
overflow occurs, a saturation value is transferred to accumulator E.
Otherwise, the rounded value is transferred to accumulator E. TMER
uses convergent rounding. Refer to SECTION 11 DIGITAL SIGNAL
PROCESSING for more information.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
—
∆
∆
∆
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Set if overflow into AM35 occurs as a result of rounding; else not affected.
Not affected.
Set if overflow into AM[34:31] occurs as a result of rounding; else not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $00 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27B4
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
MOTOROLA
6-229
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
TMET
TMET
Transfer Truncated AM to E
Operation:
If (SM ≤ (EV ✛ MV))
then Saturation Value ⇒ E
else AM[31:16] ⇒ E
Description:
If the saturation mode bit in the CCR is set and overflow has
occurred, a saturation value is transferred to accumulator E. Otherwise, AM[31:16] are transferred to accumulator E. Refer to SECTION 11 DIGITAL SIGNAL PROCESSING for more information on
overflow and data saturation.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
—
—
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $00 as a result of operation; else cleared.
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-230
Opcode
27B5
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TMXED
Transfer AM to IX : E : D
TMXED
Operation:
AM[35:32] ⇒ IX[3:0]
AM35 ⇒ IX[15:4]
AM[31:16] ⇒ E
AM[15:0] ⇒ D
Description:
Transfers content of the MAC accumulator to index register X, accumulator E, and accumulator D. See SECTION 11 DIGITAL SIGNAL
PROCESSING for more information.
Syntax:
Standard
Freescale Semiconductor, Inc...
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
27B3
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
MOTOROLA
6-231
Freescale Semiconductor, Inc.
TPA
Transfer Condition Code Register to A
TPA
Operation:
(CCR[15:8]) ⇒ A
Description:
Replaces the content of accumulator A with bits 15 to 8 of the condition code register. Content of CCR is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
37FC
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-232
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TPD
Transfer Condition Code Register to D
TPD
Operation:
(CCR) ⇒ D
Description:
Replaces the content of accumulator D with the content of the condition code register. Content of CCR is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
372C
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-233
Freescale Semiconductor, Inc.
TSKB
Transfer SK to B
TSKB
Operation:
(SK) ⇒ B[3:0]$0 ⇒ B[7:4]
Description:
Replaces bits 0 to 3 of accumulator B with the content of the SK
field. Bits 4 to 7 of B are cleared. Content of SK is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
37AF
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-234
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TST
TST
Test Byte
Operation:
(M) − $00
Description:
Subtracts $00 from the content of a memory byte and sets bits in the
condition code register accordingly. The operation does not change
memory content.
TST has minimal utility with unsigned values. BLO and BLS, for example, will not function because no unsigned value is less than zero.
BHI will function the same as BNE, which is preferred.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M7 = 1 as a result of operation; else cleared.
Set if (M) = $00 as a result of operation; else cleared.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
CPU16
REFERENCE MANUAL
Opcode
06
16
26
1706
1716
1726
1736
Operand
ff
ff
ff
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
6
6
6
6
MOTOROLA
6-235
Freescale Semiconductor, Inc.
TSTA
TSTA
Test A
Operation:
(A) − $00
Description:
Subtracts $00 from the content of accumulator A and sets bits in the
condition code register accordingly. The operation does not change
accumulator content.
TSTA has minimal utility with unsigned values. BLO and BLS, for example, will not function because no unsigned value is less than zero.
BHI will function the same as BNE, which is preferred.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if A7 = 1 as a result of operation; else cleared.
Set if (A) = $00 as a result of operation; else cleared.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-236
Opcode
3706
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TSTB
TSTB
Test B
Operation:
(B) − $00
Description:
Subtracts $00 from the content of accumulator B and sets bits in the
condition code register accordingly. The operation does not change
accumulator content.
TSTB has minimal utility with unsigned values. BLO and BLS, for example, will not function because no unsigned value is less than zero.
BHI will function the same as BNE, which is preferred.
Freescale Semiconductor, Inc...
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if B7 = 1 as a result of operation; else cleared.
Set if (B) = $00 as a result of operation; else cleared.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
3716
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-237
Freescale Semiconductor, Inc.
TSTD
TSTD
Test D
Operation:
(D) − $0000
Description:
Subtracts $0000 from the content of accumulator D and sets bits in
the condition code register accordingly. The operation does not
change accumulator content.
Freescale Semiconductor, Inc...
TSTD provides minimum information to subsequent instructions
when unsigned values are tested. BLO and BLS, for example, have
no utility because no unsigned value is less than zero. BHI will function the same as BNE, which is preferred. All signed branch instructions are available after test of signed values.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if D15 = 1 as a result of operation; else cleared.
Set if (D) = $0000 as a result of operation; else cleared.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-238
Opcode
27F6
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TSTE
TSTE
Test E
Operation:
(E) − $0000
Description:
Subtracts $0000 from the content of accumulator E and sets the bits
in the condition code register accordingly. The operation does not
change accumulator content.
Freescale Semiconductor, Inc...
TSTE provides minimum information to subsequent instructions
when unsigned values are tested. BLO and BLS, for example, have
no utility because no unsigned value is less than zero. BHI will function the same as BNE, which is preferred. All signed branch instructions are available after test of signed values.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if E15 = 1 as a result of operation; else cleared.
Set if (E) = $0000 as a result of operation; else cleared.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
2776
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-239
Freescale Semiconductor, Inc.
TSTW
TSTW
Test Word
Operation:
(M : M + 1) − $0000
Description:
Subtracts $0000 from the content of a memory word and sets the
bits in the condition code register accordingly. The operation does
not change memory content.
Freescale Semiconductor, Inc...
TSTW provides minimum information to subsequent instructions
when unsigned values are tested. BLO and BLS, for example, have
no utility because no unsigned value is less than zero. BHI will function the same as BNE, which is preferred. All signed branch instructions are available after test of signed values.
Syntax:
Standard
Condition Code Register:
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
∆
∆
0
0
—
—
—
S:
MV:
H:
EV:
N:
Z:
V:
C:
IP:
SM:
PK:
7
6
5
4
3
2
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Set if M : M + 1[15] = 1 as a result of operation; else cleared.
Set if (M : M + 1) = $0000 as a result of operation; else cleared.
Cleared.
Cleared.
Not affected.
Not affected.
Not affected.
Instruction Format:
Addressing Mode
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
6-240
Opcode
2706
2716
2726
2736
Operand
gggg
gggg
gggg
hhll
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
6
6
6
6
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TSX
Transfer SP to IX
TSX
Operation:
(SK : SP) + $0002 ⇒ XK : IX
Description:
Replaces the contents of the XK field and index register X with the
contents of the SK field and the stack pointer plus two. Contents of
SK and SP are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
274F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-241
Freescale Semiconductor, Inc.
TSY
Transfer SP to IY
TSY
Operation:
(SK : SP) + $0002 ⇒ YK : IY
Description:
Replaces the contents of the YK field and index register Y with the
contents of the SK field and the stack pointer plus two. Contents of
SK and SP are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-242
Opcode
275F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TSZ
Transfer SP to IZ
TSZ
Operation:
(SK : SP) + $0002 ⇒ ZK : IZ
Description:
Replaces the contents of the ZK field and index register Z with the
contents of the SK field and the stack pointer plus two. Contents of
SK and SP are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
276F
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-243
Freescale Semiconductor, Inc.
TXKB
Transfer XK to B
TXKB
Operation:
(XK) ⇒ B[3:0]$0 ⇒ B[7:4]
Description:
Replaces bits 0 to 3 of accumulator B with the content of the XK
field. Bits 4 to 7 of B are cleared. Content of XK is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-244
Opcode
37AC
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TXS
Transfer IX to SP
TXS
Operation:
(XK : IX) − $0002 ⇒ SK : SP
Description:
Replaces the content of the SK field and the stack pointer with the
content of the XK field and index register X minus two. Content of
XK and IX are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
374E
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-245
Freescale Semiconductor, Inc.
TXY
Transfer IX to IY
TXY
Operation:
(XK : IX) ⇒ YK : IY
Description:
Replaces the content of the YK field and index register Y with the
content of the XK field and index register X. Content of XK and IX
are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-246
Opcode
275C
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TXZ
Transfer IX to IZ
TXZ
Operation:
(XK : IX) ⇒ ZK : IZ
Description:
Replaces the content of the ZK field and index register Z with the
content of the XK field and index register X. Content of XK and IX
are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
276C
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-247
Freescale Semiconductor, Inc.
TYKB
Transfer YK to B
TYKB
Operation:
(YK) ⇒ B[3:0]$0 ⇒ B[7:4]
Description:
Replaces bits 0 to 3 of accumulator B with the content of the YK
field. Bits 4 to 7 of B are cleared. Content of YK is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-248
Opcode
37AD
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TYS
Transfer IY to SP
TYS
Operation:
(YK : IY) − $0002 ⇒ SK : SP
Description:
Replaces the content of the SK field and the stack pointer with the
content of the YK field and index register Y minus two. Content of YK
and IY are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
375E
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-249
Freescale Semiconductor, Inc.
TYX
Transfer IY to IX
TYX
Operation:
(YK : IY) ⇒ XK : IX
Description:
Replaces the content of the XK field and index register X with the
content of the YK field and index register Y. Content of YK and IY are
not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-250
Opcode
274D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
TYZ
Transfer IY to IZ
TYZ
Operation:
(YK : IY) ⇒ ZK : IZ
Description:
Replaces the content of the ZK field and index register Z with the
content of the YK field and index register Y. Content of YK and IY are
not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
276D
Operand
—
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
Cycles
2
MOTOROLA
6-251
Freescale Semiconductor, Inc.
TZKB
Transfer ZK to B
TZKB
Operation:
(ZK) ⇒ B[3:0]
$0 ⇒ B[7:4]
Description:
Replaces bits 0 to 3 of accumulator B with the content of the ZK
field. Bits 4 to 7 of B are cleared. Content of ZK is not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-252
Opcode
37AE
Operand
—
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Cycles
2
CPU16
REFERENCE MANUAL
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TZS
Transfer IZ to SP
TZS
Operation:
(ZK : IZ) − $0002 ⇒ SK : SP
Description:
Replaces the content of the SK field and the stack pointer with the
content of the ZK field and index register Z minus two. Content of ZK
and IZ are not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
376E
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
MOTOROLA
6-253
Freescale Semiconductor, Inc.
TZX
Transfer IZ to IX
TZX
Operation:
(ZK : IZ) ⇒ XK : IX
Description:
Replaces the content of the XK field and index register X with the
content of the ZK field and index register Z. Content of ZK and IZ are
not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-254
Opcode
274E
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
CPU16
REFERENCE MANUAL
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TZY
Transfer IZ to IY
TZY
Operation:
(ZK : IZ) ⇒ YK : IY
Description:
Replaces the content of the YK field and index register Y with the
content of the ZK field and index register Z. Content of ZK and IZ are
not changed.
Syntax:
Standard
Condition Code Register: Not affected.
Freescale Semiconductor, Inc...
Instruction Format:
Addressing Mode
INH
CPU16
REFERENCE MANUAL
Opcode
275E
Operand
—
INSTRUCTION GLOSSARY
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Cycles
2
MOTOROLA
6-255
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
WAI
Wait for Interrupt
WAI
Operation:
WAIT
Description:
Internal CPU clocks are stopped, and normal execution of instructions ceases. Instruction execution can resume in one of two ways. If
a reset occurs, a reset exception is generated. If an interrupt request
of higher priority than the current IP value is received, an Interrupt
exception is generated.
Interrupts are acknowledged faster after WAI than after LPSTOP, because IMB clocks continue to run during WAI operation, and the
CPU16 does not copy the IP field to the system integration module
external bus interface. However, LPSTOP minimizes microcontroller
power consumption during inactivity. Refer to SECTION 9 EXCEPTION PROCESSING for more information.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Addressing Mode
INH
MOTOROLA
6-256
Opcode
27F3
Operand
—
INSTRUCTION GLOSSARY
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Cycles
8
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
XGAB
Exchange A and B
Operation:
(A) ⇔ (B)
Description:
Exchanges contents of accumulators A and B.
Syntax:
Standard
XGAB
Condition Code Register: Not affected.
Instruction Format:
Opcode
371A
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
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MOTOROLA
6-257
Freescale Semiconductor, Inc.
XGDE
Exchange D and E
Operation:
(D) ⇔ (E)
Description:
Exchanges contents of accumulators D and E.
Syntax:
Standard
XGDE
Condition Code Register: Not affected.
Instruction Format:
Opcode
277A
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-258
INSTRUCTION GLOSSARY
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XGDX
Exchange D and IX
XGDX
Operation:
(D) ⇔ (IX)
Description:
Exchanges contents of accumulator D and index register X.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
37CC
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
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MOTOROLA
6-259
Freescale Semiconductor, Inc.
XGDY
Exchange D and IY
XGDY
Operation:
(D) ⇔ (IY)
Description:
Exchanges contents of accumulator D and index register IY.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
37DC
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-260
INSTRUCTION GLOSSARY
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CPU16
REFERENCE MANUAL
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XGDZ
Exchange D and IZ
XGDZ
Operation:
(D) ⇔ (IZ)
Description:
Exchanges contents of accumulator D and index register IZ.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
37EC
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
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MOTOROLA
6-261
Freescale Semiconductor, Inc.
XGEX
Exchange E and IX
XGEX
Operation:
(E) ⇔ (IX)
Description:
Exchanges contents of accumulator E and index register X.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
374C
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-262
INSTRUCTION GLOSSARY
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CPU16
REFERENCE MANUAL
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XGEY
Exchange E and IY
XGEY
Operation:
(E) ⇔ (IY)
Description:
Exchanges contents of accumulator E and index register Y.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
375C
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
CPU16
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MOTOROLA
6-263
Freescale Semiconductor, Inc.
XGEZ
Exchange E and IZ
XGEZ
Operation:
(E) ⇔ (IZ)
Description:
Exchanges contents of accumulator E and index register Z.
Syntax:
Standard
Condition Code Register: Not affected.
Instruction Format:
Opcode
376C
Operand
—
Cycles
2
Freescale Semiconductor, Inc...
Addressing Mode
INH
MOTOROLA
6-264
INSTRUCTION GLOSSARY
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CPU16
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6.3 Condition Code Evaluation
The following table contains Boolean expressions used to evaluate the effect of an operation on condition code register status flags.
Table 6-35 Condition Code Evaluation
Mnemonic
Freescale Semiconductor, Inc...
ABA
Evaluation
H = A3 • B3 ÷ B3 • R3 ÷ R3 • A3
N = R7
Z = R7 • R6 •... • R1 • R0
V = A7 • B7 • R7 ÷ A7 • B7 • R7
C = A7 • B7 ÷ B7 • R7 ÷ R7 • A7
ACE
ACED
EV = [(AM35 ÷...÷ AM31) • (AM35 ÷... ÷ AM31)] ÷ MV
MV — cannot be represented by a Boolean equation
ADCA
ADCB
H = X3 • M3 ÷ M3 • R3 ÷ R3 • X3
N = R7
Z = R7 • R6 •... • R1 • R0
V = X7 • M7 • R7 ÷ X7 • M7 • R7
C = X7 • M7 ÷ M7 • R7 ÷ R7 • X7
ADCD
ADCE
N = R15
Z = R15 • R14 •... • R1 • R0
V = X15 • M15 • R15 ÷ X15 • M15 • R15
C = X15 • M15 ÷ M15 • R15 ÷ X15 • R15
ADDA
ADDB
H = X3 • M3 ÷ M3 • R3 ÷ R3 • X3
N = R7
Z = R7 • R6 •... • R1 • R0
V = X7 • M7 • R7 ÷ X7 • M7 • R7
C = X7 • M7 ÷ M7 • R7 ÷ R7 • X7
ADDD
ADDE
N = R15
Z = R15 • R14 •... • R1 • R0
V = X15 • M15 • R15 ÷ X15 • M15 • R15
C = X15 • M15 ÷ M15 • R15 ÷ X15 • R15
ADE
N = R15
Z = R15 • R14 •... • R1 • R0
V = D15 • E15 • R15 ÷ D15 • D15 • R15
C = D15 • E15 ÷ D15 • R15 ÷ E15 • R15
AIX
AIY
AIZ
Z = R15 • R14 •... • R10 • R9
ANDA
ANDB
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
ANDD
ANDE
N = R15
Z = R15 • R14 •... • R1 • R0
V=0
ANDP
CCR[15:4] changed by AND with 16-bit immediate data,
CCR[3:0] not affected.
ASL
ASLA
ASLB
N = R7
Z = R7 • R6 •... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = MSB of unshifted byte (accumulator)
ASLD
ASLE
ASLW
N = R15
Z = R15 • R14 •... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = MSB of unshifted word (accumulator)
CPU16
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MOTOROLA
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Table 6-35 Condition Code Evaluation
Freescale Semiconductor, Inc...
Mnemonic
ASLM
EV = [(AM35 ÷... ÷ AM31) • (AM35 ÷... ÷ AM31)] ÷ MV
N = R35
C = MSB of unshifted accumulator
MV — cannot be represented by a Boolean equation
ASR
ASRA
ASRB
N = R7
Z = R7 • R6 •... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = LSB of unshifted byte (accumulator)
ASRD
ASRE
ASRW
N = R15
Z = R15 • R14 •... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = LSB of unshifted word (accumulator)
ASRM
EV = [(AM35 ÷... ÷ AM31) • (AM35 ÷... ÷ AM31)] ÷ MV
N = R35
C = LSB of unshifted accumulator
BCLR
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
BCLRW
MOTOROLA
6-266
Evaluation
N = R15
Z = R15 • R14 •... • R1 • R0
V=0
BITA
BITB
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
BSET
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
CBA
N = R7
Z = R7 • R6 •... • R1 • R0
V = A7 • B7 • R7 ÷ A7 • B7 • R7
C = A7 • B7 ÷ B7 • R7 ÷ R7 • A7
CLR
CLRA
CLRB
CLRD
CLRE
CLRW
N=0
Z=1
V=0
C=0
CLRM
EV = 0
MV = 0
CMPA
CMPB
N = R7
Z = R7 • R6 •.. • R1 • R0
V = X7 • M7 • R7 ÷ X7 • M7 • R7
C = X7 • M7 ÷ M7 • R7 ÷ R7 • X7
COM
COMA
COMB
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
C=1
COMD
COME
COMW
N = R15
Z = R15 • R14 •... • R1 • R0
V=0
C=1
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Table 6-35 Condition Code Evaluation
Freescale Semiconductor, Inc...
Mnemonic
Evaluation
CPD
CPE
CPS
CPX
CPY
CPZ
N = R15
Z = R15 • R14 •... • R1 • R0
V = X15 • M15 • R15 ÷ X15 • M15 • R15
C = X15 • M15 ÷ M15 • R15 ÷ R15 • X15
DAA
N = R7
Z = R7 • R6 •... • R1 • R0
V=U
C = Determined by adjustment
DEC
DECA
DECB
N = R7
Z = R7 • R6 •... • R1 • R0
V = R7 • R6 •... • R1 • R0
DECW
N = R15
Z = R15 • R14 •... • R1 • R0
V = R15 • R14 •... • R1 • R0
EDIV
EDIVS
N = R15
Z = R15 • R14 •... • R1 • R0
V = 1 if R > $FFFF
C = 1 if2 ∗ Remainder ≥ Divisor
EORA
EORB
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
EORD
EORE
N = R15
Z = R15 • R14 •... • R1 • R0
V=0
FDIV
FMULS
Z = R15 • R14 •... • R1 • R0
V = 1, if (IX) • (D)
C = IX15 • IX14 •... • IX1 • IX0
N = R31 (E15)
Z = R31 • R30 •... • R1 • R0
V = (D15 • (D14 • D13 •... • D1 • D0)) •
(E15 • (E14 • E13 •... • E1 • E0))
C = R15 (D15)
IDIV
Z = R15 • R14 •... • R1 • R0
V=0
C = IX15 • IX14 •... • IX1 • IX0
INC
INCA
INCB
N = R7
Z = R7 • R6 •... • R1 • R0
V = R7 • R6 •... • R1 • R0
INCW
N = R15
Z = R15 • R14 •... • R1 • R0
V = R15 • R14 •... • R1 • R0
LDAA
LDAB
N = R7
Z = R7 • R6 •... • R1 • R0
V=0
LDD
LDE
LDS
LDX
LDY
LDZ
CPU16
REFERENCE MANUAL
N = R15
Z = R15 • R14 • ... • R1 • R0
V=0
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Table 6-35 Condition Code Evaluation
Mnemonic
LSR
LSRA
LSRB
N=0
Z = R7 • R6 • ... • R1 • R0
V = [N • C] ÷ [N • C]
C = MSB of unshifted byte (accumulator)
LSRD
LSRE
LSRW
N=0
Z = R15 • R14 • ... • R1 • R0
V = [N • C] ÷ [N • C]
C = MSB of unshifted word (accumulator)
Freescale Semiconductor, Inc...
MAC
EV = [(AM35 ÷ ... ÷ AM31) • (AM35 ÷ ... ÷ AM31)] ÷ MV
V = (H15 • (H14 • ... • H0)) • (I15 • (I14 • ... •I0))
MV — cannot be represented by a Boolean equation
MOVB
N = MSB of source data
Z = S7 • S6 • ... • S1 • S0
MOVW
N = MSB of source data
Z = S15 • S14 • ... • S1 • S0
MUL
ORAA
ORAB
MOTOROLA
6-268
Evaluation
C = R7 (D7)
N = R7
Z = R7 • R6 • ... • R1 • R0
V=0
ORD
ORE
N = R15
Z = R15 • R14 • ... • R1 • R0
V=0
ORP
CCR[15:4] changed by OR with 16-bit immediate data,
CCR[3:0] not affected.
PULM
Entire CCR changed if a stacked CCR is pulled.
RMAC
EV = [(AM35 ÷ ... ÷ AM31) • (AM35 ÷ ... ÷ AM31)] ÷ MV
V = (H15 • (H14 • ... • H0)) • (I15 • (I14 • ... •I0))
MV — cannot be represented by a Boolean equation
ROL
ROLA
ROLB
N = R7
Z = R7 • R6 • ... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = MSB of unshifted byte (accumulator)
ROLD
ROLE
ROLW
N = R15
Z = R15 • R14 • ... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = MSB of unshifted word (accumulator)
ROR
RORA
RORB
N = R7
Z = R7 • R6 • ... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = MSB of unshifted byte (accumulator)
RORD
RORE
RORW
N = R15
Z = R15 • R14 • ... • R1 • R0
V = N ⊕ C = [N • C] ÷ [N ÷ C]
C = MSB of unshifted word (accumulator)
RTI
Entire CCR changed when stacked CCR is pulled.
SBA
N = R7
Z = R7 • R6 • ... • R1 • R0
V = A7 • B7 • R7 ÷ A7 • B7 • R7
C = A7 • B7 ÷ B7 • R7 ÷ R7 • A7
SBCA
SBCB
N = R7
Z = R7 • R6 • ... • R1 • R0
V = X7 • M7 • R7 ÷ X7 • M7 • R7
C = X7 • M7 ÷ M7 • R7 ÷ R7 • X7
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Table 6-35 Condition Code Evaluation
Freescale Semiconductor, Inc...
Mnemonic
Evaluation
SBCD
SBCE
N = R15
Z = R15 • R14 • ... • R1 • R0
V = X15 • M15 • R15 ÷ X15 • M15 • R15
C = X15 • M15 ÷ X15 • R15 ÷ M15 • R15
SDE
N = R15
Z = R15 • R14 • ... • R1 • R0
V = E15 • D15 • R15 ÷ E15 • D15 • R15
C = E15 • D15 ÷ E15 • R15 ÷ D15 • R15
STAA
STAB
N = R7
Z = R7 • R6 • ... • R1 • R0
V=0
STD
STE
STS
STX
STY
STZ
N = R15
Z = R15 • R14 • ... • R1 • R0
V=0
SUBA
SUBB
N = R7
Z = R7 • R6 • ... • R1 • R0
V = X7 • M7 • R7 ÷ X7 • M7 • R7
C = X7 • M7 ÷ M7 • R7 ÷ R7 • X7
SUBD
SUBE
N = R15
Z = R15 • R14 • ... • R1 • R0
V = X15 • M15 • R15 ÷ X15 • M15 • R15
C = X15 • M15 ÷ X15 • R15 ÷ M15 • R15
SXT
N = R15
Z = R15 • R14 • ... • R1 • R0
TAB
TBA
N = R7
Z = R7 • R6 • ... • R1 • R0
V=0
TAP
CCR[15:8] replaced by content of Accumulator A.
CCR[7:0] not affected.
TDE
TED
N = R15
Z = R15 • R14 • ... • R1 • R0
V=0
TDP
CCR[15:4] replaced by content of Accumulator D.
CCR[3:0] not affected.
TEDM
TEM
EV = 0
MV = 0
TMER
EV = [(AM35 ÷ ... ÷ AM31) • (AM35 ÷ ... ÷ AM31)] ÷ MV
MV not representable with Boolean equation
TMET
N = R15
Z = R15 • R14 • ... • R1 • R0
TST
TSTA
TSTB
N = R7
Z = R7 • R6 • ... • R1 • R0
V=0
C=0
TSTD
TSTE
TSTW
N = R15
Z = R15 • R14 • ... • R1 • R0
V=0
C=0
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MOTOROLA
6-269
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6.4 Instruction Set Summary
The following table is a summary of the CPU16 instruction set. Because it is only affected by a few instructions, the LSB of the condition code register is not shown in the
table — instructions that affect the interrupt mask and PK field are noted.
Table 6-36 Instruction Set Summary
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
INH
INH
INH
INH
INH
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
Opcode
370B
374F
375F
376F
3722
3723
Operand
—
—
—
—
—
—
Cycles
2
2
2
2
2
4
S MV H
— — ∆
— — —
— — —
— — —
— ∆ —
— ∆ —
EV
—
—
—
—
∆
∆
N
∆
—
—
—
—
—
Z
∆
—
—
—
—
—
V
∆
—
—
—
—
—
C
∆
—
—
—
—
—
43
53
63
73
1743
1753
1763
1773
2743
2753
2763
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
∆
—
∆
∆
∆
∆
ABA
ABX
ABY
ABZ
ACE
ACED
ADCA
Add B to A
Add B to IX
Add B to IY
Add B to IZ
Add E to AM
Add E : D to AM
Add with Carry to A
(A ) + (B) ⇒ A
(XK : IX) + (000 : B) ⇒ XK : IX
(YK : IY) + (000 : B) ⇒ YK : IY
(ZK : IZ) + (000 : B) ⇒ ZK : IZ
(AM[31:16]) + (E) ⇒ AM
(AM) + (E : D) ⇒ AM
(A) + (M) + C ⇒ A
ADCB
Add with Carry to B
(B) + (M) + C ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C3
D3
E3
F3
17C3
17D3
17E3
17F3
27C3
27D3
27E3
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
∆
—
∆
∆
∆
∆
ADCD
Add with Carry to D
(D) + (M : M + 1) + C ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
83
93
A3
37B3
37C3
37D3
37E3
37F3
2783
2793
27A3
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
ADCE
Add with Carry to E
(E) + (M : M + 1) + C ⇒ E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3733
3743
3753
3763
3773
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
ADDA
Add to A
(A) + (M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
41
51
61
71
1741
1751
1761
1771
2741
2751
2761
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
∆
—
∆
∆
∆
∆
MOTOROLA
6-270
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
ADDB
Add to B
(B) + (M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C1
D1
E1
F1
17C1
17D1
17E1
17F1
27C1
27D1
27E1
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
∆
—
∆
∆
∆
∆
ADDD
Add to D
(D) + (M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
81
91
A1
FC
37B1
37C1
37D1
37E1
37F1
2781
2791
27A1
ff
ff
ff
ii
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
ADDE
Add to E
(E) + (M : M + 1) ⇒ E
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
7C
3731
3741
3751
3761
3771
ii
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
∆
∆
ADE
ADX
ADY
ADZ
AEX
AEY
AEZ
AIS
(E) + (D) ⇒ E
(XK : IX) + («D) ⇒ XK : IX
(YK : IY) + («D) ⇒ YK : IY
(ZK : IZ) + («D) ⇒ ZK : IZ
(XK : IX) + («E) ⇒ XK : IX
(YK : IY) + («E) ⇒ YK : IY
(ZK : IZ) + («E) ⇒ ZK : IZ
(SK : SP) + (20 « IMM) ⇒
SK : SP
(XK : IX) + (20 « IMM) ⇒
XK : IX
(YK : IY) + (20 « IMM) ⇒
YK : IY
(ZK : IZ) + (20 « IMM) ⇒
ZK : IZ
(A) • (M) ⇒ A
INH
INH
INH
INH
INH
INH
INH
IMM8
IMM16
IMM8
IMM16
IMM8
IMM16
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
2778
37CD
37DD
37ED
374D
375D
376D
3F
373F
3C
373C
3D
373D
3E
373E
—
—
—
—
—
—
—
ii
jj kk
ii
jj kk
ii
jj kk
ii
jj kk
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
—
—
—
∆
— —
—
—
—
—
—
∆
— —
—
—
—
—
—
∆
— —
ANDA
Add D to E
Add D to IX
Add D to IY
Add D to IZ
Add E to IX
Add E to IY
Add E to IZ
Add Immediate Data
to Stack Pointer
Add Immediate Value
to IX
Add Immediate Value
to IY
Add Immediate Value
to IZ
AND A
2
4
6
6
6
6
2
2
2
2
2
2
2
2
4
2
4
2
4
2
4
46
56
66
76
1746
1756
1766
1776
2746
2756
2766
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
ANDB
AND B
(B) • (M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C6
D6
E6
F6
17C6
17D6
17E6
17F6
27C6
27D6
27E6
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
AIX
AIY
AIZ
CPU16
REFERENCE MANUAL
Mode
Opcode
Operand
Cycles
S
MV
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-271
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
ANDD
AND D
(D) • (M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
86
96
A6
37B6
37C6
37D6
37E6
37F6
2786
2796
27A6
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
ANDE
AND E
(E) • (M : M + 1) ⇒ E
4
6
6
6
6
4
—
—
∆
∆
0
—
(CCR) • IMM16⇒ CCR
jj kk
gggg
gggg
gggg
hh ll
jj kk
—
AND CCR
3736
3746
3756
3766
3776
373A
—
ANDP1
ASL
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
∆
∆
∆
∆
∆
∆
∆
∆
Arithmetic Shift Left
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
04
14
24
1704
1714
1724
1734
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
∆
∆
ASLA
Arithmetic Shift Left A
INH
3704
—
8
8
8
8
8
8
8
2
—
—
—
—
∆
∆
∆
∆
ASLB
Arithmetic Shift Left B
INH
3714
—
2
—
—
—
—
∆
∆
∆
∆
ASLD
Arithmetic Shift Left D
INH
27F4
—
2
—
—
—
—
∆
∆
∆
∆
ASLE
Arithmetic Shift Left E
INH
2774
—
2
—
—
—
—
∆
∆
∆
∆
ASLM
Arithmetic Shift Left
AM
INH
27B6
—
4
—
∆
—
∆
∆
— —
∆
ASLW
Arithmetic Shift Left
Word
IND16, X
IND16, Y
IND16, Z
EXT
2704
2714
2724
2734
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
∆
∆
∆
∆
ASR
Arithmetic Shift Right
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0D
1D
2D
170D
171D
172D
173D
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
∆
∆
ASRA
Arithmetic Shift Right
A
INH
370D
—
8
8
8
8
8
8
8
2
—
—
—
—
∆
∆
∆
∆
ASRB
Arithmetic Shift Right
B
INH
371D
—
2
—
—
—
—
∆
∆
∆
∆
ASRD
Arithmetic Shift Right
D
INH
27FD
—
2
—
—
—
—
∆
∆
∆
∆
ASRE
Arithmetic Shift Right
E
INH
277D
—
2
—
—
—
—
∆
∆
∆
∆
MOTOROLA
6-272
Mode
Opcode
Operand
Cycles
S
MV
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
V
C
ASRM
Arithmetic Shift Right
AM
INH
27BA
—
4
—
—
—
∆
∆
— —
Z
∆
ASRW
Arithmetic Shift Right
Word
8
8
8
8
6, 2
—
—
∆
∆
∆
If C = 0, branch
gggg
gggg
gggg
hh ll
rr
—
Branch if Carry Clear
270D
271D
272D
273D
B4
—
BCC2
BCLR
IND16, X
IND16, Y
IND16, Z
EXT
REL8
—
—
—
—
— — — —
Clear Bit(s)
(M) • (Mask) ⇒ M
—
—
∆
∆
0
—
(M : M + 1) • (Mask) ⇒
M:M+1
8
8
8
8
8
8
8
10
—
Clear Bit(s) in a Word
1708
1718
1728
08
18
28
38
2708
—
BCLRW
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND16, X
—
—
—
—
∆
∆
0
—
IND16, Y
2718
IND16, Z
2728
EXT
2738
∆
BCS2
Branch if Carry Set
If C = 1, branch
REL8
B5
mm ff
mm ff
mm ff
mm gggg
mm gggg
mm gggg
mm hh ll
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
rr
6, 2
—
—
—
—
— — — —
BEQ2
Branch if Equal
If Z = 1, branch
REL8
B7
rr
6, 2
—
—
—
—
— — — —
BGE2
Branch if Greater Than
or Equal to Zero
Enter Background
Debug Mode
If N ⊕ V = 0, branch
REL8
BC
rr
6, 2
—
—
—
—
— — — —
If BDM enabled,
begin debug;
else, illegal instruction trap
If Z ✛ (N ⊕ V) = 0, branch
INH
37A6
—
—
—
—
—
—
— — — —
REL8
BE
rr
6, 2
—
—
—
—
— — — —
BGND
10
10
10
BHI2
Branch if Greater Than
Zero
Branch if Higher
If C ✛ Z = 0, branch
REL8
B2
rr
6, 2
—
—
—
—
— — — —
BITA
Bit Test A
(A) • (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
BITB
Bit Test B
(B) • (M)
6
6
6
2
6
6
6
6
6
6
6
6, 2
—
—
∆
∆
0
—
If Z ✛ (N ⊕ V) = 1, branch
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
rr
—
—
—
—
—
— — — —
If C ✛ Z = 1, branch
REL8
B3
rr
6, 2
—
—
—
—
— — — —
If N ⊕ V = 1, branch
REL8
BD
rr
6, 2
—
—
—
—
— — — —
BMI2
Branch if Less Than or
Equal to Zero
Branch if Lower or
Same
Branch if Less Than
Zero
Branch if Minus
C9
D9
E9
F9
17C9
17D9
17E9
17F9
27C9
27D9
27E9
BF
—
BLE2
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
REL8
If N = 1, branch
REL8
BB
rr
6, 2
—
—
—
—
— — — —
BNE2
Branch if Not Equal
If Z = 0, branch
REL8
B6
rr
6, 2
—
—
—
—
— — — —
BPL2
Branch if Plus
If N = 0, branch
REL8
BA
rr
6, 2
—
—
—
—
— — — —
BGT2
BLS2
BLT2
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
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MOTOROLA
6-273
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Mnemonic
BRA
BRCLR2
BRN
Freescale Semiconductor, Inc...
BRSET2
Operation
Branch Always
Branch if Bit(s) Clear
Branch Never
Branch if Bit(s) Set
Description
If 1 = 1, branch
If (M) • (Mask) = 0, branch
If 1 = 0, branch
If (M) • (Mask) = 0, branch
Address
Instruction
Opcode
Operand
Cycles
S
MV
H
EV
N
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B0
CB
DB
EB
0A
6
—
—
—
—
— — — —
10, 12
10, 12
10, 12
10, 14
—
—
—
—
— — — —
IND16, Y
1A
IND16, Z
2A
EXT
3A
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B1
8B
9B
AB
0B
—
—
—
—
—
—
—
—
— — — —
— — — —
IND16, Y
1B
IND16, Z
2B
EXT
3B
rr
mm ff rr
mm ff rr
mm ff rr
mm gggg
rrrr
mm gggg
rrrr
mm gggg
rrrr
mm hh ll
rrrr
rr
mm ff rr
mm ff rr
mm ff rr
mm gggg
rrrr
mm gggg
rrrr
mm gggg
rrrr
mm hh ll
rrrr
—
—
—
—
∆
∆
0
∆
—
—
—
—
∆
∆
0
∆
BSET
Set Bit(s)
(M) ✛ (Mask) ⇒ M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
1709
1719
1729
09
19
29
39
BSETW
Set Bit(s) in Word
(M : M + 1) ✛ (Mask)
⇒M:M+1
IND16, X
2709
IND16, Y
2719
IND16, Z
2729
EXT
2739
(PK : PC) - 2 ⇒ PK : PC
Push (PC)
(SK : SP) - 2 ⇒ SK : SP
Push (CCR)
(SK : SP) - 2 ⇒ SK : SP
(PK : PC) + Offset ⇒ PK : PC
If V = 0, branch
REL8
REL8
BSR
Branch to Subroutine
BVC2
Branch if Overflow
Clear
Branch if Overflow Set
Condition Codes
Mode
Z
V
C
10, 14
10, 14
10, 14
2
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
8
8
8
8
8
8
8
10
36
mm ff
mm ff
mm ff
mm gggg
mm gggg
mm gggg
mm hh ll
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
rr
10
—
—
—
—
— — — —
B8
rr
6, 2
—
—
—
—
— — — —
10
10
10
If V = 1, branch
REL8
B9
rr
6, 2
—
—
—
—
— — — —
CBA
CLR
Compare A to B
Clear a Byte in
Memory
(A) − (B)
$00 ⇒ M
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
371B
—
2
—
—
—
—
∆
∆
∆
∆
05
15
25
1705
1715
1725
1735
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
0
1
0
0
CLRA
CLRB
CLRD
CLRE
CLRM
CLRW
Clear A
Clear B
Clear D
Clear E
Clear AM
Clear a Word in
Memory
$00 ⇒ A
$00 ⇒ B
$0000 ⇒ D
$0000 ⇒ E
$000000000 ⇒ AM[35:0]
$0000 ⇒ M : M + 1
INH
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
3705
3715
27F5
2775
27B7
—
—
—
—
—
4
4
4
6
6
6
6
2
2
2
2
2
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
— — — —
2705
2715
2725
2735
gggg
gggg
gggg
hh ll
6
6
6
6
—
—
—
—
0
BVS2
MOTOROLA
6-274
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
1
0
0
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
CMPA
Compare A to Memory
(A) − (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
48
58
68
78
1748
1758
1768
1778
2748
2758
2768
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
CMPB
Compare B to Memory
(B) − (M)
6
6
6
2
6
6
6
6
6
6
6
8
8
8
8
8
8
8
2
2
2
2
—
—
∆
∆
∆
∆
$FF − (M) ⇒ M, or M ⇒ M
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
—
One’s Complement
C8
D8
E8
F8
17C8
17D8
17E8
17F8
27C8
27D8
27E8
00
10
20
1700
1710
1720
1730
3700
3710
27F0
2770
—
COM
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
—
—
—
—
∆
∆
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
1
1
1
1
IND16, X
IND16, Y
IND16, Z
EXT
2700
2710
2720
2730
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
∆
∆
0
1
COMA
COMB
COMD
COME
COMW
One’s Complement A
$FF − (A) ⇒ A, or M ⇒ A
One’s Complement B
$FF − (B) ⇒ B, or B ⇒ B
One’s Complement D $FFFF − (D) ⇒ D, or D ⇒ D
One’s Complement E $FFFF − (E) ⇒ E, or E ⇒ E
One’s Complement
$FFFF − M : M + 1 ⇒
Word
M : M + 1, or (M : M + 1) ⇒
M:M+1
Mode
Opcode
Operand
Cycles
S
MV
CPD
Compare D to Memory
(D) − (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
88
98
A8
37B8
37C8
37D8
37E8
37F8
2788
2798
27A8
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
CPE
Compare E to Memory
(E) − (M : M + 1)
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3738
3748
3758
3768
3778
jjkk
gggg
gggg
gggg
hhll
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
CPS
Compare Stack
Pointer to Memory
(SP) − (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
4F
5F
6F
377F
174F
175F
176F
177F
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-275
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
Z
V
C
CPX
Compare IX to
Memory
(IX) − (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
4C
5C
6C
377C
174C
175C
176C
177C
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
CPY
Compare IY to
Memory
(IY) − (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
4D
5D
6D
377D
174D
175D
176D
177D
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
CPZ
Compare IZ to
Memory
(IZ) − (M : M + 1)
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
4E
5E
6E
377E
174E
175E
176E
177E
3721
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
6
6
6
4
6
6
6
6
2
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
U
∆
—
—
—
—
∆
∆
∆
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
—
—
DAA
Decimal Adjust A
(A)10
DEC
Decrement Memory
(M) − $01 ⇒ M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
01
11
21
1701
1711
1721
1731
ff
ff
ff
gggg
gggg
gggg
hh ll
DECA
DECB
DECW
Decrement A
Decrement B
Decrement Memory
Word
(A) − $01 ⇒ A
(B) − $01 ⇒ B
(M : M + 1) − $0001
⇒M:M+1
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
3701
3711
—
—
8
8
8
8
8
8
8
2
2
2701
2711
2721
2731
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
∆
∆
∆
—
EDIV
Extended Unsigned
Integer Divide
INH
3728
—
24
—
—
—
—
∆
∆
∆
∆
EDIVS
Extended Signed
Integer Divide
INH
3729
—
38
—
—
—
—
∆
∆
∆
∆
EMUL
Extended Unsigned
Multiply
Extended Signed
Multiply
Exclusive OR A
(E : D) / (IX)
Quotient ⇒ IX
Remainder ⇒ D
(E : D) / (IX)
Quotient ⇒ IX
Remainder ⇒ D
(E) ∗ (D) ⇒ E : D
INH
3725
—
10
—
—
—
—
∆
∆
—
∆
(E) ∗ (D) ⇒ E : D
INH
3726
—
8
—
—
—
—
∆
∆
—
∆
(A) ⊕ (M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
44
54
64
74
1744
1754
1764
1774
2744
2754
2764
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
EMULS
EORA
MOTOROLA
6-276
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
EORB
Exclusive OR B
(B) ⊕ (M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C4
D4
E4
F4
17C4
17D4
17E4
17F4
27C4
27D4
27E4
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
EORD
Exclusive OR D
(D) ⊕ (M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
84
94
A4
37B4
37C4
37D4
37E4
37F4
2784
2794
27A4
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
EORE
Exclusive OR E
(E) ⊕ (M : M + 1) ⇒ E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3734
3744
3754
3764
3774
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
0
—
FDIV
372B
—
—
—
—
—
—
∆
∆
∆
INH
3727
—
8
—
—
—
—
∆
∆
∆
∆
INH
372A
—
22
—
—
—
—
—
∆
0
∆
INC
Increment Memory
(D) / (IX) ⇒ IX
Remainder ⇒ D
(E) ∗ (D) ⇒ E : D[31:1]
0 ⇒ D[0]
(D) / (IX) ⇒ IX
Remainder ⇒ D
(M) + $01 ⇒ M
INH
IDIV
Fractional
Unsigned Divide
Fractional Signed
Multiply
Integer Divide
4
6
6
6
6
22
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
03
13
23
1703
1713
1723
1733
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
∆
—
INCA
INCB
INCW
Increment A
Increment B
Increment Memory
Word
(A) + $01 ⇒ A
(B) + $01 ⇒ B
(M : M + 1) + $0001
⇒M:M+1
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
3703
3713
—
—
8
8
8
8
8
8
8
2
2
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
—
—
2703
2713
2723
2733
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
∆
∆
∆
—
JMP
Jump
〈ea〉 ⇒ PK : PC
EXT20
IND20, X
IND20, Y
IND20, Z
7A
4B
5B
6B
zb hh ll
zg gggg
zg gggg
zg gggg
6
8
8
8
—
—
—
—
— — — —
JSR
Jump to Subroutine
EXT20
IND20, X
IND20, Y
IND20, Z
FA
89
99
A9
zb hh ll
zg gggg
zg gggg
zg gggg
10
12
12
12
—
—
—
—
— — — —
LBCC2
Long Branch if Carry
Clear
Long Branch if Carry
Set
Long Branch if Equal
to Zero
Long Branch if EV Set
Push (PC)
(SK : SP) − $0002 ⇒ SK : SP
Push (CCR)
(SK : SP) − $0002 ⇒ SK : SP
〈ea〉 ⇒ PK : PC
If C = 0, branch
REL16
3784
rrrr
6, 4
—
—
—
—
— — — —
If C = 1, branch
REL16
3785
rrrr
6, 4
—
—
—
—
— — — —
If Z = 1, branch
REL16
3787
rrrr
6, 4
—
—
—
—
— — — —
FMULS
LBCS2
LBEQ2
LBEV2
LBGE2
LBGT2
Long Branch if Greater
Than or Equal to Zero
Long Branch if Greater
Than Zero
CPU16
REFERENCE MANUAL
Mode
Opcode
Operand
Cycles
S
MV
If EV = 1, branch
REL16
3791
rrrr
6, 4
—
—
—
—
— — — —
If N ⊕ V = 0, branch
REL16
378C
rrrr
6, 4
—
—
—
—
— — — —
If Z ✛ (N ⊕ V) = 0, branch
REL16
378E
rrrr
6, 4
—
—
—
—
— — — —
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-277
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Mnemonic
Description
Address
Instruction
Condition Codes
H
EV
N
2
Long Branch if Higher
If C ✛ Z = 0, branch
REL16
3782
rrrr
6, 4
—
—
—
—
— — — —
LBLE2
If Z ✛ (N ⊕ V) = 1, branch
REL16
378F
rrrr
6, 4
—
—
—
—
— — — —
If C ✛ Z = 1, branch
REL16
3783
rrrr
6, 4
—
—
—
—
— — — —
If N ⊕ V = 1, branch
REL16
378D
rrrr
6, 4
—
—
—
—
— — — —
LBMI2
Long Branch if Less
Than or Equal to Zero
Long Branch if Lower
or Same
Long Branch if Less
Than Zero
Long Branch if Minus
If N = 1, branch
REL16
378B
rrrr
6, 4
—
—
—
—
— — — —
LBMV2
Long Branch if MV Set
If MV = 1, branch
REL16
3790
rrrr
6, 4
—
—
—
—
— — — —
LBNE2
Long Branch if Not
Equal to Zero
Long Branch if Plus
If Z = 0, branch
REL16
3786
rrrr
6, 4
—
—
—
—
— — — —
If N = 0, branch
REL16
378A
rrrr
6, 4
—
—
—
—
— — — —
If 1 = 1, branch
If 1 = 0, branch
Push (PC)
(SK : SP) − 2 ⇒ SK : SP
Push (CCR)
(SK : SP) − 2 ⇒ SK : SP
(PK : PC) + Offset ⇒
PK : PC
If V = 0, branch
REL16
REL16
3780
3781
rrrr
rrrr
6
6
—
—
—
—
—
—
—
—
— — — —
— — — —
REL16
27F9
rrrr
10
—
—
—
—
— — — —
REL16
3788
rrrr
6, 4
—
—
—
—
— — — —
LBHI
LBLS2
LBLT2
LBPL2
Freescale Semiconductor, Inc...
Operation
Mode
Opcode
Operand
Cycles
S
MV
Z
V
C
LBRA
LBRN
LBSR
Long Branch Always
Long Branch Never
Long Branch to
Subroutine
LBVC2
Long Branch if
Overflow Clear
LBVS2
If V = 1, branch
REL16
3789
rrrr
6, 4
—
—
—
—
— — — —
LDAA
Long Branch if
Overflow Set
Load A
(M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
45
55
65
75
1745
1755
1765
1775
2745
2755
2765
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
LDAB
Load B
(M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C5
D5
E5
F5
17C5
17D5
17E5
17F5
27C5
27D5
27E5
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
∆
LDD
Load D
(M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
85
95
A5
37B5
37C5
37D5
37E5
37F5
2785
2795
27A5
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
LDE
Load E
(M : M + 1) ⇒ E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3735
3745
3755
3765
3775
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
0
—
LDED
Load Concatenated
E and D
(M : M + 1) ⇒ E
(M + 2 : M + 3) ⇒ D
EXT
2771
hh ll
4
6
6
6
6
8
—
—
—
—
— — — —
MOTOROLA
6-278
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
(M : M + 1)X ⇒ H R
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
INH
27B0
—
8
—
—
—
—
— — — —
Z
V
C
LDHI
Initialize H and I
LDS
Load SP
(M : M + 1) ⇒ SP
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
CF
DF
EF
17CF
17DF
17EF
17FF
37BF
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
6
6
6
6
6
6
6
4
—
—
—
—
∆
∆
0
—
LDX
Load IX
(M : M + 1) ⇒ IX
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CC
DC
EC
37BC
17CC
17DC
17EC
17FC
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
0
—
LDY
Load IY
(M : M + 1) ⇒ IY
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
CD
DD
ED
37BD
17CD
17DD
17ED
17FD
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
6
6
6
4
6
6
6
6
—
—
—
—
∆
∆
0
—
LDZ
Load IZ
(M : M + 1) ⇒ IZ
6
6
6
4
6
6
6
6
4, 20
—
—
∆
∆
0
—
If S
then STOP
else NOP
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
Low Power Stop
CE
DE
EE
37BE
17CE
17DE
17EE
17FE
27F1
—
LPSTOP
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
—
—
—
—
— — — —
LSR
Logical Shift Right
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0F
1F
2F
170F
171F
172F
173F
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
0
∆
∆
∆
LSRA
Logical Shift Right A
INH
370F
—
8
8
8
8
8
8
8
2
—
—
—
—
0
∆
∆
∆
LSRB
Logical Shift Right B
INH
371F
—
2
—
—
—
—
0
∆
∆
∆
LSRD
Logical Shift Right D
INH
27FF
—
2
—
—
—
—
0
∆
∆
∆
LSRE
Logical Shift Right E
INH
277F
—
2
—
—
—
—
0
∆
∆
∆
LSRW
Logical Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270F
271F
272F
273F
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
0
∆
∆
∆
Freescale Semiconductor, Inc...
(M : M + 1)Y ⇒ I R
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-279
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IMM8
Opcode
7B
Operand
xoyo
Cycles
12
S MV H
— ∆ —
EV N Z
∆ — —
IXP to EXT
EXT to IXP
EXT to
EXT
IXP to EXT
EXT to IXP
EXT to
EXT
30
32
37FE
ff hh ll
ff hh ll
hh ll hh ll
31
33
37FF
V C
∆ —
8
8
10
—
—
—
—
∆
∆
0
—
ff hh ll
ff hh ll
hh ll hh ll
8
8
10
—
—
—
—
∆
∆
0
—
3724
—
10
—
—
—
—
— — —
∆
02
12
22
1702
1712
1722
1732
ff
ff
ff
gggg
gggg
gggg
hh ll
8
8
8
8
8
8
8
2
2
2
2
—
—
—
—
∆
∆
∆
∆
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
MAC
Multiply and
Accumulate
Signed 16-Bit
Fractions
(HR) ∗ (IR) ⇒ E : D
(AM) + (E : D) ⇒ AM
Qualified (IX) ⇒ IX
Qualified (IY) ⇒ IY
(HR) ⇒ IZ
(M : M + 1)X ⇒ HR
(M : M + 1)Y ⇒ IR
MOVB
Move Byte
(M1) ⇒ M2
MOVW
Move Word
(M : M + 11) ⇒ M : M + 12
MUL
NEG
Multiply
Negate Memory
(A) ∗ (B) ⇒ D
$00 − (M) ⇒ M
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
NEGA
NEGB
NEGD
NEGE
NEGW
Negate A
Negate B
Negate D
Negate E
Negate Memory Word
$00 − (A) ⇒ A
$00 − (B) ⇒ B
$0000 − (D) ⇒ D
$0000 − (E) ⇒ E
$0000 − (M : M + 1)
⇒M:M+1
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
3702
3712
27F2
2772
—
—
—
—
2702
2712
2722
2732
gggg
gggg
gggg
hh ll
NOP
ORAA
Null Operation
OR A
—
(A) ✛ (M) ⇒ A
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
274C
—
8
8
8
8
2
—
—
—
—
— — — —
47
57
67
77
1747
1757
1767
1777
2747
2757
2767
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
ORAB
OR B
(B) ✛ (M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C7
D7
E7
F7
17C7
17D7
17E7
17F7
27C7
27D7
27E7
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
ORD
OR D
(D) ✛ (M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
87
97
A7
37B7
37C7
37D7
37E7
37F7
2787
2797
27A7
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
MOTOROLA
6-280
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Operand
Cycles
S
MV
H
EV
N
Z
V
C
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
3737
3747
3757
3767
3777
373B
jj kk
gggg
gggg
gggg
hh ll
jj kk
4
6
6
6
6
4
—
—
—
—
∆
∆
0
—
∆
∆
∆
∆
∆
∆
∆
∆
(SK : SP) + $0001 ⇒ SK : SP
Push (A)
(SK : SP) − $0002 ⇒ SK : SP
(SK : SP) + $0001 ⇒ SK : SP
Push (B)
(SK : SP) − $0002 ⇒ SK : SP
INH
3708
—
4
—
—
—
—
— — — —
INH
3718
—
4
—
—
—
—
— — — —
For mask bits 0 to 7:
IMM8
34
ii
4 + 2N
—
—
—
—
— — — —
(E) ✛ (M : M + 1) ⇒ E
ORP 1
(CCR) ✛ IMM16 ⇒ CCR
PSHA
OR Condition Code
Register
Push A
PSHB
Push B
PSHM
Push Multiple
Registers
PULB
PULM1
PULMAC
RMAC
If mask bit set
Push register
(SK : SP) − 2 ⇒ SK : SP
Push MAC Registers
MAC Registers ⇒ Stack
Pull A
(SK : SP) + $0002 ⇒ SK : SP
Pull (A)
(SK : SP) – $0001 ⇒ SK : SP
Pull B
(SK : SP) + $0002 ⇒ SK : SP
Pull (B)
(SK : SP) – $0001 ⇒ SK : SP
Pull Multiple Registers
For mask bits 0 to 7:
Mask bits:
0 = CCR[15:4]
1=K
2 = IZ
3 = IY
4 = IX
5=E
6=D
7 = (Reserved)
Pull MAC State
Repeating
Multiply and
Accumulate
Signed 16-Bit
Fractions
Condition Codes
Opcode
OR E
PSHMAC
PULA
Instruction
Mode
ORE
Mask bits:
0=D
1=E
2 = IX
3 = IY
4 = IZ
5=K
6 = CCR
7 = (Reserved)
Address
N=
number of
registers
pushed
INH
27B8
—
14
—
—
—
—
— — — —
INH
3709
—
6
—
—
—
—
— — — —
INH
3719
—
6
—
—
—
—
— — — —
IMM8
35
ii
4+2(N+1)
∆
∆
∆
∆
∆
Repeat until (E) < 0
(AM) + (H) ∗ (I) ⇒ AM
Qualified (IX) ⇒ IX;
Qualified (IY) ⇒ IY;
(M : M + 1)X ⇒ H;
(M : M + 1) ⇒ I
—
—
∆
—
—
—
—
∆
— — — —
∆
∆
N=
number of
registers
pulled
If mask bit set
(SK : SP) + 2 ⇒ SK : SP
Pull register
Stack ⇒ MAC Registers
∆
INH
IMM8
27B9
FB
—
xoyo
16
6 + 12
per
iteration
— — — —
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
Y
(E) − 1 ⇒ E
Until (E) < $0000
ROL
Rotate Left
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0C
1C
2C
170C
171C
172C
173C
ff
ff
ff
gggg
gggg
gggg
hh ll
ROLA
Rotate Left A
INH
370C
—
8
8
8
8
8
8
8
2
ROLB
Rotate Left B
INH
371C
—
2
CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-281
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
ROLD
Rotate Left D
INH
27FC
—
2
—
—
—
—
∆
∆
∆
∆
ROLE
Rotate Left E
INH
277C
—
2
—
—
—
—
∆
∆
∆
∆
ROLW
Rotate Left Word
IND16, X
IND16, Y
IND16, Z
EXT
270C
271C
272C
273C
gggg
gggg
gggg
hh ll
8
8
8
8
—
—
—
—
∆
∆
∆
∆
ROR
Rotate Right Byte
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
0E
1E
2E
170E
171E
172E
173E
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
∆
∆
RORA
Rotate Right A
INH
370E
—
8
8
8
8
8
8
8
2
—
—
—
—
∆
∆
∆
∆
RORB
Rotate Right B
INH
371E
—
2
—
—
—
—
∆
∆
∆
∆
RORD
Rotate Right D
INH
27FE
—
2
—
—
—
—
∆
∆
∆
∆
RORE
Rotate Right E
INH
277E
—
2
—
—
—
—
∆
∆
∆
∆
RORW
Rotate Right Word
gggg
gggg
gggg
hh ll
—
8
8
8
8
12
—
—
—
∆
∆
∆
∆
Return from Interrupt
270E
271E
272E
273E
2777
—
RTI3
IND16, X
IND16, Y
IND16, Z
EXT
INH
∆
∆
∆
∆
∆
∆
∆
∆
RTS4
Return from Subroutine
INH
27F7
—
12
—
—
—
—
— — — —
SBA
SBCA
Subtract B from A
Subtract with Carry
from A
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
370A
—
2
—
—
—
—
∆
∆
∆
∆
42
52
62
72
1742
1752
1762
1772
2742
2752
2762
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
MOTOROLA
6-282
(SK : SP) + 2 ⇒ SK : SP
Pull CCR
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) − 6 ⇒ PK : PC
(SK : SP) + 2 ⇒ SK : SP
Pull PK
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) − 2 ⇒ PK : PC
(A) − (B) ⇒ A
(A) − (M) − C ⇒ A
Mode
Opcode
Operand
Cycles
S
MV
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
SBCB
Subtract with Carry
from B
(B) − (M) − C ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C2
D2
E2
F2
17C2
17D2
17E2
17F2
27C2
27D2
27E2
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
SBCD
Subtract with Carry
from D
(D) − (M : M + 1) − C ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
82
92
A2
37B2
37C2
37D2
37E2
37F2
2782
2792
27A2
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
SBCE
Subtract with Carry
from E
(E) − (M : M + 1) − C ⇒ E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3732
3742
3752
3762
3772
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
∆
∆
SDE
STAA
Subtract D from E
Store A
(E) − (D)⇒ E
(A) ⇒ M
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
2779
—
4
6
6
6
6
2
—
—
—
—
∆
∆
∆
∆
4A
5A
6A
174A
175A
176A
177A
274A
275A
276A
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
4
4
4
6
6
6
6
4
4
4
—
—
—
—
∆
∆
0
—
STAB
Store B
(B) ⇒ M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CA
DA
EA
17CA
17DA
17EA
17FA
27CA
27DA
27EA
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
4
4
4
6
6
6
6
4
4
4
—
—
—
—
∆
∆
0
—
STD
Store D
(D) ⇒ M : M + 1
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
8A
9A
AA
37CA
37DA
37EA
37FA
278A
279A
27AA
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
4
4
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
0
—
STE
Store E
(E) ⇒ M : M + 1
IND16, X
IND16, Y
IND16, Z
EXT
374A
375A
376A
377A
gggg
gggg
gggg
hh ll
6
6
6
6
—
—
—
—
∆
∆
0
—
STED
Store Concatenated
D and E
(E) ⇒ M : M + 1
(D) ⇒ M + 2 : M + 3
EXT
2773
hh ll
8
—
—
—
—
— — — —
CPU16
REFERENCE MANUAL
Mode
Opcode
Operand
Cycles
S
MV
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6-283
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
H
EV
N
Z
V
C
STS
Store Stack Pointer
(SP) ⇒ M : M + 1
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8F
9F
AF
178F
179F
17AF
17BF
ff
ff
ff
gggg
gggg
gggg
hh ll
4
4
4
6
6
6
6
—
—
—
—
∆
∆
0
—
STX
Store IX
(IX) ⇒ M : M + 1
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8C
9C
AC
178C
179C
17AC
17BC
ff
ff
ff
gggg
gggg
gggg
hh ll
4
4
4
6
6
6
6
—
—
—
—
∆
∆
0
—
STY
Store IY
(IY) ⇒ M : M + 1
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8D
9D
AD
178D
179D
17AD
17BD
ff
ff
ff
gggg
gggg
gggg
hh ll
4
4
4
6
6
6
6
—
—
—
—
∆
∆
0
—
STZ
Store Z
(IZ) ⇒ M : M + 1
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
8E
9E
AE
178E
179E
17AE
17BE
ff
ff
ff
gggg
gggg
gggg
hh ll
4
4
4
6
6
6
6
—
—
—
—
∆
∆
0
—
SUBA
Subtract from A
(A) − (M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
40
50
60
70
1740
1750
1760
1770
2740
2750
2760
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
SUBB
Subtract from B
(B) − (M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
C0
D0
E0
F0
17C0
17D0
17E0
17F0
27C0
27D0
27E0
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
SUBD
Subtract from D
(D) − (M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
80
90
A0
37B0
37C0
37D0
37E0
37F0
2780
2790
27A0
ff
ff
ff
jj kk
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
4
6
6
6
6
6
6
6
—
—
—
—
∆
∆
∆
∆
SUBE
Subtract from E
(E) − (M : M + 1) ⇒ E
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
3730
3740
3750
3760
3770
jj kk
gggg
gggg
gggg
hh ll
4
6
6
6
6
—
—
—
—
∆
∆
∆
∆
MOTOROLA
6-284
Mode
Opcode
Operand
Cycles
S
MV
INSTRUCTION GLOSSARY
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
SWI
Software Interrupt
SXT
Sign Extend B into A
TAB
TAP
TBA
TBEK
TBSK
TBXK
TBYK
TBZK
TDE
TDMSK
Transfer A to B
Transfer A to CCR
Transfer B to A
Transfer B to EK
Transfer B to SK
Transfer B to XK
Transfer B to YK
Transfer B to ZK
Transfer D to E
Transfer D to
XMSK : YMSK
Transfer D to CCR
TDP1
TED
TEDM
Transfer E to D
Transfer E and D to
AM[31:0]
Sign Extend AM
Description
(PK : PC) + $0002 ⇒ PK : PC
Push (PC)
(SK : SP) − $0002 ⇒ SK : SP
Push (CCR)
(SK : SP) − $0002 ⇒ SK : SP
$0 ⇒ PK
SWI Vector ⇒ PC
If B7 = 1
then $FF ⇒ A
else $00 ⇒ A
(A) ⇒ B
(A[7:0]) ⇒ CCR[15:8]
(B) ⇒ A
(B[3:0]) ⇒ EK
(B[3:0]) ⇒ SK
(B[3:0]) ⇒ XK
(B[3:0]) ⇒ YK
(B[3:0]) ⇒ ZK
(D) ⇒ E
(D[15:8]) ⇒ X MASK
(D[7:0]) ⇒ Y MASK
(D) ⇒ CCR[15:4]
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
INH
3720
—
16
—
—
—
—
— — — —
Z
V
C
INH
27F8
—
2
—
—
—
—
∆
∆
— —
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3717
37FD
3707
27FA
379F
379C
379D
379E
277B
372F
—
—
—
—
—
—
—
—
—
—
2
4
2
2
2
2
2
2
2
2
—
∆
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
∆
∆
∆
—
—
—
—
—
∆
—
∆
∆
∆
—
—
—
—
—
∆
—
0
∆
0
—
—
—
—
—
0
—
—
∆
—
—
—
—
—
—
—
—
INH
372D
—
4
∆
∆
∆
∆
∆
∆
∆
∆
(E) ⇒ D
INH
27FB
—
2
—
—
—
—
∆
∆
0
—
(E) ⇒ AM[31:16]
(D) ⇒ AM[15:0]
AM[35:32] = AM31
(EK) ⇒ B[3:0]
$0 ⇒ B[7:4]
INH
27B1
—
4
—
0
—
0
— — — —
INH
27BB
—
2
—
—
—
—
— — — —
TEKB
Transfer EK to B
TEM
Transfer E to
AM[31:16]
Sign Extend AM
Clear AM LSB
(E) ⇒ AM[31:16]
$00 ⇒ AM[15:0]
AM[35:32] = AM31
INH
27B2
—
4
—
0
—
0
— — — —
TMER
Transfer Rounded AM
to E
INH
27B4
—
6
—
∆
—
∆
∆
∆
— —
TMET
Transfer Truncated
AM to E
INH
27B5
—
2
—
—
—
—
∆
∆
— —
TMXED
Transfer AM to
IX : E : D
INH
27B3
—
6
—
—
—
—
— — — —
TPA
TPD
TSKB
Transfer CCR to A
Transfer CCR to D
Transfer SK to B
INH
INH
INH
37FC
372C
37AF
—
—
—
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
— — — —
— — — —
— — — —
TST
Test Byte
Zero or Minus
Rounded (AM) ⇒ Temp
If (SM • (EV ✛ MV))
then Saturation Value ⇒ E
else Temp[31:16] ⇒ E
If (SM • (EV ✛ MV))
then Saturation Value ⇒ E
else AM[31:16] ⇒ E
AM[35:32] ⇒ IX[3:0]
AM35 ⇒ IX[15:4]
AM[31:16] ⇒ E
AM[15:0] ⇒ D
(CCR[15:8]) ⇒ A
(CCR) ⇒ D
(SK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(M) − $00
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
06
16
26
1706
1716
1726
1736
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
∆
∆
0
0
TSTA
Test A for
Zero or Minus
Test B for
Zero or Minus
Test D for
Zero or Minus
Test E for
Zero or Minus
(A) − $00
INH
3706
—
6
6
6
6
6
6
6
2
—
—
—
—
∆
∆
0
0
(B) − $00
INH
3716
—
2
—
—
—
—
∆
∆
0
0
(D) − $0000
INH
27F6
—
2
—
—
—
—
∆
∆
0
0
(E) − $0000
INH
2776
—
2
—
—
—
—
∆
∆
0
0
TSTB
TSTD
TSTE
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6-285
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Table 6-36 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
Z
V
C
—
—
—
—
∆
∆
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSTW
Test for
Zero or Minus Word
(M : M + 1) − $0000
IND16, X
IND16, Y
IND16, Z
EXT
2706
2716
2726
2736
gggg
gggg
gggg
hh ll
TSX
TSY
TSZ
TXKB
Transfer SP to X
Transfer SP to Y
Transfer SP to Z
Transfer XK to B
INH
INH
INH
INH
274F
275F
276F
37AC
—
—
—
—
TXS
TXY
TXZ
TYKB
Transfer X to SP
Transfer X to Y
Transfer X to Z
Transfer YK to B
INH
INH
INH
INH
374E
275C
276C
37AD
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TYS
TYX
TYZ
TZKB
Transfer Y to SP
Transfer Y to X
Transfer Y to Z
Transfer ZK to B
INH
INH
INH
INH
375E
274D
276D
37AE
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TZS
TZX
TZY
WAI
XGAB
XGDE
XGDX
XGDY
XGDZ
XGEX
XGEY
XGEZ
Transfer Z to SP
Transfer Z to X
Transfer Z to Y
Wait for Interrupt
Exchange A with B
Exchange D with E
Exchange D with IX
Exchange D with IY
Exchange D with IZ
Exchange E with IX
Exchange E with IY
Exchange E with IZ
(SK : SP) + $0002 ⇒ XK : IX
(SK : SP) + $0002 ⇒ YK : IY
(SK : SP) + $0002 ⇒ ZK : IZ
(XK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(XK : IX) − $0002 ⇒ SK : SP
(XK : IX) ⇒ YK : IY
(XK : IX) ⇒ ZK : IZ
(YK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(YK : IY) − $0002 ⇒ SK : SP
(YK : IY) ⇒ XK : IX
(YK : IY) ⇒ ZK : IZ
(ZK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(ZK : IZ) − $0002 ⇒ SK : SP
(ZK : IZ) ⇒ XK : IX
(ZK : IZ) ⇒ YK : IY
WAIT
(A) ⇔ (B)
(D) ⇔ (E)
(D) ⇔ (IX)
(D) ⇔ (IY)
(D) ⇔ (IZ)
(E) ⇔ (IX)
(E) ⇔ (IY)
(E) ⇔ (IZ)
6
6
6
6
2
2
2
2
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
376E
274E
275E
27F3
371A
277A
37CC
37DC
37EC
374C
375C
376C
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
8
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NOTES:
1. CCR[15:4] change according to the results of the operation. The PK field is not affected.
2. Cycle times for conditional branches are shown in “taken, not taken” order.
3. CCR[15:0] change according to the copy of the CCR pulled from the stack.
4. PK field changes according to the state pulled from the stack. The rest of the CCR is not affected.
MOTOROLA
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INSTRUCTION GLOSSARY
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SECTION 7 INSTRUCTION PROCESS
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This section explains how the CPU16 fetches and executes instructions. Topics include instruction format, pipelining, and changes in program flow. Other forms of the
instruction process are covered in SECTION 9 EXCEPTION PROCESSING and SECTION 11 DIGITAL SIGNAL PROCESSING. See SECTION 5 INSTRUCTION SET
and SECTION 6 INSTRUCTION GLOSSARY for detailed information concerning instructions.
7.1 Instruction Format
CPU16 instructions consist of an 8-bit opcode, which may be preceded by an 8-bit prebyte and/or followed by one or more operands.
Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone, but
page 1, 2, and 3 opcodes are pointed to by a prebyte code on page 0. The prebytes
are $17 (page 1), $27 (page 2), and $37 (page 3).
Operands can be four bits, eight bits, or sixteen bits in length. However, because the
CPU16 fetches 16-bit instruction words from even byte boundaries, each instruction
must contain an even number of bytes.
Operands are organized as bytes, words, or a combination of bytes and words. Fourbit operands are either zero-extended to eight bits, or packed two to a byte. The largest
instructions are six bytes in length. Size, order, and function of operands are evaluated
when an instruction is decoded.
A page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions that
use 8-bit indexed, immediate, and relative addressing modes have this form — code
written with these instructions is very compact.
Table 7-1 shows basic CPU16 instruction formats. Table 7-2, Table 7-3, Table 7-4,
and Table 7-5 show instructions in opcode order by page.
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7-1
Freescale Semiconductor, Inc.
Table 7-1 Basic Instruction Formats
8-Bit Opcode with 8-Bit Operand
15
14
13
12
11
10
9
8
7
6
5
Opcode
4
3
2
1
0
2
1
0
Operand
8-Bit Opcode with 4-Bit Index Extensions
15
14
13
12
11
10
9
8
7
Opcode
6
5
4
3
X Extension
Y Extension
8-Bit Opcode, Argument(s)
15
14
13
12
11
10
9
8
7
6
5
Opcode
4
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Operand
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Operand(s)
Operand(s)
8-Bit Opcode with 8-Bit Prebyte, No Argument
15
14
13
12
11
10
9
8
7
6
5
4
Prebyte
Opcode
8-Bit Opcode with 8-Bit Prebyte, Argument(s)
15
14
13
12
11
10
9
8
7
6
5
4
Prebyte
Opcode
Operand(s)
Operand(s)
8-Bit Opcode with 20-Bit Argument
15
14
13
12
11
10
9
8
Opcode
7
6
5
4
$0
Extension
Operand
7.2 Execution Model
This description builds up a conceptual model of the mechanism the CPU16 uses to
fetch and execute instructions. The functional divisions in the model do not necessarily
correspond to distinct architectural subunits of the microprocessor. SECTION 10 DEVELOPMENT SUPPORT expands the model to include the concept of deterministic
opcode tracking.
As shown in Figure 7-1, there are three functional blocks involved in fetching, decoding, and executing instructions. These are the microsequencer, the instruction pipeline, and the execution unit. These elements function concurrently; at any given time,
all three may be active.
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IPIPE0
IPIPE1
MICROSEQUENCER
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INSTRUCTION PIPELINE
DATA
BUS
A
B
C
EXECUTION UNIT
16 EXEC UNIT MODEL
Figure 7-1 Instruction Execution Model
7.2.1 Microsequencer
The microsequencer controls the order in which instructions are fetched, advanced
through the pipeline, and executed. It increments the program counter and generates
multiplexed external tracking signals IPIPE0 and IPIPE1 from internal signals that control execution sequence.
7.2.2 Instruction Pipeline
The pipeline is a three stage FIFO that holds instructions while they are decoded and
executed. Depending upon instruction size, as many as three instructions can be in
the pipeline at one time (single-word instructions, one held in stage C, one being executed in stage B, and one latched in stage A).
7.2.3 Execution Unit
The execution unit evaluates opcodes, interfaces with the microsequencer to advance
instructions through the pipeline, and performs instruction operations.
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7.3 Execution Process
Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are
evaluated in stage B. The execution unit can access operands in either stage A or
stage B (stage B accesses are limited to 8-bit operands). When execution is complete,
opcodes are moved from stage B to stage C, where they remain until the next instruction is complete.
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A prefetch mechanism in the microsequencer reads instruction words from memory
and increments the program counter. When instruction execution begins, the program
counter points to an address six bytes after the address of the first word of the instruction being executed.
The number of machine cycles necessary to complete an execution sequence varies
according to the complexity of the instruction. SECTION 8 INSTRUCTION TIMING
gives detailed information concerning execution time calculation.
7.3.1 Detailed Process
The following description divides execution processing into discrete steps in order to
describe it fully. Events in the steps are often concurrent. Refer to SECTION 10 DEVELOPMENT SUPPORT for information concerning signals used to track the sequence of execution. Relative PC values are given to aid following instructions through
the pipeline.
A. PK : PC points to the first word address (FWA) of the instruction to be executed
(PK : PC = FWA + $0000).
B. The microsequencer initiates a read from the memory address pointed to by PK
: PC, signals pipeline stage A to latch the word (FWA + $0000) read from memory, then increments PK : PC (PK : PC = FWA + $0002).
C. The latched word contains either an 8-bit prebyte and an 8-bit opcode or an 8bit opcode and an 8-bit operand. The microsequencer advances (FWA +
$0000) to stage B, prefetches (FWA + $0002) from the data bus, and increments PK : PC (PK : PC = FWA + $0004).
D. Stage A now contains (FWA + $0002) and stage B contains (FWA + $0000).
The execution unit determines what operations must be performed and the
character of the operands needed to perform them. The microsequencer initiates a prefetch from FWA + $0004 and increments PK : PC (PK : PC = FWA
+ $0006). Subsequent execution depends upon instruction format.
1. 8-bit opcode with 8-bit operand — The execution unit reads the operand and
signals that execution has begun. The instruction executes, the content of
stage B advances to stage C, the content of stage A advances to stage B,
and (FWA + $0004) is latched into stage A.
2. 16-bit opcode with no argument — The execution unit signals that execution
has begun. The instruction executes, the content of stage B advances to
stage C, the content of stage A advances to stage B, and (FWA + $0004) is
latched into stage A.
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3. 8-bit opcode with 20-bit argument — The execution unit reads the operand
byte from stage B and the operand word from stage A, then signals that execution has begun. The instruction executes, the content of stage B advances to stage C, and (FWA + $0004) is latched into stage A.
4. 8-bit opcode with argument — The execution unit determines the number of
operands needed, reads an operand byte from stage B and an operand
word from stage A, then signals that execution has begun. The instruction
executes, the content of stage B advances to stage C, and (FWA + $0004)
is latched into stage A — this word can be either the third word of the current
instruction or the first word of a new instruction.
5. 16-bit opcode with argument — The execution unit determines the number
of operand words needed, reads the first operand word from stage A, then
signals that execution has begun. The instruction executes, the content of
stage B advances to stage C, and (FWA + $0004) is latched into stage A —
this word can be either the third word of the current instruction or the first
word of a new instruction.
E. At this point PK : PC = $0006, and the process repeats, but entry points differ
for instructions of different lengths:
1. One-word instructions — Stage B contains a new opcode for the execution
unit to evaluate, and process repeats from D.
2. Two-word instructions — Stage A contains a new opcode, and process repeats from C.
3. Three-word instructions — Stages A and B contain operands from the instruction just completed, and process repeats from B.
Note
Due to the action of the prefetch mechanism, it is necessary to leave
a two-word buffer at the end of program space. The last word of an
instruction must be located at End of Memory – $0004.
The microsequencer always prefetches two words past the first word
address of an instruction while that instruction is executing.
If an instruction is placed in either of the two highest available word
addresses, these fetches may attempt access to addresses that do
not exist — these attempts can cause bus errors.
7.3.2 Changes in Program Flow
When program flow changes, instructions are fetched from a new address. Before execution can begin at the new address, instructions and operands from the previous instruction stream must be removed from the pipeline. If a change in flow is temporary,
a return address must be stored, so that execution of the original instruction stream
can resume after the change in flow.
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At the time an instruction that causes a change in program flow executes, PK : PC
point to FWA + $0006. During execution of an instruction that causes a change of flow,
PK : PC is loaded with the FWA of the new instruction stream. However, stages A and
B still contain words from the old instruction stream. Process steps A through C must
be performed prior to execution from the new instruction stream.
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7.3.2.1 Jumps
Jump instructions cause an immediate, unconditional change in program flow. The
CPU16 jump instruction uses 20-bit extended and indexed addressing modes. It consists of an 8-bit opcode with a 20-bit argument.
7.3.2.2 Branches
Branch instructions cause a change in program flow when a specific precondition is
met. The CPU16 supports 8-bit relative displacement (short), and 16-bit relative displacement (long) branch instructions, as well as specialized bit condition branches that
use indexed addressing modes.
Short branch instructions consist of an 8-bit opcode and an 8-bit operand contained in
one word. Long branch instructions consist of an 8-bit prebyte and an 8-bit opcode in
one word, followed by an operand word. Bit condition branches consist of an 8-bit opcode and an 8-bit operand in one word, followed by one or two operand words.
At the time a branch instruction is executed, PK : PC point to an address equal to the
address of the instruction plus $0006. The range of displacement for each type of
branch is relative to this value, not to the address of the instruction. In addition, because prefetches are automatically aligned to word boundaries, only even offsets are
valid — an odd offset value is rounded down.
The numeric range of short branch and 8-bit indexed offset values is $80 (–128) to $7F
(127). Due to word-alignment, maximum positive offset is $7E. At maximum positive
offset, displacement from the branch instruction is 132. At maximum negative offset
($80), displacement is –122.
The numeric range of long branch and 16-bit indexed offset values is $8000 (–32768)
to $7FFF (32767). Due to word-alignment, maximum positive offset is $7FFE. At maximum positive offset, displacement from the instruction is 32772. At maximum negative offset ($8000), displacement is –32762.
7.3.2.3 Subroutines
Subroutine instructions optimize the process of temporarily executing instructions from
another instruction stream, usually to perform a particular task. The CPU16 can
branch or jump to subroutines. A single instruction returns to the original instruction
stream.
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Subroutines can be called by short (BSR) or long (LBSR) branches, or by a jump
(JSR). The RTS instruction returns control to the calling routine. BSR consists of an 8bit opcode with an 8-bit operand. LBSR consists of an 8-bit prebyte and an 8-bit opcode in one word, followed by an operand word. JSR consists of an 8-bit opcode with
a 20-bit argument. RTS consists of an 8-bit prebyte and an 8-bit opcode in one word.
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When a subroutine instruction is executed, PK : PC contain the address of the calling
instruction plus $0006. All three calling instructions stack return PK : PC values prior
to processing instructions from the new instruction stream. In order for RTS to work
with all three calling instructions, however, the value stacked by BSR must be adjusted.
LBSR and JSR are two-word instructions. In order for program execution to resume
with the instruction immediately following them, RTS must subtract $0002 from the
stacked PK : PC value. BSR is a one-word instruction — it subtracts $0002 from PK :
PC prior to stacking so that execution will resume correctly after RTS.
7.3.2.4 Interrupts
An interrupt routine usually performs a critical task, then returns control to the interrupted instruction stream. Interrupts are a type of exception, and are thus subject to
special rules regarding execution process. SECTION 9 EXCEPTION PROCESSING
covers interrupt exception processing in detail. This discussion is limited to the effects
of SWI (software interrupt) and RTI (return from interrupt) instructions.
Both SWI and RTI consist of an 8-bit prebyte and an 8-bit opcode in one word. SWI
initiates synchronous exception processing. RTI causes execution to resume with the
instruction following the last instruction that completed execution prior to interrupt.
Asynchronous interrupts are serviced at instruction boundaries. PK : PC + $0006 for
the following instruction is stacked, and exception processing begins. In order to resume execution with the correct instruction, RTI subtracts $0006 from the stacked value.
Interrupt exception processing is included in the SWI instruction definition. The PK :
PC value at the time of execution is the first word address of SWI plus $0006. If this
value were stacked, RTI would cause SWI to execute again. In order to resume execution with the instruction following SWI, $0002 is added to the PK : PC value prior to
stacking.
CPU16
REFERENCE MANUAL
INSTRUCTION PROCESS
For More Information On This Product,
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MOTOROLA
7-7
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-2 Page 0 Opcodes
Opcode
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
MOTOROLA
7-8
Mnemonic
COM
DEC
NEG
INC
ASL
CLR
TST
—
BCLR
BSET
BRCLR
BRSET
ROL
ASR
ROR
LSR
COM
DEC
NEG
INC
ASL
CLR
TST
PREBYTE
BCLR
BSET
BRCLR
BRSET
ROL
ASR
ROR
LSR
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
JMP
CPX
CPY
CPZ
CPS
Mode
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
—
IND16, X
IND16, X
IND16, X
IND16, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
PAGE 1
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND20, X
IND8, X
IND8, X
IND8, X
IND8, X
Opcode
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
Mnemonic
COM
DEC
NEG
INC
ASL
CLR
TST
PREBYTE
BCLR
BSET
BRCLR
BRSET
ROL
ASR
ROR
LSR
MOVB
MOVW
MOVB
MOVW
PSHM
PULM
BSR
PREBYTE
BCLR
BSET
BRCLR
BRSET
AIX
AIY
AIZ
AIS
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
JMP
CPX
CPY
CPZ
CPS
INSTRUCTION PROCESS
For More Information On This Product,
Go to: www.freescale.com
Mode
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
PAGE 2
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IXP to EXT
IXP to EXT
EXT to IXP
EXT to IXP
INH
INH
REL8
PAGE 3
EXT
EXT
EXT
EXT
IMM8
IMM8
IMM8
IMM8
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND20, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-2 Page 0 Opcodes (Continued)
Opcode
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
CPU16
REFERENCE MANUAL
Mnemonic
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
JMP
CPX
CPY
CPZ
CPS
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
JSR
STD
BRSET
STX
STY
STZ
STS
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
JSR
STD
BRSET
STX
STY
STZ
STS
Mode
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND20, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND20, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND20, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
Opcode
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Mnemonic
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
JMP
MAC
ADDE
—
—
—
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
JSR
STD
BRSET
STX
STY
STZ
STS
BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
INSTRUCTION PROCESS
For More Information On This Product,
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Mode
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
EXT
IMM8
IMM8
—
—
—
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND20, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
MOTOROLA
7-9
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-2 Page 0 Opcodes (Continued)
Opcode
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
MOTOROLA
7-10
Mnemonic
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
BRCLR
LDX
LDY
LDZ
LDS
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
BRCLR
LDX
LDY
LDZ
LDS
Mode
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, X
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
IND8, Y
Opcode
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Mnemonic
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
BRCLR
LDX
LDY
LDZ
LDS
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
JSR
RMAC
ADDD
—
—
—
INSTRUCTION PROCESS
For More Information On This Product,
Go to: www.freescale.com
Mode
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IND8, Z
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
EXT
IMM8
IMM8
—
—
—
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-3 Page 1 Opcodes
Opcode
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
170A
170B
170C
170D
170E
170F
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
171A
171B
171C
171D
171E
171F
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
174A
174B
174C
174D
174E
174F
CPU16
REFERENCE MANUAL
Mnemonic
COM
DEC
NEG
INC
ASL
CLR
TST
—
BCLR
BSET
—
—
ROL
ASR
ROR
LSR
COM
DEC
NEG
INC
ASL
CLR
TST
—
BCLR
BSET
—
—
ROL
ASR
ROR
LSR
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
CPX
CPY
CPZ
CPS
Mode
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
—
IND8, X
IND8, X
—
—
IND16, X
IND16, X
IND16, X
IND16, X
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
IND8, Y
IND8, Y
—
—
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
—
IND16, X
IND16, X
IND16, X
IND16, X
Opcode
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
172A
172B
172C
172D
172E
172F
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
173A
173B
173C
173D
173E
173F
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
176A
176B
176C
176D
176E
176F
Mnemonic
COM
DEC
NEG
INC
ASL
CLR
TST
—
BCLR
BSET
—
—
ROL
ASR
ROR
LSR
COM
DEC
NEG
INC
ASL
CLR
TST
—
—
—
—
—
ROL
ASR
ROR
LSR
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
CPX
CPY
CPZ
CPS
INSTRUCTION PROCESS
For More Information On This Product,
Go to: www.freescale.com
Mode
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
IND8, Z
IND8, Z
—
—
IND16, Z
IND16, Z
IND16, Z
IND16, Z
EXT
EXT
EXT
EXT
EXT
EXT
EXT
—
—
—
—
—
EXT
EXT
EXT
EXT
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
IND16, Z
IND16, Z
IND16, Z
IND16, Z
MOTOROLA
7-11
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-3 Page 1 Opcodes (Continued)
Opcode
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
175A
175B
175C
175D
175E
175F
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
178A
178B
178C
178D
178E
178F
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
179A
179B
179C
179D
179E
179F
MOTOROLA
7-12
Mnemonic
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
CPX
CPY
CPZ
CPS
—
—
—
—
—
—
—
—
—
—
—
—
STX
STY
STZ
STS
—
—
—
—
—
—
—
—
—
—
—
—
STX
STY
STZ
STS
Mode
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
—
—
—
—
—
—
—
—
—
—
—
IND16, X
IND16, X
IND16, X
IND16, X
—
—
—
—
—
—
—
—
—
—
—
—
IND16, Y
IND16, Y
IND16, Y
IND16, Y
Opcode
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
177A
177B
177C
177D
177E
177F
17A0
17A1
17A2
17A3
17A4
17A5
17A6
17A7
17A8
17A9
17AA
17AB
17AC
17AD
17AE
17AF
17B0
17B1
17B2
17B3
17B4
17B5
17B6
17B7
17B8
17B9
17BA
17BB
17BC
17BD
17BE
17BF
Mnemonic
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
CPX
CPY
CPZ
CPS
—
—
—
—
—
—
—
—
—
—
—
—
STX
STY
STZ
STS
—
—
—
—
—
—
—
—
—
—
—
—
STX
STY
STZ
STS
INSTRUCTION PROCESS
For More Information On This Product,
Go to: www.freescale.com
Mode
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
—
EXT
EXT
EXT
EXT
—
—
—
—
—
—
—
—
—
—
—
—
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
—
—
—
—
—
—
—
—
—
—
—
EXT
EXT
EXT
EXT
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-3 Page 1 Opcodes (Continued)
Opcode
17C0
17C1
17C2
17C3
17C4
17C5
17C6
17C7
17C8
17C9
17CA
17CB
17CC
17CD
17CE
17CF
17D0
17D1
17D2
17D3
17D4
17D5
17D6
17D7
17D8
17D9
17DA
17DB
17DC
17DD
17DE
17DF
CPU16
REFERENCE MANUAL
Mnemonic
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
LDX
LDY
LDZ
LDS
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
LDX
LDY
LDZ
LDS
Mode
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
—
IND16, X
IND16, X
IND16, X
IND16, X
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
IND16, Y
IND16, Y
IND16, Y
IND16, Y
Opcode
17E0
17E1
17E2
17E3
17E4
17E5
17E6
17E7
17E8
17E9
17EA
17EB
17EC
17ED
17EE
17EF
17F0
17F1
17F2
17F3
17F4
17F5
17F6
17F7
17F8
17F9
17FA
17FB
17FC
17FD
17FE
17FF
Mnemonic
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
LDX
LDY
LDZ
LDS
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
LDX
LDY
LDZ
LDS
INSTRUCTION PROCESS
For More Information On This Product,
Go to: www.freescale.com
Mode
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
IND16, Z
IND16, Z
IND16, Z
IND16, Z
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
—
EXT
EXT
EXT
EXT
MOTOROLA
7-13
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-4 Page 2 Opcodes
Opcode
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
270A
270B
270C
270D
270E
270F
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
271A
271B
271C
271D
271E
271F
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
274A
274B
274C
274D
274E
274F
MOTOROLA
7-14
Mnemonic
COMW
DECW
NEGW
INCW
ASLW
CLRW
TSTW
—
BCLRW
BSETW
—
—
ROLW
ASRW
RORW
LSRW
COMW
DECW
NEGW
INCW
ASLW
CLRW
TSTW
—
BCLRW
BSETW
—
—
ROLW
ASRW
RORW
LSRW
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
NOP
TYX
TZX
TSX
Mode
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
—
IND16, X
IND16, X
—
—
IND16, X
IND16, X
IND16, X
IND16, X
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
IND16, Y
IND16, Y
—
—
IND16, Y
IND16, Y
IND16, Y
IND16, Y
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
—
INH
INH
INH
INH
Opcode
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
272A
272B
272C
272D
272E
272F
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
273A
273B
273C
273D
273E
273F
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
276A
276B
276C
276D
276E
276F
Mnemonic
COMW
DECW
NEGW
INCW
ASLW
CLRW
TSTW
—
BCLRW
BSETW
—
—
ROLW
ASRW
RORW
LSRW
COMW
DECW
NEGW
INCW
ASLW
CLRW
TSTW
—
BCLRW
BSETW
—
—
ROLW
ASRW
RORW
LSRW
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
TXZ
TYZ
—
TSZ
INSTRUCTION PROCESS
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Mode
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
IND16, Z
IND16, Z
—
—
IND16, Z
IND16, Z
IND16, Z
IND16, Z
EXT
EXT
EXT
EXT
EXT
EXT
EXT
—
EXT
EXT
—
—
EXT
EXT
EXT
EXT
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
—
INH
INH
—
INH
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-4 Page 2 Opcodes (Continued)
Opcode
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
275A
275B
275C
275D
275E
275F
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
278A
278B
278C
278D
278E
278F
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
279A
279B
279C
279D
279E
279F
CPU16
REFERENCE MANUAL
Mnemonic
SUBA
ADDA
SBCA
ADCA
EORA
LDAA
ANDA
ORAA
CMPA
BITA
STAA
—
TXY
—
TZY
TSY
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
—
—
—
—
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
—
—
—
—
Mode
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
—
INH
—
INH
INH
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
—
E, X
—
—
—
—
—
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
—
E, Y
—
—
—
—
—
Opcode
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
277A
277B
277C
277D
277E
277F
27A0
27A1
27A2
27A3
27A4
27A5
27A6
27A7
27A8
27A9
27AA
27AB
27AC
27AD
27AE
27AF
27B0
27B1
27B2
27B3
27B4
27B5
27B6
27B7
27B8
27B9
27BA
27BB
27BC
27BD
27BE
27BF
Mnemonic
COME
LDED
NEGE
STED
ASLE
CLRE
TSTE
RTI
ADE
SDE
XGDE
TDE
ROLE
ASRE
RORE
LSRE
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
—
—
—
—
LDHI
TEDM
TEM
TMXED
TMER
TMET
ASLM
CLRM
PSHMAC
PULMAC
ASRM
TEKB
—
—
—
—
INSTRUCTION PROCESS
For More Information On This Product,
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Mode
INH
EXT
INH
EXT
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
—
E, Z
—
—
—
—
—
EXT
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
—
—
—
—
MOTOROLA
7-15
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-4 Page 2 Opcodes (Continued)
Opcode
27C0
27C1
27C2
27C3
27C4
27C5
27C6
27C7
27C8
27C9
27CA
27CB
27CC
27CD
27CE
27CF
27D0
27D1
27D2
27D3
27D4
27D5
27D6
27D7
27D8
27D9
27DA
27DB
27DC
27DD
27DE
27DF
MOTOROLA
7-16
Mnemonic
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
—
—
—
—
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
—
—
—
—
Mode
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
E, X
—
—
—
—
—
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
E, Y
—
—
—
—
—
Opcode
27E0
27E1
27E2
27E3
27E4
27E5
27E6
27E7
27E8
27E9
27EA
27EB
27EC
27ED
27EE
27EF
27F0
27F1
27F2
27F3
27F4
27F5
27F6
27F7
27F8
27F9
27FA
27FB
27FC
27FD
27FE
27FF
Mnemonic
SUBB
ADDB
SBCB
ADCB
EORB
LDAB
ANDB
ORAB
CMPB
BITB
STAB
—
—
—
—
—
COMD
LPSTOP
NEGD
WAI
ASLD
CLRD
TSTD
RTS
SXT
LBSR
TBEK
TED
ROLD
ASRD
RORD
LSRD
INSTRUCTION PROCESS
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Mode
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
E, Z
—
—
—
—
—
INH
INH
INH
INH
INH
INH
INH
INH
INH
REL16
INH
INH
INH
INH
INH
INH
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-5 Page 3 Opcodes
Opcode
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
370A
370B
370C
370D
370E
370F
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
371A
371B
371C
371D
371E
371F
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
374B
374A
374C
374D
374E
374F
CPU16
REFERENCE MANUAL
Mnemonic
COMA
DECA
NEGA
INCA
ASLA
CLRA
TSTA
TBA
PSHA
PULA
SBA
ABA
ROLA
ASRA
RORA
LSRA
COMB
DECB
NEGB
INCB
ASLB
CLRB
TSTB
TAB
PSHB
PULB
XGAB
CBA
ROLB
ASRB
RORB
LSRB
SUBE
ADDE
SBCE
ADCE
EORE
LDE
ANDE
ORE
CPE
—
—
STE
XGEX
AEX
TXS
ABX
Mode
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
—
—
IND16, X
INH
INH
INH
INH
Opcode
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
372A
372B
372C
372D
372E
372F
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
373A
373B
373C
373D
373E
373F
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
376A
376B
376C
376D
376E
376F
Mnemonic
SWI
DAA
ACE
ACED
MUL
EMUL
EMULS
FMULS
EDIV
EDIVS
IDIV
FDIV
TPD
TDP
—
TDMSK
SUBE
ADDE
SBCE
ADCE
EORE
LDE
ANDE
ORE
CPE
—
ANDP
ORP
AIX
AIY
AIZ
AIS
SUBE
ADDE
SBCE
ADCE
EORE
LDE
ANDE
ORE
CPE
—
STE
—
XGEZ
AEZ
TZS
ABZ
INSTRUCTION PROCESS
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Mode
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
—
INH
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
—
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
IND16, Z
—
INH
INH
INH
INH
MOTOROLA
7-17
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-5 Page 3 Opcodes (Continued)
Opcode
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
375A
375B
375C
375D
375E
375F
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
378A
378B
378C
378D
378E
378F
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
379A
379B
379C
379D
379E
379F
MOTOROLA
7-18
Mnemonic
SUBE
ADDE
SBCE
ADCE
EORE
LDE
ANDE
ORE
CPE
—
STE
—
XGEY
AEY
TYS
ABY
LBRA
LBRN
LBHI
LBLS
LBCC
LBCS
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
LBLE
LBMV
LBEV
—
—
—
—
—
—
—
—
—
—
TBXK
TBYK
TBZK
TBSK
Mode
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
IND16, Y
—
INH
INH
INH
INH
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
REL16
—
—
—
—
—
—
—
—
—
—
INH
INH
INH
INH
Opcode
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
377A
377B
377C
377D
377E
377F
37A0
37A1
37A2
37A3
37A4
37A5
37A6
37A7
37A8
37A9
37AA
37AB
37AC
37AD
37AE
37AF
37B0
37B1
37B2
37B3
37B4
37B5
37B6
37B7
37B8
37B9
37BA
37BA
37BC
37BD
37BE
37BF
Mnemonic
SUBE
ADDE
SBCE
ADCE
EORE
LDE
ANDE
ORE
CPE
—
STE
—
CPX
CPY
CPZ
CPS
—
—
—
—
—
—
BGND
—
—
—
—
—
TXKB
TYKB
TZKB
TSKB
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
—
—
LDX
LDY
LDZ
LDS
INSTRUCTION PROCESS
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Mode
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
—
EXT
—
IMM16
IMM16
IMM16
IMM16
—
—
—
—
—
—
INH
—
—
—
—
—
INH
INH
INH
INH
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
IMM16
—
—
—
IMM16
IMM16
IMM16
IMM16
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 7-5 Page 3 Opcodes (Continued)
Opcode
37C0
37C1
37C2
37C3
37C4
37C5
37C6
37C7
37C8
37C9
37CA
37CB
37CC
37CD
37CE
37CF
37D0
37D1
37D2
37D3
37D4
37D5
37D6
37D7
37D8
37D9
37DA
37DB
37DC
37DD
37DE
37DF
CPU16
REFERENCE MANUAL
Mnemonic
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
XGDX
ADX
—
—
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
XGDY
ADY
—
—
Mode
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
IND16, X
—
IND16, X
—
INH
INH
—
—
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
IND16, Y
—
IND16, Y
—
INH
INH
—
—
Opcode
37E0
37E1
37E2
37E3
37E4
37E5
37E6
37E7
37E8
37E9
37EA
37EB
37EC
37ED
37EE
37EF
37F0
37F1
37F2
37F3
37F4
37F5
37F6
37F7
37F8
37F9
37FA
37FB
37FC
37FD
37FE
37FF
Mnemonic
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
XGDZ
ADZ
—
—
SUBD
ADDD
SBCD
ADCD
EORD
LDD
ANDD
ORD
CPD
—
STD
—
TPA
TAP
MOVB
MOVW
INSTRUCTION PROCESS
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Mode
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
IND16, Z
—
IND16, Z
—
INH
INH
—
—
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
—
EXT
—
INH
INH
EXT to EXT
EXT to EXT
MOTOROLA
7-19
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MOTOROLA
7-20
INSTRUCTION PROCESS
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CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SECTION 8 INSTRUCTION TIMING
This section gives detailed information concerning calculating the amount of time required to execute instructions.
Freescale Semiconductor, Inc...
8.1 Execution Time Components
CPU16 instruction execution time has three components:
Bus cycles required to prefetch the next instruction.
Bus cycles required for operand accesses.
Clock cycles required for internal operations.
Each bus cycle requires a minimum of two system clock cycles. If the time required to
access an external device exceeds two system clock cycles, bus cycles must be longer. However, all bus cycles must be made up of an integer number of clock cycles.
CPU16 internal operations always require an integer multiple of two system clock cycles.
NOTE
To avoid confusion between bus cycles and system clock cycles, this
discussion subsequently refers to the time required by system clock
cycles, or clock periods, rather than to the clock cycles themselves.
Dynamic bus sizing affects bus cycle time. The CPU16 is a component of a modular
microcontroller. Modules in the system communicate via a standardized intermodule
bus and access external devices via an external bus interface. The microcontroller
system integration module manages all accesses in order to make more efficient use
of common resources. See SECTION 3 SYSTEM RESOURCES for more information.
The CPU16 does not execute more than one instruction at a time. The total time required to execute a particular instruction stream can be calculated by summing the individual execution times of each instruction in the stream.
Total execution time is calculated using the expression:
(CLT) = (CLP) + (CLO) + (CLI)
Where:
(CLT) = Total clock periods per instruction
(CLI) = Clock periods used for internal operation
(CLP) = Clock periods used for program access
(CLO) = Clock periods used for operand access
CLT is the value provided in the instruction glossary pages.
CPU16
REFERENCE MANUAL
INSTRUCTION TIMING
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MOTOROLA
8-1
Freescale Semiconductor, Inc.
8.2 Program and Operand Access Time
The number of bus cycles required by a prefetch or an operand access generally depends upon three factors:
Data bus width (8- or 16-bit). Access size (byte, word, or long-word). Access alignment
(aligned or misaligned with even byte boundaries).
Prefetches are always word-sized, and are always aligned with even byte boundaries.
Operand accesses vary in size and alignment. Table 8-1 shows the number of bus cycles required by accesses of various sizes and alignments.
Freescale Semiconductor, Inc...
Table 8-1 Access Bus Cycles
Access
Size
Byte
Word
Long-word
8-Bit
Data Bus
1
2
4
16-Bit Data Bus
Aligned
1
1
2
16-Bit Data Bus
Misaligned
—
2
4
8.2.1 Program Accesses
For all instructions except those that cause a change in program flow, there is one
prefetch access per instruction word. These accesses keep the instruction pipeline
full. Once the number of prefetches is determined, the number of bus cycles can be
found in Table 8-1.
Instructions that cause changes in program flow also have various forms of operand
access. See 8.2.2.3 Change-of-Flow Instructions for complete information on
prefetch access and operand access.
8.2.2 Operand Accesses
The number of operand accesses per instruction is not fixed. Most instructions follow
a regular pattern, but there are several variant types. Immediate operands are considered to be part of the instruction — immediate operand access time is considered to
be a prefetch access.
8.2.2.1 Regular Instructions
Regular instructions require one operand access per operand. Determine the number
of byte and/or word operands, then use Table 8-1 to determine the number of cycles.
8.2.2.2 Read-Modify-Write Instructions
Read-modify-write instructions, which include the byte and word forms of ASL, ASR,
BCLR, BSET, COM, DEC, LSR, NEG, ROL, and ROR, require two accesses per
memory operand. The first access is needed to read the operand, and the second access is needed to write it back after modification. Determine the number and size of
operands, multiply by two (the mask used in bit clear and set instructions is considered
to be an immediate operand), then use Table 8-1 to determine the number of cycles.
MOTOROLA
8-2
INSTRUCTION TIMING
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CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
8.2.2.3 Change-of-Flow Instructions
Operand access for change of flow instructions varies according to type. Unary
branches, conditional branches, and jumps have no operand access. Bit-condition
branches must make one memory access in order to perform masking. Subroutine
and interrupt instructions must make stack accesses.
In addition, when an instruction that can cause a change in flow executes, no prefetch
is made until after the precondition for change of flow is evaluated.
There are two evaluation cases:
Freescale Semiconductor, Inc...
If the instruction causes an unconditional change, or meets a specific precondition
for change, the program counter is loaded with the first address of a new instruction
stream, and the pipeline is filled with new instructions.
If the instruction does not meet a specific precondition (preconditions of unary
branches are always true or always false), prefetch is made and execution of the
old instruction stream resumes.
Table 8-2 shows the number of program and operand access cycles for each instruction that causes a change in program flow.
Table 8-2 Change-of-Flow Instruction Timing
Instruction
BRA
BRN
Short Branches
LBRA
LBRN
Long Branches
BRCLR
Operand
Access
0
0
0
0
0
0
1
Program
Access
3
1
3/1
3
2
3/2
4/3
BRCLR
1
5/3
BRSET
1
4/3
BRSET
1
5/3
JMP
JSR
BSR
LBSR
RTS
SWI
0
2
2
2
2
3
3
3
3
3
3
3
RTI
2
3
Comment
Unary branch (1 = 1)
Unary branch (1 = 0)
Conditional branches
Unary branch (1 = 1)
Unary branch (1 = 0)
Conditional branches
Bit-condition branch,
IND8 addressing mode
Bit-condition branch,
EXT, IND16 addressing modes
Bit-condition branch,
IND8 addressing mode
Bit-condition branch,
EXT, IND16 addressing modes
Unconditional
Operand accesses include stack access
Operand accesses include stack access
Operand accesses include stack access
Operand accesses include stack access
Operand accesses include stack access
and vector fetch
Operand accesses include stack access
In program access values for conditional branches, the first value is for branch taken, the second value is for branch
not taken.
CPU16
REFERENCE MANUAL
INSTRUCTION TIMING
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8.2.2.4 Stack Manipulation Instructions
Aligned stack manipulation instructions comply with normal program access constraints, but have extra operand access cycles for stacking operations. Treat misaligned stacking operations as byte transfers on a misaligned 16-bit bus.
Table 8-3 shows program and operand access cycles for each instruction.
Table 8-3 Stack Manipulation Timing
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Instruction
PSHA/PSHB
PULA/PULB
PSHM
PULM
PSHMAC/PULMAC
Operand
Access
1
1
N
N+1
6
Program
Access
1
1
1
1
1
Comment
Byte operation
Byte operation
N = Number of registers pushed
N = Number of registers pulled*
Stacks/retrieves all MAC registers
*The last operand read from the stack is ignored
8.2.2.5 Stop and Wait Instructions
Stop and wait instructions have normal program access cycles, but differ from regular
instructions in number of operand accesses. If LPSTOP is executed at a time when
the CCR S bit is equal to zero, it must make one operand access to store the CCR IP
field. WAI performs one prefetch access to establish a PC value that insures proper
stacking and return from interrupt.
Table 8-4 shows program and operand access cycles for each instruction.
Table 8-4 Stop and Wait Timing
Instruction
LPSTOP1
WAI
Operand
Access
0
Program
Access
1
1
Comment
Operand access only when CCR S Bit = 0
—
8.2.2.6 Move Instructions
Move instructions have normal program access cycles, but differ from regular instructions in number of operand accesses. Each move requires two operand accesses, one
to read the data from the source address and one to write it to the destination address.
Table 8-5 shows program and operand access cycles for each instruction.
Table 8-5 Move Timing
Instruction
MOVB/MOVW
MOVB/MOVW
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Operand
Access
2
2
Program
Access
2
3
Comment
IXP to EXT, EXT to IXP addressing modes
EXT to EXT addressing mode
INSTRUCTION TIMING
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8.2.2.7 Multiply and Accumulate Instructions
MAC instructions have normal program access cycles, but differ from regular instructions in number of operand accesses. During multiply and accumulate operation, two
words pointed to by index registers X and Y are accessed and transferred to the H and
I registers. MAC makes only these two operand accesses, but RMAC repeats the operation a specified number of times.
Table 8-6 shows program and operand access cycles for each instruction.
Table 8-6 MAC Timing
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Instruction
Operand
Access
2
2N
MAC
RMAC
Program
Access
1
1
Comment
—
N = Number of iterations
8.3 Internal Operation Time
To determine the number of clock periods associated with internal operation, first determine program and operand access time using the appropriate table, then use instruction cycle time (CLT) from the instruction glossary to evaluate the following
expression:
CLI = (CLT) − (CLP + CLO)
Assume that:
1. All program and operand accesses are aligned on a 16-bit data bus.
2. Each bus cycle takes two clock periods.
This figure is constant regardless of the speed of memory used. Internal operations,
prefetches, and operand fetches are wholly concurrent for many instructions — the
calculated CLI will be zero.
8.4 Calculating Execution Times for Slower Accesses
Because CLI is constant for all bus speeds, CLT will only change when CLP and CLO
change. Clock periods are calculated using the following expression:
CLX = (Clock periods per bus cycle) (Number of bus cycles)
Where:
CLX is either CLP or CLO
To determine the number of clock periods required to execute an instruction when bus
cycles longer than two system clock periods are necessary, determine the number of
cycles needed, calculate CLP and CLO values, then add to CLI.
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8.5 Examples
The examples below illustrate the effect of bus width, alignment, and access speed on
three instructions. Separate entries for operand and program access show the effect
of accesses from differing types of memory.
The first example for each instruction assumes two system clock cycles per bus cycle
and 16-bit aligned access, so that CLI can be determined and used in the subsequent
examples. Calculated values are underlined.
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8.5.1 LDD (Load D) Instruction
The general form of this instruction is: LDD (operand). Examples show effects of various access parameters on a single-word instruction.
8.5.1.1 LDD IND8, X
16-bit operand data bus, 2 clocks per bus cycle, aligned
16-bit program data bus, 2 clocks per bus cycle
Operand
Program
Number of
Accesses
1
Number of
Accesses
1
Bus
Width
16
Bus
Width
16
Number of
Bus Cycles
1
Number of
Bus Cycles
1
Clocks per
Bus Cycle
2
Clocks per
Bus Cycle
2
CLT
6
CLO
2
CLP
2
CLI
2
8.5.1.2 LDD IND8, X
8-bit operand data bus, 3 clocks per bus cycle, aligned
16-bit program data bus, 2 clocks per bus cycle
Operand
Program
Number of
Accesses
1
Number of
Accesses
1
Bus
Width
8
Bus
Width
16
Number of
Bus Cycles
2
Number of
Bus Cycles
1
Clocks per
Bus Cycle
3
Clocks per
Bus Cycle
2
CLT
10
CLO
6
CLP
2
CLI
2
8.5.1.3 LDD IND8, X
Operand
Program
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16-bit operand data bus, 2 clocks per bus cycle, misaligned
8-bit program data bus, 3 clocks per bus cycle
Number of
Bus
Number of
Accesses
Width
Bus Cycles
1
16
2
Number of
Bus
Number of
Accesses
Width
Bus Cycles
1
8
2
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Clocks per
Bus Cycle
2
Clocks per
Bus Cycle
3
CLT
12
CLO
4
CLP
6
CLI
2
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8.5.2 NEG (Negate) Instruction
The general form of this instruction is: NEG (operand). Examples show effects of various access parameters on a two-word instruction. Note that operand alignment affects only the 8-bit operand data bus.
8.5.2.1 NEG EXT
16-bit operand data bus, 2 clocks per bus cycle
16-bit program data bus, 2 clocks per bus cycle
Number of
Bus
Number of
Accesses
Width
Bus Cycles
2
16
2
Number of
Bus
Number of
Accesses
Width
Bus Cycles
2
16
2
Operand
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Program
Clocks per
Bus Cycle
2
Clocks per
Bus Cycle
2
CLT
8
CLO
4
CLP
4
CLI
0
8.5.2.2 NEG EXT
8-bit operand data bus, 3 clocks per bus cycle, aligned
8-bit program data bus, 3 clocks per bus cycle
Operand
Program
Number of
Accesses
2
Number of
Accesses
2
Bus
Width
8
Bus
Width
8
Number of
Bus Cycles
2
Number of
Bus Cycles
4
Clocks per
Bus Cycle
3
Clocks per
Bus Cycle
3
CLT
18
CLO
6
CLP
12
CLI
0
8.5.2.3 NEG EXT
16-bit operand data bus, 3 clocks per bus cycle
16-bit program data bus, 3 clocks per bus cycle
Operand
Program
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Number of
Accesses
2
Number of
Accesses
2
Bus
Width
16
Bus
Width
16
Number of
Bus Cycles
2
Number of
Bus Cycles
2
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CLT
12
Clocks per
Bus Cycle
3
Clocks per
Bus Cycle
3
6
CLP
6
CLI
0
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8.5.3 STED (Store Accumulators E and D) Instruction
The general form of this instruction is: STED (operand). Examples show effects of various access parameters on an instruction that writes to memory twice during execution.
8.5.3.1 STED EXT
16-bit operand data bus, 2 clocks per bus cycle, aligned
16-bit program data bus, 2 clocks per bus cycle
Operand
Number of
Accesses
1
Number of
Accesses
2
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Program
Bus
Width
16
Bus
Width
16
Number of
Bus Cycles
2
Number of
Bus Cycles
2
Clocks per
Bus Cycle
2
Clocks per
Bus Cycle
2
CLT
8
CLO
4
CLP
4
CLI
0
8.5.3.2 STED EXT
8-bit operand data bus, 2 clocks per bus cycle, misaligned
16-bit program data bus, 3 clocks per bus cycle
Operand
Program
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8-8
Number of
Accesses
1
Number of
Accesses
2
Bus
Width
8
Bus
Width
16
Number of
Bus Cycles
4
Number of
Bus Cycles
2
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Clocks per
Bus Cycle
2
Clocks per
Bus Cycle
3
CLT
14
CLO
8
CLP
6
CLI
0
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SECTION 9 EXCEPTION PROCESSING
This section discusses exception handling, exception processing sequence, and specific features of individual exceptions.
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9.1 Definition of Exception
An exception is an event that pre-empts normal instruction process. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception.
Each exception has an assigned vector that points to an associated handler routine.
Exception processing includes all operations required to transfer control to a handler
routine, but does not include execution of the handler routine itself. Keep the distinction between exception processing and execution of an exception handler in mind
while reading this section.
9.2 Exception Vectors
An exception vector is the address of a routine that handles an exception. Exception
vectors are contained in a data structure called the instruction vector table, which is
located in the first 512 bytes of bank 0.
All vectors except the reset vector consist of one word and reside in data space. The
reset vector consists of four words that reside in program space. There are 52 predefined or reserved vectors, and 200 user-defined vectors.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are
generated by external devices; others are supplied by the processor. There is a direct
mapping of vector number to vector table address. The processor left shifts the vector
number one place (multiplies by two) to convert it to an address.
Table 9-1 shows exception vector table organization. Vector numbers and addresses
are given in hexadecimal notation.
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Table 9-1 Exception Vector Table
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Vector
Number
0
4
5
6
7
8
9–E
F
10
11
12
13
14
15
16
17
18
19 – 37
38 – FF
Vector
Address
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012 – 001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032 – 006E
0070 – 01FE
Address
Space
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Type of
Exception
RESET — Initial ZK, SK, and PK
RESET — Initial PC
RESET — Initial SP
RESET — Initial IZ (Direct Page)
BKPT (Breakpoint)
BERR (Bus Error)
SWI (Software Interrupt)
Illegal Instruction
Division by Zero
Unassigned, Reserved
Uninitialized Interrupt
Unassigned, Reserved
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Spurious Interrupt
Unassigned, Reserved
User-defined Interrupts
9.3 Types of Exceptions
Exceptions can be either internally or externally generated. External exceptions, which
are defined as asynchronous, include interrupts, bus errors (BERR), breakpoints
(BKPT), and resets (RESET). Internal exceptions, which are defined as synchronous,
include the software interrupt (SWI) instruction, the background (BGND) instruction,
illegal instruction exceptions, and the divide-by-zero exception.
9.4 Exception Stack Frame
During exception processing, a subset of the current processor state is saved on the
current stack. Specifically, the contents of the program counter and condition code
register at the time exception processing begins are stacked at the location pointed to
by SK: SP. Unless specifically altered during exception processing, the stacked PK:
PC value is the address of the next instruction in the current instruction stream, plus
$0006. Figure 9-1 shows the exception stack frame.
⇐ SP After Exception Stacking
Low Address
High Address
Condition Code Register
Program Counter
⇐ SP Before Exception Stacking
Figure 9-1 Exception Stack Frame Format
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9.5 Exception Processing Sequence
This is a general description of exception processing. Figure 9-2 shows detailed processing flow and relative priority of each type of exception.
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Exception processing is performed in four distinct phases.
1. Priority of all pending exceptions is evaluated, and the highest priority exception
is processed first.
2. Processor state is stacked, then the CCR PK extension field is cleared.
3. An exception vector number is acquired and converted to a vector address.
4. The content of the vector address is loaded into the PC, and the processor
jumps to the exception handler routine.
There are variations within each phase for differing types of exceptions. However, all
vectors but RESET are 16-bit addresses, and the PK field is cleared — either exception handlers must be located within bank 0, or vectors must point to a jump table. See
9.7 Processing of Specific Exceptions.
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RESET
NEGATED
1A
LATCH STATE
OF BKPT
INSURE
INSTRUCTION
PIPE FULL
INITIALIZE CCR
CLEAR
K REGISTER
DID BERR
OCCUR
NO
2A
FETCH RESET
VECTORS
DID BERR
OCCUR
1B
2B
YES
YES
DID BKPT
OCCUR
NO
2C
NO
2D
1A
Figure 9-2 (Sheet 1 of 5) Exception Processing Flow Diagram
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2A
2B
STACK PROCESSOR
STATE
CLEAR PK
FETCH BERR
VECTOR
BACKGROUND
MODE
ENABLED
NO
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YES
INSURE
INSTRUCTION
PIPE FULL
DID
ANOTHER
BERR
OCCUR
ENTER
BACKGROUND
MODE
NO
RUN BKPT
ACKNOWLEDGE
CYCLE
STACK PROCESSOR
STATE
CLEAR PK
FETCH BKPT VECTOR
1B
YES
2D
1A
BDM
ENABLED
NO
2C
YES
ENTER
BDM
STOP
INSTRUCTION
EXECUTION
ASSERT HALT
3A
NO
FIRST
INSTRUCTION OF
EXCEPTION
ROUTINE
YES
4A
Figure 9-2 (Sheet 2 of 5) Exception Processing Flow Diagram
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3A
IS PENDING
INTERRUPT >
IP MASK
NO
4A
YES
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3B
STACK PROCESSOR
STATE
CLEAR PK
SET IP MASK TO
INTERRUPT
PRIORITY
RUN IACK CYCLE
SPURIOUS
INTERRUPT
YES
NO
AUTO VECTOR
NO
YES
FETCH SPURIOUS
INTERRUPT VECTOR
FETCH INTERRUPT
AUTO VECTOR
FETCH INTERRUPT
VECTOR
1A
1A
1A
Figure 9-2 (Sheet 3 of 5) Exception Processing Flow Diagram
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4A
ILLEGAL
INSTRUCTION
YES
4B
NO
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YES
STACK PROCESSOR
STATE
CLEAR PK
FETCH ILLEGAL
VECTOR
SWI
INSTRUCTION
STACK PROCESSOR
STATE
CLEAR PK
FETCH SWI VECTOR
NO
1A
WAIT
INSTRUCTION
YES
1A
NO
4C
YES
LPSTOP
INSTRUCTION
NO
S BIT SET IN
CCR
NO
5A
IS PENDING
INTERRUPT >
MASK
NO
YES
YES
1A
RUN CPU SPACE
3 BUS CYCLE
3B
4C
Figure 9-2 (Sheet 4 of 5) Exception Processing Flow Diagram
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5A
EDIV, EDIVS
INSTRUCTION
YES
NO
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YES
RESTORE
PROCESSOR
STATE
NO
DIVISOR
ZERO
RTI
INSTRUCTION
YES
STACK PROCESSOR
STATE
CLEAR PK
FETCH DIVIDE BY
ZERO VECTOR
NO
BGND
INSTRUCTION
NO
1A
1A
YES
EXECUTE ILLEGAL
INSTRUCTION
NO
BACKGROUND
MODE
ENABLED
EXECUTE
INSTRUCTION
YES
4B
ENTER
BACKGROUND
MODE
1A
Figure 9-2 (Sheet 5 of 5) Exception Processing Flow Diagram
9.6 Multiple Exceptions
Each exception has a priority based upon its relative importance to system operation.
Asynchronous exceptions have higher priorities than synchronous exceptions. Exception processing for multiple exceptions is done by priority, from highest to lowest. Priority governs the order in which exception processing occurs, not the order in which
exception handlers are executed.
When simultaneous exceptions occur, handler routines for lower priority exceptions
are generally executed before handler routines for higher priority exceptions.
Unless BERR, BKPT, or RESET occur during exception processing, the first instruction of all exception handler routines is guaranteed to execute before another exception is processed. Since interrupt exceptions have higher priority than synchronous
exceptions, this means that the first instruction in an interrupt handler will be executed
before other interrupts are sensed.
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Note
If interrupt latency is a concern, it is best to lead interrupt service routines with a NOP instruction, rather than with an instruction that requires considerable cycle time to execute, such as PSHM.
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RESET, BERR, and BKPT exceptions that occur during exception processing of a previous exception will be processed before the first instruction of that exception's handler
routine. The converse is not true — if an interrupt occurs during BERR exception processing, for example, the first instruction of the BERR handler will be executed before
interrupts are sensed. This permits the exception handler to mask interrupts during execution.
9.7 Processing of Specific Exceptions
The following detailed discussion of exceptions is organized by type and priority. Proximate causes of each exception are discussed, as are variations from the standard
processing sequence described above.
9.7.1 Asynchronous Exceptions
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing is synchronized. For all asynchronous exceptions besides RESET, exception processing begins at the first instruction boundary following detection of an
exception.
Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than RESET, is equal to the address of the next instruction in the current
instruction stream plus $0006. The RTI instruction, which must terminate all exception
handler routines, subtracts $0006 from the stacked value in order to resume execution
of the interrupted instruction stream.
9.7.1.1 Processor Reset (RESET)
RESET is the highest-priority exception. It provides for system initialization and for recovery from catastrophic failure. The RESET vector contains information necessary
for basic CPU16 initialization. Figure 9-3 shows the RESET vector.
Address
$0000
$0002
$0004
$0006
15
12
Reserved
11
8
7
Initial ZK
4
Initial SK
3
0
Initial PK
Initial PC
Initial SP
Initial IZ (Direct Page Pointer)
Figure 9-3 RESET Vector
RESET is caused by assertion of the IMB MSTRST signal. Conditions for assertion of
MSTRST may vary among members of the modular microcontroller family. Refer to
the appropriate microcontroller user's manual for details.
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Unlike all other exceptions, RESET occurs at the end of a bus cycle, and not at an instruction boundary. Any processing in progress at the time RESET occurs will be
aborted, and cannot be recovered.
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The following events take place when MSTRST is asserted.
A. Instruction execution is aborted.
B. The condition code register is initialized.
1. The IP field is set to $7, disabling all interrupts below priority 7.
2. The S bit is set, disabling LPSTOP mode.
3. The SM bit is cleared, disabling MAC saturation mode.
C. The K register is cleared.
It is important to be aware that all CCR bits that are not initialized are not affected by
reset. However, out of power-on reset, these bits will be indeterminate.
The following events take place when MSTRST is negated after assertion.
A. The CPU16 samples the BKPT input.
B. The CPU16 fetches RESET vectors in the following order:
1. Initial ZK, SK, and PK extension field values.
2. Initial PC.
3. Initial SP.
4. Initial IZ value.
C. The CPU16 begins fetching instructions pointed to by the initial PK : PC.
The CPU16 samples the BKPT inputs to determine whether to enable background debugging mode.
If either BKPT input is at logic level zero when sampled, an internal BDM flag is set,
and the CPU16 enters BDM whenever either BKPT input is subsequently asserted.
If both BKPT inputs are at logic level one when sampled, normal BKPT exception processing begins whenever either BKPT input is subsequently asserted.
When BDM is enabled, the CPU16 will enter debugging mode whenever the conditions for breakpoint are met. See 9.7.1.3 Breakpoint Exception (BKPT) for more information.
ZK : IZ are initialized for use as a direct bank pointer. Using the pointer, any location
in memory can be accessed out of reset by means of indexed addressing. This capability maintains compatibility with MC68HC11 routines that use direct addressing
mode.
Only essential RESET tasks are performed during exception processing. Other initialization tasks must be accomplished by the exception handler routine.
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9.7.1.2 Bus Error (BERR)
BERR is caused by assertion of the IMB BERR signal. BERR can be asserted by any
of three sources:
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1. External logic, via the BERR pin.
2. Another microcontroller module.
3. Microcontroller system watchdog functions.
Refer to the appropriate microcontroller user's manual for more information.
BERR assertions do not force immediate exception processing. The signal is synchronized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle
in which it was asserted. Since bus cycles can overlap instruction boundaries, bus error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several factors:
Which bus cycle of an instruction is terminated by assertion of BERR.
The number of bus cycles in the instruction during which BERR is asserted.
The number of bus cycles in the instruction following the instruction in which BERR
is asserted.
Whether BERR is asserted during a program space access or a data space access.
Because of these factors, it is impossible to predict precisely how long after occurrence of a bus error the bus error exception will be processed.
Caution
The external bus interface in the system integration module does not
latch data when an external bus cycle is terminated by a bus error.
When this occurs during an instruction prefetch, the IMB precharge
state (bus pulled high, or $FF) is latched into the CPU16 instruction
register, with indeterminate results. Refer to SECTION 3 SYSTEM
RESOURCES for more information concerning the IMB and bus interfacing.
Bus error exception support in the CPU16 is provided to allow for dynamic memory
sizing after reset. To implement this feature, use a small routine similar to the example
below. The example assumes that memory starts at address $00000, and is contiguous through the highest memory address —it must be modified for other memory
maps.
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Example — Dynamic Memory Sizing
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loop
*
*
*
*
*
*
*
*
*
*
*
*
berr_ex
clrb
tbxk
ldx
ldd
nop
aix
bra
set xk = 0
#$0000
0,x
#2
loop
xk:ix initialized to address $00000
access memory location
nop in case a bus error is pending
increment pointer to next word address.
When xk:ik is incremented past the highest available memory
address, a BERR exception occurs; after exception processing,
the CPU16 executes the exception handler at location berr_ex.
berr_ex – BERR Exception Handler for Dynamic Memory Sizing
This routine computes the address of the last word of memory,
then stores the bank number at a location called “bank” and the
word address within the bank at a location called “address”.
It assumes that ek is properly initialized.
aix
txkb
stab
stx
#–2
compute LWA of memory
bank
address
store bank number
store address
Exception processing for bus error exceptions follows the standard exception processing sequence. However, two special cases of bus error, called double bus faults, can
abort exception processing.
BERR assertion is not detected until an instruction is complete. The BERR latch is
cleared by the first instruction of the BERR exception handler. Double bus fault occurs
in two ways:
1. When bus error exception processing begins and a second BERR is detected
before the first instruction of the BERR exception handler is executed.
2. When one or more bus errors occur before the first instruction after a RESET
exception is executed.
Multiple bus errors within a single instruction which can generate multiple bus cycles,
such as read-modify-write instructions (refer to SECTION 8 INSTRUCTION TIMING
for more information), will cause a single bus error exception after the instruction has
executed.
Immediately after assertion of a second BERR, the CPU16 ceases instruction processing and asserts the IMB HALT signal. The CPU16 will remain in this state until a
RESET occurs.
9.7.1.3 Breakpoint Exception (BKPT)
BKPT is caused by internal assertion of the IMB BKPT signal or by external assertion
of the microcontroller BKPT pin. BKPT assertions do not force immediate exception
processing. They are synchronized with normal bus cycles and latched into the
CPU16 at the end of the bus cycle in which they are asserted.
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When a BKPT assertion is synchronized with an instruction prefetch, processing of the
BKPT exception occurs at the end of that instruction. The prefetched instruction is
“tagged” with the breakpoint when it enters the instruction pipeline, and the breakpoint
exception occurs after the instruction executes. When a BKPT assertion is synchronized with an operand fetch, exception processing occurs at the end of the instruction
during which BKPT is latched.
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When background debugging mode has been enabled, the CPU16 will enter BDM
whenever either BKPT input is asserted. Refer to SECTION 10 DEVELOPMENT
SUPPORT for complete information on background debugging mode. When background debugging mode is not enabled, a breakpoint acknowledge bus cycle is run,
and subsequent exception processing follows the normal sequence.
Breakpoint acknowledge is a type of CPU space cycle. Cycles of this type are managed by the external bus interface (EBI) in the microcontroller system integration module. See SECTION 3 SYSTEM RESOURCES for more information.
9.7.1.4 Interrupts
There are eight levels of interrupt priority (0–7), seven automatic interrupt vectors, and
200 assignable interrupt vectors. All interrupts with priorities less than 7 can be
masked by writing to the CCR interrupt priority field.
Interrupt requests do not force immediate exception processing, but are left pending
until the current instruction is complete. Pending interrupts are processed at instruction boundaries or when exception processing for higher-priority exceptions is complete. All interrupt requests must be held asserted until they are acknowledged by the
CPU.
Interrupt recognition and subsequent processing are based on the state of interrupt request signals IRQ7 – IRQ1 and the IP mask value.
IRQ6 – IRQ1 are active-low level-sensitive inputs. IRQ7 is an active-low transitionsensitive input. A transition-sensitive input requires both an edge and a voltage level
for validity. Interrupt requests are synchronized and debounced by input circuitry on
consecutive rising edges of the processor clock. To be valid, an interrupt request must
be asserted for at least two consecutive clock periods. Each input corresponds to an
interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the highest priority.
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide
eight priority masks. Masks prevent an interrupt request of a priority less than or equal
to the mask value (except for IRQ7) from being recognized and processed. When IP
contains %000, no interrupt is masked.
IRQ6 – IRQ1 are maskable. IRQ7 is non-maskable. The IRQ7 input is transition-sensitive in order to prevent redundant servicing and stack overflow. An NMI is generated
each time IRQ7 is asserted, and each time the priority mask changes from %111 to a
lower number while IRQ7 is asserted.
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The IP field is automatically set to the priority of the pending interrupt as a part of interrupt exception processing. The TDP, ANDP, and ORP instructions can be used to
change the IP mask value. IP can also be changed by pushing a modified CCR onto
the stack, then using the PULM instruction. IP is also modified by the action of the return from interrupt (RTI) instruction.
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Interrupt exception processing sequence is as follows:
A. Priority of all pending exceptions is evaluated, and the highest priority exception
is processed first.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. Mask value of the pending interrupt is written to the IP field.
D. An interrupt acknowledge cycle (IACK) is run.
1. If the interrupting device supplies a vector number, the CPU16 acquires it.
2. If the interrupting device asserts the autovector (AVEC) signal in response
to IACK, the CPU16 generates an autovector number corresponding to the
interrupt priority.
3. If a BERR signal occurs during IACK, the CPU16 generates the spurious interrupt vector number.
E. The vector number is converted to a vector address.
F. The content of the vector address is loaded into the PC, and the processor
jumps to the exception handler routine.
SECTION 3 SYSTEM RESOURCES contains more information about bus control signals and interfacing.
9.7.2 Synchronous Exceptions
Synchronous exception processing is part of an instruction definition. Exception processing for synchronous exceptions will always be completed, and the first instruction
of the handler routine will always be executed, before interrupts are detected.
Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to the address of the instruction that causes the exception plus $0006.
Since RTI always subtracts $0006 upon return, the stacked PK : PC must be adjusted
by the instruction that caused the exception so that execution will resume with the following instruction —$0002 is added to the PK : PC value before it is stacked.
9.7.2.1 Illegal Instructions
An illegal instruction exception can occur at two times:
1. When the execution unit identifies an opcode for which there is no instruction
definition.
2. When an attempt is made to execute the BGND instruction with background debugging mode disabled.
In both cases, exception processing follows the normal sequence, except that the PK
: PC value is adjusted before it is stacked.
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9.7.2.2 Division By Zero
This exception is a part of the instruction definition for division instructions EDIV and
EDIVS. If the divisor is zero when either is executing, the exception is taken. In both
cases, exception processing follows the normal sequence, except that the PK : PC value is adjusted before it is stacked.
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9.7.2.3 BGND Instruction
Execution of the BGND instruction differs depending upon whether background debugging mode has been enabled. See 9.7.1.3 Breakpoint Exception (BKPT) for information concerning enabling BDM.
1. If BDM has been enabled, BDM is entered. See SECTION 10 DEVELOPMENT
SUPPORT for more information concerning BDM.
2. If BDM is not enabled, an illegal instruction exception occurs. In this case, exception processing follows the normal sequence, except that the PK : PC value
is adjusted before it is stacked.
9.7.2.4 SWI Instruction
The software interrupt instruction initiates synchronous exception processing. Exception processing for SWI follows the normal sequence, except that the PK : PC value is
adjusted before it is stacked.
9.8 Return from Interrupt (RTI)
RTI must be the last instruction in all exception handlers except for the RESET handler. RTI pulls the exception stack frame and restores processor state. Normal program flow resumes at the address of the instruction that follows the last instruction
executed before exception processing began. RTI is not used in the RESET handler
because RESET initializes the stack pointer and does not create a stack frame.
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SECTION 10 DEVELOPMENT SUPPORT
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The CPU16 incorporates powerful tools for tracking program execution and for system
debugging. These tools are deterministic opcode tracking, breakpoint exceptions, and
the background debugging mode. Judicious use of CPU16 capabilities permits in-circuit emulation and system debugging using a bus state analyzer, a simple serial interface, and a terminal.
10.1 Deterministic Opcode Tracking
The CPU16 has two multiplexed outputs, IPIPE0 and IPIPE1, that enable external
hardware to monitor the instruction pipeline during normal program execution. The signals IPIPE0 and IPIPE1 can be demultiplexed into six pipeline state signals that allow
a state analyzer to synchronize with instruction stream activity.
10.1.1 Instruction Pipeline
There are three functional blocks involved in fetching, decoding, and executing instructions. These are the microsequencer, the instruction pipeline, and the execution
unit. These elements function concurrently. Figure 10-1 shows the functional blocks.
The microsequencer controls the order in which instructions are fetched, advanced
through the pipeline, and executed. It increments the program counter and generates
IPIPE0 and IPIPE1 from internal signals.
The execution unit evaluates opcodes, interfaces with the microsequencer to advance
instructions through the pipeline, and performs instruction operations.
The effects of microsequencer and execution unit actions are always reflected in pipeline status — consequently, monitoring the pipeline provides an accurate picture of
CPU16 operation for debugging purposes.
The pipeline is a three stage FIFO. Fetched opcodes are latched into stage A, then
advanced to stage B, where opcodes are evaluated. The execution unit accesses operands from either stage A or stage B (stage B accesses are limited to 8-bit operands).
After execution, opcodes are moved from stage B to stage C, where they remain until
the next instruction is complete.
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IPIPE0
IPIPE1
MICROSEQUENCER
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INSTRUCTION PIPELINE
BKPT
BKPT
BKPT
DATA
BUS
A
B
C
EXECUTION UNIT
Figure 10-1 Instruction Execution Model
10.1.2 IPIPE0/IPIPE1 Multiplexing
Six types of information are required to track pipeline activity. To generate the six state
signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1.
The multiplexed signals have two phases. State signals are active low. Table 10-1
shows the encoding and multiplexing scheme.
Table 10-1 IPIPE0/IPIPE1 Encoding
Phase
IPIPE1 State
IPIPE0 State
State Signal Name
1
0
0
1
1
0
1
0
1
START & FETCH
FETCH
START
NULL
2
0
0
1
1
0
1
0
1
INVALID
ADVANCE
EXCEPTION
NULL
IPIPE0 and IPIPE1 are timed so that a logic analyzer can capture all six pipeline state
signals and address, data, or control bus state in any single bus cycle.
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State signals can be latched asynchronously on the falling and rising edges of either
address strobe (AS) or data strobe (DS). They can also be latched synchronously using the microcontroller CLKOUT signal. SECTION 3 SYSTEM RESOURCES contains
more information about bus control signals. Refer to the appropriate microcontroller
user's manual for specific timing information.
Figure 10-2 shows minimum logic required to demultiplex IPIPE0 and IPIPE1.
IPIPE0
(PHASE 2)
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IPIPE0
D
Q
IPIPE0
(PHASE 1)
IPIPE1
(PHASE 2)
IPIPE1
D
Q
AS
IPIPE1
(PHASE 1)
ANALYZER
STROBE
DS
Figure 10-2 IPIPE DEMUX Logic
10.1.3 Pipeline State Signals
The six state signals show instruction execution sequence. The order in which a development system evaluates the signals is critical. In particular, the development system must first evaluate START, then ADVANCE, and then FETCH for each instruction
word. When combined START & FETCH signals are asserted, START applies to the
current content of pipeline stage B, while FETCH applies to current data bus content.
Relationships between state signals are discussed in the following descriptions.
10.1.3.1 NULL — No Instruction Pipeline Activity
NULL assertion indicates that there is no instruction pipeline activity associated with
the current bus cycle.
10.1.3.2 START — Instruction Start
START assertion indicates that an instruction in stage B has begun to execute. START
affects subsequent operation of ADVANCE and FETCH. The development system
must flag the instruction word in stage B as started when START is asserted.
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10.1.3.3 ADVANCE — Instruction Pipeline Advance
ADVANCE assertion indicates that words in the instruction pipeline are being copied
from one stage to another.
If START has been asserted for the word in stage B, the content of stage B is copied
into stage C. Regardless of START assertion, content of stage A is copied into stage
B.
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When a word is copied from stage B to stage C, instruction execution is complete, and
a new opcode must be copied into stage B.
When the content of stage A is copied into stage B, prior content of stage B is overwritten. ADVANCE assertion without an associated START assertion indicates that
the pipeline is being filled, either before normal execution of instructions begins or after
a change of program flow.
If the development system has flagged the instruction word in stage B as started, that
flag must be cleared when ADVANCE is asserted.
10.1.3.4 FETCH — Instruction Fetch
FETCH assertion shows that the current content of the data bus is being latched into
stage A. FETCH occurs only during instruction fetch bus cycles.
10.1.3.5 EXCEPTION — Exception Processing in Progress
EXCEPTION assertion indicates that all subsequent bus cycles until the next START
assertion are part of an exception processing sequence.
EXCEPTION is not asserted during exceptions initiated by the SWI instruction nor during division by zero exceptions. The timing of EXCEPTION assertion for other exceptions differs according to the type of exception.
Exceptions are recognized at instruction boundaries. Time elapses between detection
of the exception and the start of exception processing. A prefetch bus cycle for the next
instruction is initiated during this period.
Because interrupts are recognized quickly, EXCEPTION is asserted during the
prefetch bus cycle. The bus cycle is completed, and the prefetched word is overwritten
when the pipeline is filled with interrupt handler instructions.
For exceptions other than interrupt, the prefetch bus cycle is completed before EXCEPTION is asserted. Assertion coincides with the first stacking operation. The
prefetched word is overwritten when the pipeline is refilled with exception handler instructions.
10.1.3.6 INVALID — PHASE1/PHASE2 Signal Invalid
INVALID is always asserted during phase 2. INVALID assertion indicates that all nonnull signals derived from PHASE1 must be ignored.
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10.1.4 Combining Opcode Tracking with Other Capabilities
Pipeline state signals are useful during normal instruction execution and execution of
exception handlers. Refer to SECTION 9 EXCEPTION PROCESSING for a detailed
discussion of exceptions and exception handlers. The signals provide a complete
model of the pipeline up to the point a breakpoint is acknowledged.
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Breakpoints are acknowledged after an instruction has executed, when it is in pipeline
stage C. A breakpoint can initiate either exception processing or background debugging mode. See10.2 Breakpoints10.2 Breakpoints and 10.3 Opcode Tracking and
Breakpoints10.3 Opcode Tracking and Breakpointsfor more information. IPIPE0/
IPIPE1 are not usable when the CPU16 is in background debugging mode. Complete
information is contained in 10.4 Background Debug Mode (BDM).
10.1.5 CPU16 Instruction Pipeline State Signal Flow
Figure 10-3 is the flow diagram required to properly interpret instruction pipeline state
signals.
10.2 Breakpoints
Breakpoints are set by internal assertion of the IMB BKPT signal or by external assertion of the microcontroller BKPT pin. The CPU16 supports breakpoints on any memory
access. Acknowledged breakpoints can initiate either exception processing or background debugging mode. After BDM has been enabled, the CPU16 will enter BDM
when either BKPT input is asserted.
If BKPT assertion is synchronized with an instruction prefetch, the instruction is
“tagged” with the breakpoint when it enters the pipeline, and the breakpoint occurs after the instruction executes.
If BKPT assertion is synchronized with an operand fetch, breakpoint processing occurs at the end of the instruction during which BKPT is latched.
Breakpoints on instructions that are flushed from the pipeline before execution are not
acknowledged, but operand breakpoints are always acknowledged. There is no breakpoint acknowledge bus cycle when BDM is entered. See SECTION 9 EXCEPTION
PROCESSING for complete information about breakpoint exceptions.
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START
1
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LATCH
IPIPE0/IPIPE1
DECODE
(BOTH PHASES)
BOTH
PHASES
NULL
YES
1
NO
INVALID
ASSERTED
YES
1
NO
START
ASSERTED
NO
YES
FLAG WORD
IN STAGE B
2
Figure 10-3 (Sheet 1 of 3) Instruction Pipeline Flow
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2
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ADVANCE
ASSERTED
YES
NO
WORD
FLAGGED
NO
YES
COPY STAGE B
INTO STAGE C:
CLEAR FLAG
COPY STAGE A
INTO STAGE B
3
Figure 10-3 (Sheet 2 of 3) Instruction Pipeline Flow
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3
FETCH
ASSERTED
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NO
EXCEPTION
ASSERTED
NO
YES
LATCH WORD
FROM DATA BUS
INTO STAGE A
YES
EXCEPTION
PROCESSING
UNTIL NEXT
START ASSERTION
1
Figure 10-3 (Sheet 3 of 3) Instruction Pipeline Flow
10.3 Opcode Tracking and Breakpoints
Breakpoints are acknowledged after a tagged instruction has executed, when it is copied from pipeline stage B to stage C. At the time START is asserted for an instruction,
stage C contains the opcode of the previous instruction.
When an instruction is tagged, IPIPE0/IPIPE1 show START and the appropriate number of ADVANCE and FETCH assertions for instruction execution before the breakpoint is acknowledged. If background debugging mode is enabled, these signals
model the pipeline before BDM is entered.
10.4 Background Debug Mode (BDM)
Microprocessor debugging programs are generally implemented in external software.
CPU16 BDM provides a debugger implemented in CPU microcode.
BDM incorporates a full set of debug options — registers can be viewed and altered,
memory can be read or written, and test features can be invoked.
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BDM also simplifies in-circuit emulation. In a common setup (Figure 10-4), emulator
hardware replaces the target system processor. Communication between target system and emulator takes place via a complex interface.
TARGET
SYSTEM
IN-CIRCUIT
EMULATOR
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TARGET
MCU
Figure 10-4 In-Circuit Emulator Configuration
CPU16 emulation requires a bus state analyzer only. The processor remains in the target system (see Figure 10-5) and the interface is less complex.
TARGET
SYSTEM
BUS STATE
ANALYZER
TARGET
MCU
Figure 10-5 Bus State Analyzer Configuration
The analyzer monitors processor operation and the on-chip debugger controls the operating environment. Emulation is much “closer” to target hardware, and interfacing
problems such as limited clock speed, AC and DC parametric mismatch, and restricted cable length are minimized.
BDM is an alternate CPU16 operating mode. During BDM, normal instruction execution is suspended, and special microcode performs debugging functions under external control.
BDM can be initiated by external assertion of the BKPT input, by internal assertion of
the IMB BKPT signal, or by the BGND instruction. While in BDM, the CPU16 ceases
to fetch instructions via the parallel bus and communicates with the development system via a dedicated serial interface.
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10.4.1 Enabling BDM
The CPU16 samples the BKPT inputs during reset to determine whether to enable
BDM. If either BKPT input is at logic level zero when sampled, an internal BDM enabled flag is set.
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BDM operation is enabled when BKPT is asserted at the rising edge of the RESET signal. BDM remains enabled until the next system reset. If BKPT is at logic level one on
the trailing edge of RESET, BDM is disabled. BKPT is relatched on each rising transition of RESET. BKPT is synchronized internally, and must be asserted for at least two
clock cycles prior to negation of RESET.
BDM enable logic must be designed with special care. If BKPT hold time extends into
the first bus cycle following reset, the bus cycle could inadvertently be tagged with a
breakpoint. Figure 10-6 shows a sample BDM enable circuit.
BKPT
MCU
EXTERNAL
RESET
LOGIC
RESET
Figure 10-6 Sample BDM Enable Circuit
The microcontroller itself asserts RESET for 512 clock periods after it is released by
external reset logic, and latches the state of BKPT on the rising edge of RESET at the
end of this period. If enable circuitry only monitors the external reset, BKPT will not be
enabled. Figure 10-7 shows BDM enable timing. Refer to the appropriate modular microcontroller user's manual for specific timing information.
2 CLOCK
PERIODS
RESET
≥10 CLOCK PERIODS
RESET DRIVEN BY EXTERNAL LOGIC
512 CLOCK PERIODS
RESET DRIVEN BY MICROCONTROLLER
BKPT
BDM ENABLE LATCHED
Figure 10-7 BDM Enable Waveforms
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10.4.2 BDM Sources
When BDM is enabled, external breakpoint hardware, internal IMB module breakpoints, and the BGND instruction can cause the CPU16 to enter BDM. If BDM is not
enabled when a breakpoint occurs, a breakpoint exception is processed. Table 10-2
summarizes the processing of each source for both enabled and disabled cases.
Table 10-2 BDM Source Summary
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Source
BKPT
BGND Instruction
Double Bus Fault
BDM Enabled
Background
Background
Background
BDM Disabled
Breakpoint Exception
Illegal Instruction
Assert HALT
10.4.2.1 BKPT Signal
If enabled, BDM is initiated when assertion of BKPT is acknowledged. BKPT can be
asserted on the IMB by another module in the microcontroller, or by taking the microcontroller BKPT pin low. There is no breakpoint acknowledge bus cycle when BDM is
entered. See the appropriate microcontroller user's manual for more information concerning assertion of BKPT.
10.4.2.2 BGND Instruction
If BDM has been enabled, executing BGND will cause the CPU16 to suspend normal
operation and enter BDM. If BDM has not been correctly enabled, an illegal instruction
exception is generated. Illegal instruction exceptions are discussed in SECTION 9 EXCEPTION PROCESSING.
10.4.2.3 Microcontroller Module Breakpoints
If BDM has been enabled, the CPU16 will enter BDM when other microcontroller modules assert the BKPT signal. Consult the appropriate microcontroller user's manual for
a description of these capabilities.
10.4.2.4 Double Bus Fault
If BDM has been enabled, the CPU16 will enter BDM when a double bus fault is detected. If BDM has not been enabled, the HALT signal is asserted and processing
stops.
10.4.3 BDM Signals
When BDM is entered, the BKPT and IPIPE signals change function and become BDM
serial communication signals. The following table summarizes the changes.
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Table 10-3 BDM Signals
State
No Background Mode
Background Mode
Signal Name
BKPT
IPIPE0
IPIPE1
DSCLCK
DSO
DSI
Type
Input
Output
Output
Input
Output
Input
Description
Signals breakpoint to CPU16
Shows instruction pipeline state
Shows instruction pipeline state
BDM serial clock
BDM serial output
BDM serial input
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10.4.4 Entering BDM
When the processor detects a breakpoint or decodes a BGND instruction, it suspends
instruction execution and asserts the FREEZE output. Once FREEZE has been asserted, the CPU enables the serial communication hardware and awaits a command.
Assertion of FREEZE causes opcode tracking signals IPIPE0 and IPIPE1 to change
definition and become serial communication signals DSO and DSI. FREEZE is asserted at the next instruction boundary after BKPT is asserted. IPIPE0 and IPIPE1 change
function before an EXCEPTION signal can be generated. The development system
must use FREEZE assertion as an indication that BDM has been entered. When BDM
is exited, FREEZE is negated prior to initiation of normal bus cycles — IPIPE0 and
IPIPE1 will be valid when normal instruction prefetch begins.
10.4.5 Command Execution
Figure 10-8 summarizes BDM command execution. Commands consist of one 16-bit
operation word and can include one or more 16-bit extension words. Each incoming
word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the command is complete. Result operands are loaded into the output shift register to be shifted out as the next command
is read. This process is repeated for each command until the CPU returns to normal
operating mode.
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DEVELOPMENT SYSTEM ACTIVITY
CPU ACTIVITY
ENTER BDM
ASSERT FREEZE SIGNAL
WAIT FOR COMMAND
SEND INITIAL COMMAND
LOAD COMMAND REGISTER
ENABLE SHIFT CLOCK
SHIFT OUT 17 BITS
DISABLE SHIFT CLOCK
EXECUTE COMMAND
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LOAD:NOT READY/RESPONSE
PERFORM COMMAND
STORE RESULTS
READ RESULTS/NEW COMMAND
LOAD COMMAND REGISTER
ENABLE SHIFT CLOCK
SHIFT IN/OUT 17 BITS
DISABLE SHIFT CLOCK
READ RESULT REGISTER
IF RESULTS =
"NOT READY"
YES
NO
CONTINUE
Figure 10-8 BDM Command Flow Diagram
10.4.6 Returning from BDM
BDM is terminated when a resume execution (GO) command is received. GO refills
the instruction pipeline from address (PK: PC − $0006). FREEZE is negated prior to
the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the
DSO/DSI signals revert to IPIPE0/IPIPE1 functionality.
10.4.7 BDM Serial Interface
The serial interface uses a synchronous protocol similar to that of the Motorola Serial
Peripheral Interface (SPI). Figure 10-9 is a development system serial logic diagram.
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CPU
DEVELOPMENT SYSTEM
INSTRUCTION
REGISTER BUS
DATA
16
16
0
RCV DATA LATCH
SERIAL IN
PARALLEL OUT
COMMAND LATCH
DSI
PARALLEL IN
SERIAL OUT
DSO
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PARALLEL IN
SERIAL OUT
SERIAL IN
PARALLEL OUT
16
STATUS
RESULT LATCH
EXECUTION
UNIT
16
SYNCHRONIZE
MICROSEQUENCER
DATA
STATUS
CONTROL
LOGIC
DSCLK
CONTROL
LOGIC
SERIAL
CLOCK
Figure 10-9 BDM Serial I/O Block Diagram
The development system serves as the master of the serial link, and is responsible for
the generation of serial interface clock signal DSCLK.
Serial clock frequency range is from DC to one-half the CPU16 clock frequency. If
DSCLK is derived from the CPU16 system clock, development system serial logic can
be synchronized with the target processor.
The serial interface operates in full-duplex mode. Data transfers occur on the falling
edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide — 16 data bits and a status/control bit.
16
15
S/C
0
DATA FIELD
⇑
STATUS CONTROL BIT
Figure 10-10 Serial Data Word Format
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Bit 16 indicates status of CPU-generated messages as shown in Table 10-4.
Table 10-4 CPU Generated Message Encoding
Bit 16
0
0
1
1
Data
xxxx
FFFF
0000
FFFF
Message Type
Valid Data Transfer
Command Complete; Status OK
Not Ready with Response; Come Again
Illegal Command
Freescale Semiconductor, Inc...
Command and data transfers initiated by the development system must clear bit 16.
All commands that return a result return 16 bits of data plus one status bit.
10.4.7.1 CPU Serial Logic
CPU16 serial logic, shown in the left-hand portion of Figure 10-9, consists of transmit
and receive shift registers and of control logic that includes synchronization, serial
clock generation circuitry, and a received bit counter.
Both DSCLK and DSI are synchronized to internal clocks. Data is sampled during the
high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made
available to internal logic. If there is no synchronization between CPU16 and development system hardware, the minimum hold time on DSI with respect to DSCLK is one
full period of CLKOUT.
Serial transfer is based on the DSCLK signal (see Figure 10-11). At the rising edge of
the internal synchronized DSCLK, synchronized data is transferred to the input shift
register, and the received bit counter is decremented. One-half clock period later, the
output shift register is updated, bringing the next output bit to the DSO signal. DSO
changes relative to the rising edge of DSCLK and does not necessarily remain stable
until the falling edge of DSCLK.
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CLKOUT
FREEZE
DSCLK
DSI
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SAMPLE
WINDOW
INTERNAL
SYNCHRONIZED
DSCLK
INTERNAL
SYNCHRONIZED
DSI
DSO
CLKOUT
Figure 10-11 Serial Interface Timing Diagram
One full clock period after the rising edge of DSCLK, the updated counter value is
checked. If the counter has reached zero, the receive data latch is updated from the
input shift register. At the same time, the output shift register is reloaded with a “not
ready/come again” response. When the receive data latch is loaded, the CPU is released to act on the new data. Response data overwrites “not ready” when the CPU
has completed the current operation.
Data written into the output shift register appears immediately on the DSO signal. In
general, this action changes the state of the signal from logic level one (“not ready”) to
logic level zero (valid data). However, this level change only occurs if the transfer is
completed. Error conditions cause the “not ready” status bit to be overwritten.
The DSO state change can be used to signal interface hardware that the next serial
transfer may begin. A time-out of sufficient length to trap error conditions that do not
change the state of DSO must be incorporated into the design. Hardware interlocks in
the CPU prevent result data from corrupting serial transfers in progress.
10.4.7.2 Development System Serial Logic
The development system must initiate BDM and supply the BDM serial clock. Serial
logic must be designed so that these functions do not affect one another.
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Breakpoint requests are made by asserting BKPT in either of two ways. The preferred
method is to assert BKPT during the bus cycle for which an exception is desired. The
second method is to assert BKPT until the CPU16 responds by asserting FREEZE.
This method is useful for forcing a transition into BDM when the bus is not being monitored. Both methods require logic that precludes spurious serial clocks.
Figure 10-12 shows timing for BKPT assertion during a single bus cycle. Figure 1013 shows BKPT/FREEZE timing. In both cases, the serial clock output is left high after
the final shift of each transfer. This prevents tagging the prefetch initiated when BDM
terminates.
SHIFT_CLK
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FORCE_BGND
BKPT_TAG
BKPT
FREEZE
Figure 10-12 BKPT Timing for Single Bus Cycle
SHIFT_CLK
FORCE_BGND
BKPT_TAG
BKPT
FREEZE
Figure 10-13 BKPT Timing for Forcing BDM
Figure 10-14 shows a sample circuit that accommodates either method of BKPT assertion. FORCE_BGND can either be pulsed or remain asserted until FREEZE is asserted. Once FORCE_BGND is asserted, the set-reset latch holds BKPT low until the
first SHIFT_CLK is applied.
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BKPT_TAG
SHIFT_CLK
BKPT/DSCLK
S1
RESET
FORCE_BGND
Q
S2
R
Q
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Figure 10-14 BKPT/DSCLK Logic Diagram
Since it is not latched, BKPT_TAG must be synchronized with CPU16 bus cycles. If
negation of BKPT_TAG extends past FREEZE assertion, the CPU16 will clock on it as
though it were the first DSCLK pulse.
DSCLK is the gated serial clock. Normally high, it pulses low for each bit transferred.
At the end of the seventeenth clock period, it remains high until the start of the next
transmission. Clock frequency is implementation dependent and may range from dc
to the maximum specified frequency.
10.4.8 BDM Command Format
The following standard bit format is utilized by all BDM commands.
15
0
OPERATION WORD
EXTENSION WORD(S)
Operation Word
All commands have a unique 16-bit operation word. No command requires an extension word to specify the operation to be performed.
Extension Words
Some commands require extension words for addresses or immediate data. Addresses require two extension words to accommodate 20 bits. Immediate data can be either
one or two words in length — byte and word data each require a single extension word,
long-word data requires two words. Both operands and addresses are transferred
most significant word first.
10.4.9 Command Sequence Diagram
A command sequence diagram illustrates the serial bus traffic for each command.
Each bubble in the diagram represents a single 17-bit transfer across the bus. The top
half of each bubble shows data sent from the development system to the CPU16. The
bottom half shows data returned by the CPU16 in response to commands. Transmissions overlap to minimize latency.
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Figure 10-15 shows an example command sequence diagram. A description of the information in the diagram follows.
COMMANDS
TRANSMITTED TO
THE CPU16
COMMAND
TRANSMITTED
THIS CYCLE
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RPMEM
*
4 MSB OF
ADDRESS
MS ADDR
NOT READY
LS ADDR
NOT READY
NOT USED
ILLEGAL
NEXT CMD
NOT READY
SEQUENCE TAKEN WHEN
AN ILLEGAL COMMAND
IS RECEIVED
16 LSB OF
ADDRESS
READ
MEMORY
LOCATION
COMMAND
EXECUTION
NOT USED
NOT READY
SEQUENCE TAKEN
WHEN OPERATION
IS NOT COMPLETE
NEXT
COMMAND
CODE
NEXT CMD
RESULT
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
RESPONSES FROM
THE CPU16
Figure 10-15 Command Sequence Diagram Example
The cycle in which the command is issued contains the command word (RPMEM).
During the same cycle, the CPU16 responds with either the low order results of the
previous command or with a command complete status if no results were required.
During the second cycle, the development system supplies the 4 high-order bits of a
memory address. The CPU16 returns a NOT READY response unless the received
command was decoded as unimplemented, in which case the response is the ILLEGAL command encoding. When an ILLEGAL response occurs, the development system must retransmit the command.
In the third cycle, the development system supplies the 16 low-order bits of the memory address. The CPU16 always returns a NOT READY response in this cycle. At the
completion of the third cycle, the CPU16 initiates a memory read operation. Any serial
transfers that begin while the memory access is in progress return the NOT READY
response.
Results are returned in the serial transfer cycle following completion of the memory access. If the serial clock is slow, there may be additional NOT READY responses from
the CPU16. The data transmitted to the CPU during the final transfer is the next command word.
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10.4.10 BDM Command Set
The BDM command set is summarized in Table 10-5. Subsequent pages contain a
BDM command glossary. Glossary entries are in the same order as the table. Each
entry contains detailed information concerning commands and results, and includes a
command sequence diagram.
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Table 10-5 Command Summary
Command
Read Registers
from Mask
Write Registers
from Mask
Read MAC Registers
Mnemonic
RREGM
Write MAC Registers
Read PC and SP
Write PC and SP
Read Data Memory
WRMAC
RPCSP
WPCSP
RDMEM
Write Data Memory
WDMEM
Read Program Memory
RPMEM
Write Program Memory
WPMEM
Execute from current
PK: PC
Null Operation
GO
WREGM
RDMAC
NOP
Description
Read contents of registers specified by
command word register mask
Write to registers specified by
command word register mask
Read contents of entire
multiply and accumulate register set
Write to entire multiply and accumulate register set
Read contents of program counter and stack pointer
Write to program counter and stack pointer
Read data from specified 20-bit address
in data space
Write data to specified 20-bit address
in data space
Read data from specified 20-bit address
in program space
Write data to specified 20-bit address
in program space
Instruction pipeline flushed and refilled;
instructions executed from current PC – $0006
Null command — performs no operation
10.4.10.1 BDM Memory Commands and Bus Errors
If a bus error occurs while a BDM command that accesses memory (RDMEM, WDMEM, RPMEM, or WPMEM) is executing, it is ignored by the CPU16. Data returned
by a read access during which a bus error occurs is indeterminate.
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RREGM
RREGM
Read Registers From Mask
Description:
Registers specified by a register mask operand are read and
returned via the serial link.
Operand:
A 7-bit mask operand is right-justified in an operand word. Registers
are specified as follows:
Bit 0: Condition Code Register [15:4]
Bit 1: Address Extension (K) Register
Bit 2: Index Register Z
Bit 3: Index Register Y
Bit 4: Index Register X
Bit 5: Accumulator E
Bit 6: Accumulator D
Registers are received in order from bit 0 to bit 6.
Result:
A 16-bit word for each register specified. Register content is
returned MSB first. Command complete status ($FFFF) is returned
after the last register has been returned.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
NOT USED
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RREGM
RREGM
Read Registers From Mask
Command Sequence Diagram:
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RREGM
*
NOT USED
ILLEGAL
NEXT CMD
NOT READY
MASK
NOT READY
BIT 0 SET
NOT USED
CCR[15:4]
BIT 1 SET
NOT USED
K
BIT 2 SET
NOT USED
IZ
BIT 3 SET
NOT USED
IY
BIT 4 SET
NOT USED
IX
BIT 5 SET
NOT USED
E
BIT 6 SET
NOT USED
D
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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WREGM
WREGM
Write Registers From Mask
Description:
Registers specified by a register mask operand are written with data
received via the serial link.
Operand:
A 7-bit mask operand is right-justified in an operand word. Registers
are specified as follows:
Bit 0: Condition Code Register [15:4]
Bit 1: Address Extension (K) Register
Bit 2: Index Register Z
Bit 3: Index Register Y
Bit 4: Index Register X
Bit 5: Accumulator E
Bit 6: Accumulator D
Registers are written in order from bit 0 to bit 6.
Result:
A 16-bit word for each register specified. Register content is
returned MSB first. Command complete status ($FFFF) is returned
after the last register has been written.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
1
NOT USED
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WREGM
WREGM
Write Registers From Mask
Command Sequence Diagram:
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WREGM
*
NOT USED
ILLEGAL
NEXT CMD
NOT READY
MASK
NOT READY
BIT 0 SET
CCR
NOT READY
BIT 1 SET
K
NOT READY
BIT 2 SET
IZ
NOT READY
BIT 3 SET
IY
NOT READY
BIT 4 SET
IX
NOT READY
BIT 5 SET
E
NOT READY
BIT 6 SET
D
NOT READY
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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RDMAC
RDMAC
Read MAC Register Set
Description:
The entire multiply and accumulate register set is read and returned
via the serial link.
Operand:
None
Result:
A 16-bit word for each register. Register content is returned MSB
first in the following order:
H Register
I Register
AM[15:0]
AM[31:16]
SL and AM[35:32]
XM: YM
DSP sign latch bit SL is returned in bit 15 of a result word,
AM[35:32] are returned in bits [3:0] of the same word, and bits [14:4]
are undefined.
Command complete status ($FFFF) is returned after the last register
value has been returned.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
0
1
0
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RDMAC
Read MAC Register Set
RDMAC
Command Sequence Diagram:
RDMAC
*
NOT USED
ILLEGAL
NEXT CMD
NOT READY
NOT USED
H
NOT USED
I
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NOT USED
AM [15:0]
NOT USED
AM [31:16]
NOT USED
SL:AM[35:32]
NOT USED
XM/YM
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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WRMAC
WRMAC
Write MAC Register Set
Description:
The entire multiply and accumulate register set is written with data
received via the serial link.
Operand:
A 16-bit word for each register is received (MSB first) via the serial
link. Words are read and written in the following order:
XM: YM
SL and AM[35:32]
AM[31:16]
AM[15:0]
I Register
H Register
DSP sign latch bit SL must be bit 15 of an operand, AM[35:32] must
be bits [3:0] of the same word, and bits [14:4] can be undefined.
Result:
Command complete status ($FFFF) is returned after the last register
is written.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
0
1
1
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WRMAC
Write MAC Register Set
WRMAC
Command Sequence Diagram:
WRMAC
*
NOT USED
ILLEGAL
NEXT CMD
NOT READY
XM/YM
NOT READY
SL:AM[35:32]
NOT READY
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AM[31:16]
NOT READY
AM[15:0]
NOT READY
I
NOT READY
H
NOT READY
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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RPCSP
RPCSP
Read PC and SP
Description:
Program counter and stack pointer are read, then transmitted via the
serial link.
Operand:
None
Result:
Four words are returned MSB first in the following order:
PK extension field and PCSK extension field and SP
PK and SK are contained in bits [3:0] of the respective result words.
Bits [15:4] of the words are undefined.
Command complete status ($FFFF) is returned after the last register
is returned.
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Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
0
Command Sequence Diagram:
RPSCP
*
NOT USED
ILLEGAL
NEXT CMD
NOT READY
NOT USED
PK
NOT USED
PC
NOT USED
SK
NOT USED
SP
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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WPCSP
WPCSP
Write PC and SP
Description:
Program counter and stack pointer are written with data received via
the serial link.
Operand:
Registers are received and written in the following order:
PK extension field and PCSK extension field and SP
PK and SK are contained in bits [3:0] of the respective operand
words. Bits [15:4] of the words are undefined.
Result:
Command complete status ($FFFF) is returned after the last register
is written.
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Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
1
Command Sequence Diagram:
WPSCP
*
NOT USED
ILLEGAL
NEXT CMD
NOT READY
PK
NOT READY
PC
NOT READY
SK
NOT READY
SP
NOT READY
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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RDMEM
RDMEM
Read Data Space Memory
Description:
A byte, word, or long word is read from an address in data space
and transmitted via the serial link.
Operand:
Two extension words specify 20-bit memory address and operand
size. Bits [3:0] of the first word are the bank address. Bits [15:14] are
encoded to specify operand size. Bits [13:4] are reserved for future
use. The second word is the operand address.
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Table 10-6 Operand Size Encoding
Bits
[15:14]
00
01
1X
Result:
Operand
Size
Byte
Word
Long Word
Eight, 16, and 32-bit data. Eight and 16-bit data are transmitted as
16-bit data words, MSB first. For 8-bit data, the upper byte of each
word contains $FF. 32-bit data is transmitted as two 16-bit data
words in MSW, LSW order beginning with the MSB of each word.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
0
Command Sequence Diagram:
RDMEM
*
EXT WD 1
NOT READY
EXT WD 2
NOT READY
NOT USED
ILLEGAL
NEXT CMD
NOT READY
BYTE
WORD
READ
MEMORY
LOCATION
NOT USED
NOT READY
NEXT CMD
RESULT
LONG
WORD
READ
MSW
LOCATION
NOT USED
NOT READY
NOT USED
RESULT
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
READ
LSW
LOCATION
NOT USED
NOT READY
NOT USED
RESULT
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WDMEM
WDMEM
Write Data Space Memory
Description:
A byte, word, or long word is received via the serial link and written
to an address in data space.
Operand:
Two extension words specify 20-bit memory address and operand
size. Third and fourth (long word operands only) words contain data
to be written. Bits [3:0] of the first word are the bank address. Bits
[15:14] are encoded to specify operand size. Bits [13:4] are reserved
for future use. The second word is the operand address. When byte
data is written, the upper byte of the third extension word is not used
— these bits are reserved for future use.
Freescale Semiconductor, Inc...
Table 10-7 Operand Size Encoding
Bits
[15:14]
00
01
1X
Result:
Operand
Size
Byte
Word
Long Word
Command complete status ($FFFF) is returned after memory is written.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
Command Sequence Diagram:
WDMEM
*
EXT WD 1
NOT READY
EXT WD 2
NOT READY
NOT USED
ILLEGAL
NEXT CMD
NOT READY
BYTE
WORD
DATA
NOT READY
WRITE
MEMORY
LOCATION
NEXT CMD
COMPLETE
LONG
WORD
MSW DATA
NOT READY
WRITE
MSW
LOCATION
NOT USED
NOT READY
LSW DATA
NOT READY
WRITE
LSW
LOCATION
NOT USED
NOT READY
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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NOT READY
NEXT CMD
COMPLETE
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RPMEM
RPMEM
Read Program Space Memory
Description:
A 16-bit memory word is read from an address in program space
and transmitted via the serial link.
Operand:
Two extension words specify the 20-bit memory address. Bits [3:0]
of the first word are the bank address (bits [15:4] are undefined).
The second word is the word address. A word address must be even
— misaligned program space reads are not allowed — address LSB
is cleared before the read.
Result:
16-bit data word, transmitted MSB first.
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Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
0
Command Sequence Diagram:
RPMEM
*
MS ADDR
NOT READY
LS ADDR
NOT READY
NOT USED
ILLEGAL
NEXT CMD
NOT READY
READ
MEMORY
LOCATION
NOT USED
NOT READY
NEXT CMD
RESULT
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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WPMEM
WPMEM
Write Program Space Memory
Description:
A 16-bit memory word is received via the serial link and written to an
address in program space.
Operand:
Two extension words specify the 20-bit memory address, and a third
word contains the data to be written. Bits [3:0] of the first word are
the bank address (bits [15:4] are undefined). The second word is the
word address. A word address must be even — misaligned program
space writes are not allowed — address LSB is cleared before the
read.
Result:
Command complete status ($FFFF) is returned after memory is written.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
1
1
Command Sequence Diagram:
WPMEM
*
MS ADDR
NOT READY
LS ADDR
NOT READY
NOT USED
ILLEGAL
NEXT CMD
NOT READY
DATA
NOT READY
WRITE
MEMORY
LOCATION
NOT USED
NOT READY
NEXT CMD
COMPLETE
*RESULTS OF PREVIOUS COMMAND
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GO
GO
Execute Instructions From Current PK: PC
Description:
Background debugging mode is exited, the pipeline is flushed and
refilled, then the CPU16 resumes normal execution of instructions at
PK: PC − $0006. PK and PC retain the values they had when BDM
began unless altered by a WPCSP command.
Operand:
None
Result:
None
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Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
0
0
0
Command Sequence Diagram:
GO
*
NORMAL
MODE
NOT USED
ILLEGAL
NEXT CMD
NOT READY
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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NOP
NOP
Null Operation
Description:
A command is transmitted, but no operation is performed.
Operand:
None
Result:
Command complete status ($FFFF) is returned.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
0
0
1
Command Sequence Diagram:
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GO
*
NEXT CMD
COMPLETE
NOT USED
ILLEGAL
NEXT CMD
NOT READY
*RESULTS OF PREVIOUS COMMAND
OR COMMAND COMPLETE STATUS
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10.4.11 Future Commands
Unassigned command opcodes are reserved by Motorola for future expansion. All unused formats within any revision level will perform a NOP and return the ILLEGAL
command response.
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10.4.12 Recommended BDM Connection
In order to provide for use of development tools when an MCU is installed in a system,
Motorola recommends that appropriate signal lines be routed to a male Berg connector or double-row header installed on the circuit board with the MCU, as shown in the
following figure.
DS
1
2
BERR
GND
3
4
BKPT/DSCLK
GND
5
6
FREEZE
RESET
7
8
IPIPE1/DSI
VDD
9
10
IPIPE0/DSO
16 BERG
Figure 10-16 BDM Connector Pinout
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SECTION 11 DIGITAL SIGNAL PROCESSING
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This section contains detailed information about CPU16 digital signal processing
(DSP) capabilities. A comprehensive presentation of signal processing theory is beyond the scope of this manual — discussion is limited to CPU16 hardware and instructions that support control-oriented DSP.
11.1 General
The CPU16 performs low frequency digital signal processing algorithms in real time.
The most common DSP operation in embedded control applications is filtering, but the
CPU16 can perform several other useful DSP functions. These include autocorrelation
(detecting a periodic signal in the presence of noise), cross-correlation (determining
the presence of a defined periodic signal), and closed-loop control routines (selective
filtration in a feedback path).
Although derivation of DSP algorithms is often a complex mathematic task, the algorithms themselves typically consist of a series of multiply and accumulate (MAC) operations. The CPU16 contains a dedicated set of registers that are used to perform
MAC operations. These are collectively called the MAC unit.
DSP operations generally require a large number of MAC iterations. The CPU16 instruction set includes instructions that perform MAC setup and repetitive MAC operations. Other instructions, such as 32-bit load and store instructions, can also be used
in DSP routines.
Many DSP algorithms require extensive data address manipulation. To increase
throughput, the CPU16 performs effective address calculations and data prefetches
during MAC operations. In addition, the MAC unit provides modulo addressing to efficiently implement circular DSP buffers.
11.2 Digital Signal Processing Hardware
The MAC unit consists of a 16-bit multiplicand register (IR), a 16-bit multiplier register
(HR), a 36-bit accumulator (AM), and two 8-bit address mask registers (XMSK and
YMSK). Figure 11-1 is a programmer's model of the MAC unit.
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20
16 15
8 7
XMSK
0 Bit Position
HR
MAC Multiplier Register
IR
MAC Multiplicand Register
AM
AM
MAC Accumulator MSB [35:16]
MAC Accumulator LSB [15:0]
YMSK
MAC XY Mask Register
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Figure 11-1 MAC Unit Register Model
11.3 Modulo Addressing
The MAC unit uses a simplified form of modulo addressing to implement finite impulse
response filters and circular buffers during execution of MAC and RMAC instructions.
It is accomplished by means of address masks.
During execution of MAC and RMAC, an offset is added to the content of IX and IY to
compute the effective address of data accesses. XMSK and YMSK are used to determine which bits change when an offset is added.
Each address mask consists of eight bits. Each bit in the mask corresponds to a bit in
the low byte of an index register. When a mask bit is set, the corresponding index register bit is changed by addition of the offset. This permits modulo addressing on any
power of two boundary from 21 to 28. The possible buffer sizes are 2, 4, 8, 16, 32, 64,
128, and 256 bytes.
To enable a buffer, set the mask bits corresponding to a particular power of two. All
set bits must be right-justified within the mask. For example, a mask value of
$00011111 (25) enables a 32-byte buffer, while a mask value of $00001111 (24) enables a 16-byte buffer. If all set bits in the mask are not right-justified, results of the
masking operation are undefined. Clear the masks to disable modulo addressing.
Modulo addressing cannot cross bank boundaries. Buffers must be within the bank
specified by the current index register extension field (XK or YK).
11.4 MAC Data Types
Multiplicand and multiplier operands are 16-bit fractions. Bit 15 is the sign bit. An implied radix point lies between bits 15 and 14. There are 15 bits of magnitude. The
range of values is –1 ($8000) to 1 – 2 -15 ($7FFF).
The product of a MAC multiplication is a 32-bit signed fraction. Bit 31 is the sign bit. An
implied radix point lies between bits 31 and 30. There are 31 bits of magnitude, but bit
0 is always cleared. The range of values is –1 ($80000000) to 1 – 2 -30 ($7FFFFFFE).
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The MAC accumulator uses 36-bit signed mixed numbers. The accumulator contains
36 bits. Bit 35 is the sign bit. Bits [34:31] are extension bits. Bits [30:0] are a 31-bit
fixed-point fraction. There is an implied radix point between bits 31 and 30. There are
31 bits of magnitude, but use of the sign and extension bits allows representation of
numbers in the range –16 ($800000000) to 15.999999999 ($7FFFFFFFF).
Figure 11-2 shows fractional data types and weighting of bits. Notice that signed fractions and signed mixed numbers can be interpreted as different arithmetic values
when the same bits in the numbers are set.
15
0
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2–1
±
2–2
2–3
2–4
2–5
⇐ (Radix Point)
2–6
2–7
2–8
2–9
2–
10
2–
11
2–
12
2–
13
2–
14
2–
2–
2–
2–
2–
2–
10
11
12
13
14
15
2–
28
2–
29
2–
30
16
2–1
2–2
2–3
2–4
⇐ (Radix Point)
2–5
2–6
2–7
2–8
2–9
MSW 32-BIT SIGNED FRACTION 1
15
2–
16
0
2–
17
2–
18
2–
19
2–
20
2–
21
2–
22
2–
23
2–
24
2–
25
2–
26
2–
27
LSW 32-BIT SIGNED FRACTION 1
35
23
±
«
22
«
32
31
21
20
«
«
2–
31
0
16
2–1
2–2
2–3
2–4
⇐ (Radix Point)
2–5
2–6
2–7
2–8
2–9
2–
2–
2–
2–
2–
2–
10
11
12
13
14
15
2–
28
2–
29
2–
30
MSW 32-BIT SIGNED FRACTION
15
2–
16
15
16-BIT SIGNED FRACTION
31
±
2–
0
2–
17
2–
18
2–
19
2–
20
2–
21
2–
22
2–
23
2–
24
2–
25
2–
26
2–
27
2–
31
LSW 32-BIT SIGNED FRACTION
Figure 11-2 MAC Data Types
11.5 MAC Accumulator Overflow
It is possible to accumulate to the point of overflow during successive and iterative
multiply and accumulate operations. Overflow becomes important when the 36-bit
number in AM is transferred to accumulator E by a TMER or TMET instruction. The
16-bit fraction in E does not have as great a range of values as the 36-bit number in
AM. Two types of overflow detection are used.
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11.5.1 Extension Bit Overflow
Extension bit overflow occurs when successive accumulation causes overflow into
AM[34:31]. Although an overflow has occurred, sign and magnitude are still represented in 36 bits. Accumulator content cannot be directly converted into a 16-bit fraction,
but it is possible to recover from extension bit overflow during subsequent multiply and
accumulate operations.
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A check for overflow into AM[34:31] is performed at the end of MAC, TMER, ACED,
ASLM, and ACE instructions, and after each iteration of the RMAC instruction. When
overflow has occurred, the EV bit in the CPU16 condition code register is set. Table
11-1 shows the range of AM values and the effects of extension bit overflow. Bit values
are binary.
Table 11-1 AM Values and Effect on EV
AM Magnitude
1 ≤ AM ≤ 15.999999999
0 ≤ AM < 1
–1 ≤ AM < 0
–16 ≤ AM < –1
AM35
0
0
1
1
AM[34:31]
0001 — 1111
0000
1111
0000 — 1110
EV
1
0
0
1
EV is set when extension bit overflow occurs, but will be cleared when a subsequent
accumulation produces a value within the acceptable range.
Note
The RMAC instruction can be interrupted and restarted. Interrupt service routines which include branches based on EV status must be
carefully designed.
11.5.2 Sign Bit Overflow
Sign bit overflow occurs when successive accumulation causes AM35 to be overwritten. The sign of the number in AM is lost. It is no longer accurately represented in 36
bits and accurate conversion to a 16-bit value is impossible.
A check for overflow into AM35 is performed at the end of MAC, TMER, ACED, ASLM,
and ACE instructions, and after each iteration of the RMAC instruction. When overflow
has occurred, the MV bit in the CPU16 condition code register is set. Since sign bit
overflow can only occur after bits [34:31] have been overwritten, the EV bit must also
be set.
The value of AM35 is latched when MV is set. The latched bit, called the sign latch
(SL), shows the sign of AM immediately after overflow, and is therefore the complement of the value in AM35 at the time of overflow. SL is stacked by the PSHM instruction.
Even when a subsequent accumulation produces a value within the acceptable range,
and EV is cleared, MV remains set until cleared by an ANDP, CLRM, TAP, TDP, TEM,
or TEDM instruction. The SL value remains latched until the first sign bit overflow after
MV has been cleared.
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11.6 Data Saturation
The CPU16 can simulate the effect of saturation in analog systems. Saturation mode
is enabled by setting the SM bit in the condition code register. If saturation mode is
enabled, a saturation value will be written to accumulator E when either of the TMER
or TMET instructions is executed while EV or MV is set. Saturation mode operation
does not affect the content of AM.
$7FFF is the positive saturation value; $8000 is the negative saturation value. When
extension overflow occurs, AM35 determines saturation value. When sign bit overflow
occurs, SL determines saturation value. Table 11-2 summarizes bit values and saturation values.
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Table 11-2 Saturation Values
AM35
0
1
—
—
EV
1
1
1
1
MV
0
0
1
1
SL
—
—
1
0
Saturation Value
$7FFF
$8000
$7FFF
$8000
11.7 DSP Instructions
Following are detailed descriptions of each DSP instruction. Instructions are grouped
by function.
11.7.1 Initialization Instructions
The following instructions are used to set up multiply and accumulate operations.
11.7.1.1 LDHI — Load Registers H and I
LDHI must be used to initialize the multiplier and multiplicand registers before execution of MAC and RMAC instructions. HR is loaded with a memory word located at address (XK : IX). IR is loaded with a memory word located at address (YK : IY). LDHI
operation does not affect the CCR.
11.7.1.2 TDMSK — Transfer D to XMSK:YMSK
TDMSK must be used to initialize the X and Y address masks prior to execution of
MAC and RMAC instructions. The contents of the masks are replaced by the content
of accumulator D. D[15:8] are transferred to XMSK, and D[7:0] are transferred to YMSK. The masks are used in modulo addressing. TDMSK operation does not affect the
CCR.
11.7.1.3 TEDM — Transfer E and D to AM
TEDM places 32 bits of data in accumulator M. The content of accumulator E is transferred to AM[31:16], and the content of accumulator D is transferred to AM[15:0].
AM[35:32] reflect the state of AM31 after transfer is complete. TEDM also clears the
CCR EV and MV bits.
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11.7.1.4 TEM — Transfer E to AM
TEM initializes the upper 16 bits of accumulator M and clears the lower 16 bits. The
content of accumulator E is transferred to AM[31:16]. AM[15:0] are cleared. AM[35:32]
reflect the state of bit 31 after transfer is complete. TEM also clears the CCR EV and
MV bits.
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11.7.2 Transfer Instructions
The following instructions are used to transfer MAC data to general-purpose accumulators.
11.7.2.1 TMER — Transfer AM to E Rounded
The TMER instruction rounds a signed 32-bit fraction in accumulator M to 16 bits, then
places the signed 16-bit fraction in accumulator E. The value represented by bits [15:0]
of the fraction are rounded into the value represented by bits [31:16].
Bits [15:0] can have any value in the range $0000 to $FFFF. A value greater than
$8000 must be rounded up, and a value less than $8000 must be rounded down. However, rounding values equal to $8000 in a single direction will introduce a bias. The
CPU16 uses convergent rounding to avoid bias.
In convergent rounding, bit 16 determines whether a value of $8000 in bits [15:0] will
be rounded up or down. When bit 16 = 1, a value of $8000 is rounded up; when bit 16
= 0, a value of $8000 is rounded down.
The EV, MV, N and Z bits in the CCR are set according to the results of the rounding
operation. When saturation mode has been enabled, and either EV or MV is set, the
appropriate saturation value will be placed in accumulator E.
If TMER is executed when saturation mode has not been enabled, and either EV or
MV is set, the value in accumulator E will be meaningless.
11.7.2.2 TMET — Transfer AM to E Truncated
The TMET instruction truncates a signed 32-bit fraction in accumulator M to 16 bits,
then places the signed 16-bit fraction in accumulator E. AM[31:16] are transferred to
accumulator E.
The N and Z bits in the CCR are set according to the results of the transfer operation.
When AM31 is set, N is set. When saturation mode has been enabled, and either EV
or MV is set, the appropriate saturation value will be placed in accumulator E.
If TMER is executed when saturation mode has not been enabled, and either EV or
MV is set, the value in accumulator E will be meaningless.
11.7.2.3 TMXED — Transfer AM to IX : E : D
TMXED provides a way to normalize AM when saturation mode is disabled and recovery from an extension bit overflow is necessary. AM[35:32] are transferred to IX[3:0].
IX[15:4] are sign-extended according to the content of AM35. AM[31:16] are transferred to accumulator E. AM[15:0] are transferred to accumulator D.
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After TMXED is executed, transfer the content of IX to a RAM location, load data into
E : D, then shift and round appropriately.
11.7.2.4 LDED/STED — Long Word Load and Store Instructions
While LDED and STED are not specifically intended for DSP, they operate on the concatenated E and D accumulators, and are useful for handling DSP values. See listings
in SECTION 6 INSTRUCTION GLOSSARY.
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11.7.3 Multiplication and Accumulation Instructions
These instructions are the heart of CPU16 digital signal processing capability. The
MAC and RMAC instructions provide flexible control-oriented processing with modulo
addressing, while the FMULS, ACE, and ACED instructions provide the ability to prescale and add constants.
11.7.3.1 MAC — Multiply and Accumulate
MAC multiplies a 16-bit signed fractional multiplicand contained in IR by a 16-bit
signed fractional multiplier contained in HR. The product is left-shifted once to align
the radix point between bits 31 and 30, then placed in E : D[31:1]. D0 is cleared. The
aligned product is then added to the content of AM.
As the multiply and accumulate operation takes place, 4-bit X and Y offsets (xo, yo)
specified by an instruction operand are sign-extended to 16 bits and used with XMSK
and YMSK values to qualify the corresponding index registers. The following expressions are used to qualify the index registers:
IX = ((IX) • X MASK) ✛ ((IX) + xo) • X MASK)
IY = ((IY) • Y MASK) ✛ ((IY) + yo) • Y MASK)
Writing a non-zero value into a mask register prior to MAC execution enables modulo
addressing. The TDMSK instruction writes mask values. When a mask contains $0,
the sign-extended offset is added to the content of the corresponding index register.
After accumulation, HR content is transferred to IZ, then a word at the address pointed
to by IX is loaded into HR, and a word at the address pointed to by IY is loaded into
IR. The fractional product remains in E : D.
When both registers contain $8000 (–1), a value of $80000000 (1.0 in 36-bit format)
is accumulated, (E : D) is $80000000 (–1.0 in 32-bit format), and the CCR V bit is set.
11.7.3.2 RMAC — Repeating Multiply and Accumulate
RMAC performs repeated multiplication of 16-bit signed fractional multiplicands contained in IR by 16-bit signed fractional multipliers contained in HR. Accumulator D is
used for temporary storage during multiplication. Each product is added to the content
of the accumulator M. A 16-bit integer contained by accumulator E determines the
number of repetitions.
There are implied radix points between bits 15 and 14 of HR and IR. Each product is
left-shifted one place to align the radix point between bits 31 and 30 before addition to
AM.
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As multiply and accumulate operations take place, 4-bit offsets (xo, yo) specified by
an instruction operand are sign-extended to 16 bits and used with XMSK and YMSK
to qualify the corresponding index registers. The following expressions are used to
qualify the index registers:
IX = ((IX) • X MASK) ✛ ((IX) + xo) • X MASK)
IY = ((IY) • Y MASK) ✛ ((IY) + yo) • Y MASK)
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Writing a non-zero value into a mask register prior to RMAC execution enables modulo
addressing. The TDMSK instruction writes mask values. When a mask contains $0,
the sign-extended offset is added to the content of the corresponding index register.
After accumulation, a word pointed to by XK: IX is loaded into HR, and a word pointed
to by YK: IY is loaded into IR, then the value in E is decremented and tested. If these
values are to be used in successive RMAC operations, the registers must be re-initialized with the LDHI instruction. RMAC always iterates at least once, even when executed with a zero or negative value in E. Since the value in E is decremented, then
tested, loading E with $8000 results in 32,770 iterations.
If HR and IR both contain $8000 (–1), a value of $80000000 (1.0 in 36-bit format) is
accumulated, but no condition code is set.
RMAC execution is suspended during bus error, breakpoint, and interrupt exceptions.
Operation resumes when RTI is executed at the end of the exception handler. In order
for execution to resume correctly, all registers used by RMAC must be stacked or left
unchanged by the exception handler. The PSHMAC and PULMAC instructions stack
MAC unit resources. See SECTION 9 EXCEPTION PROCESSING for more information.
11.7.3.3 FMULS — Signed Fractional Multiply
FMULS left-shifts the product of a 16-bit signed fractional multiplication once before
placing it in concatenated accumulators E and D.
A 16-bit signed fractional multiplicand contained by accumulator E is multiplied by a
16-bit signed fractional multiplier contained by accumulator D. There are implied radix
points between bits 15 and 14 of the accumulators. The product is left-shifted one
place to align the radix point between bits 31 and 30, then placed in E : D[31:1]. D0 is
cleared.
When both accumulators contain $8000 (–1), the product is $80000000 (–1.0) and the
CCR V bit is set.
11.7.3.4 ACED — Add E: D to AM
ACED is used with either of the FMULS or MAC instructions. It allows direct addition
of 32-bit signed fractions to accumulator M. The concatenated contents of accumulators E and D are added to the content of accumulator M.
The value in the concatenated accumulators is assumed to be a 32-bit signed fraction
with an implied radix point aligned between bits 31 and 30.
EV and MV in the CCR are set according to the result of ACED operation.
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11.7.3.5 ACE — Add E to AM
ACE is used with either of the FMULS or MAC instructions. It allows direct addition of
16-bit signed fractions to accumulator M. The content of accumulator E is added to
AM[31:16]. Bits 15 to 0 of accumulator M are not affected.
The value in E is assumed to be a 16-bit signed fraction with an implied radix point
between bits 15 and 14.
EV and MV in the CCR are set according to the result of ACE operation.
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11.7.4 Bit Manipulation Instructions
There are three instructions that operate directly on the bits in accumulator M. ASLM
and ASRM perform 36-bit arithmetic shifts and CLRM clears the accumulator.
11.7.4.1 ASLM — Arithmetic Shift Left AM
Shifts all 36 bits of accumulator M one place to the left. Bit 35 is transferred to the CCR
C bit. Bit 0 is loaded with a zero.
EV, MV, and N in the CCR are set according to the result of ASLM operation.
11.7.4.2 ASRM — Arithmetic Shift Right AM
Shifts all 36 bits of accumulator M one place to the right. Bit 0 is transferred to the CCR
C bit. Bit 35 is held constant.
EV, MV, and N in the CCR are set according to the result of ASRM operation.
11.7.4.3 CLRM — Clear AM
CLRM provides a simple way to initialize accumulator M when a starting value of
$000000000 is needed. AM[35:0] are cleared to zero. EV and MV in the CCR are also
cleared.
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11.7.5 Stacking Instructions
The PSHMAC and PULMAC instructions stack and restore all MAC resources.
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11.7.5.1 PSHMAC — Push MAC Registers
PSHMAC stacks MAC registers in the sequence shown, beginning at the address
pointed to by the stack pointer.
15
(SP)
(SP) – $0002
(SP) – $0004
(SP) – $0006
(SP) – $0008 SL
(SP) – $000A
8 7
H REGISTER
I REGISTER
ACCUMULATOR M[15:0]
ACCUMULATOR M[31:16]
RESERVED
IX ADDRESS MASK
IY ADDRESS MASK
0
AM[35:32]
The entire MAC unit internal state is saved on the system stack. Registers are stacked
from high to low address. The stack pointer is automatically decremented after each
save operation (the stack grows downward in memory). If SP overflow occurs as a result of operation, the SK field is decremented.
11.7.5.2 PULMAC — Pull MAC Registers
PULMAC restores MAC registers in the sequence shown, beginning at the address
pointed to by the stack pointer.
15
(SP) + $000A
(SP) + $0008 SL
(SP) + $0006
(SP) + $0004
(SP) + $0002
(SP)
8
IX ADDRESS MASK
7
0
IY ADDRESS MASK
RESERVED
ACCUMULATOR M[31:16]
ACCUMULATOR M[15:0]
I REGISTER
H REGISTER
AM[35:32]
The entire MAC unit internal state is restored from the system stack. Registers are restored in order from low to high address. The SP is incremented after each restoration
(stack shrinks upward in memory). If SP overflow occurs as a result of operation, the
SK field is incremented.
11.7.6 Branch Instructions
LBEV and LBMV are conditional long branch instructions associated with the EV and
MV bits in the CCR.
11.7.6.1 LBEV — Long Branch if EV Set
LBEV causes a long program branch if the EV bit in the condition code register has a
value of one. A 16-bit signed relative offset is added to the current value of the program
counter. When the operation causes PC overflow, the PK field is incremented or decremented.
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Because the EV flag can be set and cleared more than once during the execution of
RMAC instructions, exception handler routines that contain an LBEV instruction must
be carefully designed.
11.7.6.2 LBMV — Long Branch if MV Set
LBMV causes a long program branch if the MV bit in the condition code register has a
value of one. A 16-bit signed relative offset is added to the current value of the program
counter. When the operation causes PC overflow, the PK field is incremented or decremented.
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The MV bit is latched when sign bit overflow occurs, and must be cleared by an ANDP,
CLRM, TAP, TDP, TEM, or TEDM instruction.
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APPENDIX A COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY
LANGUAGE
A.1 Introduction
This appendix compares the assembly language of the M68HC11 microcontroller and
the M68HC16 microcontroller. It provides information concerning functionally equivalent instructions and discusses cases that need special attention. It is intended to supplement the CPU16 Reference Manual — refer to appropriate sections of the manual
for detailed information on system resources, addressing modes, instruction set, and
processing flow.
The appendix is divided into eight sections. The first section shows M68HC11 CPU
and CPU16 register models. The second discusses CPU16 instruction formats and
pipelining. The third lists M68HC11 CPU instructions that have an equivalent CPU16
instruction. The fourth lists M68HC11 CPU instructions that operate differently on the
CPU16. The fifth lists M68HC11 CPU assembler directives that operate differently on
the CPU16, but for which the difference is transparent to the programmer. The sixth
lists directives that have a new syntax. The seventh section discusses changes to
addressing modes. The last section is an assembly language comparison in tabular
format.
The CPU16 is designed for maximum compatibility with the M68HC11 CPU, and only
moderate effort is required to port an application from an M68HC11 microcontroller to
an M68HC16 microcontroller. Certain M68HC11instructions have been modified to
support the improved addressing and exception handling capabilities of the CPU16.
Other M68HC11 CPU instructions, particularly those related to manipulation of the
condition code register, have been replaced.
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A.2 Register Models
20
16 15
8 7
0 BIT POSITION
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A
D
B
ACCUMULATORS A AND B
ACCUMULATOR D (A : B)
IX
INDEX REGISTER X
IY
INDEX REGISTER Y
SP
STACK POINTER
PC
PROGRAM COUNTER
CCR
CONDITION CODE REGISTER
Figure A-1 M68HC11 CPU Registers
7
N
6
X
5
H
4
I
3
N
2
Z
1
V
0
C
Figure A-2 M68HC11 CPU Condition Code Register
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20
16 15
8 7
0 BIT POSITION
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A
D
B
ACCUMULATORS A AND B
ACCUMULATOR D (A : B)
E
ACCUMULATOR E
XK
IX
INDEX REGISTER X
YK
IY
INDEX REGISTER Y
ZK
IZ
INDEX REGISTER Z
SK
SP
STACK POINTER
PK
PC
PROGRAM COUNTER
CCR
EK
XK
YK
PK
CONDITION CODE REGISTER/
PC EXTENSION REGISTER
ZK
ADDRESS EXTENSION REGISTER
SK
STACK EXTENSION REGISTER
HR
MAC MULTIPLIER REGISTER
IR
MAC MULTIPLICAND REGISTER
AM
AM
MAC ACCUMULATOR MSB [35:16]
MAC ACCUMULATOR LSB [15:0]
XMSK
YMSK
MAC XY MASK REGISTER
Figure A-3 CPU16 Registers
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
7
6
IP
5
4
3
SM
2
1
0
PK
Figure A-4 CPU16 Condition Code Register
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A.3 CPU16 Instruction Formats and Pipelining Mechanism
A.3.1 Instruction Format
CPU16 instructions consist of an 8-bit opcode, which may be preceded by an 8-bit prebyte and/or followed by one or more operands.
Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone, but
page 1, 2, and 3 opcodes are pointed to by a prebyte code on page 0. The prebytes
are $17 (page 1), $27 (page 2), and $37 (page 3).
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Operands can be four bits, eight bits or sixteen bits in length. However, because the
CPU16 fetches instructions from even byte boundaries, each instruction must contain
an even number of bytes.
Operands are organized as bytes, words, or a combination of bytes and words. Fourbit operands are either zero-extended to eight bits, or packed two to a byte. The largest
instructions are 6 bytes in length. Size, order, and function of operands are evaluated
when an instruction is decoded.
A page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions that
use 8-bit indexed, immediate, and relative addressing modes have this form — code
written with these instructions is very compact.
A.3.2 Execution Model
This description is a simplified model of the mechanism the CPU16 uses to fetch and
execute instructions. Functional divisions in the model do not necessarily correspond
to distinct architectural subunits of the microprocessor.
There are three functional blocks involved in fetching, decoding, and executing
instructions. These are the microsequencer, the instruction pipeline, and the execution
unit. These elements function concurrently — at any given time, all three may be
active.
A.3.2.1 Microsequencer
The microsequencer controls the order in which instructions are fetched, advanced
through the pipeline, and executed. It increments the program counter and generates
multiplexed external tracking signals IPIPE0 and IPIPE1 from internal signals that control execution sequence.
A.3.2.2 Instruction Pipeline
The pipeline is a three stage FIFO that holds instructions while they are decoded and
executed. As many as three instructions can be in the pipeline at one time (single-word
instructions, one held in stage C, one being executed in stage B, and one latched in
stage A).
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A.3.2.3 Execution Unit
The execution unit evaluates opcodes, interfaces with the microsequencer to advance
instructions through the pipeline, and performs instruction operations.
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A.3.3 Execution Process
Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are
evaluated in stage B. The execution unit can access operands in either stage A or
stage B (stage B accesses are limited to 8-bit operands). When execution is complete,
opcodes are moved from stage B to stage C, where they remain until the next instruction is complete.
A prefetch mechanism in the microsequencer reads instruction words from memory
and increments the program counter. When instruction execution begins, the program
counter points to an address six bytes after the address of the first word of the instruction being executed.
The number of machine cycles necessary to complete an execution sequence varies
according to the complexity of the instruction.
A.3.4 Changes in Program Flow
When program flow changes, instructions are fetched from a new address. Before
execution can begin at the new address, instructions and operands from the previous
instruction stream must be removed from the pipeline. If a change in flow is temporary,
a return address must be stored, so that execution of the original instruction stream
can resume after the change in flow.
At the time an instruction that causes a change in program flow executes, PK : PC
point to the address of the first word of the instruction + $0006. During execution of the
instruction, PK : PC is loaded with the address of the first word of the new instruction
stream. However, stages A and B still contain words from the old instruction stream.
The CPU16 prefetches to advance the new instruction to stage C, and fills the pipeline
from the new instruction stream.
A.3.4.1 Jumps
The CPU16 jump instruction uses 20-bit extended and indexed addressing modes. It
consists of an 8-bit opcode with a 20-bit argument. No return PK : PC is stacked for a
jump.
A.3.4.2 Branches
The CPU16 supports 8-bit relative displacement (short), and 16-bit relative displacement (long) branch instructions, as well as specialized bit condition branches that use
indexed addressing modes. CPU16 short branches are generally equivalent to
M68HC11 CPU branches, although opcodes are not identical. M68HC11 BHI and
BLO are replaced by CPU16 BCC and BCS.
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Short branch instructions consist of an 8-bit opcode and an 8-bit operand contained in
one word. Long branch instructions consist of an 8-bit prebyte and an 8-bit opcode in
one word, followed by an operand word. Bit condition branches consist of an 8-bit
opcode and an 8-bit operand in one word, followed by one or two operand words.
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When a branch instruction executes, PK : PC point to an address equal to the address
of the first word of the instruction plus $0006. The range of displacement for each type
of branch is relative to this value. In addition, because prefetches are automatically
aligned to word boundaries, only even offsets are valid — an odd offset value is
rounded down.
A.3.4.3 Subroutines
Subroutines can be called by short (BSR) or long (LBSR) branches, or by a jump
(JSR). The RTS instruction returns control to the calling routine. BSR consists of an 8bit opcode with an 8-bit operand. LBSR consists of an 8-bit prebyte and an 8-bit
opcode in one word, followed by an operand word. JSR consists of an 8-bit opcode
with a 20-bit argument. RTS consists of an 8-bit prebyte and an 8-bit opcode in one
word.
When a subroutine instruction is executed, PK: PC contain the address of the calling
instruction plus $0006. All three calling instructions stack return PK : PC values prior
to processing instructions from the new instruction stream. In order for RTS to work
with all three calling instructions, however, the value stacked by BSR must be
adjusted.
LBSR and JSR are two-word instructions. In order for program execution to resume
with the instruction immediately following them, RTS must subtract $0002 from the
stacked PK : PC value. BSR is a one-word instruction — it subtracts $0002 from PK :
PC prior to stacking so that execution will resume correctly.
A.3.4.4 Interrupts
Interrupts are a type of exception, and are thus subject to special rules regarding execution process. This comparison is limited to the effects of SWI (software interrupt) and
RTI (return from interrupt) instructions.
Both SWI and RTI consist of an 8-bit prebyte and an 8-bit opcode in one word. SWI
initiates synchronous exception processing. RTI causes execution to resume with the
instruction following the last instruction that completed execution prior to interrupt.
Asynchronous interrupts are serviced at instruction boundaries. PK : PC + $0006 for
the following instruction is stacked, and exception processing begins. In order to
resume execution with the correct instruction, RTI subtracts $0006 from the stacked
value.
Interrupt exception processing is included in the SWI instruction definition. The PK :
PC value at the time of execution is the first word address of SWI plus $0006. If this
value were stacked, RTI would cause SWI to execute again. In order to resume execution with the instruction following SWI, $0002 is added to the PK : PC value prior to
stacking.
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A.3.4.5 Interrupt Priority
There are eight levels of interrupt priority. All interrupts with priorities less than seven
can be masked by writing to the CCR interrupt priority (IP) field.
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The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide
eight priority masks. Masks prevent an interrupt request of a priority less than or equal
to the mask value (except for NMI) from being recognized and processed. When IP
contains %000, no interrupt is masked.
A.3.5 Stack Frame
When a change of flow occurs, the contents of the program counter and condition code
register are stacked at the location pointed to by SK : SP. Figure A-5 shows the stack
frame. Unless it is altered during exception processing, the stacked PK : PC value is
the address of the next instruction in the current instruction stream, plus $0006. RTS
restores only stacked PK : PC – 2, while RTI restores PK : PC – 6 and the CCR.
⇐ SP After Stacking
Low Address
High Address
Condition Code Register
Program Counter
⇐ SP Before Stacking
Figure A-5 CPU16 Stack Frame Format
A.4 Functionally Equivalent Instructions
A.4.1 BHS
The CPU16 uses only the BCC mnemonic. BHS is used in the M68HC11 CPU instruction set to differentiate a branch based on a comparison of unsigned numbers from a
branch based on operations that clear the carry bit.
A.4.2 BLO
The CPU16 uses only the BCS mnemonic. BLO is used in the M68HC11 CPU instruction set to differentiate a branch based on a comparison of unsigned numbers from a
branch based on operations that set the carry bit.
A.4.3 CLC
The CLC instruction has been replaced by ANDP. ANDP performs AND between the
content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[0:3]) is
not affected.
The following code can be used to clear the C bit in the CCR:
ANDP #$FEFF
The ANDP instruction can clear the entire CCR, except for the PK extension field, at
once.
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A.4.4 CLI
The CLI instruction has been replaced by ANDP. ANDP performs AND between the
content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[0:3]) is
not affected.
The following code can be used to clear the IP field in the CCR:
ANDP #$FF1F
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The ANDP instruction can clear the entire CCR, except for the PK extension field, at
once.
A.4.5 CLV
The CLV instruction has been replaced by ANDP. ANDP performs AND between the
content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[0:3]) is
not affected.
The following code can be used to clear the V bit in the CCR:
ANDP #$FDFF
The ANDP instruction can clear the entire CCR, except for the PK extension field, at
once.
A.4.6 DES
The DES instruction has been replaced by AIS. AIS adds a 20-bit value to concatenated SK and SP. The 20-bit value is formed by sign-extending an 8-bit or 16-bit
signed immediate operand.
The following code can be used to perform a DES:
AIS –1
CPU16 stacking operations normally use 16-bit words and even word addresses,
while M68HC11 CPU stacking operations normally use bytes and byte addresses. If
the CPU16 stack pointer is misaligned as a result of a byte operation, performance can
be degraded.
A.4.7 DEX
The DEX instruction has been replaced by AIX. AIX adds a 20-bit value to concatenated XK and IX. The 20-bit value is formed by sign-extending an 8-bit or 16-bit signed
immediate operand.
The following code can be used to perform a DEX:
AIX –1
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A.4.8 DEY
The DEY instruction has been replaced by AIY. AIY adds a 20-bit value to concatenated YK and IY. The 20-bit value is formed by sign-extending an 8-bit or 16-bit signed
immediate operand.
The following code can be used to perform a DEY:
AIY –1
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A.4.9 INS
The INS instruction has been replaced by AIS. AIS adds a 20-bit value to concatenated SK and SP. The 20-bit value is formed by sign-extending an 8-bit or 16-bit
signed immediate operand.
The following code can be used to perform an INS:
AIS –1
CPU16 stacking operations normally use 16-bit words and even word addresses,
while M68HC11 CPU stacking operations normally use bytes and byte addresses. If
the CPU16 stack pointer is misaligned as a result of a byte operation, performance can
be degraded.
A.4.10 INX
The INX instruction has been replaced by AIX. AIX adds a 20-bit value to concatenated XK and IX. The 20-bit value is formed by sign-extending an 8-bit or 16-bit signed
immediate operand.
The following code can be used to perform an INX:
A.4.11 INY
The INY instruction has been replaced by AIY. AIY adds a 20-bit value to concatenated YK and IY. The 20-bit value is formed by sign-extending an 8-bit or 16-bit signed
immediate operand.
The following code can be used to perform an INY:
AIY 1
A.4.12 PSHX
The PSHX instruction has been replaced by PSHM. PSHM stores the contents of
selected registers on the system stack. Registers are designated by setting bits in a
mask byte.
The following code can be used to stack index register X:
PSHM X
The CPU16 can stack up to seven registers with a single PSHM instruction.
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A.4.13 PSHY
The PSHY instruction has been replaced by PSHM. PSHM stores the contents of
selected registers on the system stack. Registers are designated by setting bits in a
mask byte.
The following code can be used to stack index register Y:
PSHM Y
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The CPU16 can stack up to seven registers with a single PSHM instruction.
A.4.14 PULX
The PULX instruction has been replaced by PULM. PULM restores the contents of
selected registers from the system stack. Registers are designated by setting bits in a
mask byte.
The following code can be used to restore index register X:
PULM X
The CPU16 can restore up to seven registers with a single PULM instruction. As a part
of normal execution, PULM reads an extra location in memory. The extra data is discarded. A PULM from the highest available location in memory will cause an attempt
to read an unimplemented location, with unpredictable results.
A.4.15 PULY
The PULY instruction has been replaced by PULM. PULM restores the contents of
selected registers from the system stack. Registers are designated by setting bits in a
mask byte.
The following code can be used to restore index register Y:
PULM Y
The CPU16 can restore up to seven registers with a single PULM instruction. As a part
of normal execution, PULM reads an extra location in memory. The extra data is discarded. A PULM from the highest available location in memory will cause an attempt
to read an unimplemented location, with unpredictable results.
A.4.16 SEC
The SEC instruction has been replaced by ORP. ORP performs inclusive OR between
the content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[3:0]) is
not affected.
The following code can be used to set the CCR C bit:
ORP #$0100
The ORP instruction can set all CCR bits, except the PK extension field, at once.
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A.4.17 SEI
The SEI instruction has been replaced by ORP. ORP performs inclusive OR between
the content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[3:0]) is
not affected.
The following code can be used to set all the bits in the CCR IP field:
ORP #$00E0
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The ORP instruction can set all CCR bits, except the PK extension field, at once.
A.4.18 SEV
The SEV instruction has been replaced by ORP. ORP performs inclusive OR between
the content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[3:0]) is
not affected.
The following code can be used to set the CCR V bit:
ORP #$0200
The ORP instruction can set all CCR bits, except the PK extension field, at once.
A.4.19 STOP (LPSTOP)
LPSTOP is used to minimize microcontroller power consumption. The CPU16 has
seven levels of interrupt priority. If an interrupt request of higher priority than the priority value stored when the microcontroller enters low-power stop mode is received, the
microcontroller is activated, and the CPU16 processes an interrupt exception.
A.5 Instructions that Operate Differently
A.5.1 BSR
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The CPU16
stacks the current PC and CCR, but restores only the return PK: PC. The programmer
must designate (PSHM) which other registers are stacked during a subroutine.
Because SK : SP point to the next available word address, stacked CPU16 parameters
are at a different offset from the stack pointer than stacked M68HC11 CPU parameters. In order for RTS to work with all three calling instructions, the PK : PC value
stacked by BSR is decremented by two before being pushed on to the stack. Stacked
PC value is the return address + $0002.
A.5.2 JSR
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The CPU16
stacks the current PC and CCR, but restores only the return PK : PC. The programmer
must designate (PSHM) which other registers are stacked during a subroutine.
Because SK : SP point to the next available word address, stacked CPU16 parameters
are at a different offset from the stack pointer than stacked M68HC11 CPU
parameters.
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A.5.3 PSHA, PSHB
These instructions operate in the same way as the M68HC11 instructions with the
same mnemonics. However, because the CPU16 normally pushes words from an
even boundary, pushing byte data to the stack can misalign the stack pointer and
degrade performance.
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A.5.4 PULA, PULB
These instructions operate in the same way as the M68HC11 instructions with the
same mnemonics. However, because the CPU16 normally pulls words from the stack,
pulling byte data can misalign the stack pointer and degrade performance.
A.5.5 RTI
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The CPU16
stacks only the current PC and CCR before exception processing begins. In order to
resume execution after interrupt with the correct instruction, RTI subtracts $0006 from
the stacked PK : PC.
A.5.6 SWI
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The PK : PC
value at the time of execution is the first word address of SWI plus $0006. If this value
were stacked, RTI would cause SWI to execute again. In order to resume execution
with the instruction following SWI, $0002 is added to the PK : PC value prior to stacking. The programmer must designate (PSHM) which other registers are stacked during
an interrupt.
A.5.7 TAP
The CPU16 CCR and the M68HC11 CPU CCR are different. The CPU16 interrupt priority scheme differs from that of the M68HC11 CPU. The CPU16 interrupt priority field
cannot be changed by the TAP instruction.
A.5.7.1 M68HC11 CPU Implementation:
7
A7
⇓
7
S
6
A6
⇓
6
X
5
A5
⇓
5
H
4
A4
⇓
4
I
3
A3
⇓
3
N
2
A2
⇓
2
Z
1
A1
⇓
1
V
0
A0
⇓
0
C
1
A1
⇓
9
V
0
A0
⇓
8
C
A.5.7.2 CPU16 Implementation:
7
A7
⇓
15
S
6
A6
⇓
14
MV
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A-12
5
A5
⇓
13
H
4
A4
⇓
12
EV
3
A3
⇓
11
N
2
A2
⇓
10
Z
7
6
IP
5
4
SM
3
2
1
0
PK
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A.5.8 TPA
The CPU16 CCR and the M68HC11 CPU CCR are different. TPA cannot be used to
read CPU16 interrupt priority status. Use TPD to read the CPU16 CCR interrupt priority field.
A.5.8.1 M68HC11 CPU Implementation:
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7
S
⇓
7
A7
6
X
⇓
6
A6
5
H
⇓
5
A5
4
I
⇓
4
A4
3
N
⇓
3
A3
2
Z
⇓
2
A2
1
V
⇓
1
A1
0
C
⇓
0
A0
9
V
⇓
1
A1
8
C
⇓
0
A0
A.5.8.2 CPU16 Implementation:
15
S
⇓
7
A7
14
MV
⇓
6
A6
13
H
⇓
5
A5
12
EV
⇓
4
A4
11
N
⇓
3
A3
10
Z
⇓
2
A2
7
6
IP
5
4
SM
3
2
1
0
PK
A.5.9 WAI
The CPU16 does not stack registers during WAI. The CPU16 acknowledges interrupts
faster out of WAI than LPSTOP. However, LPSTOP minimizes microcontroller power
consumption.
A.6 Instructions With Transparent Changes
A.6.1 RTS
The CPU16 stack frame differs from the M68HC11 CPU stack frame. PK : PC is
restored during an RTS. The PK field in the CCR is restored, then the PC value read
from the stack is decremented by two before being loaded into the PC. The PC value
is decremented because LBSR and JSR are two-word instructions. In order for program execution to resume with the instruction immediately following them, RTS must
subtract $0002 from the stacked PK : PC value. Because BSR is a one-word instruction, it subtracts $0002 from PK : PC prior to stacking so that execution will resume
correctly after RTS.
A.6.2 TSX
The CPU16 adds two to SK : SP before the transfer to XK : IX. The M68HC11 CPU
adds one.
A.6.3 TSY
The CPU16 adds two to SK : SP before the transfer to YK : IY. The M68HC11 CPU
adds one.
CPU16
COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY LANGUAGE
REFERENCE MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
A-13
Freescale Semiconductor, Inc.
A.6.4 TXS
The CPU16 subtracts two from XK : IX before the transfer to SK : SP. The M68HC11
CPU subtracts one.
A.6.5 TYS
The CPU16 subtracts two from YK : IY before the transfer to SK : SP. The M68HC11
CPU subtracts one.
A.7 Unimplemented Instructions
Freescale Semiconductor, Inc...
A.7.1 TEST
Causes the program counter to be continuously incremented.
A.8 Addressing Mode Differences
A.8.1 Extended Addressing Mode
In M68HC11 CPU extended addressing mode, the effective address of the instruction
appears explicitly in the two bytes following the opcode. In CPU16 extended addressing mode, the effective address is formed by concatenating the EK field and the 16-bit
byte address. A 20-bit extended mode (EXT20) is used only by the JMP and JSR
instructions. These instructions contain a 20-bit effective address that is zeroextended to 24 bits to give the instruction an even number of bytes.
A.8.2 Indexed Addressing Mode
M68HC11 CPU indexed addressing mode forms the effective address by adding the
fixed, 8-bit, unsigned offset to the index register. In CPU16 indexed addressing mode,
a fixed 16-bit offset can be used. Note however, that the 16-bit offset is signed and can
give a negative offset from the index register. An 8-bit unsigned mode is still available
on the CPU16. A 20-bit indexed mode is used for JMP and JSR instructions. In 20-bit
modes, a 20-bit signed offset is added to the value contained in an index register.
A.8.3 Post-Modified Index Addressing Mode
Post-modified index mode is used with the CPU16 MOVB and MOVW instructions. A
signed 8-bit offset is added to index register X after the effective address formed by
XK : IX is used.
A.8.4 Use of CPU16 Indexed Mode to Replace M68HC11 CPU Direct Mode
In M68HC11 systems, direct addressing mode can be used to perform rapid accesses
to RAM or I/O mapped into bank 0 ($0000 to $00FF), but the CPU16 uses the first 512
bytes of bank 0 for exception vectors. To provide an enhanced replacement for direct
mode, the ZK field and index register Z have been assigned reset initialization vectors.
After ZK : IZ have been initialized, indexed addressing provides rapid access to useful
data structures.
MOTOROLA
A-14
COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY LANGUAGE
CPU16
REFERENCE
MANUAL
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table A-1 M68HC16 Implementation of M68HC11 Instructions
M68HC11 Instruction
BHS
BLO
BSR
CLC
CLI
CLV
DES
DEX
DEY
INS
INX
INY
JMP
JSR
LSL, LSLD
PSHX
PSHY
PULX
PULY
RTI
RTS
SEC
SEI
SEV
STOP
TAP
TPA
TSX
TSY
TXS
TXY
TYS
TYX
WAI
M68HC16 Implementation
Replaced by BCC
Replaced by BCS
Generates a different stack frame
Replaced by ANDP
Replaced by ANDP
Replaced by ANDP
Replaced by AIS
Replaced by AIX
Replaced by AIY
Replaced by AIS
Replaced by AIX
Replaced by AIY
IND8 addressing modes replaced by IND20 and EXT modes
IND8 addressing modes replaced by IND20 and EXT modes
Generates a different stack frame
Use ASL instructions*
Replaced by PSHM
Replaced by PSHM
Replaced by PULM
Replaced by PULM
Reloads PC and CCR only
Uses two-word stack frame
Replaced by ORP
Replaced by ORP
Replaced by ORP
Replaced by LPSTOP
CPU16 CCR bits differ from M68HC11
CPU16 interrupt priority scheme differs from M68HC11
CPU16 CCR bits differ from M68HC11
CPU16 interrupt priority scheme differs from M68HC11
Adds two to SK : SP before transfer to XK : IX
Adds two to SK : SP before transfer to YK : IY
Subtracts two from XK : IX before transfer to SK : SP
Transfers XK field to YK field
Subtracts two from YK : IY before transfer to SK : SP
Transfers YK field to XK field
Waits indefinitely for interrupt or reset
Generates a different stack frame
*Motorola assemblers will automatically translate LSL mnemonics
CPU16
COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY LANGUAGE
REFERENCE MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
A-15
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MOTOROLA
A-16
COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY LANGUAGE
CPU16
REFERENCE
MANUAL
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
APPENDIX B MOTOROLA ASSEMBLER SYNTAX
Freescale Semiconductor, Inc...
Name
ABA
ABX
ABY
ABZ
ACE
ACED
ADCA
ADCB
ADCD
Mode
INH
INH
INH
INH
INH
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
CPU16
REFERENCE MANUAL
Syntax
aba
abx
aby
abz
ace
aced
adca ff,x
adca ff,y
adca ff,z
adca #ii
adca gggg,x
adca gggg,y
adca gggg,z
adca hhll
adca e,x
adca e,y
adca e,z
adcb ff,x
adcb ff,y
adcb ff,z
adcb #ii
adcb gggg,x
adcb gggg,y
adcb gggg,z
adcb hhll
adcb e,x
adcb e,y
adcb e,z
adcd ff,x
adcd ff,y
adcd ff,z
adcd #jjkk
adcd gggg,x
adcd gggg,y
adcd gggg,z
adcd hhll
adcd e,x
adcd e,y
adcd e,z
Name
ADCE
ADDA
ADDB
ADDD
Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
adce #jjkk
adce gggg,x
adce gggg,y
adce gggg,z
adce hhll
adda ff,x
adda ff,y
adda ff,z
adda #ii
adda gggg,x
adda gggg,y
adda gggg,z
adda hhll
adda e,x
adda e,y
adda e,z
addb ff,x
addb ff,y
addb ff,z
addb #ii
addb gggg,x
addb gggg,y
addb gggg,z
addb hhll
addb e,x
addb e,y
addb e,z
addd ff,x
addd ff,y
addd ff,z
addd #ii
addd #jjkk
addd gggg,x
addd gggg,y
addd gggg,z
addd hhll
addd e,x
addd e,y
addd e,z
MOTOROLA
B-1
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Name
ADDE
ADE
ADX
ADY
ADZ
AEX
AEY
AEZ
AIS
AIX
AIY
AIZ
ANDA
Mode
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
INH
INH
IMM8
IMM16
IMM8
IMM16
IMM8
IMM16
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
Syntax
adde #ii
adde #jjkk
adde gggg,x
adde gggg,y
adde gggg,z
adde hhll
ade
adx
ady
adz
aex
aey
aez
ais #ii
ais #jjkk
aix #ii
aix #jjkk
aiy #ii
aiy #jjkk
aiz #ii
aiy #jjkk
anda ff,x
anda ff,y
anda ff,z
anda #ii
anda gggg,x
anda gggg,y
anda gggg,z
anda hhll
anda e,x
anda e,y
anda e,z
Name
ANDB
ANDD
ANDE
ANDP
ASL
ASLA
ASLB
ASLD
ASLE
ASLM
MOTOROLA
B-2
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
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Syntax
andb ff,x
andb ff,y
andb ff,z
andb #ii
andb gggg,x
andb gggg,y
andb gggg,z
andb hhll
andb e,x
andb e,y
andb e,z
andd ff,x
andd ff,y
andd ff,z
andd #jjkk
andd gggg,x
andd gggg,y
andd gggg,z
andd hhll
andd e,x
andd e,y
andd e,z
ande #jjkk
ande gggg,x
ande gggg,y
ande gggg,z
ande hhll
andp #jjkk
asl ff,x
asl ff,y
asl ff,z
asl gggg,x
asl gggg,y
asl gggg,z
asl hhll
asla
aslb
asld
asle
aslm
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Name
ASLW
Freescale Semiconductor, Inc...
ASR
ASRA
ASRB
ASRD
ASRE
ASRM
ASRW
BCC
BCLR
BCLRW
BCS
BEQ
BGE
BGND
BGT
BHI
Mode
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND16, X
IND16, Y
IND16, Z
EXT
REL8
REL8
REL8
INH
REL8
REL8
CPU16
REFERENCE MANUAL
Syntax
aslw gggg,x
aslw gggg,y
aslw gggg,z
aslw hhll
asr ff,x
asr ff,y
asr ff,z
asr gggg,x
asr gggg,y
asr gggg,z
asr hhll
asra
asrb
asrd
asre
asrm
asrw gggg,x
asrw gggg,y
asrw gggg,z
asrw hhll
bcc rr
bclr ff,x,#mm
bclr ff,y,#mm
bclr ff,z,#mm
bclr gggg,x,#mm
bclr gggg,y,#mm
bclr gggg,z,#mm
bclr hhll,#mm
bclrw gggg,x,#mmmm
bclrw gggg,y,#mmmm
bclrw gggg,z,#mmmm
bclrw hhll,#mmmm
bcs rr
beq rr
bge rr
bgnd
bgt rr
bhi rr
Name
BITA
BITB
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRCLR
BRN
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
REL8
REL8
REL8
REL8
REL8
REL8
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
REL8
MOTOROLA ASSEMBLER SYNTAX
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Syntax
bita ff,x
bita ff,y
bita ff,z
bita #ii
bita gggg,x
bita gggg,y
bita gggg,z
bita hhll
bita e,x
bita e,y
bita e,z
bitb ff,x
bitb ff,y
bitb ff,z
bitb #ii
bitb gggg,x
bitb gggg,y
bitb gggg,z
bitb hhll
bitb e,x
bitb e,y
bitb e,z
ble rr
bls rr
blt rr
bmi rr
bne rr
bpl rr
bra rr
brclr ff,x,#mm,rr
brclr ff,y,#mm,rr
brclr ff,z,#mm,rr
brclr gggg,x,#mm,rrrr
brclr gggg,y,#mm,rrrr
brclr gggg,z,#mm,rrrr
brclr hhll,#mm,rrrr
brn rr
MOTOROLA
B-3
Freescale Semiconductor, Inc.
Name
BRSET
Freescale Semiconductor, Inc...
BSET
BSETW
BSR
BVC
BVS
CBA
CLR
CLRA
CLRB
CLRD
CLRE
CLRM
CLRW
MOTOROLA
B-4
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND16, X
IND16, Y
IND16, Z
EXT
REL8
REL8
REL8
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
Syntax
brset ff,x,#mm,rr
brset ff,y,#mm,rr
brset ff,z,#mm,rr
brset gggg,x,#mm,rrrr
brset gggg,y,#mm,rrrr
brset gggg,z,#mm,rrrr
brset hhll,#mm,rrrr
bset ff,x,#mm
bset ff,y,#mm
bset ff,z,#mm
bset gggg,x,#mm
bset gggg,y,#mm
bset gggg,z,#mm
bset hhll,#mm
bsetw gggg,x,#mmmm
bsetw gggg,y,#mmmm
bsetw gggg,z,#mmmm
bsetw hhll,#mmmm
bsr rr
bvc rr
bvs rr
cba
clr ff,x
clr ff,y
clr ff,z
clr gggg,x
clr gggg,y
clr gggg,z
clr hhll
clra
clrb
clrd
clre
clrm
clrw gggg,x
clrw gggg,y
clrw gggg,z
clrw hhll
Name
CMPA
CMPB
COM
COMA
COMB
COMD
COME
COMW
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
cmpa ff,x
cmpa ff,y
cmpa ff,z
cmpa #ii
cmpa gggg,x
cmpa gggg,y
cmpa gggg,z
cmpa hhll
cmpa e,x
cmpa e,y
cmpa e,z
cmpb ff,x
cmpb ff,y
cmpb ff,z
cmpb #ii
cmpb gggg,x
cmpb gggg,y
cmpb gggg,z
cmpb hhll
cmpb e,x
cmpb e,y
cmpb e,z
com ff,x
com ff,y
com ff,z
com gggg,x
com gggg,y
com gggg,z
com hhll
coma
comb
comd
come
comw gggg,x
comw gggg,y
comw gggg,z
comw hhll
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Name
CPD
Freescale Semiconductor, Inc...
CPE
CPS
CPX
CPY
Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
EXT
CPU16
REFERENCE MANUAL
Syntax
cpd ff,x
cpd ff,y
cpd ff,z
cpd #jjkk
cpd gggg,x
cpd gggg,y
cpd gggg,z
cpd hhll
cpd e,x
cpd e,y
cpd e,z
cpe #jjkk
cpe gggg,x
cpe gggg,y
cpe gggg,z
cpe hhll
cps ff,x
cps ff,y
cps ff,z
cps #jjkk
cps gggg,x
cps gggg,y
cps gggg,z
cps hhll
cpx ff,x
cpx ff,y
cpx ff,z
cpx #jjkk
cpx gggg,x
cpx gggg,y
cpx gggg,z
cpx hhll
cpy ff,x
cpy ff,y
cpy ff,z
cpy #jjkk
cpy gggg,x
cpy gggg,y
cpy hhll
Name
CPZ
DAA
DEC
DECA
DECB
DECW
EDIV
EDIVS
EMUL
EMULS
EORA
Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
cpz ff,x
cpz ff,y
cpz ff,z
cpz #jjkk
cpz gggg,x
cpz gggg,y
cpz gggg,z
cpz hhll
daa
dec ff,x
dec ff,y
dec ff,z
dec gggg,x
dec gggg,y
dec gggg,z
dec hhll
deca
decb
decw gggg,x
decw gggg,y
decw gggg,z
decw hhll
ediv
edivs
emul
emuls
eora ff,x
eora ff,y
eora ff,z
eora #ii
eora gggg,x
eora gggg,y
eora gggg,z
eora hhll
eora e,x
eora e,y
eora e,z
MOTOROLA
B-5
Freescale Semiconductor, Inc.
Name
EORB
Freescale Semiconductor, Inc...
EORD
EORE
FDIV
FMULS
IDIV
INC
INCA
INCB
MOTOROLA
B-6
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
Syntax
eorb ff,x
eorb ff,y
eorb ff,z
eorb #ii
eorb gggg,x
eorb gggg,y
eorb gggg,z
eorb hhll
eorb e,x
eorb e,y
eorb e,z
eord ff,x
eord ff,y
eord ff,z
eord #jjkk
eord gggg,x
eord gggg,y
eord gggg,z
eord hhll
eord e,x
eord e,y
eord e,z
eore #jjkk
eore gggg,x
eore gggg,y
eore gggg,z
eore hhll
fdiv
fmuls
idiv
inc ff,x
inc ff,y
inc ff,z
inc gggg,x
inc gggg,y
inc gggg,z
inc hhll
inca
incb
Name
INCW
JMP
JSR
LBCC
LBCS
LBEQ
LBEV
LBGE
LBGT
LBHI
LBLE
LBLS
LBLT
LBMI
LBMV
LBNE
LBPL
LBRA
LBM
LBSR
LBVC
LBVS
Mode
IND16, X
IND16, Y
IND16, Z
EXT
EXT20
IND20, X
IND20, Y
IND20, Z
EXT20
IND20, X
IND20, Y
IND20, Z
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
REL8
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
incw gggg,x
incw gggg,y
incw gggg,z
incw hhll
jmp zb hhll
jmp zg gggg,x
jmp zg gggg,y
jmp zg gggg,z
jsr zb hhll
jsr zg gggg,x
jsr zg gggg,y
jsr zg gggg,z
lbcc rrrr
lbcs rrrr
lbeq rrrr
lbev rrrr
lbge rrrr
lbgt rrrr
lbhi rrrr
lble rrrr
lbls rrrr
lblt rrrr
lbmi rrrr
lbmv rrrr
lbne rrrr
lbpl rrrr
lbra rrrr
lbrn rrrr
lbsr rrrr
lbvc rrrr
lbvs rrrr
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Name
LDAA
Freescale Semiconductor, Inc...
LDAB
LDD
LDE
LDED
LDHI
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
EXT
EXT
Syntax
ldaa ff,x
ldaa ff,y
ldaa ff,z
ldaa #ii
ldaa gggg,x
ldaa gggg,y
ldaa gggg,z
ldaa hhll
ldaa e,x
ldaa e,y
ldaa e,z
ldab ff,x
ldab ff,y
ldab ff,z
ldab #ii
ldab gggg,x
ldab gggg,y
ldab gggg,z
ldab hhll
ldab e,x
ldab e,y
ldab e,z
ldd ff,x
ldd ff,y
ldd ff,z
ldd #jjkk
ldd gggg,x
ldd gggg,y
ldd gggg,z
ldd hhll
ldd e,x
ldd e,y
ldd e,z
lde #jjkk
lde gggg,x
lde gggg,y
lde gggg,z
lde hhll
lded hhll
ldhi hhll
Name
LDS
LDX
LDY
LDZ
LPSTOP
LSL
LSLA
LSLB
CPU16
REFERENCE MANUAL
Mode
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
lds ff,x
lds ff,y
lds ff,z
lds #jjkk
lds gggg,x
lds gggg,y
lds gggg,z
lds hhll
ldx ff,x
ldx ff,y
ldx ff,z
ldx #jjkk
ldx gggg,x
ldx gggg,y
ldx gggg,z
ldx hhll
ldy ff,x
ldy ff,y
ldy ff,z
ldy #jjkk
ldy gggg,x
ldy gggg,y
ldy gggg,z
ldy hhll
ldz ff,x
ldz ff,y
ldz ff,z
ldz #jjkk
ldz gggg,x
ldz gggg,y
ldz gggg,z
ldz hhll
lpstop
lsl ff,x
lsl ff,y
lsl ff,z
lsl gggg,x
lsl gggg,y
lsl gggg,z
lsl hhll
lsla
lslb
MOTOROLA
B-7
Freescale Semiconductor, Inc.
Name
LSLD
LSLE
LSLM
LSLW
Freescale Semiconductor, Inc...
LSR
LSRA
LSRB
LSRD
LSRE
LSRW
MAC
MOVB
MOVW
MUL
NEG
NEGA
NEGB
NEGD
NEGE
MOTOROLA
B-8
Mode
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
IMM8
IXP to EXT
EXT to IXP
EXT to EXT
IXP to EXT
EXT to IXP
EXT to EXT
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
Syntax
lsld
lsle
lslm
lslw gggg,x
lslw gggg,y
lslw gggg,z
lslw hhll
lsr ff,x
lsr ff,y
lsr ff,z
lsr gggg,x
lsr gggg,y
lsr gggg,z
lsr hhll
lsra
lsrb
lsrd
lsre
lsrw gggg,y
lsrw gggg,y
lsrw gggg,z
lsrw hhll
mac xo,yo
movb ff,x,hhll
movb hhll,ff,x
movb hhll,hhll
movw ff,x,hhll
movw hhll,ff,x
movw hhll,hhll
mul
neg ff,x
neg ff,y
neg ff,z
neg gggg,x
neg gggg,y
neg gggg,z
neg hhll
nega
negb
negd
nege
Name
NEGW
NOP
ORAA
ORAB
ORD
Mode
IND16, X
IND16, Y
IND16, Z
EXT
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
negw gggg,x
negw gggg,y
negw gggg,z
negw hhll
nop
oraa ff,x
oraa ff,y
oraa ff,z
oraa #ii
oraa gggg,x
oraa gggg,y
oraa gggg,z
oraa hhll
oraa e,x
oraa e,y
oraa e,z
orab ff,x
orab ff,y
orab ff,z
orab #ii
orab gggg,x
orab gggg,y
orab gggg,z
orab hhll
orab e,x
orab e,y
orab e,z
ord ff,x
ord ff,y
ord ff,z
ord #jjkk
ord gggg,x
ord gggg,y
ord gggg,z
ord hhll
ord e,x
ord e,y
ord e,z
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Name
ORE
ORP
PSHA
PSHB
PSHM
PSHMAC
PULA
PULB
PULM
PULMAC
RMAC
ROL
ROLA
ROLB
ROLD
ROLE
ROLW
ROR
RORA
RORB
RORD
RORE
Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
INH
INH
IMM8
INH
INH
INH
IMM8
INH
IMM8
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
CPU16
REFERENCE MANUAL
Syntax
ore #jjkk
ore gggg,x
ore gggg,y
ore gggg,z
ore hhll
orp #jjkk
psha
pshb
pshm d,e,x,y,z,k,ccr
pshmac
pula
pulb
pulm d,e,x,y,z,k,ccr
pulmac
rmac xo,yo
rol ff,x
rol ff,y
rol ff,z
rol gggg,x
rol gggg,y
rol gggg,z
rol hhll
rola
rolb
rold
role
rolw gggg,x
rolw gggg,y
rolw gggg,z
rolw hhll
ror ff,x
ror ff,y
ror ff,z
ror gggg,x
ror gggg,y
ror gggg,z
ror hhll
rora
rorb
rord
rore
Name
RORW
RTI
RTS
SBA
SBCA
SBCB
SBCD
Mode
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
rorw gggg,x
rorw gggg,y
rorw gggg.z
rorw hhll
rti
rts
sba
sbca ff,x
sbca ff,y
sbca ff,z
sbca #ii
sbca gggg,x
sbca gggg,y
sbca gggg,z
sbca hhll
sbca e,x
sbca e,y
sbca e,z
sbcb ff,x
sbcb ff,y
sbcb ff,z
sbcb #ii
sbcb gggg,x
sbcb gggg,y
sbcb gggg,z
sbcb hhll
sbcb e,x
sbcb e,y
sbcb e,z
sbcd ff,x
sbcd ff,y
sbcd ff,z
sbcd #jjkk
sbcd gggg,x
sbcd gggg,y
sbcd gggg,z
sbcd hhll
sbcd e,x
sbcd e,y
sbcd e,z
MOTOROLA
B-9
Freescale Semiconductor, Inc.
Name
SBCE
Freescale Semiconductor, Inc...
SDE
STAA
STAB
STD
STE
STED
MOTOROLA
B-10
Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
EXT
Syntax
sbce #jjkk
sbce gggg,x
sbce gggg,y
sbce gggg,z
sbce hhll
sde
staa ff,x
staa ff,y
staa ff,z
staa gggg,x
staa gggg,y
staa gggg,z
staa hhll
staa e,x
staa e,y
staa e,z
stab ff,x
stab ff,y
stab ff,z
stab gggg,x
stab gggg,y
stab gggg,z
stab hhll
stab e,x
stab e,y
stab e,z
std ff,x
std ff,y
std ff,z
std gggg,x
std gggg,y
std gggg,z
std hhll
std e,x
std e,y
std e,z
ste gggg,x
ste gggg,y
ste gggg,z
ste hhll
sted hhll
Name
STS
STX
STY
STZ
SUBA
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
sts ff,x
sts ff,y
sts ff,z
sts gggg,x
sts gggg,y
sts gggg,z
sts hhll
stx ff,x
stx ff,y
stx ff,z
stx gggg,x
stx gggg,y
stx gggg,z
stx hhll
sty ff,x
sty ff,y
sty ff,z
sty gggg,x
sty gggg,y
sty gggg,z
sty hhll
stz ff,x
stz ff,y
stz ff,z
stz gggg,x
stz gggg,y
stz gggg,z
stz hhll
suba ff,x
suba ff,y
suba ff,z
suba #ii
suba gggg,x
suba gggg,y
suba gggg,z
suba hhll
suba e,x
suba e,y
suba e,z
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Name
SUBB
Freescale Semiconductor, Inc...
SUBD
SUBE
SWI
SXT
TAB
TAP
TBA
TBEK
TBSK
TBXK
TBYK
TBZK
TDE
TDMSK
TDP
TED
TEDM
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
CPU16
REFERENCE MANUAL
Syntax
subb ff,x
subb ff,y
subb ff,z
subb #ii
subb gggg,x
subb gggg,y
subb gggg,z
subb hhll
subb e,x
subb e,y
subb e,z
subd ff,x
subd ff,y
subd ff,z
subd #jjkk
subd gggg,x
subd gggg,y
subd gggg,z
subd hhll
subd e,x
subd e,y
subd e,z
sube #jjkk
sube gggg,x
sube gggg,y
sube gggg,z
sube hhll
swi
sxt
tab
tap
tba
tbek
tbsk
tbxk
tbyk
tbzk
tde
tdmsk
tdp
ted
tedm
Name
TEKB
TEM
TMER
TMET
TMXED
TPA
TPD
TSKB
TST
TSTA
TSTB
TSTD
TSTE
TSTW
TSX
TSY
TSZ
TXKB
TXS
TXY
TXZ
TYKB
TYS
TYX
TYZ
TZKB
TZS
TZX
TZY
WAI
XGAB
XGDE
XGDX
Mode
INH
INH
INH
INH
INH
INH
INH
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
Syntax
tekb
tem
tmer
tmet
tmxed
tpa
tpd
tskb
tst ff,x
tst ff,y
tst ff,z
tst gggg,x
tst gggg,y
tst gggg,z
tst hhll
tsta
tstb
tstd
tste
tstw ff,x
tstw ff,y
tstw ff,z
tstw hhll
tsx
tsy
tsz
txkb
txs
txy
txz
tykb
tys
tyx
tyz
tzkb
tzs
tzx
tzy
wai
xgab
xgde
xgdx
MOTOROLA
B-11
Freescale Semiconductor, Inc.
Mode
INH
INH
INH
INH
INH
Syntax
xgdy
xgdz
xgex
xgey
xgez
Freescale Semiconductor, Inc...
Name
XGDY
XGDZ
XGEX
XGEY
XGEZ
MOTOROLA
B-12
MOTOROLA ASSEMBLER SYNTAX
For More Information On This Product,
Go to: www.freescale.com
CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
INDEX
Freescale Semiconductor, Inc...
–A–
ABA 5-3, 5-4, 6-3
ABX 6-4
ABY 6-5
ABZ 6-6
Accumulator 3-2
A 2-1, 3-2
AM 11-1
B 2-1, 3-2
D 2-1, 3-2
E 2-1, 3-2
M 2-1
Overflow 3-4
MAC 11-3
Overflow 11-3
ACE 6-7, 11-4, 11-9
ACED 6-8, 11-4, 11-8
ADCA 5-3, 5-4, 6-9
ADCB 5-3, 5-4, 6-10
ADCD 5-3, 5-4, 6-11
ADCE 5-3, 5-4, 6-12
ADDA 5-3, 5-4, 6-13
ADDB 5-3, 5-4, 6-14
ADDD 5-3, 5-4, 6-15
ADDE 5-3, 5-4, 6-16
ADDR[15:0] 4-4
ADDR[19:0] 3-10
ADDR[19:16] 4-4
Address strobe 3-10
Addressing
Modes 2-3, 4-3
Extended 2-1, A-14
Indexed A-14
Post-Modified Index A-14
ADE 5-3, 5-4, 6-17
ADVANCE 10-3
ADX 6-18
ADY 6-19
ADZ 6-20
AEX 6-21
AEY 6-22
AEZ 6-23
AIS 6-24
AIX 6-25
AIY 6-26
AIZ 6-27
Alignment
Operand 3-12
AM 11-1
ANDA 5-8, 6-28
CPU16
REFERENCE MANUAL
ANDB 5-8, 6-29
ANDD 5-8, 6-30
ANDE 5-8, 6-31
ANDP 5-21, 5-23, 6-32, 9-14
ASL 5-8, 6-33
ASLA 6-34
ASLB 6-35
ASLD 6-36
ASLE 6-37
ASLM 6-38, 11-4, 11-9
ASLW 6-39
ASR 6-40
ASRA 6-41
ASRB 6-42
ASRD 6-43
ASRE 6-44
ASRM 6-45, 11-9
ASRW 6-46
Assembler syntax 6-1, B-1
AVEC 3-10
–B–
BCC 6-47
BCD 5-3, 5-5
BCLR 5-8, 6-48
BCLRW 5-8, 6-49
BCS 6-50
BDM 5-23, 10-8
Connection 10-37
BEQ 6-51
BERR 3-10, 9-2, 9-8, 9-11
BGE 6-52
BGND 5-23, 6-53, 9-2, 9-15, 10-11
BGT 6-54
BHI 6-55
BHS A-7
BITA 5-8, 6-56
BITB 5-8, 6-57
BKPT 9-2, 9-8, 9-12
BLE 6-58
BLO A-7
BLS 6-59
BLT 6-60
BMI 6-61
BNE 6-62
BPL 6-63
BRA 5-16, 6-64
BRCLR 6-65
Breakpoints 10-5, 10-11
BRN 5-23, 6-66
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
I-1
Freescale Semiconductor, Inc.
Saturation mode 2-2
Stop disable 2-2
CPD 5-6, 6-89
CPE 5-6, 6-90
CPS 6-91
CPX 6-92
CPY 6-93
CPZ 6-94
Cycle time 8-5
Freescale Semiconductor, Inc...
BRSET 6-67
BSET 5-8, 6-68
BSETW 5-8, 6-69
BSR 5-16, 6-70, 7-7, A-11
Bus cycle 8-1, 8-2
Bus cycles
Termination 3-10
Bus error 3-10
Bus fault 10-11
Double 10-11
Bus signals
Address bus 3-10
Data bus 3-10
Bus sizing
Dynamic 3-11, 8-1
BVC 6-71
BVS 6-72
–D–
–C–
CBA 5-6, 6-73
CCR 2-1, 2-2, 3-4, 5-2, 5-5, 11-5, A-2
Manipulation 5-2
CCR bits
C 2-2, 3-4
EV 2-2
H 2-2
IP 2-2, 3-4, 8-4
MV 2-2
N 2-2, 3-4
PK 2-2, 3-5
S 2-2, 3-4, 8-4
SM 2-2, 3-4
V 2-2, 3-4
Z 2-2, 3-4
Change of flow 7-6
CLC A-7
CLI A-8
CLR 5-7, 6-74
CLRA 5-7, 6-75
CLRB 5-7, 6-76
CLRD 5-7, 6-77
CLRE 5-7, 6-78
CLRM 6-79, 11-9
CLRW 5-7, 6-80
CLV A-8
CMPA 5-6, 6-81
CMPB 5-6, 6-82
COM 5-7, 6-83
COMA 5-7, 6-84
COMB 5-7, 6-85
COMD 5-7, 6-86
COME 5-7, 6-87
Comparison
M68HC11 vs CPU16 A-1
COMW 5-7, 6-88
Condition Code Register A-2
Connection
BDM 10-37
Control bit
MOTOROLA
I-2
DAA 5-5, 6-95, 6-96
Data
Types 4-1
Binary coded decimal 4-1
Negative 4-1
Signed 4-1
Data saturation 11-5
Data strobe 3-10
Data transfer 3-11
DATA[15:0] 3-10
Debug 10-8
DEC 5-7, 6-97
DECA 5-7, 6-98
DECB 5-7, 6-99
DECW 5-7, 6-100
DES A-8
Development 10-16
DEX A-8
DEY A-9
DSACK0 3-10
DSACK1 3-10
DSCLK 10-14
DSP 11-1
–E–
EBI 3-8
EDIV 5-6, 6-101, 9-15
EDIVS 5-6, 6-102, 9-15
EK 2-1
EMUL 5-6, 6-103
Emulation 10-9
EMULS 5-6, 6-104
EORA 5-8, 6-105
EORB 5-8, 6-106
EORD 5-8, 6-107
EORE 5-8, 6-108
EV 3-4
Exception
Asynchronous 9-9
Definition 9-1
External 9-2
Internal 9-2
Multiple 9-8
Processing 9-3, 10-4
Stack frame 9-2
Synchronous 9-14
Vector 9-1
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CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Execution
Model A-4
Process 7-4, A-5
Unit 7-3
Extension
Address 3-5
Bit overflow 11-4
Fields 3-5, 3-6
Registers 3-5
Extension bit
Overflow flag 3-4
Extension field 2-1, 3-6
Extended addressing 2-1
Modifying 3-6
Program counter 2-1, 2-2, 3-5
SK 3-3
Stack pointer 2-1
Stacking values 3-6
–F–
FDIV 5-6, 6-109
FETCH 10-3
FMULS 5-6, 6-110, 11-8
–G–
GO 10-35
–H–
HALT 3-10
HR 2-1, 11-1
–I–
IDIV 5-6, 6-111
IMB 3-8, 5-1, 10-5
IMM16 4-4
IMM8 4-4
Implementation
CPU16 A-12
M68HC11 CPU A-12
INC 5-7, 6-112
INCA 5-7, 6-113
INCB 5-7, 6-114
INCW 5-7, 6-115
Indicator
Accumulator M overflow 3-4
AM extended overflow 2-2
AM overflow 2-2
Carry/borrow 2-2
H 3-4
Half carry 2-2, 3-4
MV 3-4
Negative 2-2
Two’s complement overflow 2-2
Zero 2-2
INS A-9
CPU16
REFERENCE MANUAL
Instruction
Glossary 6-1
Set
Comparison 5-23
Summary 6-270
Instruction format 2-3
Instructions 1-1
Address Extension 5-18
Arithmetic 5-1
Background 9-15
BGND 9-15
Binary coded decimal 5-5
Bit condition 5-15
Bit manipulation 11-9
Bit test 5-8
Boolean logic 5-8
Branch 3-7, 7-6, 11-10, A-5
Clear 5-7
Compare 5-5
Complement 5-7
Condition Code 5-21
Data movement 5-1
Decrement 5-7
Digital signal processing 5-1, 5-21
Division 5-1
DSP 11-5
Exchange 5-3
Format 7-1, A-4
Functionally equivalent A-7
Illegal 9-14
Increment 5-7
Indexing 5-18
Initialization 11-5
Interrupt 5-17
Jump 3-7, 5-16, 7-6, A-5
Load 5-1
Logic 5-1
Long branch 5-13
MAC 11-5
Manipulation 5-8
Mathematic 5-3
Move 5-2, 8-4
Multiplication 5-1
Multiply and accumulate 8-5, 11-7
Negate 5-7
Operand access 8-2
Pipeline 7-2, 10-1, A-4
Pipelining 7-1
Program access 8-2
Program control 5-11
Program flow changes 7-1
Read-modify-write 8-2
Regular 8-2
RMAC 11-5
Rotate 5-8
Set 5-1
Shift 5-8
Short branch 5-12
Signed 5-1
Special purpose 5-1
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MOTOROLA
I-3
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Stack
Manipulation 8-4
Operations 5-20
Pointer 5-20
Stacking 11-10
Stop 5-22, 8-4
Store 5-2
Subroutine 5-16, 7-6, A-6
TDMSK 11-5
Test 5-5
Timing 8-1
TMER 11-6
TMET 11-6
TMXED 11-6
Transfer 5-2, 11-6
Unimplemented A-14
Unsigned 5-1
Wait 5-22, 8-4
Interrupt 9-13, A-6
Priority 2-2, 9-13, A-7
Field 3-4
Invalid
Signal 10-4
INX A-9
INY A-9
IP 2-2
IPIPE0 7-3, 10-1
IPIPE1 7-3, 10-1
IR 2-1, 11-1
IX 3-3
IY 3-3
IZ 3-3
–J–
JMP 5-16, 6-116
JSR 5-16, 6-117, 7-7, A-11
–K–
K 2-1
–L–
LBCC 6-118
LBCS 6-119
LBEQ 6-120
LBEV 6-121, 11-10
LBGE 6-122
LBGT 6-123
LBHI 6-124
LBLE 6-125
LBLS 6-126
LBLT 6-127
LBMI 6-128
LBMV 6-129, 11-10
LBNE 6-130
LBPL 6-131
LBRA 5-16, 6-132
LBRN 6-133
MOTOROLA
I-4
LBSR 5-16, 6-134, 7-7
LBVC 6-135
LBVS 6-136
LDAA 5-2, 6-137
LDAB 5-2, 6-138
LDD 5-2, 6-139, 8-6
LDE 5-2, 6-140
LDED 5-2, 6-141
LDHI 6-142, 11-5
LDS 6-143
LDX 6-144
LDY 6-145
LDZ 6-146
LPSTOP 5-22, 6-147, 8-4, A-11
LSL 5-8
LSR 6-148
LSRA 6-149
LSRB 6-150
LSRD 6-151
LSRE 6-152
LSRW 6-153
–M–
MAC 6-154, 6-155, 11-1, 11-4
Memory
Organization 4-2
Microsequencer 7-3
Modes
Accumulator Offset 4-5
Background 5-23
Direct 4-6
Extended 4-5
Immediate 4-4
Indexed 4-5, 4-6
Inherent 4-5
Post-modified index 4-5
Relative 4-5
Saturate 3-4
Modulo addressing 2-1, 11-2
MOVB 5-2, 6-156
MOVW 5-2, 6-157
MUL 5-6, 6-158
Multiplexing 10-2
Multiply and accumulate
Multiplicand register 2-1
Multiplier register 2-1
Sign latch 2-1
–N–
NEG 5-7, 6-159, 8-7
NEGA 5-7, 6-160
NEGB 5-7, 6-161
NEGD 5-7, 6-162
NEGE 5-7, 6-163
NEGW 5-7, 6-164
NOP 6-165, 10-36
NULL 10-3
Null Operations 5-23
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CPU16
REFERENCE MANUAL
Freescale Semiconductor, Inc.
–O–
ROL 6-181
ROLA 6-182
ROLB 6-183
ROLD 6-184
ROLE 6-185
ROLW 6-186
ROR 6-187
RORA 6-188
RORB 6-189
RORD 6-190
RORE 6-191
RORW 6-192
Routine
Interrupt 7-7
RPCSP 10-29
RPMEM 10-19, 10-20, 10-33
RREGM 10-21, 10-22
RTI 5-17, 6-193, 7-7, 9-15, A-12
RTS 5-17, 6-194, 7-7, A-13
Opcode
Deterministic 10-1
Tracking 10-1
Operands
Byte order 3-11
Multiplicand 11-2
Multiplier 11-2
ORAA 5-8, 6-166
ORAB 5-8, 6-167
ORD 5-8, 6-168
ORE 5-8, 6-169
ORP 5-21, 5-23, 6-170, 9-14
Freescale Semiconductor, Inc...
–P–
PC 2-1
Pipeline 7-3, 10-1, A-4
PK 2-1, 2-2, 3-7
Program counter 2-1
extension field 2-1
Program flow
Changes A-5
PSHA 6-171, A-12
PSHB 6-172, A-12
PSHM 3-6, 6-173
PSHMAC 6-174, 11-10
PSHX A-9
PSHY A-10
PULA 6-175, A-12
PULB 6-176, A-12
PULM 3-6, 6-177
PULMAC 6-178, 11-10
PULX A-10
PULY A-10
–S–
–R–
R/W 3-10
RDMAC 10-25, 10-26
RDMEM 10-20, 10-31
Register
Notation 2-1
Registers 11-5
Address extension 2-1, 3-5
Concatenated 3-3
Condition code 2-1, 3-4
Condition code bits 2-2
Index 2-1, 3-3
MAC 3-5
Model 3-1
Multiply and Accumulate 2-1, 3-5
Result
Carry flag 3-4
Negative 3-4
Overflow flag 3-4
Zero 3-4
RESET 9-2, 9-8, 9-9
RMAC 6-179, 6-180, 11-7
CPU16
REFERENCE MANUAL
Saturate mode 3-4
SBA 5-4, 6-195
SBCA 5-4, 6-196
SBCB 5-4, 6-197
SBCD 5-4, 6-198
SBCE 5-4
SDE 5-4
SEC A-10
SEI A-11
SEV A-11
Sign
Bit overflow 11-4
SIZ0 3-9
SIZ1 3-9
Size acknowledge 3-11
SK 2-1
SL 2-1
SM 2-2
SP 2-1
SPI 10-13
STAA 5-2, 6-199
STAB 5-2, 6-200
Stack
Frame A-7
Implementation 3-3
Manipulation 8-4
Pointer 2-1
Pointer (SP) 3-3
START 10-3
State Signals 10-3
STD 5-2, 6-201
STE 5-2, 6-202
STED 5-2, 6-203, 8-8
STOP 3-4, A-11
Stop Enable 3-4
STS 6-204
STX 6-205
STY 6-206
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MOTOROLA
I-5
Freescale Semiconductor, Inc.
STZ 6-207
SUBA 5-4, 6-208
SUBB 5-4, 6-209
SUBD 5-4, 6-210
SUBE 5-4, 6-211
Subroutines A-6
SWI 5-17, 6-212, 7-7, 9-2, 9-15, A-12
SXT 6-213
Freescale Semiconductor, Inc...
–T–
TAB 5-3, 6-214
TAP 5-21, 5-23, 6-215, A-12
TBA 5-3, 6-216
TBEK 6-217
TBSK 6-218
TBXK 6-219
TBYK 6-220
TBZK 6-221
TDE 5-3, 6-222
TDMSK 6-223, 11-5
TDP 5-21, 5-23, 6-224, 9-14
TED 5-3, 6-225
TEDM 6-226, 11-5
TEKB 3-6, 6-227
TEM 6-228
TMER 6-229, 11-4, 11-6
TMET 6-230, 11-6
TMXED 6-231, 11-6
TPA 6-232, A-13
TPD 6-233
TSKB 3-6, 6-234
TST 5-6, 6-235
TSTA 5-6, 6-236
TSTB 5-6, 6-237
TSTD 5-6, 6-238
TSTE 5-6, 6-239
TSTW 5-6, 6-240
TSX 3-6, 6-241, A-13
TSY 3-6, 6-242, A-13
TSZ 3-6, 6-243
TXKB 3-6, 6-244
TXS 3-6, 6-245, A-14
TXY 3-6, 6-246
TXZ 3-6, 6-247
TYKB 3-6, 6-248
TYS 3-6, 6-249, A-14
TYX 3-6, 6-250
TYZ 3-6, 6-251
TZKB 3-6, 6-252
TZS 3-6, 6-253
TZX 3-6, 6-254
TZY 3-6, 6-255
WREGM 10-23, 10-24
WRMAC 10-27, 10-28
–X–
X 2-1
X mask 2-1
XGAB 5-3, 6-257
XGDE 5-3, 6-258
XGDX 6-259
XGDY 6-260
XGDZ 6-261
XGEX 6-262
XGEY 6-263
XGEZ 6-264
XK 2-1, 3-3
XMSK 2-1, 11-1
–Y–
Y 2-1
Y mask 2-1
YK 2-1, 3-3
YMSK 2-1, 11-1
–Z–
Z 2-1, 3-4
ZK 2-1, 3-3
–W–
WAI 5-23, 6-256, A-13
WDMEM 10-20, 10-32
WPCSP 10-30
WPMEM 10-20, 10-34
MOTOROLA
I-6
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CPU16
REFERENCE MANUAL