S12CPUV2

S12CPUV2
Reference Manual
HCS12
Microcontrollers
S12CPUV2
Rev. 4.0
03/2006
freescale.com
S12CPUV2
Reference Manual
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The following revision history table summarizes changes contained in this document.
Revision History
Revision
Number
Date
3.0
April, 2002
4.0
March, 2006
Summary of Changes
Incorporated information covering HCS12 Family of 16-bit MCUs throughout the book.
Reformatted to Freescale publication standards.
Corrected mistake in ANDCC/TAP descriptions (Instruction Glossary).
Corrected mistake in MEM description (Instruction Glossary).
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© Freescale Semiconductor, Inc., 2005. All rights reserved.
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Reference Manual — S12CPUV2
List of Sections
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Section 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Section 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Section 3. Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Section 4. Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Section 5. Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . 55
Section 6. Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Section 7. Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . 311
Section 8. Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Section 9. Fuzzy Logic Support. . . . . . . . . . . . . . . . . . . . . . . . . . 337
Appendix A. Instruction Reference . . . . . . . . . . . . . . . . . . . . . . . 375
Appendix B. M68HC11 to CPU12 Upgrade Path. . . . . . . . . . . . . 403
Appendix C. High-Level Language Support . . . . . . . . . . . . . . . . 425
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
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Reference Manual — S12CPUV2
Table of Contents
Section 1. Introduction
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3
Symbols and Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.1
Abbreviations for System Resources . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.2
Memory and Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3.3
Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.3.4
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Section 2. Overview
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1
Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.2
Index Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.5.1
S Control Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2.5.2
X Mask Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2.5.3
H Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2.5.4
I Mask Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2.5.5
N Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2.5.6
Z Status Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2.5.7
V Status Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2.5.8
C Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.5
Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
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Section 3. Addressing Modes
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2
Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.3
Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.4
Inherent Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.5
Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.6
Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.7
Extended Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.8
Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.9
Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.9.1
5-Bit Constant Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . . .37
3.9.2
9-Bit Constant Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . . .37
3.9.3
16-Bit Constant Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . .38
3.9.4
16-Bit Constant Indirect Indexed Addressing . . . . . . . . . . . . . . . . . . . .38
3.9.5
Auto Pre/Post Decrement/Increment Indexed Addressing . . . . . . . . . .39
3.9.6
Accumulator Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . .40
3.9.7
Accumulator D Indirect Indexed Addressing . . . . . . . . . . . . . . . . . . . .41
3.10 Instructions Using Multiple Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.10.1 Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.10.2 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.11
Addressing More than 64 Kbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 4. Instruction Queue
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2
Queue Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2.1
Original M68HC12 Queue Implementation. . . . . . . . . . . . . . . . . . . . . .48
4.2.2
HCS12 Queue Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.3
Data Movement in the Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.3.1
No Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.2
Latch Data from Bus (Applies Only to the M68HC12 Queue) . . . . . . .49
4.3.3
Advance and Load from Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.4
Advance and Load from Buffer (Applies Only to M68HC12 Queue) . .49
4.4
Changes in Execution Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.4.1
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.4.2
Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.4.3
Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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4.4.3.1
4.4.3.2
4.4.3.3
4.4.3.4
4.4.4
Short Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Long Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Bit Condition Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Loop Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 5. Instruction Set Overview
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.2
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.3
Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4
Transfer and Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.5
Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.6
Addition and Subtraction Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.7
Binary-Coded Decimal Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.8
Decrement and Increment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.9
Compare and Test Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.10
Boolean Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.11
Clear, Complement, and Negate Instructions . . . . . . . . . . . . . . . . . . . . . .63
5.12
Multiplication and Division Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.13
Bit Test and Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.14
Shift and Rotate Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.15 Fuzzy Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.15.1 Fuzzy Logic Membership Instruction . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.15.2 Fuzzy Logic Rule Evaluation Instructions. . . . . . . . . . . . . . . . . . . . . . .67
5.15.3 Fuzzy Logic Weighted Average Instruction . . . . . . . . . . . . . . . . . . . . .68
5.16
Maximum and Minimum Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
5.17
Multiply and Accumulate Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.18
Table Interpolation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.19 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.19.1 Short Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.19.2 Long Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.19.3 Bit Condition Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.20
Loop Primitive Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.21
Jump and Subroutine Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
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5.22
Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.23
Index Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.24
Stacking Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.25
Pointer and Index Calculation Instructions . . . . . . . . . . . . . . . . . . . . . . . .83
5.26
Condition Code Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.27
Stop and Wait Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.28
Background Mode and Null Operations . . . . . . . . . . . . . . . . . . . . . . . . . .86
Section 6. Instruction Glossary
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.2
Glossary Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.3
Condition Code Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.4
Object Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.5
Source Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.6
Cycle-by-Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.7
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Section 7. Exception Processing
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
7.2
Types of Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
7.3
Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
7.4
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
7.4.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.4.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.4.3
COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.4.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
7.5.1
Non-Maskable Interrupt Request (XIRQ) . . . . . . . . . . . . . . . . . . . . . .315
7.5.2
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
7.5.3
Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
7.5.4
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
7.5.5
Return-from-Interrupt Instruction (RTI) . . . . . . . . . . . . . . . . . . . . . . . .317
7.6
Unimplemented Opcode Trap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
7.7
Software Interrupt Instruction (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
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Exception Processing Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
7.8.1
Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
7.8.2
Reset Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
7.8.3
Interrupt and Unimplemented Opcode Trap Exception Processing . .320
Section 8. Instruction Queue
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
8.2
External Reconstruction of the Queue . . . . . . . . . . . . . . . . . . . . . . . . . .323
8.3
Instruction Queue Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
8.3.1
HCS12 Timing Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
8.3.2
M68HC12 Timing Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
8.3.3
Null (Code 0:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
8.3.4
LAT — Latch Data from Bus (Code 0:1). . . . . . . . . . . . . . . . . . . . . . .327
8.3.5
ALD — Advance and Load from Data Bus (Code 1:0) . . . . . . . . . . . .327
8.3.6
ALL — Advance and Load from Latch (Code 1:1) . . . . . . . . . . . . . . .327
8.3.7
INT — Interrupt Sequence Start (Code 0:1) . . . . . . . . . . . . . . . . . . . .327
8.3.8
SEV — Start Instruction on Even Address (Code 1:0) . . . . . . . . . . . .328
8.3.9
SOD — Start Instruction on Odd Address (Code 1:1) . . . . . . . . . . . .328
8.4
Queue Reconstruction (for HCS12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
8.4.1
Queue Reconstruction Registers (for HCS12) . . . . . . . . . . . . . . . . . .329
8.4.1.1
fetch_add Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.1.2
st1_add, st1_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.1.3
st2_add, st2_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.1.4
st3_add, st3_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.2
Reconstruction Algorithm (for HCS12) . . . . . . . . . . . . . . . . . . . . . . . .330
8.5
Queue Reconstruction (for M68HC12) . . . . . . . . . . . . . . . . . . . . . . . . . .331
8.5.1
Queue Reconstruction Registers (for M68HC12). . . . . . . . . . . . . . . .331
8.5.1.1
in_add, in_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.1.2
fetch_add, fetch_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.1.3
st1_add, st1_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.1.4
st2_add, st2_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.2
Reconstruction Algorithm (for M68HC12). . . . . . . . . . . . . . . . . . . . . .332
8.5.2.1
LAT Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
8.5.2.2
ALD Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
8.5.2.3
ALL Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
8.6
Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
Section 9. Fuzzy Logic Support
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9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
9.2
Fuzzy Logic Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
9.2.1
Fuzzification (MEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
9.2.2
Rule Evaluation (REV and REVW). . . . . . . . . . . . . . . . . . . . . . . . . . .342
9.2.3
Defuzzification (WAV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
9.3
Example Inference Kernel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
9.4
MEM Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
9.4.1
Membership Function Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
9.4.2
Abnormal Membership Function Definitions. . . . . . . . . . . . . . . . . . . .349
9.4.2.1
Abnormal Membership Function Case 1 . . . . . . . . . . . . . . . . . . . .351
9.4.2.2
Abnormal Membership Function Case 2 . . . . . . . . . . . . . . . . . . . .352
9.4.2.3
Abnormal Membership Function Case 3 . . . . . . . . . . . . . . . . . . . .352
9.5
REV and REVW Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
9.5.1
Unweighted Rule Evaluation (REV) . . . . . . . . . . . . . . . . . . . . . . . . . .353
9.5.1.1
Set Up Prior to Executing REV. . . . . . . . . . . . . . . . . . . . . . . . . . . .353
9.5.1.2
Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
9.5.1.3
Cycle-by-Cycle Details for REV . . . . . . . . . . . . . . . . . . . . . . . . . . .355
9.5.2
Weighted Rule Evaluation (REVW) . . . . . . . . . . . . . . . . . . . . . . . . . .359
9.5.2.1
Set Up Prior to Executing REVW . . . . . . . . . . . . . . . . . . . . . . . . . .359
9.5.2.2
Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
9.5.2.3
Cycle-by-Cycle Details for REVW . . . . . . . . . . . . . . . . . . . . . . . . .361
9.6
WAV Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
9.6.1
Set Up Prior to Executing WAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
9.6.2
WAV Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
9.6.3
Cycle-by-Cycle Details for WAV and wavr . . . . . . . . . . . . . . . . . . . . .365
9.7
Custom Fuzzy Logic Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
9.7.1
Fuzzification Variations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
9.7.2
Rule Evaluation Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
9.7.3
Defuzzification Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
Appendix A. Instruction Reference
A.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
A.2
Stack and Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
A.3
Interrupt Vector Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
A.4
Notation Used in Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . .377
A.5
Hexadecimal to Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .402
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A.6
Decimal to Hexadecimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .402
Appendix B. M68HC11 to CPU12 Upgrade Path
B.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
B.2
CPU12 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
B.3
Source Code Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
B.4
Programmer’s Model and Stacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
B.5 True 16-Bit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
B.5.1
Bus Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
B.5.2
Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
B.5.3
Stack Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
B.6 Improved Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
B.6.1
Constant Offset Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
B.6.2
Auto-Increment Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
B.6.3
Accumulator Offset Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
B.6.4
Indirect Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
B.7 Improved Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
B.7.1
Reduced Cycle Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
B.7.2
Fast Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
B.7.3
Code Size Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
B.8 Additional Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
B.8.1
Memory-to-Memory Moves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
B.8.2
Universal Transfer and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . .420
B.8.3
Loop Construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
B.8.4
Long Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
B.8.5
Minimum and Maximum Instructions . . . . . . . . . . . . . . . . . . . . . . . . .421
B.8.6
Fuzzy Logic Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
B.8.7
Table Lookup and Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
B.8.8
Extended Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
B.8.9
Push and Pull D and CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
B.8.10 Compare SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
B.8.11 Support for Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
Appendix C. High-Level Language Support
C.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
C.2
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
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C.3 Parameters and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
C.3.1
Register Pushes and Pulls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
C.3.2
Allocating and Deallocating Stack Space . . . . . . . . . . . . . . . . . . . . . .427
C.3.3
Frame Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
C.4
Increment and Decrement Operators . . . . . . . . . . . . . . . . . . . . . . . . . . .428
C.5
Higher Math Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
C.6
Conditional If Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
C.7
Case and Switch Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
C.8
Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
C.9
Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
C.10 Instruction Set Orthogonality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
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Reference Manual — S12CPUV2
Section 1. Introduction
1.1 Introduction
This manual describes the features and operation of the core (central
processing unit, or CPU, and development support functions) used in all
HCS12 microcontrollers. For reference, information is provided for the
M68HC12.
1.2 Features
The CPU12 is a high-speed, 16-bit processing unit that has a programming
model identical to that of the industry standard M68HC11 central processor
unit (CPU). The CPU12 instruction set is a proper superset of the M68HC11
instruction set, and M68HC11 source code is accepted by CPU12
assemblers with no changes.
•
Full 16-bit data paths supports efficient arithmetic operation and
high-speed math execution
•
Supports instructions with odd byte counts, including many
single-byte instructions. This allows much more efficient use of ROM
space.
•
An instruction queue buffers program information so the CPU has
immediate access to at least three bytes of machine code at the start
of every instruction.
•
Extensive set of indexed addressing capabilities, including:
– Using the stack pointer as an indexing register in all indexed
operations
– Using the program counter as an indexing register in all but auto
increment/decrement mode
– Accumulator offsets using A, B, or D accumulators
– Automatic index predecrement, preincrement, postdecrement,
and postincrement (by –8 to +8)
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1.3 Symbols and Notation
The symbols and notation shown here are used throughout the manual.
More specialized notation that applies only to the instruction glossary or
instruction set summary are described at the beginning of those sections.
1.3.1 Abbreviations for System Resources
A
B
D
X
Y
SP
PC
CCR
—
—
—
—
—
—
—
—
Accumulator A
Accumulator B
Double accumulator D (A : B)
Index register X
Index register Y
Stack pointer
Program counter
Condition code register
S — STOP instruction control bit
X — Non-maskable interrupt control bit
H — Half-carry status bit
I — Maskable interrupt control bit
N — Negative status bit
Z — Zero status bit
V — Two’s complement overflow status bit
C — Carry/Borrow status bit
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1.3.2 Memory and Addressing
M
M : M+1
M~M+3
M(Y)~M(Y+3)
M(X)
M(SP)
M(Y+3)
PPAGE
Page
XH
XL
()
$
%
— 8-bit memory location pointed to by the effective
address of the instruction
— 16-bit memory location. Consists of the contents of the
location pointed to by the effective address
concatenated with the contents of the location at the
next higher memory address. The most significant byte
is at location M.
— 32-bit memory location. Consists of the contents of the
effective address of the instruction concatenated with
the contents of the next three higher memory locations.
The most significant byte is at location M or M(Y).
— Memory locations pointed to by index register X
— Memory locations pointed to by the stack pointer
— Memory locations pointed to by index register Y plus 3
— Program overlay page (bank) number for extended
memory (>64 Kbytes).
— Program overlay page
— High-order byte
— Low-order byte
— Content of register or memory location
— Hexadecimal value
— Binary value
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1.3.3 Operators
+
–
•
+
⊕
×
÷
M
—
—
—
—
—
—
—
—
Addition
Subtraction
Logical AND
Logical OR (inclusive)
Logical exclusive OR
Multiplication
Division
Negation. One’s complement (invert each bit of M)
: — Concatenate
Example: A : B means the 16-bit value formed by concatenating 8-bit accumulator A with 8-bit accumulator B.
A is in the high-order position.
⇒ — Transfer
Example: (A) ⇒ M means the content of accumulator A is
transferred to memory location M.
⇔ — Exchange
Example: D ⇔ X means exchange the contents of D with
those of X.
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1.3.4 Definitions
Logic level 1 is the voltage that corresponds to the true (1) state.
Logic level 0 is the voltage that corresponds to the false (0) state.
Set refers specifically to establishing logic level 1 on a bit or bits.
Cleared refers specifically to establishing logic level 0 on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal
changes from logic level 1 to logic level 0 when asserted, and an active
high signal changes from logic level 0 to logic level 1.
Negated means that an asserted signal changes logic state. An active low
signal changes from logic level 0 to logic level 1 when negated, and an
active high signal changes from logic level 1 to logic level 0.
ADDR is the mnemonic for address bus.
DATA is the mnemonic for data bus.
LSB means least significant bit or bits.
MSB means most significant bit or bits.
LSW means least significant word or words.
MSW means most significant word or words.
A specific bit location within a range is referred to by mnemonic and
number. For example, A7 is bit 7 of accumulator A.
A range of bit locations is referred to by mnemonic and the numbers that
define the range. For example, DATA[15:8] form the high byte of the data
bus.
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Reference Manual — S12CPUV2
Section 2. Overview
2.1 Introduction
This section describes the CPU12 programming model, register set, the
data types used, and basic memory organization.
2.2 Programming Model
The CPU12 programming model, shown in Figure 2-1, is the same as that
of the M68HC11 CPU. The CPU has two 8-bit general-purpose
accumulators (A and B) that can be concatenated into a single 16-bit
accumulator (D) for certain instructions. It also has:
•
Two index registers (X and Y)
•
16-bit stack pointer (SP)
•
16-bit program counter (PC)
•
8-bit condition code register (CCR)
7
A
0
B
7
0
15
D
0
8-BIT ACCUMULATORS A AND B
OR
16-BIT DOUBLE ACCUMULATOR D
15
IX
0
INDEX REGISTER X
15
IY
0
INDEX REGISTER Y
15
SP
0
STACK POINTER
15
PC
0
PROGRAM COUNTER
S
X
H
I
N
Z
V
C
CONDITION CODE REGISTER
Figure 2-1. Programming Model
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2.2.1 Accumulators
General-purpose 8-bit accumulators A and B are used to hold operands and
results of operations. Some instructions treat the combination of these two
8-bit accumulators (A : B) as a 16-bit double accumulator (D).
Most operations can use accumulator A or B interchangeably. However,
there are a few exceptions. Add, subtract, and compare instructions
involving both A and B (ABA, SBA, and CBA) only operate in one direction,
so it is important to make certain the correct operand is in the correct
accumulator. The decimal adjust accumulator A (DAA) instruction is used
after binary-coded decimal (BCD) arithmetic operations. There is no
equivalent instruction to adjust accumulator B.
2.2.2 Index Registers
16-bit index registers X and Y are used for indexed addressing. In the
indexed addressing modes, the contents of an index register are added to
5-bit, 9-bit, or 16-bit constants or to the content of an accumulator to form
the effective address of the instruction operand. The second index register
is especially useful for moves and in cases where operands from two
separate tables are used in a calculation.
2.2.3 Stack Pointer
The CPU12 supports an automatic program stack. The stack is used to save
system context during subroutine calls and interrupts and can also be used
for temporary data storage. The stack can be located anywhere in the
standard 64-Kbyte address space and can grow to any size up to the total
amount of memory available in the system.
The stack pointer (SP) holds the 16-bit address of the last stack location
used. Normally, the SP is initialized by one of the first instructions in an
application program. The stack grows downward from the address pointed
to by the SP. Each time a byte is pushed onto the stack, the stack pointer is
automatically decremented, and each time a byte is pulled from the stack,
the stack pointer is automatically incremented.
When a subroutine is called, the address of the instruction following the
calling instruction is automatically calculated and pushed onto the stack.
Normally, a return-from-subroutine (RTS) or a return-from-call (RTC)
instruction is executed at the end of a subroutine. The return instruction
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loads the program counter with the previously stacked return address and
execution continues at that address.
When an interrupt occurs, the current instruction finishes execution. The
address of the next instruction is calculated and pushed onto the stack, all
the CPU registers are pushed onto the stack, the program counter is loaded
with the address pointed to by the interrupt vector, and execution continues
at that address. The stacked registers are referred to as an interrupt stack
frame. The CPU12 stack frame is the same as that of the M68HC11.
NOTE:
These instructions can be interrupted, and they resume execution once the
interrupt has been serviced:
• REV (fuzzy logic rule evaluation)
• REVW (fuzzy logic rule evaluation (weighted))
• WAV (weighted average)
2.2.4 Program Counter
The program counter (PC) is a 16-bit register that holds the address of the
next instruction to be executed. It is automatically incremented each time an
instruction is fetched.
2.2.5 Condition Code Register
The condition code register (CCR), named for its five status indicators,
contains:
•
Five status indicators
•
Two interrupt masking bits
•
STOP instruction control bit
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The status bits reflect the results of CPU operation as it executes
instructions. The five flags are:
•
Half carry (H)
•
Negative (N)
•
Zero (Z)
•
Overflow (V)
•
Carry/borrow (C)
The half-carry flag is used only for BCD arithmetic operations. The N, Z, V,
and C status bits allow for branching based on the results of a previous
operation.
In some architectures, only a few instructions affect condition codes, so that
multiple instructions must be executed in order to load and test a variable.
Since most CPU12 instructions automatically update condition codes, it is
rarely necessary to execute an extra instruction for this purpose. The
challenge in using the CPU12 lies in finding instructions that do not alter the
condition codes. The most important of these instructions are pushes, pulls,
transfers, and exchanges.
It is always a good idea to refer to an instruction set summary (see
Appendix A. Instruction Reference) to check which condition codes are
affected by a particular instruction.
The following paragraphs describe normal uses of the condition codes.
There are other, more specialized uses. For instance, the C status bit is
used to enable weighted fuzzy logic rule evaluation. Specialized usages are
described in the relevant portions of this manual and in Section 6.
Instruction Glossary.
2.2.5.1 S Control Bit
Clearing the S bit enables the STOP instruction. Execution of a STOP
instruction normally causes the on-chip oscillator to stop. This may be
undesirable in some applications. If the CPU encounters a STOP instruction
while the S bit is set, it is treated like a no-operation (NOP) instruction and
continues to the next instruction. Reset sets the S bit.
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2.2.5.2 X Mask Bit
The XIRQ input is an updated version of the NMI input found on earlier
generations of MCUs. Non-maskable interrupts are typically used to deal
with major system failures, such as loss of power. However, enabling
non-maskable interrupts before a system is fully powered and initialized can
lead to spurious interrupts. The X bit provides a mechanism for enabling
non-maskable interrupts after a system is stable.
By default, the X bit is set to 1 during reset. As long as the X bit remains set,
interrupt service requests made via the XIRQ pin are not recognized. An
instruction must clear the X bit to enable non-maskable interrupt service
requests made via the XIRQ pin. Once the X bit has been cleared to 0,
software cannot reset it to 1 by writing to the CCR. The X bit is not affected
by maskable interrupts.
When an XIRQ interrupt occurs after non-maskable interrupts are enabled,
both the X bit and the I bit are set automatically to prevent other interrupts
from being recognized during the interrupt service routine. The mask bits
are set after the registers are stacked, but before the interrupt vector is
fetched.
Normally, a return-from-interrupt (RTI) instruction at the end of the interrupt
service routine restores register values that were present before the
interrupt occurred. Since the CCR is stacked before the X bit is set, the RTI
normally clears the X bit, and thus re-enables non-maskable interrupts.
While it is possible to manipulate the stacked value of X so that X is set after
an RTI, there is no software method to reset X (and disable XIRQ) once X
has been cleared.
2.2.5.3 H Status Bit
The H bit indicates a carry from accumulator A bit 3 during an addition
operation. The DAA instruction uses the value of the H bit to adjust a result
in accumulator A to correct BCD format. H is updated only by the add
accumulator A to accumulator B (ABA), add without carry (ADD), and add
with carry (ADC) instructions.
2.2.5.4 I Mask Bit
The I bit enables and disables maskable interrupt sources. By default, the I
bit is set to 1 during reset. An instruction must clear the I bit to enable
maskable interrupts. While the I bit is set, maskable interrupts can become
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pending and are remembered, but operation continues uninterrupted until
the I bit is cleared.
When an interrupt occurs after interrupts are enabled, the I bit is
automatically set to prevent other maskable interrupts during the interrupt
service routine. The I bit is set after the registers are stacked, but before the
first instruction in the interrupt service routine is executed.
Normally, an RTI instruction at the end of the interrupt service routine
restores register values that were present before the interrupt occurred.
Since the CCR is stacked before the I bit is set, the RTI normally clears the
I bit, and thus re-enables interrupts. Interrupts can be re-enabled by clearing
the I bit within the service routine.
2.2.5.5 N Status Bit
The N bit shows the state of the MSB of the result. N is most commonly used
in two’s complement arithmetic, where the MSB of a negative number is 1
and the MSB of a positive number is 0, but it has other uses. For instance,
if the MSB of a register or memory location is used as a status flag, the user
can test status by loading an accumulator.
2.2.5.6 Z Status Bit
The Z bit is set when all the bits of the result are 0s. Compare instructions
perform an internal implied subtraction, and the condition codes, including
Z, reflect the results of that subtraction. The increment index register X
(INX), decrement index register X (DEX), increment index register Y (INY),
and decrement index register Y (DEY) instructions affect the Z bit and no
other condition flags. These operations can only determine = (equal) and ≠
(not equal).
2.2.5.7 V Status Bit
The V bit is set when two’s complement overflow occurs as a result of an
operation.
2.2.5.8 C Status Bit
The C bit is set when a carry occurs during addition or a borrow occurs
during subtraction. The C bit also acts as an error flag for multiply and divide
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operations. Shift and rotate instructions operate through the C bit to facilitate
multiple-word shifts.
2.3 Data Types
The CPU12 uses these types of data:
•
Bits
•
5-bit signed integers
•
8-bit signed and unsigned integers
•
8-bit, 2-digit binary-coded decimal numbers
•
9-bit signed integers
•
16-bit signed and unsigned integers
•
16-bit effective addresses
•
32-bit signed and unsigned integers
Negative integers are represented in two’s complement form.
Five-bit and 9-bit signed integers are used only as offsets for indexed
addressing modes.
Sixteen-bit effective addresses are formed during addressing mode
computations.
Thirty-two-bit integer dividends are used by extended division instructions.
Extended multiply and extended multiply-and-accumulate instructions
produce 32-bit products.
2.4 Memory Organization
The standard CPU12 address space is 64 Kbytes. Some M68HC12 devices
support a paged memory expansion scheme that increases the standard
space by means of predefined windows in address space. The CPU12 has
special instructions that support use of expanded memory.
Eight-bit values can be stored at any odd or even byte address in available
memory.
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Sixteen-bit values are stored in memory as two consecutive bytes; the high
byte occupies the lowest address, but need not be aligned to an even
boundary.
Thirty-two-bit values are stored in memory as four consecutive bytes; the
high byte occupies the lowest address, but need not be aligned to an even
boundary.
All input/output (I/O) and all on-chip peripherals are memory-mapped. No
special instruction syntax is required to access these addresses. On-chip
registers and memory typically are grouped in blocks which can be
relocated within the standard 64-Kbyte address space. Refer to device
documentation for specific information.
2.5 Instruction Queue
The CPU12 uses an instruction queue to buffer program information. The
mechanism is called a queue rather than a pipeline because a typical
pipelined CPU executes more than one instruction at the same time, while
the CPU12 always finishes executing an instruction before beginning to
execute another. Refer to Section 4. Instruction Queue for more
information.
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Reference Manual — S12CPUV2
Section 3. Addressing Modes
3.1 Introduction
Addressing modes determine how the central processor unit (CPU)
accesses memory locations to be operated upon. This section discusses
the various modes and how they are used.
3.2 Mode Summary
Addressing modes are an implicit part of CPU12 instructions. Refer to
Appendix A. Instruction Reference for the modes used by each
instruction. All CPU12 addressing modes are shown in Table 3-1.
The CPU12 uses all M68HC11 modes as well as new forms of indexed
addressing. Differences between M68HC11 and M68HC12 indexed modes
are described in 3.9 Indexed Addressing Modes. Instructions that use
more than one mode are discussed in 3.10 Instructions Using Multiple
Modes.
3.3 Effective Address
Each addressing mode except inherent mode generates a 16-bit effective
address which is used during the memory reference portion of the
instruction. Effective address computations do not require extra execution
cycles.
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Table 3-1. M68HC12 Addressing Mode Summary
Addressing Mode
Source Format
Abbreviation
Description
Inherent
INST
(no externally
supplied operands)
INH
Operands (if any) are in CPU registers
Immediate
INST #opr8i
or
INST #opr16i
IMM
Operand is included in instruction stream
8- or 16-bit size implied by context
Direct
INST opr8a
DIR
Operand is the lower 8 bits of an address
in the range $0000–$00FF
Extended
INST opr16a
EXT
Operand is a 16-bit address
Relative
INST rel8
or
INST rel16
REL
An 8-bit or 16-bit relative offset from the current pc
is supplied in the instruction
Indexed
(5-bit offset)
INST oprx5,xysp
IDX
5-bit signed constant offset
from X, Y, SP, or PC
Indexed
(pre-decrement)
INST oprx3,–xys
IDX
Auto pre-decrement x, y, or sp by 1 ~ 8
Indexed
(pre-increment)
INST oprx3,+xys
IDX
Auto pre-increment x, y, or sp by 1 ~ 8
Indexed
(post-decrement)
INST oprx3,xys–
IDX
Auto post-decrement x, y, or sp by 1 ~ 8
Indexed
(post-increment)
INST oprx3,xys+
IDX
Auto post-increment x, y, or sp by 1 ~ 8
Indexed
(accumulator offset)
INST abd,xysp
IDX
Indexed with 8-bit (A or B) or 16-bit (D)
accumulator offset from X, Y, SP, or PC
Indexed
(9-bit offset)
INST oprx9,xysp
IDX1
9-bit signed constant offset from X, Y, SP, or PC
(lower 8 bits of offset in one extension byte)
Indexed
(16-bit offset)
INST oprx16,xysp
IDX2
16-bit constant offset from X, Y, SP, or PC
(16-bit offset in two extension bytes)
Indexed-Indirect
(16-bit offset)
INST [oprx16,xysp]
[IDX2]
Pointer to operand is found at...
16-bit constant offset from X, Y, SP, or PC
(16-bit offset in two extension bytes)
Indexed-Indirect
(D accumulator offset)
INST [D,xysp]
[D,IDX]
Pointer to operand is found at...
X, Y, SP, or PC plus the value in D
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3.4 Inherent Addressing Mode
Instructions that use this addressing mode either have no operands or all
operands are in internal CPU registers. In either case, the CPU does not
need to access any memory locations to complete the instruction.
Examples:
NOP
INX
;this instruction has no operands
;operand is a CPU register
3.5 Immediate Addressing Mode
Operands for immediate mode instructions are included in the instruction
stream and are fetched into the instruction queue one 16-bit word at a time
during normal program fetch cycles. Since program data is read into the
instruction queue several cycles before it is needed, when an immediate
addressing mode operand is called for by an instruction, it is already present
in the instruction queue.
The pound symbol (#) is used to indicate an immediate addressing mode
operand. One common programming error is to accidentally omit the #
symbol. This causes the assembler to misinterpret the expression that
follows it as an address rather than explicitly provided data. For example,
LDAA #$55 means to load the immediate value $55 into the A accumulator,
while LDAA $55 means to load the value from address $0055 into the A
accumulator. Without the # symbol, the instruction is erroneously
interpreted as a direct addressing mode instruction.
Examples:
LDAA
LDX
LDY
#$55
#$1234
#$67
These are common examples of 8-bit and 16-bit immediate addressing
modes. The size of the immediate operand is implied by the instruction
context. In the third example, the instruction implies a 16-bit immediate
value but only an 8-bit value is supplied. In this case the assembler will
generate the 16-bit value $0067 because the CPU expects a 16-bit value in
the instruction stream.
Example:
BRSET
FOO,#$03,THERE
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In this example, extended addressing mode is used to access the operand
FOO, immediate addressing mode is used to access the mask value $03,
and relative addressing mode is used to identify the destination address of
a branch in case the branch-taken conditions are met. BRSET is listed as
an extended mode instruction even though immediate and relative modes
are also used.
3.6 Direct Addressing Mode
This addressing mode is sometimes called zero-page addressing because
it is used to access operands in the address range $0000 through $00FF.
Since these addresses always begin with $00, only the eight low-order bits
of the address need to be included in the instruction, which saves program
space and execution time. A system can be optimized by placing the most
commonly accessed data in this area of memory. The eight low-order bits of
the operand address are supplied with the instruction, and the eight
high-order bits of the address are assumed to be 0.
Example:
LDAA
$55
This is a basic example of direct addressing. The value $55 is taken to be
the low-order half of an address in the range $0000 through $00FF. The
high order half of the address is assumed to be 0. During execution of this
instruction, the CPU combines the value $55 from the instruction with the
assumed value of $00 to form the address $0055, which is then used to
access the data to be loaded into accumulator A.
Example:
LDX
$20
In this example, the value $20 is combined with the assumed value of $00
to form the address $0020. Since the LDX instruction requires a 16-bit
value, a 16-bit word of data is read from addresses $0020 and $0021. After
execution of this instruction, the X index register will have the value from
address $0020 in its high-order half and the value from address $0021 in its
low-order half.
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3.7 Extended Addressing Mode
In this addressing mode, the full 16-bit address of the memory location to be
operated on is provided in the instruction. This addressing mode can be
used to access any location in the 64-Kbyte memory map.
Example:
LDAA
$F03B
This is a basic example of extended addressing. The value from address
$F03B is loaded into the A accumulator.
3.8 Relative Addressing Mode
The relative addressing mode is used only by branch instructions. Short and
long conditional branch instructions use relative addressing mode
exclusively, but branching versions of bit manipulation instructions (branch
if bits set (BRSET) and branch if bits cleared (BRCLR)) use multiple
addressing modes, including relative mode. Refer to
3.10 Instructions Using Multiple Modes for more information.
Short branch instructions consist of an 8-bit opcode and a signed 8-bit offset
contained in the byte that follows the opcode. Long branch instructions
consist of an 8-bit prebyte, an 8-bit opcode, and a signed 16-bit offset
contained in the two bytes that follow the opcode.
Each conditional branch instruction tests certain status bits in the condition
code register. If the bits are in a specified state, the offset is added to the
address of the next memory location after the offset to form an effective
address, and execution continues at that address. If the bits are not in the
specified state, execution continues with the instruction immediately
following the branch instruction.
Bit-condition branches test whether bits in a memory byte are in a specific
state. Various addressing modes can be used to access the memory
location. An 8-bit mask operand is used to test the bits. If each bit in memory
that corresponds to a 1 in the mask is either set (BRSET) or clear (BRCLR),
an 8-bit offset is added to the address of the next memory location after the
offset to form an effective address, and execution continues at that address.
If all the bits in memory that correspond to a 1 in the mask are not in the
specified state, execution continues with the instruction immediately
following the branch instruction.
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8-bit, 9-bit, and 16-bit offsets are signed two’s complement numbers to
support branching upward and downward in memory. The numeric range of
short branch offset values is $80 (–128) to $7F (127). Loop primitive
instructions support a 9-bit offset which allows a range of $100 (–256) to
$0FF (255). The numeric range of long branch offset values is $8000
(–32,768) to $7FFF (32,767). If the offset is 0, the CPU executes the
instruction immediately following the branch instruction, regardless of the
test involved.
Since the offset is at the end of a branch instruction, using a negative offset
value can cause the program counter (PC) to point to the opcode and initiate
a loop. For instance, a branch always (BRA) instruction consists of two
bytes, so using an offset of $FE sets up an infinite loop; the same is true of
a long branch always (LBRA) instruction with an offset of $FFFC.
An offset that points to the opcode can cause a bit-condition branch to
repeat execution until the specified bit condition is satisfied. Since
bit-condition branches can consist of four, five, or six bytes depending on
the addressing mode used to access the byte in memory, the offset value
that sets up a loop can vary. For instance, using an offset of $FC with a
BRCLR that accesses memory using an 8-bit indexed postbyte sets up a
loop that executes until all the bits in the specified memory byte that
correspond to 1s in the mask byte are cleared.
3.9 Indexed Addressing Modes
The CPU12 uses redefined versions of M68HC11 indexed modes that
reduce execution time and eliminate code size penalties for using the Y
index register. In most cases, CPU12 code size for indexed operations is the
same or is smaller than that for the M68HC11. Execution time is shorter in
all cases. Execution time improvements are due to both a reduced number
of cycles for all indexed instructions and to faster system clock speed.
The indexed addressing scheme uses a postbyte plus zero, one, or two
extension bytes after the instruction opcode. The postbyte and extensions
do the following tasks:
1. Specify which index register is used
2. Determine whether a value in an accumulator is used as an offset
3. Enable automatic pre- or post-increment or pre- or post-decrement
4. Specify size of increment or decrement
5. Specify use of 5-, 9-, or 16-bit signed offsets
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This approach eliminates the differences between X and Y register use
while dramatically enhancing the indexed addressing capabilities.
Major advantages of the CPU12 indexed addressing scheme are:
•
The stack pointer can be used as an index register in all indexed
operations.
•
The program counter can be used as an index register in all but
autoincrement and autodecrement modes.
•
A, B, or D accumulators can be used for accumulator offsets.
•
Automatic pre- or post-increment or pre- or post-decrement by –8 to
+8
•
A choice of 5-, 9-, or 16-bit signed constant offsets
•
Use of two new indexed-indirect modes:
– Indexed-indirect mode with 16-bit offset
– Indexed-indirect mode with accumulator D offset
Table 3-2 is a summary of indexed addressing mode capabilities and a
description of postbyte encoding. The postbyte is noted as xb in instruction
descriptions. Detailed descriptions of the indexed addressing mode
variations follow the table.
All indexed addressing modes use a 16-bit CPU register and additional
information to create an effective address. In most cases the effective
address specifies the memory location affected by the operation. In some
variations of indexed addressing, the effective address specifies the
location of a value that points to the memory location affected by the
operation.
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Table 3-2. Summary of Indexed Operations
Postbyte
Code (xb)
Source
Code
Syntax
rr0nnnnn
,r
n,r
–n,r
5-bit constant offset n = –16 to +15
r can specify X, Y, SP, or PC
111rr0zs
n,r
–n,r
Constant offset (9- or 16-bit signed)
z- 0 = 9-bit with sign in LSB of postbyte(s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
r can specify X, Y, SP, or PC
111rr011
[n,r]
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
rr1pnnnn
Comments
rr; 00 = X, 01 = Y, 10 = SP, 11 = PC
n,–r n,+r
n,r–
n,r+
–256 ≤ n ≤ 255
–32,768 ≤ n ≤ 65,535
–32,768 ≤ n ≤ 65,535
Auto predecrement, preincrement, postdecrement, or postincrement;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
r can specify X, Y, or SP (PC not a valid choice)
+8 = 0111
…
+1 = 0000
–1 = 1111
…
–8 = 1000
111rr1aa
A,r
B,r
D,r
Accumulator offset (unsigned 8-bit or 16-bit)
aa-00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC
111rr111
[D,r]
Accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC
Indexed addressing mode instructions use a postbyte to specify index
registers (X and Y), stack pointer (SP), or program counter (PC) as the base
index register and to further classify the way the effective address is formed.
A special group of instructions cause this calculated effective address to be
loaded into an index register for further calculations:
•
Load stack pointer with effective address (LEAS)
•
Load X with effective address (LEAX)
•
Load Y with effective address (LEAY)
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3.9.1 5-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 5-bit signed offset which is included
in the instruction postbyte. This short offset is added to the base index
register (X, Y, SP, or PC) to form the effective address of the memory
location that will be affected by the instruction. This gives a range of –16
through +15 from the value in the base index register. Although other
indexed addressing modes allow 9- or 16-bit offsets, those modes also
require additional extension bytes in the instruction for this extra
information. The majority of indexed instructions in real programs use
offsets that fit in the shortest 5-bit form of indexed addressing.
Examples:
LDAA
STAB
0,X
–8,Y
For these examples, assume X has a value of $1000 and Y has a value of
$2000 before execution. The 5-bit constant offset mode does not change
the value in the index register, so X will still be $1000 and Y will still be $2000
after execution of these instructions. In the first example, A will be loaded
with the value from address $1000. In the second example, the value from
the B accumulator will be stored at address $1FF8 ($2000 –$8).
3.9.2 9-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 9-bit signed offset which is added to
the base index register (X, Y, SP, or PC) to form the effective address of the
memory location affected by the instruction. This gives a range of –256
through +255 from the value in the base index register. The most significant
bit (sign bit) of the offset is included in the instruction postbyte and the
remaining eight bits are provided as an extension byte after the instruction
postbyte in the instruction flow.
Examples:
LDAA
LDAB
$FF,X
–20,Y
For these examples, assume X is $1000 and Y is $2000 before execution of
these instructions.
NOTE:
These instructions do not alter the index registers so they will still be $1000
and $2000, respectively, after the instructions.
The first instruction will load A with the value from address $10FF and the
second instruction will load B with the value from address $1FEC.
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This variation of the indexed addressing mode in the CPU12 is similar to the
M68HC11 indexed addressing mode, but is functionally enhanced. The
M68HC11 CPU provides for unsigned 8-bit constant offset indexing from X
or Y, and use of Y requires an extra instruction byte and thus, an extra
execution cycle. The 9-bit signed offset used in the CPU12 covers the same
range of positive offsets as the M68HC11, and adds negative offset
capability. The CPU12 can use X, Y, SP, or PC as the base index register.
3.9.3 16-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 16-bit offset which is added to the
base index register (X, Y, SP, or PC) to form the effective address of the
memory location affected by the instruction. This allows access to any
address in the 64-Kbyte address space. Since the address bus and the
offset are both 16 bits, it does not matter whether the offset value is
considered to be a signed or an unsigned value ($FFFF may be thought of
as +65,535 or as –1). The 16-bit offset is provided as two extension bytes
after the instruction postbyte in the instruction flow.
3.9.4 16-Bit Constant Indirect Indexed Addressing
This indexed addressing mode adds a 16-bit instruction-supplied offset to
the base index register to form the address of a memory location that
contains a pointer to the memory location affected by the instruction. The
instruction itself does not point to the address of the memory location to be
acted upon, but rather to the location of a pointer to the address to be acted
on. The square brackets distinguish this addressing mode from 16-bit
constant offset indexing.
Example:
LDAA
[10,X]
In this example, X holds the base address of a table of pointers. Assume
that X has an initial value of $1000, and that the value $2000 is stored at
addresses $100A and $100B. The instruction first adds the value 10 to the
value in X to form the address $100A. Next, an address pointer ($2000) is
fetched from memory at $100A. Then, the value stored in location $2000 is
read and loaded into the A accumulator.
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3.9.5 Auto Pre/Post Decrement/Increment Indexed Addressing
This indexed addressing mode provides four ways to automatically change
the value in a base index register as a part of instruction execution. The
index register can be incremented or decremented by an integer value
either before or after indexing takes place. The base index register may be
X, Y, or SP. (Auto-modify modes would not make sense on PC.)
Pre-decrement and pre-increment versions of the addressing mode adjust
the value of the index register before accessing the memory location
affected by the instruction — the index register retains the changed value
after the instruction executes. Post-decrement and post-increment versions
of the addressing mode use the initial value in the index register to access
the memory location affected by the instruction, then change the value of the
index register.
The CPU12 allows the index register to be incremented or decremented by
any integer value in the ranges –8 through –1 or 1 through 8. The value
need not be related to the size of the operand for the current instruction.
These instructions can be used to incorporate an index adjustment into an
existing instruction rather than using an additional instruction and increasing
execution time. This addressing mode is also used to perform operations on
a series of data structures in memory.
When an LEAS, LEAX, or LEAY instruction is executed using this
addressing mode, and the operation modifies the index register that is being
loaded, the final value in the register is the value that would have been used
to access a memory operand. (Premodification is seen in the result but
postmodification is not.)
Examples:
STAA
STX
LDX
LDAA
1,–SP
2,–SP
2,SP+
1,SP+
;equivalent
;equivalent
;equivalent
;equivalent
to
to
to
to
PSHA
PSHX
PULX
PULA
For a “last-used” type of stack like the CPU12 stack, these four examples
are equivalent to common push and pull instructions.
For a “next-available” stack like the M68HC11 stack, push A onto stack
(PSHA) is equivalent to store accumulator A (STAA) 1,SP– and pull A from
stack (PULA) is equivalent to load accumulator A (LDAA) 1,+SP. However,
in the M68HC11, 16-bit operations like push register X onto stack (PSHX)
and pull register X from stack (PULX) require multiple instructions to
decrement the SP by one, then store X, then decrement SP by one again.
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In the STAA 1,–SP example, the stack pointer is pre-decremented by one
and then A is stored to the address contained in the stack pointer. Similarly
the LDX 2,SP+ first loads X from the address in the stack pointer, then
post-increments SP by two.
Example:
MOVW
2,X+,4,+Y
This example demonstrates how to work with data structures larger than
bytes and words. With this instruction in a program loop, it is possible to
move words of data from a list having one word per entry into a second table
that has four bytes per table element. In this example the source pointer is
updated after the data is read from memory (post-increment) while the
destination pointer is updated before it is used to access memory
(pre-increment).
3.9.6 Accumulator Offset Indexed Addressing
In this indexed addressing mode, the effective address is the sum of the
values in the base index register and an unsigned offset in one of the
accumulators. The value in the index register itself is not changed. The
index register can be X, Y, SP, or PC and the accumulator can be either of
the 8-bit accumulators (A or B) or the 16-bit D accumulator.
Example:
LDAA
B,X
This instruction internally adds B to X to form the address from which A will
be loaded. B and X are not changed by this instruction. This example is
similar to the following 2-instruction combination in an M68HC11.
Examples:
ABX
LDAA
0,X
However, this 2-instruction sequence alters the index register. If this
sequence was part of a loop where B changed on each pass, the index
register would have to be reloaded with the reference value on each loop
pass. The use of LDAA B,X is more efficient in the CPU12.
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3.9.7 Accumulator D Indirect Indexed Addressing
This indexed addressing mode adds the value in the D accumulator to the
value in the base index register to form the address of a memory location
that contains a pointer to the memory location affected by the instruction.
The instruction operand does not point to the address of the memory
location to be acted upon, but rather to the location of a pointer to the
address to be acted upon. The square brackets distinguish this addressing
mode from D accumulator offset indexing.
Examples:
JMP
GO1
GO2
GO3
[D,PC]
DC.W
DC.W
DC.W
PLACE1
PLACE2
PLACE3
This example is a computed GOTO. The values beginning at GO1 are
addresses of potential destinations of the jump (JMP) instruction. At the time
the JMP [D,PC] instruction is executed, PC points to the address GO1, and
D holds one of the values $0000, $0002, or $0004 (determined by the
program some time before the JMP).
Assume that the value in D is $0002. The JMP instruction adds the values
in D and PC to form the address of GO2. Next the CPU reads the address
PLACE2 from memory at GO2 and jumps to PLACE2. The locations of
PLACE1 through PLACE3 were known at the time of program assembly but
the destination of the JMP depends upon the value in D computed during
program execution.
3.10 Instructions Using Multiple Modes
Several CPU12 instructions use more than one addressing mode in the
course of execution.
3.10.1 Move Instructions
Move instructions use separate addressing modes to access the source and
destination of a move. There are move variations for all practical
combinations of immediate, extended, and indexed addressing modes.
The only combinations of addressing modes that are not allowed are those
with an immediate mode destination (the operand of an immediate mode
instruction is data, not an address). For indexed moves, the reference index
register may be X, Y, SP, or PC.
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Move instructions do not support indirect modes, 9-bit, or 16-bit offset
modes requiring extra extension bytes. There are special considerations
when using PC-relative addressing with move instructions. The original
M68HC12 implemented the instruction queue slightly differently than the
newer HCS12. In the older M68HC12 implementation, the CPU did not
maintain a pointer to the start of the instruction after the current instruction
(what the user thinks of as the PC value during execution). This caused an
offset for PC-relative move instructions.
PC-relative addressing uses the address of the location immediately
following the last byte of object code for the current instruction as a
reference point. The CPU12 normally corrects for queue offset and for
instruction alignment so that queue operation is transparent to the user.
However, in the original M68HC12, move instructions pose three special
problems:
•
Some moves use an indexed source and an indexed destination.
•
Some moves have object code that is too long to fit in the queue all at
one time, so the PC value changes during execution.
•
All moves do not have the indexed postbyte as the last byte of object
code.
These cases are not handled by automatic queue pointer maintenance, but
it is still possible to use PC-relative indexing with move instructions by
providing for PC offsets in source code.
Table 3-3 shows PC offsets from the location immediately following the
current instruction by addressing mode.
Table 3-3. PC Offsets for MOVE Instructions (M68HC12 Only)
MOVE Instruction
MOVB
MOVW
Addressing Modes
Offset Value
IMM ⇒ IDX
+1
EXT ⇒ IDX
+2
IDX ⇒ EXT
–2
IDX ⇒ IDX
–1 for first operand
+1 for second operand
IMM ⇒ IDX
+2
EXT ⇒ IDX
+2
IDX ⇒ EXT
–2
IDX ⇒ IDX
–1 for first operand
+1 for second operand
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Example:
1000
18 09 C2 20 00
MOVB
$2000 2,PC
Moves a byte of data from $2000 to $1009
The expected location of the PC = $1005. The offset = +2.
[1005 + 2 (for 2,PC) + 2 (for correction) = 1009]
$18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the
indexed postbyte for 2,PC (without correction).
The Freescale MCUasm assembler produces corrected object code for
PC-relative moves (18 09 C0 20 00 for the example shown).
NOTE:
Instead of assembling the 2,PC as C2, the correction has been applied to
make it C0. Check whether an assembler makes the correction before using
PC-relative moves.
On the newer HCS12, the instruction queue was implemented such that an
internal pointer, to the start of the next instruction, is always available. On
the HCS12, PC-relative move instructions work as expected without any
offset adjustment. Although this is different from the original M68HC12, it is
unlikely to be a problem because PC-relative indexing is rarely, if ever, used
with move instructions.
3.10.2 Bit Manipulation Instructions
Bit manipulation instructions use either a combination of two or a
combination of three addressing modes.
The clear bits in memory (BCLR) and set bits in memory (BSET) instructions
use an 8-bit mask to determine which bits in a memory byte are to be
changed. The mask must be supplied with the instruction as an immediate
mode value. The memory location to be modified can be specified by means
of direct, extended, or indexed addressing modes.
The branch if bits cleared (BRCLR) and branch if bits set (BRSET)
instructions use an 8-bit mask to test the states of bits in a memory byte. The
mask is supplied with the instruction as an immediate mode value. The
memory location to be tested is specified by means of direct, extended, or
indexed addressing modes. Relative addressing mode is used to determine
the branch address. A signed 8-bit offset must be supplied with the
instruction.
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3.11 Addressing More than 64 Kbytes
Some M68HC12 devices incorporate hardware that supports addressing a
larger memory space than the standard 64 Kbytes. The expanded memory
system uses fast on-chip logic to implement a transparent bank-switching
scheme.
Increased code efficiency is the greatest advantage of using a switching
scheme instead of a large linear address space. In systems with large linear
address spaces, instructions require more bits of information to address a
memory location, and CPU overhead is greater. Other advantages include
the ability to change the size of system memory and the ability to use
various types of external memory.
However, the add-on bank switching schemes used in other
microcontrollers have known weaknesses. These include the cost of
external glue logic, increased programming overhead to change banks, and
the need to disable interrupts while banks are switched.
The M68HC12 system requires no external glue logic. Bank switching
overhead is reduced by implementing control logic in the MCU. Interrupts do
not need to be disabled during switching because switching tasks are
incorporated in special instructions that greatly simplify program access to
extended memory.
MCUs with expanded memory treat the 16 Kbytes of memory space from
$8000 to $BFFF as a program memory window. Expanded-memory
architecture includes an 8-bit program page register (PPAGE), which allows
up to 256 16-Kbyte program memory pages to be switched into and out of
the program memory window. This provides for up to 4 Megabytes of paged
program memory.
The CPU12 instruction set includes call subroutine in expanded memory
(CALL) and return from call (RTC) instructions, which greatly simplify the
use of expanded memory space. These instructions also execute correctly
on devices that do not have expanded-memory addressing capability, thus
providing for portable code.
The CALL instruction is similar to the jump-to-subroutine (JSR) instruction.
When CALL is executed, the current value in PPAGE is pushed onto the
stack with a return address, and a new instruction-supplied value is written
to PPAGE. This value selects the page the called subroutine resides upon
and can be considered part of the effective address. For all addressing
mode variations except indexed indirect modes, the new page value is
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provided by an immediate operand in the instruction. For indexed indirect
variations of CALL, a pointer specifies memory locations where the new
page value and the address of the called subroutine are stored. Use of
indirect addressing for both the page value and the address within the page
frees the program from keeping track of explicit values for either address.
The RTC instruction restores the saved program page value and the return
address from the stack. This causes execution to resume at the next
instruction after the original CALL instruction.
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Reference Manual — S12CPUV2
Section 4. Instruction Queue
4.1 Introduction
The CPU12 uses an instruction queue to increase execution speed.
This section describes queue operation during normal program execution
and changes in execution flow. These concepts augment the descriptions of
instructions and cycle-by-cycle instruction execution in subsequent
sections, but it is important to note that queue operation is automatic, and
generally transparent to the user.
The material in this section is general. Section 6. Instruction Glossary
contains detailed information concerning cycle-by-cycle execution of each
instruction. Section 8. Instruction Queue contains detailed information
about tracking queue operation and instruction execution.
4.2 Queue Description
The fetching mechanism in the CPU12 is best described as a queue rather
than as a pipeline. Queue logic fetches program information and positions it
for execution, but instructions are executed sequentially. A typical pipelined
central processor unit (CPU) can execute more than one instruction at the
same time, but interactions between the prefetch and execution
mechanisms can make tracking and debugging difficult. The CPU12 thus
gains the advantages of independent fetches, yet maintains a
straightforward relationship between bus and execution cycles.
Each instruction refills the queue by fetching the same number of bytes that
the instruction uses. Program information is fetched in aligned 16-bit words.
Each program fetch (P) indicates that two bytes need to be replaced in the
instruction queue. Each optional fetch (O) indicates that only one byte needs
to be replaced. For example, an instruction composed of five bytes does two
program fetches and one optional fetch. If the first byte of the five-byte
instruction was even-aligned, the optional fetch is converted into a free
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cycle. If the first byte was odd-aligned, the optional fetch is executed as a
program fetch.
Two external pins, IPIPE[1:0], provide time-multiplexed information about
data movement in the queue and instruction execution. Decoding and use
of these signals is discussed in Section 8. Instruction Queue.
4.2.1 Original M68HC12 Queue Implementation
There are two 16-bit queue stages and one 16-bit buffer. Program
information is fetched in aligned 16-bit words. Unless buffering is required,
program information is first queued into stage 1, then advanced to stage 2
for execution.
At least two words of program information are available to the CPU when
execution begins. The first byte of object code is in either the even or odd
half of the word in stage 2, and at least two more bytes of object code are in
the queue.
The buffer is used when a program word arrives before the queue can
advance. This occurs during execution of single-byte and odd-aligned
instructions. For instance, the queue cannot advance after an aligned,
single-byte instruction is executed, because the first byte of the next
instruction is also in stage 2. In these cases, information is latched into the
buffer until the queue can advance.
4.2.2 HCS12 Queue Implementation
There are three 16-bit stages in the instruction queue. Instructions enter the
queue at stage 1 and shift out of stage 3 as the CPU executes instructions
and fetches new ones into stage 1. Each byte in the queue is selectable. An
opcode prediction algorithm determines the location of the next opcode in
the instruction queue.
4.3 Data Movement in the Queue
All queue operations are combinations of four basic queue movement
cycles. Descriptions of each of these cycles follows. Queue movement
cycles are only one factor in instruction execution time and should not be
confused with bus cycles.
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4.3.1 No Movement
There is no data movement in the instruction queue during the cycle. This
occurs during execution of instructions that must perform a number of
internal operations, such as division instructions.
4.3.2 Latch Data from Bus (Applies Only to the M68HC12 Queue Implementation)
All instructions initiate fetches to refill the queue as execution proceeds.
However, a number of conditions, including instruction alignment and the
length of previous instructions, affect when the queue advances. If the
queue is not ready to advance when fetched information arrives, the
information is latched into the buffer. Later, when the queue does advance,
stage 1 is refilled from the buffer. If more than one latch cycle occurs before
the queue advances, the buffer is filled on the first latch event and
subsequent latch events are ignored until the queue advances.
4.3.3 Advance and Load from Data Bus
The content of queue is advanced by one stage, and stage 1 is loaded with
a word of program information from the data bus. The information was
requested two bus cycles earlier but has only become available this cycle,
due to access delay.
4.3.4 Advance and Load from Buffer (Applies Only to M68HC12 Queue Implementation)
The content of queue stage 1 advances to stage 2, and stage 1 is loaded
with a word of program information from the buffer. The information in the
buffer was latched from the data bus during a previous cycle because the
queue was not ready to advance when it arrived.
4.4 Changes in Execution Flow
During normal instruction execution, queue operations proceed as a
continuous sequence of queue movement cycles. However, situations arise
which call for changes in flow. These changes are categorized as resets,
interrupts, subroutine calls, conditional branches, and jumps. Generally
speaking, resets and interrupts are considered to be related to events
outside the current program context that require special processing, while
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subroutine calls, branches, and jumps are considered to be elements of
program structure.
During design, great care is taken to assure that the mechanism that
increases instruction throughput during normal program execution does not
cause bottlenecks during changes of program flow, but internal queue
operation is largely transparent to the user. The following information is
provided to enhance subsequent descriptions of instruction execution.
4.4.1 Exceptions
Exceptions are events that require processing outside the normal flow of
instruction execution. CPU12 exceptions include five types of exceptions:
•
Reset (including COP, clock monitor, and pin)
•
Unimplemented opcode trap
•
Software interrupt instruction
•
X-bit interrupts
•
I-bit interrupts
All exceptions use the same microcode, but the CPU follows different
execution paths for each type of exception.
CPU12 exception handling is designed to minimize the effect of queue
operation on context switching. Thus, an exception vector fetch is the first
part of exception processing, and fetches to refill the queue from the
address pointed to by the vector are interleaved with the stacking operations
that preserve context, so that program access time does not delay the
switch. Refer to Section 7. Exception Processing for detailed information.
4.4.2 Subroutines
The CPU12 can branch to (BSR), jump to (JSR), or call (CALL) subroutines.
BSR and JSR are used to access subroutines in the normal 64-Kbyte
address space. The CALL instruction is intended for use in MCUs with
expanded memory capability.
BSR uses relative addressing mode to generate the effective address of the
subroutine, while JSR can use various other addressing modes. Both
instructions calculate a return address, stack the address, then perform
three program word fetches to refill the queue.
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Subroutines in the normal 64-Kbyte address space are terminated with a
return-from-subroutine (RTS) instruction. RTS unstacks the return address,
then performs three program word fetches from that address to refill the
queue.
CALL is similar to JSR. MCUs with expanded memory treat 16 Kbytes of
addresses from $8000 to $BFFF as a memory window. An 8-bit PPAGE
register switches memory pages into and out of the window. When CALL is
executed, a return address is calculated, then it and the current PPAGE
value are stacked, and a new instruction-supplied value is written to
PPAGE. The subroutine address is calculated, then three program word
fetches are made from that address to refill the instruction queue.
The return-from-call (RTC) instruction is used to terminate subroutines in
expanded memory. RTC unstacks the PPAGE value and the return
address, then performs three program word fetches from that address to
refill the queue.
CALL and RTC execute correctly in the normal 64-Kbyte address space,
thus providing for portable code. However, since extra execution cycles are
required, routinely substituting CALL/RTC for JSR/RTS is not
recommended.
4.4.3 Branches
Branch instructions cause execution flow to change when specific
pre-conditions exist. The CPU12 instruction set includes:
•
Short conditional branches
•
Long conditional branches
•
Bit-condition branches
Types and conditions of branch instructions are described in
5.19 Branch Instructions. All branch instructions affect the queue similarly,
but there are differences in overall cycle counts between the various types.
Loop primitive instructions are a special type of branch instruction used to
implement counter-based loops.
Branch instructions have two execution cases:
•
The branch condition is satisfied, and a change of flow takes place.
•
The branch condition is not satisfied, and no change of flow occurs.
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4.4.3.1 Short Branches
The “not-taken” case for short branches is simple. Since the instruction
consists of a single word containing both an opcode and an 8-bit offset, the
queue advances, another program word is fetched, and execution continues
with the next instruction.
The “taken” case for short branches requires that the queue be refilled so
that execution can continue at a new address. First, the effective address of
the destination is calculated using the relative offset in the instruction. Then,
the address is loaded into the program counter, and the CPU performs three
program word fetches at the new address to refill the instruction queue.
4.4.3.2 Long Branches
The “not-taken” case for all long branches requires three cycles, while the
“taken” case requires four cycles. This is due to differences in the amount of
program information needed to fill the queue.
Long branch instructions begin with a $18 prebyte which indicates that the
opcode is on page 2 of the opcode map. The CPU12 treats the prebyte as
a special one-byte instruction. If the prebyte is not aligned, the first cycle is
used to perform a program word access; if the prebyte is aligned, the first
cycle is used to perform a free cycle. The first cycle for the prebyte is
executed whether or not the branch is taken.
The first cycle of the branch instruction is an optional cycle. Optional cycles
make the effects of byte-sized and misaligned instructions consistent with
those of aligned word-length instructions. Program information is always
fetched as aligned 16-bit words. When an instruction has an odd number of
bytes, and the first byte is not aligned with an even byte boundary, the
optional cycle makes an additional program word access that maintains
queue order. In all other cases, the optional cycle is a free cycle.
In the “not-taken” case, the queue must advance so that execution can
continue with the next instruction. Two cycles are used to refill the queue.
Alignment determines how the second of these cycles is used.
In the “taken” case, the effective address of the branch is calculated using
the 16-bit relative offset contained in the second word of the instruction. This
address is loaded into the program counter, then the CPU performs three
program word fetches at the new address.
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4.4.3.3 Bit Condition Branches
Bit condition branch instructions read a location in memory, and branch if
the bits in that location are in a certain state. These instructions can use
direct, extended, or indexed addressing modes. Indexed operations require
varying amounts of information to determine the effective address, so
instruction length varies according to the mode used, which in turn affects
the amount of program information fetched. To shorten execution time,
these branches perform one program word fetch in anticipation of the
“taken” case. The data from this fetch is ignored in the “not-taken” case. If
the branch is taken, the CPU fetches three program word fetches at the new
address to fill the instruction queue.
4.4.3.4 Loop Primitives
The loop primitive instructions test a counter value in a register or
accumulator and branch to an address specified by a 9-bit relative offset
contained in the instruction if a specified condition is met. There are
auto-increment and auto-decrement versions of these instructions. The test
and increment/decrement operations are performed on internal CPU
registers, and require no additional program information. To shorten
execution time, these branches perform one program word fetch in
anticipation of the “taken” case. The data from this fetch is ignored if the
branch is not taken, and the CPU does one program fetch and one optional
fetch to refill the queue1. If the branch is taken, the CPU finishes refilling the
queue with two additional program word fetches at the new address.
4.4.4 Jumps
Jump (JMP) is the simplest change of flow instruction. JMP can use
extended or indexed addressing. Indexed operations require varying
amounts of information to determine the effective address, so instruction
length varies according to the mode used, which in turn affects the amount
of program information fetched. All forms of JMP perform three program
word fetches at the new address to refill the instruction queue.
1. In the original M68HC12, the implementation of these two cycles are both program word
fetches.
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Reference Manual — S12CPUV2
Section 5. Instruction Set Overview
5.1 Introduction
This section contains general information about the central processor unit
(CPU12) instruction set. It is organized into instruction categories grouped
by function.
5.2 Instruction Set Description
CPU12 instructions are a superset of the M68HC11 instruction set. Code
written for an M68HC11 can be reassembled and run on a CPU12 with no
changes. The CPU12 provides expanded functionality and increased code
efficiency. There are two implementations of the CPU12, the original
M68HC12 and the newer HCS12. Both implementations have the same
instruction set, although there are small differences in cycle-by-cycle access
details (the order of some bus cycles changed to accommodate differences
in the way the instruction queue was implemented). These minor
differences are transparent for most users.
In the M68HC12 and HCS12 architecture, all memory and input/output (I/O)
are mapped in a common 64-Kbyte address space (memory-mapped I/O).
This allows the same set of instructions to be used to access memory, I/O,
and control registers. General-purpose load, store, transfer, exchange, and
move instructions facilitate movement of data to and from memory and
peripherals.
The CPU12 has a full set of 8-bit and 16-bit mathematical instructions.
There are instructions for signed and unsigned arithmetic, division, and
multiplication with 8-bit, 16-bit, and some larger operands.
Special arithmetic and logic instructions aid stacking operations, indexing,
binary-coded decimal (BCD) calculation, and condition code register
manipulation. There are also dedicated instructions for multiply and
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accumulate operations, table interpolation, and specialized fuzzy logic
operations that involve mathematical calculations.
Refer to Section 6. Instruction Glossary for detailed information about
individual instructions. Appendix A. Instruction Reference contains
quick-reference material, including an opcode map and postbyte encoding
for indexed addressing, transfer/exchange instructions, and loop primitive
instructions.
5.3 Load and Store Instructions
Load instructions copy memory content into an accumulator or register.
Memory content is not changed by the operation. Load instructions (but not
LEA_ instructions) affect condition code bits so no separate test instructions
are needed to check the loaded values for negative or 0 conditions.
Store instructions copy the content of a CPU register to memory.
Register/accumulator content is not changed by the operation. Store
instructions automatically update the N and Z condition code bits, which can
eliminate the need for a separate test instruction in some programs.
Table 5-1 is a summary of load and store instructions.
Table 5-1. Load and Store Instructions
Mnemonic
Function
Operation
Load Instructions
LDAA
Load A
(M) ⇒ A
LDAB
Load B
(M) ⇒ B
LDD
Load D
(M : M + 1) ⇒ (A:B)
LDS
Load SP
(M : M + 1) ⇒ SPH:SPL
LDX
Load index register X
(M : M + 1) ⇒ XH:XL
LDY
Load index register Y
(M : M + 1) ⇒ YH:YL
LEAS
Load effective address into SP
Effective address ⇒ SP
LEAX
Load effective address into X
Effective address ⇒ X
LEAY
Load effective address into Y
Effective address ⇒ Y
Continued on next page
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Table 5-1. Load and Store Instructions (Continued)
Store Instructions
STAA
Store A
(A) ⇒ M
STAB
Store B
(B) ⇒ M
STD
Store D
(A) ⇒ M, (B) ⇒ M + 1
STS
Store SP
(SPH:SPL) ⇒ M : M + 1
STX
Store X
(XH:XL) ⇒ M : M + 1
STY
Store Y
(YH:YL) ⇒ M : M + 1
5.4 Transfer and Exchange Instructions
Transfer instructions copy the content of a register or accumulator into
another register or accumulator. Source content is not changed by the
operation. Transfer register to register (TFR) is a universal transfer
instruction, but other mnemonics are accepted for compatibility with the
M68HC11. The transfer A to B (TAB) and transfer B to A (TBA) instructions
affect the N, Z, and V condition code bits in the same way as M68HC11
instructions. The TFR instruction does not affect the condition code bits.
The sign extend 8-bit operand (SEX) instruction is a special case of the
universal transfer instruction that is used to sign extend 8-bit two’s
complement numbers so that they can be used in 16-bit operations. The
8-bit number is copied from accumulator A, accumulator B, or the condition
code register to accumulator D, the X index register, the Y index register, or
the stack pointer. All the bits in the upper byte of the 16-bit result are given
the value of the most-significant bit (MSB) of the 8-bit number.
Exchange instructions exchange the contents of pairs of registers or
accumulators. When the first operand in an EXG instruction is 8-bits and the
second operand is 16 bits, a zero-extend operation is performed on the 8-bit
register as it is copied into the 16-bit register.
Section 6. Instruction Glossary contains information concerning other
transfers and exchanges between 8- and 16-bit registers.
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Table 5-2 is a summary of transfer and exchange instructions.
Table 5-2. Transfer and Exchange Instructions
Mnemonic
Function
Operation
Transfer Instructions
TAB
Transfer A to B
(A) ⇒ B
TAP
Transfer A to CCR
(A) ⇒ CCR
TBA
Transfer B to A
(B) ⇒ A
TFR
Transfer register
to register
(A, B, CCR, D, X, Y, or SP) ⇒
A, B, CCR, D, X, Y, or SP
TPA
Transfer CCR to A
(CCR) ⇒ A
TSX
Transfer SP to X
(SP) ⇒ X
TSY
Transfer SP to Y
(SP) ⇒ Y
TXS
Transfer X to SP
(X) ⇒ SP
TYS
Transfer Y to SP
(Y) ⇒ SP
Exchange Instructions
EXG
Exchange register
to register
(A, B, CCR, D, X, Y, or SP) ⇔
(A, B, CCR, D, X, Y, or SP)
XGDX
Exchange D with X
(D) ⇔ (X)
XGDY
Exchange D with Y
(D) ⇔ (Y)
Sign Extension Instruction
Sign extend
8-Bit operand
SEX
Sign-extended (A, B, or CCR) ⇒
D, X, Y, or SP
5.5 Move Instructions
Move instructions move (copy) data bytes or words from a source
(M1 or M : M +11) to a destination (M2 or M : M +12) in memory. Six
combinations of immediate, extended, and indexed addressing are allowed
to specify source and destination addresses (IMM ⇒ EXT,
IMM ⇒ IDX, EXT ⇒ EXT, EXT ⇒ IDX, IDX ⇒ EXT, IDX ⇒ IDX). Addressing
mode combinations with immediate for the destination would not be useful.
Table 5-3 shows byte and word move instructions.
Table 5-3. Move Instructions
Mnemonic
Function
Operation
MOVB
Move byte (8-bit)
(M1) ⇒ M2
MOVW
Move word (16-bit)
(M : M + 11) ⇒ M : M + 12
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5.6 Addition and Subtraction Instructions
Signed and unsigned 8- and 16-bit addition can be performed between
registers or between registers and memory. Special instructions support
index calculation. Instructions that add the carry bit in the condition code
register (CCR) facilitate multiple precision computation.
Signed and unsigned 8- and 16-bit subtraction can be performed between
registers or between registers and memory. Special instructions support
index calculation. Instructions that subtract the carry bit in the CCR facilitate
multiple precision computation. Refer to Table 5-4 for addition and
subtraction instructions.
Load effective address (LEAS, LEAX, and LEAY) instructions could also be
considered as specialized addition and subtraction instructions. See 5.25
Pointer and Index Calculation Instructions for more information.
Table 5-4. Addition and Subtraction Instructions
Mnemonic
Function
Operation
Addition Instructions
ABA
Add B to A
(A) + (B) ⇒ A
ABX
Add B to X
(B) + (X) ⇒ X
ABY
Add B to Y
(B) + (Y) ⇒ Y
ADCA
Add with carry to A
(A) + (M) + C ⇒ A
ADCB
Add with carry to B
(B) + (M) + C ⇒ B
ADDA
Add without carry to A
(A) + (M) ⇒ A
ADDB
Add without carry to B
(B) + (M) ⇒ B
ADDD
Add to D
(A:B) + (M : M + 1) ⇒ A : B
Subtraction Instructions
SBA
Subtract B from A
(A) – (B) ⇒ A
SBCA
Subtract with borrow from A
(A) – (M) – C ⇒ A
SBCB
Subtract with borrow from B
(B) – (M) – C ⇒ B
SUBA
Subtract memory from A
(A) – (M) ⇒ A
SUBB
Subtract memory from B
(B) – (M) ⇒ B
SUBD
Subtract memory from D (A:B)
(D) – (M : M + 1) ⇒ D
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5.7 Binary-Coded Decimal Instructions
To add binary-coded decimal (BCD) operands, use addition instructions that
set the half-carry bit in the CCR, then adjust the result with the decimal
adjust A (DAA) instruction. Table 5-5 is a summary of instructions that can
be used to perform BCD operations.
Table 5-5. BCD Instructions
Mnemonic
Function
Operation
ABA
Add B to A
(A) + (B) ⇒ A
ADCA
Add with carry to A
(A) + (M) + C ⇒ A
ADCB(1)
Add with carry to B
(B) + (M) + C ⇒ B
ADDA(1)
Add memory to A
(A) + (M) ⇒ A
ADDB
Add memory to B
(B) + (M) ⇒ B
DAA
Decimal adjust A
(A)10
1. These instructions are not normally used for BCD operations because, although they affect H
correctly, they do not leave the result in the correct accumulator (A) to be used with the DAA
instruction. Thus additional steps would be needed to adjust the result to correct BCD form.
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5.8 Decrement and Increment Instructions
The decrement and increment instructions are optimized 8- and 16-bit
addition and subtraction operations. They are generally used to implement
counters. Because they do not affect the carry bit in the CCR, they are
particularly well suited for loop counters in multiple-precision computation
routines. Refer to 5.20 Loop Primitive Instructions for information
concerning automatic counter branches. Table 5-6 is a summary of
decrement and increment instructions.
Table 5-6. Decrement and Increment Instructions
Mnemonic
Function
Operation
Decrement Instructions
DEC
Decrement memory
(M) – $01 ⇒ M
DECA
Decrement A
(A) – $01 ⇒ A
DECB
Decrement B
(B) – $01 ⇒ B
DES
Decrement SP
(SP) – $0001 ⇒ SP
DEX
Decrement X
(X) – $0001 ⇒ X
DEY
Decrement Y
(Y) – $0001 ⇒ Y
Increment Instructions
INC
Increment memory
(M) + $01 ⇒ M
INCA
Increment A
(A) + $01 ⇒ A
INCB
Increment B
(B) + $01 ⇒ B
INS
Increment SP
(SP) + $0001 ⇒ SP
INX
Increment X
(X) + $0001 ⇒ X
INY
Increment Y
(Y) + $0001 ⇒ Y
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5.9 Compare and Test Instructions
Compare and test instructions perform subtraction between a pair of
registers or between a register and memory. The result is not stored, but
condition codes are set by the operation. These instructions are generally
used to establish conditions for branch instructions. In this architecture,
most instructions update condition code bits automatically, so it is often
unnecessary to include separate test or compare instructions. Table 5-7 is
a summary of compare and test instructions.
Table 5-7. Compare and Test Instructions
Mnemonic
Function
Operation
Compare Instructions
CBA
Compare A to B
(A) – (B)
CMPA
Compare A to memory
(A) – (M)
CMPB
Compare B to memory
(B) – (M)
CPD
Compare D to memory (16-bit)
(A : B) – (M : M + 1)
CPS
Compare SP to memory (16-bit)
(SP) – (M : M + 1)
CPX
Compare X to memory (16-bit)
(X) – (M : M + 1)
CPY
Compare Y to memory (16-bit)
(Y) – (M : M + 1)
Test Instructions
TST
Test memory for zero or minus
(M) – $00
TSTA
Test A for zero or minus
(A) – $00
TSTB
Test B for zero or minus
(B) – $00
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5.10 Boolean Logic Instructions
The Boolean logic instructions perform a logic operation between an 8-bit
accumulator or the CCR and a memory value. AND, OR, and exclusive OR
functions are supported. Table 5-8 summarizes logic instructions.
Table 5-8. Boolean Logic Instructions
Mnemonic
Function
Operation
ANDA
AND A with memory
(A) • (M) ⇒ A
ANDB
AND B with memory
(B) • (M) ⇒ B
ANDCC
AND CCR with memory (clear CCR bits)
(CCR) • (M) ⇒ CCR
EORA
Exclusive OR A with memory
(A) ⊕ (M) ⇒ A
EORB
Exclusive OR B with memory
(B) ⊕ (M) ⇒ B
ORAA
OR A with memory
(A) + (M) ⇒ A
ORAB
OR B with memory
(B) + (M) ⇒ B
ORCC
OR CCR with memory (set CCR bits)
(CCR) + (M) ⇒ CCR
5.11 Clear, Complement, and Negate Instructions
Each of the clear, complement, and negate instructions performs a specific
binary operation on a value in an accumulator or in memory. Clear
operations clear the value to 0, complement operations replace the value
with its one’s complement, and negate operations replace the value with its
two’s complement. Table 5-9 is a summary of clear, complement, and
negate instructions.
Table 5-9. Clear, Complement, and Negate Instructions
Mnemonic
Function
Operation
CLC
Clear C bit in CCR
0⇒C
CLI
Clear I bit in CCR
0⇒I
CLR
Clear memory
$00 ⇒ M
CLRA
Clear A
$00 ⇒ A
CLRB
Clear B
$00 ⇒ B
CLV
Clear V bit in CCR
0⇒V
COM
One’s complement memory
$FF – (M) ⇒ M or (M) ⇒ M
COMA
One’s complement A
$FF – (A) ⇒ A or (A) ⇒ A
COMB
One’s complement B
$FF – (B) ⇒ B or (B) ⇒ B
NEG
Two’s complement memory
$00 – (M) ⇒ M or (M) + 1 ⇒ M
NEGA
Two’s complement A
$00 – (A) ⇒ A or (A) + 1 ⇒ A
NEGB
Two’s complement B
$00 – (B) ⇒ B or (B) + 1 ⇒ B
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5.12 Multiplication and Division Instructions
There are instructions for signed and unsigned 8- and 16-bit multiplication.
Eight-bit multiplication operations have a 16-bit product. Sixteen-bit
multiplication operations have 32-bit products.
Integer and fractional division instructions have 16-bit dividend, divisor,
quotient, and remainder. Extended division instructions use a 32-bit
dividend and a 16-bit divisor to produce a 16-bit quotient and a 16-bit
remainder.
Table 5-10 is a summary of multiplication and division instructions.
Table 5-10. Multiplication and Division Instructions
Mnemonic
Function
Operation
Multiplication Instructions
EMUL
16 by 16 multiply (unsigned)
(D) × (Y) ⇒ Y : D
EMULS
16 by 16 multiply (signed)
(D) × (Y) ⇒ Y : D
MUL
8 by 8 multiply (unsigned)
(A) × (B) ⇒ A : B
Division Instructions
EDIV
32 by 16 divide (unsigned)
(Y : D) ÷ (X) ⇒ Y
Remainder ⇒ D
EDIVS
32 by 16 divide (signed)
(Y : D) ÷ (X) ⇒ Y
Remainder ⇒ D
FDIV
16 by 16 fractional divide
(D) ÷ (X) ⇒ X
Remainder ⇒ D
IDIV
16 by 16 integer divide (unsigned)
(D) ÷ (X) ⇒ X
Remainder ⇒ D
IDIVS
16 by 16 integer divide (signed)
(D) ÷ (X) ⇒ X
Remainder ⇒ D
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5.13 Bit Test and Manipulation Instructions
The bit test and manipulation operations use a mask value to test or change
the value of individual bits in an accumulator or in memory. Bit test A (BITA)
and bit test B (BITB) provide a convenient means of testing bits without
altering the value of either operand. Table 5-11 is a summary of bit test and
manipulation instructions.
Table 5-11. Bit Test and Manipulation Instructions
Mnemonic
Function
Operation
BCLR
Clear bits in memory
(M) • (mm) ⇒ M
BITA
Bit test A
(A) • (M)
BITB
Bit test B
(B) • (M)
BSET
Set bits in memory
(M) + (mm) ⇒ M
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5.14 Shift and Rotate Instructions
There are shifts and rotates for all accumulators and for memory bytes. All
pass the shifted-out bit through the C status bit to facilitate multiple-byte
operations. Because logical and arithmetic left shifts are identical, there are
no separate logical left shift operations. Logic shift left (LSL) mnemonics are
assembled as arithmetic shift left memory (ASL) operations. Table 5-12
shows shift and rotate instructions.
Table 5-12. Shift and Rotate Instructions
Mnemonic
Function
Operation
Logical Shifts
LSL
LSLA
LSLB
Logic shift left memory
Logic shift left A
Logic shift left B
LSLD
Logic shift left D
LSR
LSRA
LSRB
Logic shift right memory
Logic shift right A
Logic shift right B
LSRD
Logic shift right D
0
C
b7
b7
A
b0
0
C
b0
B
b0
b0
C
b7
0
b7
0
b0
A
b7
b7
b0
B
C
Arithmetic Shifts
ASL
ASLA
ASLB
Arithmetic shift left memory
Arithmetic shift left A
Arithmetic shift left B
ASLD
Arithmetic shift left D
ASR
ASRA
ASRB
Arithmetic shift right memory
Arithmetic shift right A
Arithmetic shift right B
0
b0
b7
C
0
C
b0
b7 A
b7
B
b0
b0
b7
C
Rotates
ROL
ROLA
ROLB
Rotate left memory through carry
Rotate left A through carry
Rotate left B through carry
ROR
RORA
RORB
Rotate right memory through carry
Rotate right A through carry
Rotate right B through carry
b0
b7
C
b7
b0
C
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5.15 Fuzzy Logic Instructions
The CPU12 instruction set includes instructions that support efficient
processing of fuzzy logic operations. The descriptions of fuzzy logic
instructions given here are functional overviews. Table 5-13 summarizes
the fuzzy logic instructions. Refer to Section 9. Fuzzy Logic Support for
detailed discussion.
5.15.1 Fuzzy Logic Membership Instruction
The membership function (MEM) instruction is used during the fuzzification
process. During fuzzification, current system input values are compared
against stored input membership functions to determine the degree to which
each label of each system input is true. This is accomplished by finding the
y value for the current input on a trapezoidal membership function for each
label of each system input. The MEM instruction performs this calculation
for one label of one system input. To perform the complete fuzzification task
for a system, several MEM instructions must be executed, usually in a
program loop structure.
5.15.2 Fuzzy Logic Rule Evaluation Instructions
The MIN-MAX rule evaluation (REV and REVW) instructions perform
MIN-MAX rule evaluations that are central elements of a fuzzy logic
inference program. Fuzzy input values are processed using a list of rules
from the knowledge base to produce a list of fuzzy outputs. The REV
instruction treats all rules as equally important. The REVW instruction
allows each rule to have a separate weighting factor. The two rule
evaluation instructions also differ in the way rules are encoded into the
knowledge base. Because they require a number of cycles to execute, rule
evaluation instructions can be interrupted. Once the interrupt has been
serviced, instruction execution resumes at the point the interrupt occurred.
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5.15.3 Fuzzy Logic Weighted Average Instruction
The weighted average (WAV) instruction computes a sum-of-products and
a sum-of-weights used for defuzzification. To be usable, the fuzzy outputs
produced by rule evaluation must be defuzzified to produce a single output
value which represents the combined effect of all of the fuzzy outputs. Fuzzy
outputs correspond to the labels of a system output and each is defined by
a membership function in the knowledge base. The CPU12 typically uses
singletons for output membership functions rather than the trapezoidal
shapes used for inputs. As with inputs, the x-axis represents the range of
possible values for a system output. Singleton membership functions
consist of the x-axis position for a label of the system output. Fuzzy outputs
correspond to the y-axis height of the corresponding output membership
function. The WAV instruction calculates the numerator and denominator
sums for a weighted average of the fuzzy outputs. Because WAV requires
a number of cycles to execute, it can be interrupted. The WAVR
pseudo-instruction causes execution to resume at the point where it was
interrupted.
Table 5-13. Fuzzy Logic Instructions
Mnemonic
Function
Operation
µ (grade) ⇒ M(Y)
(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged
MEM
Membership
function
if (A) < P1 or (A) > P2, then µ = 0, else
µ = MIN [((A) – P1) × S1, (P2 – (A)) × S2, $FF]
where:
A = current crisp input value
X points to a 4-byte data structure
that describes a trapezoidal membership
function as base intercept
points and slopes (P1, P2, S1, S2)
Y points at fuzzy input (RAM location)
Continued on next page
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Table 5-13. Fuzzy Logic Instructions (Continued)
Mnemonic
Function
Operation
Find smallest rule input (MIN)
Store to rule outputs unless fuzzy output is larger
(MAX)
Rules are unweighted
REV
MIN-MAX rule
evaluation
Each rule input is an 8-bit offset
from a base address in Y
Each rule output is an 8-bit offset
from a base address in Y
$FE separates rule inputs from rule outputs
$FF terminates the rule list
REV can be interrupted
Find smallest rule input (MIN)
Multiply by a rule weighting factor (optional)
Store to rule outputs unless fuzzy output is larger
(MAX)
REVW
MIN-MAX rule
evaluation
Each rule input is the 16-bit address
of a fuzzy input
Each rule output is the 16-bit address
of a fuzzy output
Address $FFFE separates rule inputs
from rule outputs
$FFFF terminates the rule list
Weights are 8-bit values in a separate table
REVW can be interrupted
WAV
WAVR
Calculates numerator
(sum of products)
and denominator
(sum of weights)
for weighted average
calculation
Results are placed in
correct registers
for EDIV immediately
after WAV
Resumes execution
of interrupted WAV
instruction
B
∑ Si Fi ⇒ Y:D
i=1
B
∑ Fi ⇒ X
i=1
Recover immediate results from stack
rather than initializing them to 0.
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5.16 Maximum and Minimum Instructions
The maximum (MAX) and minimum (MIN) instructions are used to make
comparisons between an accumulator and a memory location. These
instructions can be used for linear programming operations, such as
simplex-method optimization, or for fuzzification.
MAX and MIN instructions use accumulator A to perform 8-bit comparisons,
while EMAX and EMIN instructions use accumulator D to perform 16-bit
comparisons. The result (maximum or minimum value) can be stored in the
accumulator (EMAXD, EMIND, MAXA, MINA) or the memory address
(EMAXM, EMINM, MAXM, MINM).
Table 5-14 is a summary of minimum and maximum instructions.
Table 5-14. Minimum and Maximum Instructions
Mnemonic
Function
Operation
Minimum Instructions
EMIND
MIN of two unsigned 16-bit values
result to accumulator
MIN ((D), (M : M + 1)) ⇒ D
EMINM
MIN of two unsigned 16-bit values
result to memory
MIN ((D), (M : M + 1)) ⇒ M : M+1
MINA
MIN of two unsigned 8-bit values
result to accumulator
MIN ((A), (M)) ⇒ A
MINM
MIN of two unsigned 8-bit values
result to memory
MIN ((A), (M)) ⇒ M
Maximum Instructions
EMAXD
MAX of two unsigned 16-bit values
result to accumulator
MAX ((D), (M : M + 1)) ⇒ D
EMAXM
MAX of two unsigned 16-bit values
result to memory
MAX ((D), (M : M + 1)) ⇒ M : M + 1
MAXA
MAX of two unsigned 8-bit values
result to accumulator
MAX ((A), (M)) ⇒ A
MAXM
MAX of two unsigned 8-bit values
result to memory
MAX ((A), (M)) ⇒ M
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5.17 Multiply and Accumulate Instruction
The multiply and accumulate (EMACS) instruction multiplies two 16-bit
operands stored in memory and accumulates the 32-bit result in a third
memory location. EMACS can be used to implement simple digital filters
and defuzzification routines that use 16-bit operands. The WAV instruction
incorporates an 8- to 16-bit multiply and accumulate operation that obtains
a numerator for the weighted average calculation. The EMACS instruction
can automate this portion of the averaging operation when 16-bit operands
are used. Table 5-15 shows the EMACS instruction.
Table 5-15. Multiply and Accumulate Instructions
Mnemonic
Function
Operation
EMACS
Multiply and accumulate (signed)
16 bit by 16 bit ⇒ 32 bit
((M(X):M(X+1)) × (M(Y):M(Y+1)))
+ (M ~ M + 3) ⇒ M ~ M + 3
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5.18 Table Interpolation Instructions
The table interpolation instructions (TBL and ETBL) interpolate values from
tables stored in memory. Any function that can be represented as a series
of linear equations can be represented by a table of appropriate size.
Interpolation can be used for many purposes, including tabular fuzzy logic
membership functions. TBL uses 8-bit table entries and returns an 8-bit
result; ETBL uses 16-bit table entries and returns a 16-bit result. Use of
indexed addressing mode provides great flexibility in structuring tables.
Consider each of the successive values stored in a table to be y-values for
the endpoint of a line segment. The value in the B accumulator before
instruction execution begins represents the change in x from the beginning
of the line segment to the lookup point divided by total change in x from the
beginning to the end of the line segment. B is treated as an 8-bit binary
fraction with radix point left of the MSB, so each line segment is effectively
divided into 256 smaller segments. During instruction execution, the change
in y between the beginning and end of the segment (a signed byte for TBL
or a signed word for ETBL) is multiplied by the content of the B accumulator
to obtain an intermediate delta-y term. The result (stored in the A
accumulator by TBL, and in the D accumulator by ETBL) is the y-value of
the beginning point plus the signed intermediate delta-y value. Table 5-16
shows the table interpolation instructions.
Table 5-16. Table Interpolation Instructions
Mnemonic
Function
Operation
ETBL
16-bit table lookup
and interpolate
(no indirect addressing
modes allowed)
(M : M + 1) + [(B) × ((M + 2 : M + 3)
– (M : M + 1))] ⇒ D
Initialize B, and index before ETBL.
<ea> points to the first table entry (M : M + 1)
B is fractional part of lookup value
TBL
8-bit table lookup
and interpolate
(no indirect addressing
modes allowed)
(M) + [(B) × ((M + 1) – (M))] ⇒ A
Initialize B, and index before TBL.
<ea> points to the first 8-bit table entry (M)
B is fractional part of lookup value.
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5.19 Branch Instructions
Branch instructions cause a sequence to change when specific conditions
exist. The CPU12 uses three kinds of branch instructions. These are short
branches, long branches, and bit condition branches.
Branch instructions can also be classified by the type of condition that must
be satisfied in order for a branch to be taken. Some instructions belong to
more than one classification. For example:
•
Unary branch instructions always execute.
•
Simple branches are taken when a specific bit in the condition code
register is in a specific state as a result of a previous operation.
•
Unsigned branches are taken when comparison or test of unsigned
quantities results in a specific combination of condition code register
bits.
•
Signed branches are taken when comparison or test of signed
quantities results in a specific combination of condition code register
bits.
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5.19.1 Short Branch Instructions
Short branch instructions operate this way: When a specified condition is
met, a signed 8-bit offset is added to the value in the program counter.
Program execution continues at the new address.
The numeric range of short branch offset values is $80 (–128) to $7F (127)
from the address of the next memory location after the offset value.
Table 5-17 is a summary of the short branch instructions.
Table 5-17. Short Branch Instructions
Mnemonic
Function
Equation or Operation
Unary Branches
BRA
Branch always
1=1
BRN
Branch never
1=0
Simple Branches
BCC
Branch if carry clear
C=0
BCS
Branch if carry set
C=1
BEQ
Branch if equal
Z=1
BMI
Branch if minus
N=1
BNE
Branch if not equal
Z=0
BPL
Branch if plus
N=0
BVC
Branch if overflow clear
V=0
BVS
Branch if overflow set
V=1
Unsigned Branches
Relation
BHI
Branch if higher
R>M
C+Z=0
BHS
Branch if higher or same
R≥M
C=0
BLO
Branch if lower
R<M
C=1
BLS
Branch if lower or same
R≤M
C+Z=1
Signed Branches
BGE
Branch if greater than or equal
R≥M
N⊕V=0
BGT
Branch if greater than
R>M
Z + (N ⊕ V) = 0
BLE
Branch if less than or equal
R≤M
Z + (N ⊕ V) = 1
BLT
Branch if less than
R<M
N⊕V=1
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5.19.2 Long Branch Instructions
Long branch instructions operate this way: When a specified condition is
met, a signed 16-bit offset is added to the value in the program counter.
Program execution continues at the new address. Long branches are used
when large displacements between decision-making steps are necessary.
The numeric range of long branch offset values is $8000 (–32,768) to $7FFF
(32,767) from the address of the next memory location after the offset value.
This permits branching from any location in the standard 64-Kbyte address
map to any other location in the 64-Kbyte map.
Table 5-18 is a summary of the long branch instructions.
Table 5-18. Long Branch Instructions
Mnemonic
Function
Equation or Operation
Unary Branches
LBRA
Long branch always
1=1
LBRN
Long branch never
1=0
Simple Branches
LBCC
Long branch if carry clear
C=0
LBCS
Long branch if carry set
C=1
LBEQ
Long branch if equal
Z=1
LBMI
Long branch if minus
N=1
LBNE
Long branch if not equal
Z=0
LBPL
Long branch if plus
N=0
LBVC
Long branch if overflow clear
V=0
LBVS
Long branch if overflow set
V=1
Unsigned Branches
LBHI
Long branch if higher
C+Z=0
LBHS
Long branch if higher or same
C=0
LBLO
Long branch if lower
Z=1
LBLS
Long branch if lower or same
C+Z=1
Signed Branches
LBGE
Long branch if greater than or equal
N⊕V=0
LBGT
Long branch if greater than
Z + (N ⊕ V) = 0
LBLE
Long branch if less than or equal
Z + (N ⊕ V) = 1
LBLT
Long branch if less than
N⊕V=1
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5.19.3 Bit Condition Branch Instructions
The bit condition branches are taken when bits in a memory byte are in a
specific state. A mask operand is used to test the location. If all bits in that
location that correspond to ones in the mask are set (BRSET) or cleared
(BRCLR), the branch is taken.
The numeric range of 8-bit offset values is $80 (–128) to $7F (127)
from the address of the next memory location after the offset value.
Table 5-19 is a summary of bit condition branches.
Table 5-19. Bit Condition Branch Instructions
Mnemonic
Function
Equation or Operation
BRCLR
Branch if selected bits clear
(M) • (mm) = 0
BRSET
Branch if selected bits set
(M) • (mm) = 0
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5.20 Loop Primitive Instructions
The loop primitives can also be thought of as counter branches. The
instructions test a counter value in a register or accumulator (A, B, D, X, Y,
or SP) for zero or non-zero value as a branch condition. There are
predecrement, preincrement, and test-only versions of these instructions.
The numeric range of 9-bit offset values is $100 (–256) to $0FF (255)
from the address of the next memory location after the offset value.
Table 5-20 is a summary of loop primitive branches.
Table 5-20. Loop Primitive Instructions
Mnemonic
Function
Equation or Operation
DBEQ
Decrement counter and branch if = 0
(counter = A, B, D, X, Y, or SP)
(counter) – 1⇒ counter
If (counter) = 0, then branch;
else continue to next instruction
DBNE
Decrement counter and branch if ≠ 0
(counter = A, B, D, X, Y, or SP)
(counter) – 1⇒ counter
If (counter) not = 0, then branch;
else continue to next instruction
IBEQ
Increment counter and branch if = 0
(counter = A, B, D, X, Y, or SP)
(counter) + 1⇒ counter
If (counter) = 0, then branch;
else continue to next instruction
IBNE
Increment counter and branch if ≠ 0
(counter = A, B, D, X, Y, or SP)
(counter) + 1⇒ counter
If (counter) not = 0, then branch;
else continue to next instruction
TBEQ
Test counter and branch if = 0
(counter = A, B, D, X,Y, or SP)
If (counter) = 0, then branch;
else continue to next instruction
TBNE
Test counter and branch if ≠ 0
(counter = A, B, D, X,Y, or SP)
If (counter) not = 0, then branch;
else continue to next instruction
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5.21 Jump and Subroutine Instructions
Jump (JMP) instructions cause immediate changes in sequence. The JMP
instruction loads the PC with an address in the 64-Kbyte memory map, and
program execution continues at that address. The address can be provided
as an absolute 16-bit address or determined by various forms of indexed
addressing.
Subroutine instructions optimize the process of transferring control to a
code segment that performs a particular task. A short branch (BSR), a jump
to subroutine (JSR), or an expanded-memory call (CALL) can be used to
initiate subroutines. There is no LBSR instruction, but a PC-relative JSR
performs the same function. A return address is stacked, then execution
begins at the subroutine address. Subroutines in the normal 64-Kbyte
address space are terminated with a return-from-subroutine (RTS)
instruction. RTS unstacks the return address so that execution resumes
with the instruction after BSR or JSR.
The call subroutine in expanded memory (CALL) instruction is intended for
use with expanded memory. CALL stacks the value in the PPAGE register
and the return address, then writes a new value to PPAGE to select the
memory page where the subroutine resides. The page value is an
immediate operand in all addressing modes except indexed indirect modes;
in these modes, an operand points to locations in memory where the new
page value and subroutine address are stored. The return from call (RTC)
instruction is used to terminate subroutines in expanded memory. RTC
unstacks the PPAGE value and the return address so that execution
resumes with the next instruction after CALL. For software compatibility,
CALL and RTC execute correctly on devices that do not have expanded
addressing capability. Table 5-21 summarizes the jump and subroutine
instructions.
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Table 5-21. Jump and Subroutine Instructions
Mnemonic
Function
Operation
BSR
Branch to subroutine
SP – 2 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP+1)
Subroutine address ⇒ PC
CALL
Call subroutine
in expanded memory
SP – 2 ⇒ SP
RTNH:RTNL⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP
(PPAGE) ⇒ M(SP)
Page ⇒ PPAGE
Subroutine address ⇒ PC
JMP
Jump
Address ⇒ PC
JSR
Jump to subroutine
SP – 2 ⇒ SP
RTNH : RTNL⇒ M(SP) : M(SP+1)
Subroutine address ⇒ PC
RTC
Return from call
M(SP) ⇒ PPAGE
SP + 1 ⇒ SP
M(SP) : M(SP+1) ⇒ PCH : PCL
SP + 2 ⇒ SP
RTS
Return from subroutine
M(SP) : M(SP+1) ⇒ PCH : PCL
SP + 2 ⇒ SP
5.22 Interrupt Instructions
Interrupt instructions handle transfer of control to a routine that performs a
critical task. Software interrupts are a type of exception. Section 7.
Exception Processing covers interrupt exception processing in detail.
The software interrupt (SWI) instruction initiates synchronous exception
processing. First, the return PC value is stacked. After CPU context is
stacked, execution continues at the address pointed to by the SWI vector.
Execution of the SWI instruction causes an interrupt without an interrupt
service request. SWI is not inhibited by global mask bits I and X in the CCR,
and execution of SWI sets the I mask bit. Once an SWI interrupt begins,
maskable interrupts are inhibited until the I bit in the CCR is cleared. This
typically occurs when a return from interrupt (RTI) instruction at the end of
the SWI service routine restores context.
The CPU12 uses a variation of the software interrupt for unimplemented
opcode trapping. There are opcodes in all 256 positions in the page 1
opcode map, but only 54 of the 256 positions on page 2 of the opcode map
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are used. If the CPU attempts to execute one of the unimplemented
opcodes on page 2, an opcode trap interrupt occurs. Traps are essentially
interrupts that share the $FFF8:$FFF9 interrupt vector.
The RTI instruction is used to terminate all exception handlers, including
interrupt service routines. RTI first restores the CCR, B:A, X, Y, and the
return address from the stack. If no other interrupt is pending, normal
execution resumes with the instruction following the last instruction that
executed prior to interrupt.
Table 5-22 is a summary of interrupt instructions.
Table 5-22. Interrupt Instructions
Mnemonic
RTI
SWI
TRAP
Function
Operation
Return
from interrupt
(M(SP)) ⇒ CCR; (SP) + $0001 ⇒ SP
(M(SP) : M(SP+1)) ⇒ B : A; (SP) + $0002 ⇒ SP
(M(SP) : M(SP+1)) ⇒ XH : XL; (SP) + $0004 ⇒ SP
(M(SP) : M(SP+1)) ⇒ PCH : PCL; (SP) + $0002 ⇒ SP
(M(SP) : M(SP+1)) ⇒ YH : YL; (SP) + $0004 ⇒ SP
Software interrupt
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
Unimplemented
opcode interrupt
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
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5.23 Index Manipulation Instructions
The index manipulation instructions perform 8- and 16-bit operations on the
three index registers and accumulators, other registers, or memory, as
shown in Table 5-23.
Table 5-23. Index Manipulation Instructions
Mnemonic
Function
Operation
Addition Instructions
ABX
Add B to X
(B) + (X) ⇒ X
ABY
Add B to Y
(B) + (Y) ⇒ Y
Compare Instructions
CPS
Compare SP to memory
(SP) – (M : M + 1)
CPX
Compare X to memory
(X) – (M : M + 1)
CPY
Compare Y to memory
(Y) – (M : M + 1)
Load Instructions
LDS
Load SP from memory
M : M+1 ⇒ SP
LDX
Load X from memory
(M : M + 1) ⇒ X
LDY
Load Y from memory
(M : M + 1) ⇒ Y
LEAS
Load effective address into SP
Effective address ⇒ SP
LEAX
Load effective address into X
Effective address ⇒ X
LEAY
Load effective address into Y
Effective address ⇒ Y
Store Instructions
STS
Store SP in memory
(SP) ⇒ M:M+1
STX
Store X in memory
(X) ⇒ M : M + 1
STY
Store Y in memory
(Y) ⇒ M : M + 1
Transfer Instructions
TFR
Transfer register to register
(A, B, CCR, D, X, Y, or SP)
⇒ A, B, CCR, D, X, Y, or SP
TSX
Transfer SP to X
(SP) ⇒ X
TSY
Transfer SP to Y
(SP) ⇒ Y
TXS
transfer X to SP
(X) ⇒ SP
TYS
transfer Y to SP
(Y) ⇒ SP
Exchange Instructions
EXG
Exchange register to register
(A, B, CCR, D, X, Y, or SP)
⇔ (A, B, CCR, D, X, Y, or SP)
XGDX
EXchange D with X
(D) ⇔ (X)
XGDY
EXchange D with Y
(D) ⇔ (Y)
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5.24 Stacking Instructions
The two types of stacking instructions, are shown in Table 5-24. Stack
pointer instructions use specialized forms of mathematical and data transfer
instructions to perform stack pointer manipulation. Stack operation
instructions save information on and retrieve information from the system
stack.
Table 5-24. Stacking Instructions
Mnemonic
Function
Operation
Stack Pointer Instructions
CPS
Compare SP to memory
(SP) – (M : M + 1)
DES
Decrement SP
(SP) – 1 ⇒ SP
INS
Increment SP
(SP) + 1 ⇒ SP
LDS
Load SP
(M : M + 1) ⇒ SP
LEAS
Load effective address
into SP
Effective address ⇒ SP
STS
Store SP
(SP) ⇒ M : M + 1
TSX
Transfer SP to X
(SP) ⇒ X
TSY
Transfer SP to Y
(SP) ⇒ Y
TXS
Transfer X to SP
(X) ⇒ SP
TYS
Transfer Y to SP
(Y) ⇒ SP
Stack Operation Instructions
PSHA
Push A
(SP) – 1 ⇒ SP; (A) ⇒ M(SP)
PSHB
Push B
(SP) – 1 ⇒ SP; (B) ⇒ M(SP)
PSHC
Push CCR
(SP) – 1 ⇒ SP; (A) ⇒ M(SP)
PSHD
Push D
(SP) – 2 ⇒ SP; (A : B) ⇒ M(SP) : M(SP+1)
PSHX
Push X
(SP) – 2 ⇒ SP; (X) ⇒ M(SP) : M(SP+1)
PSHY
Push Y
(SP) – 2 ⇒ SP; (Y) ⇒ M(SP) : M(SP+1)
PULA
Pull A
(M(SP)) ⇒ A; (SP) + 1 ⇒ SP
PULB
Pull B
(M(SP)) ⇒ B; (SP) + 1 ⇒ SP
PULC
Pull CCR
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
PULD
Pull D
(M(SP) : M(SP+1)) ⇒ A : B; (SP) + 2 ⇒ SP
PULX
Pull X
(M(SP) : M(SP+1)) ⇒ X; (SP) + 2 ⇒ SP
PULY
Pull Y
(M(SP) : M(SP+1)) ⇒ Y; (SP) + 2 ⇒ SP
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5.25 Pointer and Index Calculation Instructions
The load effective address instructions allow 5-, 8-, or 16-bit constants or the
contents of 8-bit accumulators A and B or 16-bit accumulator D to be added
to the contents of the X and Y index registers, or to the SP.
Table 5-25 is a summary of pointer and index instructions.
Table 5-25. Pointer and Index Calculation Instructions
Mnemonic
Function
Operation
LEAS
Load result of indexed addressing mode
effective address calculation
into stack pointer
r ± constant ⇒ SP or
(r) + (accumulator) ⇒ SP
r = X, Y, SP, or PC
LEAX
Load result of indexed addressing mode
effective address calculation
into x index register
r ± constant ⇒X or
(r) + (accumulator) ⇒X
r = X, Y, SP, or PC
LEAY
Load result of indexed addressing mode
effective address calculation
into y index register
r ± constant ⇒Y or
(r) + (accumulator) ⇒ Y
r = X, Y, SP, or PC
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5.26 Condition Code Instructions
Condition code instructions are special forms of mathematical and data
transfer instructions that can be used to change the condition code register.
Table 5-26 shows instructions that can be used to manipulate the CCR.
Table 5-26. Condition Code Instructions
Mnemonic
Function
Operation
ANDCC
Logical AND CCR with memory
(CCR) • (M) ⇒ CCR
CLC
Clear C bit
0⇒C
CLI
Clear I bit
0⇒I
CLV
Clear V bit
0⇒V
ORCC
Logical OR CCR with memory
(CCR) + (M) ⇒ CCR
PSHC
Push CCR onto stack
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
PULC
Pull CCR from stack
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
SEC
Set C bit
1⇒C
SEI
Set I bit
1⇒I
SEV
Set V bit
1⇒V
TAP
Transfer A to CCR
(A) ⇒ CCR
TPA
Transfer CCR to A
(CCR) ⇒ A
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5.27 Stop and Wait Instructions
As shown in Table 5-27, two instructions put the CPU12 in an inactive state
that reduces power consumption.
The stop instruction (STOP) stacks a return address and the contents of
CPU registers and accumulators, then halts all system clocks.
The wait instruction (WAI) stacks a return address and the contents of CPU
registers and accumulators, then waits for an interrupt service request;
however, system clock signals continue to run.
Both STOP and WAI require that either an interrupt or a reset exception
occur before normal execution of instructions resumes. Although both
instructions require the same number of clock cycles to resume normal
program execution after an interrupt service request is made, restarting
after a STOP requires extra time for the oscillator to reach operating speed.
Table 5-27. Stop and Wait Instructions
Mnemonic
STOP
WAI
Function
Operation
Stop
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
Stop CPU clocks
Wait for interrupt
SP – 2 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; YH : YL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; XH : XL ⇒ M(SP) : M(SP+1)
SP – 2 ⇒ SP; B : A ⇒ M(SP) : M(SP+1)
SP – 1 ⇒ SP; CCR ⇒ M(SP)
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5.28 Background Mode and Null Operations
Background debug mode (BDM) is a special CPU12 operating mode that is
used for system development and debugging. Executing enter background
debug mode (BGND) when BDM is enabled puts the CPU12 in this mode.
For complete information, refer to Section 8. Instruction Queue.
Null operations are often used to replace other instructions during software
debugging. Replacing conditional branch instructions with branch never
(BRN), for instance, permits testing a decision-making routine by disabling
the conditional branch without disturbing the offset value.
Null operations can also be used in software delay programs to consume
execution time without disturbing the contents of other CPU registers or
memory.
Table 5-28 shows the BGND and null operation (NOP) instructions.
Table 5-28. Background Mode and Null Operation Instructions
Mnemonic
Function
Operation
BGND
Enter background debug mode
If BDM enabled, enter BDM;
else resume normal processing
BRN
Branch never
Does not branch
LBRN
Long branch never
Does not branch
NOP
Null operation
—
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Reference Manual — S12CPUV2
Section 6. Instruction Glossary
6.1 Introduction
This section is a comprehensive reference to the CPU12 instruction set.
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6.2 Glossary Information
The glossary contains an entry for each assembler mnemonic, in alphabetic
order. Figure 6-1 is a representation of a glossary page.
MNEMONIC
LDX
Operation:
SYMBOLIC DESCRIPTION
OF OPERATION
Description:
DETAILED DESCRIPTION
OF OPERATION
CCR Details:
Load Index Regi
(M : M+1) ⇒ X
Loads the most significa
memory at the addres
content of the next b
S
X
H
—
—
—
N: Set if MSB of resu
Z: Set if result is $00
V: 0; Cleared.
EFFECT ON
CONDITION CODE REGISTER
STATUS BITS
Source Form
DETAILED SYNTAX
AND CYCLE-BY-CYCLE
OPERATION
Address Mode
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CE
DE
FE
EE
EE
EE
EE
EE
jj
dd
hh
xb
xb
xb
xb
xb
Figure 6-1. Example Glossary Page
Each entry contains symbolic and textual descriptions of operation,
information concerning the effect of operation on status bits in the condition
code register, and a table that describes assembler syntax, address mode
variations, and cycle-by-cycle execution of the instruction.
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6.3 Condition Code Changes
The following special characters are used to describe the effects of
instruction execution on the status bits in the condition code register.
–
0
1
∆
⇓
—
—
—
—
—
Status bit not affected by operation
Status bit cleared by operation
Status bit set by operation
Status bit affected by operation
Status bit may be cleared or remain set, but is not set
by operation.
⇑ — Status bit may be set or remain cleared, but is not
cleared by operation.
? — Status bit may be changed by operation, but the final
state is not defined.
! — Status bit used for a special purpose
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6.4 Object Code Notation
The digits 0 to 9 and the uppercase letters A to F are used to express
hexadecimal values. Pairs of lowercase letters represent the 8-bit values as
described here.
dd — 8-bit direct address $0000 to $00FF; high byte
assumed to be $00
ee — High-order byte of a 16-bit constant offset for indexed
addressing
eb — Exchange/transfer post-byte
ff — Low-order eight bits of a 9-bit signed constant offset
for indexed addressing, or low-order byte of a 16-bit
constant offset for indexed addressing
hh — High-order byte of a 16-bit extended address
ii — 8-bit immediate data value
jj — High-order byte of a 16-bit immediate data value
kk — Low-order byte of a 16-bit immediate data value
lb — Loop primitive (DBNE) post-byte
ll — Low-order byte of a 16-bit extended address
mm — 8-bit immediate mask value for bit manipulation
instructions; set bits indicate bits to be affected
pg — Program overlay page (bank) number used in CALL
instruction
qq — High-order byte of a 16-bit relative offset for long
branches
tn — Trap number $30–$39 or $40–$FF
rr — Signed relative offset $80 (–128) to $7F (+127)
offset relative to the byte following the relative offset
byte, or low-order byte of a 16-bit relative offset for
long branches
xb — Indexed addressing post-byte
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6.5 Source Forms
The glossary pages provide only essential information about assembler
source forms. Assemblers generally support a number of assembler
directives, allow definition of program labels, and have special conventions
for comments. For complete information about writing source files for a
particular assembler, refer to the documentation provided by the assembler
vendor.
Assemblers are typically flexible about the use of spaces and tabs. Often,
any number of spaces or tabs can be used where a single space is shown
on the glossary pages. Spaces and tabs are also normally allowed before
and after commas. When program labels are used, there must also be at
least one tab or space before all instruction mnemonics. This required
space is not apparent in the source forms.
Everything in the source forms columns, except expressions in italic
characters, is literal information which must appear in the assembly source
file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal
expression. All commas, pound signs (#), parentheses, square brackets ( [
or ] ), plus signs (+), minus signs (–), and the register designation D (as in
[D,... ), are literal characters.
Groups of italic characters in the columns represent variable information to
be supplied by the programmer. These groups can include any
alphanumeric character or the underscore character, but cannot include a
space or comma. For example, the groups xysp and oprx0_xysp are both
valid, but the two groups oprx0 xysp are not valid because there is a space
between them. Permitted syntax is described here.
The definition of a legal label or expression varies from assembler to
assembler. Assemblers also vary in the way CPU registers are specified.
Refer to assembler documentation for detailed information. Recommended
register designators are a, A, b, B, ccr, CCR, d, D, x, X, y, Y, sp, SP, pc, and
PC.
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abc — Any one legal register designator for accumulators A or
B or the CCR
abcdxys — Any one legal register designator for accumulators A or
B, the CCR, the double accumulator D, index registers X
or Y, or the SP. Some assemblers may accept t2, T2, t3,
or T3 codes in certain cases of transfer and exchange
instructions, but these forms are intended for Freescale
use only.
abd — Any one legal register designator for accumulators A or
B or the double accumulator D
abdxys — Any one legal register designator for accumulators A or
B, the double accumulator D, index register X or Y, or the
SP
dxys — Any one legal register designation for the double
accumulator D, index registers X or Y, or the SP
msk8 — Any label or expression that evaluates to an 8-bit value.
Some assemblers require a # symbol before this value.
opr8i — Any label or expression that evaluates to an 8-bit
immediate value
opr16i — Any label or expression that evaluates to a 16-bit
immediate value
opr8a — Any label or expression that evaluates to an 8-bit value.
The instruction treats this 8-bit value as the low-order 8
bits of an address in the direct page of the 64-Kbyte
address space ($00xx).
opr16a — Any label or expression that evaluates to a 16-bit value.
The instruction treats this value as an address in the
64-Kbyte address space.
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oprx0_xysp — This word breaks down into one of the following
alternative forms that assemble to an 8-bit indexed
addressing postbyte code. These forms generate the
same object code except for the value of the postbyte
code, which is designated as xb in the object code
columns of the glossary pages. As with the source
forms, treat all commas, plus signs, and minus signs as
literal syntax elements. The italicized words used in
these forms are included in this key.
oprx5,xysp
oprx3,–xys
oprx3,+xys
oprx3,xys–
oprx3,xys+
abd,xysp
oprx3 — Any label or expression that evaluates to a value in the
range +1 to +8
oprx5 — Any label or expression that evaluates to a 5-bit value in
the range –16 to +15
oprx9 — Any label or expression that evaluates to a 9-bit value in
the range –256 to +255
oprx16 — Any label or expression that evaluates to a 16-bit value.
Since the CPU12 has a 16-bit address bus, this can be
either a signed or an unsigned value.
page — Any label or expression that evaluates to an 8-bit value.
The CPU12 recognizes up to an 8-bit page value for
memory expansion but not all MCUs that include the
CPU12 implement all of these bits. It is the
programmer’s responsibility to limit the page value to
legal values for the intended MCU system. Some
assemblers require a # symbol before this value.
rel8 — Any label or expression that refers to an address that is
within –128 to +127 locations from the next address after
the last byte of object code for the current instruction.
The assembler will calculate the 8-bit signed offset and
include it in the object code for this instruction.
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rel9 — Any label or expression that refers to an address that is
within –256 to +255 locations from the next address after
the last byte of object code for the current instruction.
The assembler will calculate the 9-bit signed offset and
include it in the object code for this instruction. The sign
bit for this 9-bit value is encoded by the assembler as a
bit in the looping postbyte (lb) of one of the loop control
instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or
TBNE. The remaining eight bits of the offset are included
as an extra byte of object code.
rel16 — Any label or expression that refers to an address
anywhere in the 64-Kbyte address space. The
assembler will calculate the 16-bit signed offset between
this address and the next address after the last byte of
object code for this instruction and include it in the object
code for this instruction.
trapnum — Any label or expression that evaluates to an 8-bit
number in the range $30–$39 or $40–$FF. Used for
TRAP instruction.
xys — Any one legal register designation for index registers X
or Y or the SP
xysp — Any one legal register designation for index registers X
or Y, the SP, or the PC. The reference point for
PC-relative instructions is the next address after the last
byte of object code for the current instruction.
6.6 Cycle-by-Cycle Execution
This information is found in the tables at the bottom of each instruction
glossary page. Entries show how many bytes of information are accessed
from different areas of memory during the course of instruction execution.
With this information and knowledge of the type and speed of memory in the
system, a user can determine the execution time for any instruction in any
system.
A single letter code in the column represents a single CPU cycle. Uppercase
letters indicate 16-bit access cycles. There are cycle codes for each
addressing mode variation of each instruction. Simply count code letters to
determine the execution time of an instruction in a best-case system. An
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example of a best-case system is a single-chip 16-bit system with no 16-bit
off-boundary data accesses to any locations other than on-chip RAM.
Many conditions can cause one or more instruction cycles to be stretched,
but the CPU is not aware of the stretch delays because the clock to the CPU
is temporarily stopped during these delays.
The following paragraphs explain the cycle code letters used and note
conditions that can cause each type of cycle to be stretched.
f — Free cycle. This indicates a cycle where the CPU
does not require use of the system buses. An f cycle
is always one cycle of the system bus clock. These
cycles can be used by a queue controller or the
background debug system to perform single cycle
accesses without disturbing the CPU.
g — Read 8-bit PPAGE register. These cycles are used
only with the CALL instruction to read the current
value of the PPAGE register and are not visible on the
external bus. Since the PPAGE register is an internal
8-bit register, these cycles are never stretched.
I — Read indirect pointer. Indexed indirect instructions
use this 16-bit pointer from memory to address the
operand for the instruction. These are always 16-bit
reads but they can be either aligned or misaligned.
These cycles are extended to two bus cycles if the
MCU is operating with an 8-bit external data bus and
the corresponding data is stored in external memory.
There can be additional stretching when the address
space is assigned to a chip-select circuit programmed
for slow memory. These cycles are also stretched if
they correspond to misaligned access to a memory
that is not designed for single-cycle misaligned
access.
i — Read indirect PPAGE value. These cycles are only
used with indexed indirect versions of the CALL
instruction, where the 8-bit value for the memory
expansion page register of the CALL destination is
fetched from an indirect memory location. These
cycles are stretched only when controlled by a
chip-select circuit that is programmed for slow
memory.
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n — Write 8-bit PPAGE register. These cycles are used
only with the CALL and RTC instructions to write the
destination value of the PPAGE register and are not
visible on the external bus. Since the PPAGE register
is an internal 8-bit register, these cycles are never
stretched.
O — Optional cycle. Program information is always fetched
as aligned 16-bit words. When an instruction consists
of an odd number of bytes, and the first byte is
misaligned, an O cycle is used to make an additional
program word access (P) cycle that maintains queue
order. In all other cases, the O cycle appears as a free
(f) cycle. The $18 prebyte for page two opcodes is
treated as a special 1-byte instruction. If the prebyte is
misaligned, the O cycle is used as a program word
access for the prebyte; if the prebyte is aligned, the O
cycle appears as a free cycle. If the remainder of the
instruction consists of an odd number of bytes,
another O cycle is required some time before the
instruction is completed. If the O cycle for the prebyte
is treated as a P cycle, any subsequent O cycle in the
same instruction is treated as an f cycle; if the O cycle
for the prebyte is treated as an f cycle, any
subsequent O cycle in the same instruction is treated
as a P cycle. Optional cycles used for program word
accesses can be extended to two bus cycles if the
MCU is operating with an 8-bit external data bus and
the program is stored in external memory. There can
be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow
memory. Optional cycles used as free cycles are
never stretched.
P — Program word access. Program information is fetched
as aligned 16-bit words. These cycles are extended to
two bus cycles if the MCU is operating with an 8-bit
external data bus and the program is stored
externally. There can be additional stretching when
the address space is assigned to a chip-select circuit
programmed for slow memory.
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r — 8-bit data read. These cycles are stretched only when
controlled by a chip-select circuit programmed for
slow memory.
R — 16-bit data read. These cycles are extended to two
bus cycles if the MCU is operating with an 8-bit
external data bus and the corresponding data is
stored in external memory. There can be additional
stretching when the address space is assigned to a
chip-select circuit programmed for slow memory.
These cycles are also stretched if they correspond to
misaligned accesses to memory that is not designed
for single-cycle misaligned access.
s — Stack 8-bit data. These cycles are stretched only
when controlled by a chip-select circuit programmed
for slow memory.
S — Stack 16-bit data. These cycles are extended to two
bus cycles if the MCU is operating with an 8-bit
external data bus and the SP is pointing to external
memory. There can be additional stretching if the
address space is assigned to a chip-select circuit
programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses
to a memory that is not designed for single cycle
misaligned access. The internal RAM is designed to
allow single cycle misaligned word access.
w — 8-bit data write. These cycles are stretched only when
controlled by a chip-select circuit programmed for
slow memory.
W — 16-bit data write. These cycles are extended to two
bus cycles if the MCU is operating with an 8-bit
external data bus and the corresponding data is
stored in external memory. There can be additional
stretching when the address space is assigned to a
chip-select circuit programmed for slow memory.
These cycles are also stretched if they correspond to
misaligned access to a memory that is not designed
for single-cycle misaligned access.
u — Unstack 8-bit data. These cycles are stretched only
when controlled by a chip-select circuit programmed
for slow memory.
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97
U — Unstack 16-bit data. These cycles are extended to two
bus cycles if the MCU is operating with an 8-bit
external data bus and the SP is pointing to external
memory. There can be additional stretching when the
address space is assigned to a chip-select circuit
programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses
to a memory that is not designed for single-cycle
misaligned access. The internal RAM is designed to
allow single-cycle misaligned word access.
V — Vector fetch. Vectors are always aligned 16-bit words.
These cycles are extended to two bus cycles if the
MCU is operating with an 8-bit external data bus and
the program is stored in external memory. There can
be additional stretching when the address space is
assigned to a chip-select circuit programmed for slow
memory.
t — 8-bit conditional read. These cycles are either data
read cycles or unused cycles, depending on the data
and flow of the REVW instruction. These cycles are
stretched only when controlled by a chip-select circuit
programmed for slow memory.
T — 16-bit conditional read. These cycles are either data
read cycles or free cycles, depending on the data and
flow of the REV or REVW instruction. These cycles
are extended to two bus cycles if the MCU is operating
with an 8-bit external data bus and the corresponding
data is stored in external memory. There can be
additional stretching when the address space is
assigned to a chip-select circuit programmed for slow
memory. These cycles are also stretched if they
correspond to misaligned accesses to a memory that
is not designed for single-cycle misaligned access.
x — 8-bit conditional write. These cycles are either data
write cycles or free cycles, depending on the data and
flow of the REV or REVW instruction. These cycles
are only stretched when controlled by a chip-select
circuit programmed for slow memory.
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Special Notation for Branch Taken/Not Taken Cases
PPP/P — Short branches require three cycles if taken, one cycle
if not taken. Since the instruction consists of a single
word containing both an opcode and an 8-bit offset,
the not-taken case is simple — the queue advances,
another program word fetch is made, and execution
continues with the next instruction. The taken case
requires that the queue be refilled so that execution
can continue at a new address. First, the effective
address of the destination is determined, then the
CPU performs three program word fetches from that
address.
OPPP/OPO — Long branches require four cycles if taken, three
cycles if not taken. Optional cycles are required
because all long branches are page two opcodes, and
thus include the $18 prebyte. The CPU12 treats the
prebyte as a special 1-byte instruction. If the prebyte
is misaligned, the optional cycle is used to perform a
program word access; if the prebyte is aligned, the
optional cycle is used to perform a free cycle. As a
result, both the taken and not-taken cases use one
optional cycle for the prebyte. In the not-taken case,
the queue must advance so that execution can
continue with the next instruction, and another
optional cycle is required to maintain the queue. The
taken case requires that the queue be refilled so that
execution can continue at a new address. First, the
effective address of the destination is determined,
then the CPU performs three program word fetches
from that address.
6.7 Glossary
This subsection contains an entry for each assembler mnemonic, in
alphabetic order.
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99
ABA
Operation:
Description:
CCR Details:
Add Accumulator B to Accumulator A
ABA
(A) + (B) ⇒ A
Adds the content of accumulator B to the content of accumulator A and
places the result in A. The content of B is not changed. This instruction
affects the H status bit so it is suitable for use in BCD arithmetic operations.
See DAA instruction for additional information.
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H: A3 • B3 + B3 • R3 + R3 • A3
Set if there was a carry from bit 3; cleared otherwise
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • B7 • R7 + A7 • B7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • B7 + B7 • R7 + R7 • A7
Set if there was a carry from the MSB of the result; cleared
otherwise
Source Form
ABA
Address
Mode
INH
Access Detail
Object Code
HCS12
18 06
OO
M68HC12
OO
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ABX
Operation:
Description:
Add Accumulator B to Index Register X
ABX
(B) + (X) ⇒ X
Adds the 8-bit unsigned content of accumulator B to the content of index
register X considering the possible carry out of the low-order byte of X;
places the result in X. The content of B is not changed.
This mnemonic is implemented by the LEAX B,X instruction. The LEAX
instruction allows A, B, D, or a constant to be added to X. For compatibility
with the M68HC11, the mnemonic ABX is translated into the LEAX B,X
instruction by the assembler.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
ABX
translates to... LEAX B,X
Address
Mode
IDX
Access Detail
Object Code
HCS12
1A E5
Pf
M68HC12
PP(1)
1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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101
ABY
Operation:
Description:
Add Accumulator B to Index Register Y
ABY
(B) + (Y) ⇒ Y
Adds the 8-bit unsigned content of accumulator B to the content of index
register Y considering the possible carry out of the low-order byte of Y;
places the result in Y. The content of B is not changed.
This mnemonic is implemented by the LEAY B,Y instruction. The LEAY
instruction allows A, B, D, or a constant to be added to Y. For compatibility
with the M68HC11, the mnemonic ABY is translated into the LEAY B,Y
instruction by the assembler.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
ABY
translates to... LEAY B,Y
Address
Mode
IDX
Access Detail
Object Code
HCS12
19 ED
Pf
M68HC12
PP(1)
1. Due to internal M68HC12CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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ADCA
Operation:
Description:
CCR Details:
Add with Carry to A
ADCA
(A) + (M) + C ⇒ A
Adds the content of accumulator A to the content of memory location M,
then adds the value of the C bit and places the result in A. This instruction
affects the H status bit, so it is suitable for use in BCD arithmetic operations.
See DAA instruction for additional information.
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H: A3 • M3 + M3 • R3 + R3 • A3
Set if there was a carry from bit 3; cleared otherwise
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if there was a carry from the MSB of the result; cleared
otherwise
Source Form
ADCA #opr8i
ADCA opr8a
ADCA opr16a
ADCA oprx0_xysp
ADCA oprx9,xysp
ADCA oprx16,xysp
ADCA [D,xysp]
ADCA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
89
99
B9
A9
A9
A9
A9
A9
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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103
ADCB
Operation:
Description:
CCR Details:
Add with Carry to B
ADCB
(B) + (M) + C ⇒ B
Adds the content of accumulator B to the content of memory location M,
then adds the value of the C bit and places the result in B. This instruction
affects the H status bit, so it is suitable for use in BCD arithmetic operations.
See DAA instruction for additional information.
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H: X3 • M3 + M3 • R3 + R3 • X3
Set if there was a carry from bit 3; cleared otherwise
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: X7 • M7 • R7 + X7 • M7 • R7
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: X7 • M7 + M7 • R7 + R7 • X7
Set if there was a carry from the MSB of the result; cleared
otherwise
Source Form
ADCB #opr8i
ADCB opr8a
ADCB opr16a
ADCB oprx0_xysp
ADCB oprx9,xysp
ADCB oprx16,xysp
ADCB [D,xysp]
ADCB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C9
D9
F9
E9
E9
E9
E9
E9
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Freescale Semiconductor
ADDA
Operation:
Description:
CCR Details:
Add without Carry to A
ADDA
(A) + (M) ⇒ A
Adds the content of memory location M to accumulator A and places the
result in A. This instruction affects the H status bit, so it is suitable for use in
BCD arithmetic operations. See DAA instruction for additional information.
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H: A3 • M3 + M3 • R3 + R3 • A3
Set if there was a carry from bit 3; cleared otherwise
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if there was a carry from the MSB of the result; cleared
otherwise
Source Form
ADDA #opr8i
ADDA opr8a
ADDA opr16a
ADDA oprx0_xysp
ADDA oprx9,xysp
ADDA oprx16,xysp
ADDA [D,xysp]
ADDA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
8B
9B
BB
AB
AB
AB
AB
AB
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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ADDB
Operation:
Description:
CCR Details:
Add without Carry to B
ADDB
(B) + (M) ⇒ B
Adds the content of memory location M to accumulator B and places the
result in B. This instruction affects the H status bit, so it is suitable for use in
BCD arithmetic operations. See DAA instruction for additional information.
S
X
H
I
N
Z
V
C
–
–
∆
–
∆
∆
∆
∆
H: B3 • M3 + M3 • R3 + R3 • B3
Set if there was a carry from bit 3; cleared otherwise
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: B7 • M7 • R7 + B7 • M7 • R7
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: B7 • M7 + M7 • R7 + R7 • B7
Set if there was a carry from the MSB of the result; cleared
otherwise
Source Form
ADDB #opr8i
ADDB opr8a
ADDB opr16a
ADDB oprx0_xysp
ADDB oprx9,xysp
ADDB oprx16,xysp
ADDB [D,xysp]
ADDB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
CB
DB
FB
EB
EB
EB
EB
EB
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Freescale Semiconductor
ADDD
Operation:
Description:
CCR Details:
Add Double Accumulator
ADDD
(A : B) + (M : M+1) ⇒ A : B
Adds the content of memory location M concatenated with the content of
memory location M +1 to the content of double accumulator D and places
the result in D. Accumulator A forms the high-order half of 16-bit double
accumulator D; accumulator B forms the low-order half.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if there was a carry from the MSB of the result; cleared
otherwise
Source Form
ADDD #opr16i
ADDD opr8a
ADDD opr16a
ADDD oprx0_xysp
ADDD oprx9,xysp
ADDD oprx16,xysp
ADDD [D,xysp]
ADDD [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C3
D3
F3
E3
E3
E3
E3
E3
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPF
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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107
ANDA
Operation:
Description:
CCR Details:
ANDA
Logical AND A
(A) • (M) ⇒ A
Performs logical AND between the content of memory location M and the
content of accumulator A. The result is placed in A. After the operation is
performed, each bit of A is the logical AND of the corresponding bits of M
and of A before the operation began.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared.
Source Form
ANDA #opr8i
ANDA opr8a
ANDA opr16a
ANDA oprx0_xysp
ANDA oprx9,xysp
ANDA oprx16,xysp
ANDA [D,xysp]
ANDA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
84
94
B4
A4
A4
A4
A4
A4
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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ANDB
Operation:
Description:
CCR Details:
ANDB
Logical AND B
(B) • (M) ⇒ B
Performs logical AND between the content of memory location M and the
content of accumulator B. The result is placed in B. After the operation is
performed, each bit of B is the logical AND of the corresponding bits of M
and of B before the operation began.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
ANDB #opr8i
ANDB opr8a
ANDB opr16a
ANDB oprx0_xysp
ANDB oprx9,xysp
ANDB oprx16,xysp
ANDB [D,xysp]
ANDB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C4
D4
F4
E4
E4
E4
E4
E4
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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109
ANDCC
Operation:
Description:
Logical AND CCR with Mask
ANDCC
(CCR) • (Mask) ⇒ CCR
Performs bitwise logical AND between the content of a mask operand and
the content of the CCR. The result is placed in the CCR. After the operation
is performed, each bit of the CCR is the result of a logical AND with the
corresponding bits of the mask. To clear CCR bits, clear the corresponding
mask bits. CCR bits that correspond to ones in the mask are not changed
by the ANDCC operation.
If the I mask bit is cleared, there is a 1-cycle delay before the system allows
interrupt requests. This prevents interrupts from occurring between
instructions in the sequences CLI, WAI and CLI, STOP (CLI is equivalent to
ANDCC #$EF).
CCR Details:
S
X
H
I
N
Z
V
C
⇓
⇓
⇓
⇓
⇓
⇓
⇓
⇓
Condition code bits are cleared if the corresponding bit was 0 before the
operation or if the corresponding bit in the mask is 0.
Source Form
ANDCC #opr8i
Address
Mode
IMM
Access Detail
Object Code
HCS12
10 ii
P
M68HC12
P
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ASL
ASL
Arithmetic Shift Left Memory
(same as LSL)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
0
Shifts all bits of memory location M one bit position to the left. Bit 0 is loaded
with a 0. The C status bit is loaded from the most significant bit of M.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: M7
Set if the MSB of M was set before the shift; cleared otherwise
Source Form
ASL opr16a
ASL oprx0_xysp
ASL oprx9,xysp
ASL oprx16,xysp
ASL [D,xysp]
ASL [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
78
68
68
68
68
68
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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ASLA
ASLA
Arithmetic Shift Left A
(same as LSLA)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
0
Shifts all bits of accumulator A one bit position to the left. Bit 0 is loaded with
a 0. TheC status bit is loaded from the most significant bit of A.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: A7
Set if the MSB of A was set before the shift; cleared otherwise
Source Form
ASLA
Address
Mode
INH
Access Detail
Object Code
HCS12
48
O
M68HC12
O
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Freescale Semiconductor
ASLB
ASLB
Arithmetic Shift Left B
(same as LSLB)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
0
Shifts all bits of accumulator B one bit position to the left. Bit 0 is loaded with
a 0. The C status bit is loaded from the most significant bit of B.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: B7
Set if the MSB of B was set before the shift; cleared otherwise
Source Form
ASLB
Address
Mode
INH
Access Detail
Object Code
HCS12
58
1
M68HC12
O
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Freescale Semiconductor
113
ASLD
Arithmetic Shift Left Double Accumulator
(same as LSLD)
ASLD
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
b7 – – – – – – b0
Accumulator A
Accumulator B
0
Shifts all bits of double accumulator D one bit position to the left. Bit 0 is
loaded with a 0. The C status bit is loaded from the most significant bit of D.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: D15
Set if the MSB of D was set before the shift; cleared otherwise
Source Form
ASLD
Address
Mode
INH
Access Detail
Object Code
HCS12
59
O
M68HC12
O
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Freescale Semiconductor
ASR
Arithmetic Shift Right Memory
ASR
Operation:
b7 – – – – – – b0
Description:
CCR Details:
C
Shifts all bits of memory location M one place to the right. Bit 7 is held
constant. Bit 0 is loaded into the C status bit. This operation effectively
divides a two’s complement value by two without changing its sign. The
carry bit can be used to round the result.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: M0
Set if the LSB of M was set before the shift; cleared otherwise
Source Form
ASR opr16a
ASR oprx0_xysp
ASR oprx9,xysp
ASR oprx16,xysp
ASR [D,xysp]
ASR [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
77
67
67
67
67
67
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Freescale Semiconductor
115
ASRA
ASRA
Arithmetic Shift Right A
Operation:
b7 – – – – – – b0
Description:
CCR Details:
C
Shifts all bits of accumulator A one place to the right. Bit 7 is held constant.
Bit 0 is loaded into the C status bit. This operation effectively divides a two’s
complement value by two without changing its sign. The carry bit can be
used to round the result.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: A0
Set if the LSB of A was set before the shift; cleared otherwise
Source Form
ASRA
Address
Mode
INH
Access Detail
Object Code
HCS12
47
O
M68HC12
O
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Freescale Semiconductor
ASRB
ASRB
Arithmetic Shift Right B
Operation:
b7 – – – – – – b0
Description:
CCR Details:
C
Shifts all bits of accumulator B one place to the right. Bit 7 is held constant.
Bit 0 is loaded into the C status bit. This operation effectively divides a two’s
complement value by two without changing its sign. The carry bit can be
used to round the result.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: B0
Set if the LSB of B was set before the shift; cleared otherwise
Source Form
ASRB
Address
Mode
INH
Access Detail
Object Code
HCS12
57
O
M68HC12
O
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Freescale Semiconductor
117
BCC
Operation:
Branch if Carry Cleared
(Same as BHS)
BCC
If C = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 0.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BCC rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
24 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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Freescale Semiconductor
BCLR
Operation:
Description:
CCR Details:
Clear Bits in Memory
BCLR
(M) • (Mask) ⇒ M
Clears bits in location M. To clear a bit, set the corresponding bit in the mask
byte. Bits in M that correspond to 0s in the mask byte are not changed. Mask
bytes can be located at PC + 2, PC + 3, or PC + 4, depending on addressing
mode used.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
BCLR opr8a, msk8
BCLR opr16a, msk8
BCLR oprx0_xysp, msk8
BCLR oprx9,xysp, msk8
BCLR oprx16,xysp, msk8
Access Detail
Address
Mode(1)
DIR
EXT
IDX
IDX1
IDX2
Object Code
HCS12
4D
1D
0D
0D
0D
dd
hh
xb
xb
xb
mm
ll mm
mm
ff mm
ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
M68HC12
rPOw
rPPw
rPOw
rPwP
frPwOP
1. Indirect forms of indexed addressing cannot be used with this instruction.
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Freescale Semiconductor
119
BCS
Operation:
BCS
Branch if Carry Set
(Same as BLO)
If C = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 1.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BCS rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
25 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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Freescale Semiconductor
BEQ
Operation:
BEQ
Branch if Equal
If Z = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 1.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BEQ rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
27 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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Freescale Semiconductor
121
BGE
Operation:
Branch if Greater than or Equal to Zero
BGE
If N ⊕ V = 0, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement values
if (Accumulator) ≥ (Memory), then branch
Description:
BGE can be used to branch after comparing or subtracting signed two’s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is greater than or equal to the value in M. After CBA or SBA, the branch
occurs if the value in B is greater than or equal to the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BGE rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
2C rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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122
Freescale Semiconductor
BGND
Description:
Enter Background Debug Mode
BGND
BGND operates like a software interrupt, except that no registers are
stacked. First, the current PC value is stored in internal CPU register TMP2.
Next, the BDM ROM and background register block become active. The
BDM ROM contains a substitute vector, mapped to the address of the
software interrupt vector, which points to routines in the BDM ROM that
control background operation. The substitute vector is fetched, and
execution continues from the address that it points to. Finally, the CPU
checks the location that TMP2 points to. If the value stored in that location
is $00 (the BGND opcode), TMP2 is incremented, so that the instruction that
follows the BGND instruction is the first instruction executed when normal
program execution resumes.
For all other types of BDM entry, the CPU performs the same sequence of
operations as for a BGND instruction, but the value stored in TMP2 already
points to the instruction that would have executed next had BDM not
become active. If active BDM is triggered just as a BGND instruction is
about to execute, the BDM firmware does increment TMP2, but the change
does not affect resumption of normal execution.
While BDM is active, the CPU executes debugging commands received via
a special single-wire serial interface. BDM is terminated by the execution of
specific debugging commands. Upon exit from BDM, the background/boot
ROM and registers are disabled, the instruction queue is refilled starting
with the return address pointed to by TMP2, and normal processing
resumes.
BDM is normally disabled to avoid accidental entry. While BDM is disabled,
BGND executes as described, but the firmware causes execution to return
to the user program. Refer to Section 8. Instruction Queue for more
information concerning BDM.
CCR Details:
Source Form
BGND
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
00
HCS12
M68HC12
VfPPP
VfPPP
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Freescale Semiconductor
123
BGT
Operation:
BGT
Branch if Greater than Zero
If Z + (N ⊕ V) = 0, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement values
if (Accumulator) > (Memory), then branch
Description:
BGT can be used to branch after comparing or subtracting signed two’s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is greater than the value in M. After CBA or SBA, the branch occurs if the
value in B is greater than the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BGT rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
2E rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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Freescale Semiconductor
BHI
Operation:
BHI
Branch if Higher
If C + Z = 0, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) > (Memory), then branch
Description:
BHI can be used to branch after comparing or subtracting unsigned values.
After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB,
or SUBD, the branch occurs if the CPU register value is greater than the
value in M. After CBA or SBA, the branch occurs if the value in B is greater
than the value in A. BHI should not be used for branching after instructions
that do not affect the C bit, such as increment, decrement, load, store, test,
clear, or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BHI rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
22 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
125
BHS
Operation:
Branch if Higher or Same
(Same as BCC)
BHS
If C = 0, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) ≥ (Memory), then branch
Description:
BHS can be used to branch after subtracting or comparing unsigned values.
After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB,
or SUBD, the branch occurs if the CPU register value is greater than or
equal to the value in M. After CBA or SBA, the branch occurs if the value in
B is greater than or equal to the value in A. BHS should not be used for
branching after instructions that do not affect the C bit, such as increment,
decrement, load, store, test, clear, or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BHS rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
24 rr
HCS12
M68HC12
PPP/P(1)
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
126
Freescale Semiconductor
BITA
Operation:
Description:
CCR Details:
BITA
Bit Test A
(A) • (M)
Performs bitwise logical AND on the content of accumulator A and the
content of memory location M and modifies the condition codes accordingly.
Each bit of the result is the logical AND of the corresponding bits of the
accumulator and the memory location. Neither the content of the
accumulator nor the content of the memory location is affected.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
BITA #opr8i
BITA opr8a
BITA opr16a
BITA oprx0_xysp
BITA oprx9,xysp
BITA oprx16,xysp
BITA [D,xysp]
BITA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
85
95
B5
A5
A5
A5
A5
A5
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
127
BITB
Operation:
Description:
CCR Details:
BITB
Bit Test B
(B) • (M)
Performs bitwise logical AND on the content of accumulator B and the
content of memory location M and modifies the condition codes accordingly.
Each bit of the result is the logical AND of the corresponding bits of the
accumulator and the memory location. Neither the content of the
accumulator nor the content of the memory location is affected.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
BITB #opr8i
BITB opr8a
BITB opr16a
BITB oprx0_xysp
BITB oprx9,xysp
BITB oprx16,xysp
BITB [D,xysp]
BITB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C5
D5
F5
E5
E5
E5
E5
E5
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
S12CPUV2 Reference Manual, Rev. 4.0
128
Freescale Semiconductor
BLE
Operation:
BLE
Branch if Less Than or Equal to Zero
If Z + (N ⊕ V) = 1, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement numbers
if (Accumulator) ≤ (Memory), then branch
Description:
BLE can be used to branch after subtracting or comparing signed two’s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is less than or equal to the value in M. After CBA or SBA, the branch occurs
if the value in B is less than or equal to the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BLE rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
2F rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
129
BLO
Operation:
BLO
Branch if Lower
(Same as BCS)
If C = 1, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) < (Memory), then branch
Description:
BLO can be used to branch after subtracting or comparing unsigned values.
After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB,
or SUBD, the branch occurs if the CPU register value is less than the value
in M. After CBA or SBA, the branch occurs if the value in B is less than the
value in A. BLO should not be used for branching after instructions that do
not affect the C bit, such as increment, decrement, load, store, test, clear,
or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BLO rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
25 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
130
Freescale Semiconductor
BLS
Operation:
BLS
Branch if Lower or Same
If C + Z = 1, then (PC) + $0002 + Rel ⇒ PC
For unsigned values, if (Accumulator) ≤ (Memory), then branch
Description:
If BLS is executed immediately after execution of CBA, CMPA, CMPB,
CMPD, CPX, CPY, SBA, SUBA, SUBB, or SUBD, a branch occurs if and
only if the unsigned binary number in the accumulator is less than or equal
to the unsigned binary number in memory. Generally not useful after
INC/DEC, LD/ST, and TST/CLR/COM because these instructions do not
affect the C status bit.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BLS rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
23 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
131
BLT
Operation:
BLT
Branch if Less than Zero
If N ⊕ V = 1, then (PC) + $0002 + Rel ⇒ PC
For signed two’s complement numbers
if (Accumulator) < (Memory), then branch
Description:
BLT can be used to branch after subtracting or comparing signed two’s
complement values. After CMPA, CMPB, CMPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is less than the value in M. After CBA or SBA, the branch occurs if the value
in B is less than the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BLT rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
2D rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
132
Freescale Semiconductor
BMI
Operation:
BMI
Branch if Minus
If N = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 1.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BMI rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
2B rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
133
BNE
Operation:
Branch if Not Equal to Zero
BNE
If Z = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 0.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BNE rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
26 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
134
Freescale Semiconductor
BPL
Operation:
BPL
Branch if Plus
If N = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 0.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BPL rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
2A rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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BRA
Operation:
Description:
Branch Always
BRA
(PC) + $0002 + Rel ⇒ PC
Unconditional branch to an address calculated as shown in the expression.
Rel is a relative offset stored as a two’s complement number in the second
byte of the branch instruction.
Execution time is longer when a conditional branch is taken than when it is
not, because the instruction queue must be refilled before execution
resumes at the new address. Since the BRA branch condition is always
satisfied, the branch is always taken, and the instruction queue must always
be refilled.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BRA rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
20 rr
PPP
M68HC12
PPP
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BRCLR
Operation:
Description:
BRCLR
Branch if Bits Cleared
If (M) • (Mask) = 0, then branch
Performs a bitwise logical AND of memory location M and the mask supplied
with the instruction, then branches if and only if all bits with a value of 1 in
the mask byte correspond to bits with a value of 0 in the tested byte. Mask
operands can be located at PC + 1, PC + 2, or PC + 4, depending on
addressing mode. The branch offset is referenced to the next address after
the relative offset (rr) which is the last byte of the instruction object code.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
BRCLR opr8a, msk8, rel8
BRCLR opr16a, msk8, rel8
BRCLR oprx0_xysp, msk8, rel8
BRCLR oprx9,xysp, msk8, rel8
BRCLR oprx16,xysp, msk8, rel8
Access Detail
Address
Mode(1)
DIR
EXT
IDX
IDX1
IDX2
Object Code
4F
1F
0F
0F
0F
dd
hh
xb
xb
xb
mm
ll
mm
ff
ee
rr
mm rr
rr
mm rr
ff mm rr
HCS12
M68HC12
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
rPPP
rfPPP
rPPP
rffPPP
frPffPPP
1. Indirect forms of indexed addressing cannot be used with this instruction.
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BRN
Operation:
Description:
BRN
Branch Never
(PC) + $0002 ⇒ PC
Never branches. BRN is effectively a 2-byte NOP that requires one cycle to
execute. BRN is included in the instruction set to provide a complement to
the BRA instruction. The instruction is useful during program debug, to
negate the effect of another branch instruction without disturbing the offset
byte. A complement for BRA is also useful in compiler implementations.
Execution time is longer when a conditional branch is taken than when it is
not, because the instruction queue must be refilled before execution
resumes at the new address. Since the BRN branch condition is never
satisfied, the branch is never taken, and only a single program fetch is
needed to update the instruction queue.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BRN rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
21 rr
P
M68HC12
P
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BRSET
Operation:
Description:
BRSET
Branch if Bits Set
If (M) • (Mask) = 0, then branch
Performs a bitwise logical AND of the inverse of memory location M and the
mask supplied with the instruction, then branches if and only if all bits with
a value of 1 in the mask byte correspond to bits with a value of one in the
tested byte. Mask operands can be located at PC + 1, PC + 2, or PC + 4,
depending on addressing mode. The branch offset is referenced to the next
address after the relative offset (rr) which is the last byte of the instruction
object code.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
BRSET opr8a, msk8, rel8
BRSET opr16a, msk8, rel8
BRSET oprx0_xysp, msk8, rel8
BRSET oprx9,xysp, msk8, rel8
BRSET oprx16,xysp, msk8, rel8
Access Detail
Address
Mode(1)
DIR
EXT
IDX
IDX1
IDX2
Object Code
4E
1E
0E
0E
0E
dd
hh
xb
xb
xb
mm
ll
mm
ff
ee
rr
mm rr
rr
mm rr
ff mm rr
HCS12
M68HC12
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
rPPP
rfPPP
rPPP
rffPPP
frPffPPP
1. Indirect forms of indexed addressing cannot be used with this instruction.
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139
BSET
Operation:
Description:
CCR Details:
Set Bit(s) in Memory
BSET
(M) + (Mask) ⇒ M
Sets bits in memory location M. To set a bit, set the corresponding bit in the
mask byte. All other bits in M are unchanged. The mask byte can be located
at PC + 2, PC + 3, or PC + 4, depending upon addressing mode.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
BSET opr8a, msk8
BSET opr16a, msk8
BSET oprx0_xysp, msk8
BSET oprx9,xysp, msk8
BSET oprx16,xysp, msk8
Access Detail
Address
Mode(1)
DIR
EXT
IDX
IDX1
IDX2
Object Code
HCS12
4C
1C
0C
0C
0C
dd
hh
xb
xb
xb
mm
ll mm
mm
ff mm
ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
M68HC12
rPOw
rPPw
rPOw
rPwP
frPwOP
1. Indirect forms of indexed addressing cannot be used with this instruction.
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BSR
Operation:
Description:
BSR
Branch to Subroutine
(SP) – $0002 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP+1)
(PC) + Rel ⇒ PC
Sets up conditions to return to normal program flow, then transfers control
to a subroutine. Uses the address of the instruction after the BSR as a return
address.
Decrements the SP by two, to allow the two bytes of the return address to
be stacked.
Stacks the return address (the SP points to the high-order byte of the return
address).
Branches to a location determined by the branch offset.
Subroutines are normally terminated with an RTS instruction, which
restores the return address from the stack.
CCR Details:
Source Form
BSR rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
07 rr
SPPP
M68HC12
PPPS
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BVC
Operation:
Branch if Overflow Cleared
BVC
If V = 0, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 0.
BVC causes a branch when a previous operation on two’s complement
binary values does not cause an overflow. That is, when BVC follows a two’s
complement operation, a branch occurs when the result of the operation is
valid.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BVC rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
28 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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BVS
Operation:
BVS
Branch if Overflow Set
If V = 1, then (PC) + $0002 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 1.
BVS causes a branch when a previous operation on two’s complement
binary values causes an overflow. That is, when BVS follows a two’s
complement operation, a branch occurs when the result of the operation is
invalid.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
BVS rel8
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
29 rr
PPP/P(1)
M68HC12
PPP/P(1)
1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program
fetch cycle if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
BGT
2E
BGE
2C
BEQ
27
BLE
2F
BLT
2D
BHI
22
BHS/BCC
24
BEQ
27
BLS
23
BLO/BCS
25
BCS
25
BMI
2B
BVS
29
BEQ
27
BRA
20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
BLE
2F
Signed
BLT
2D
Signed
BNE
26
Signed
BGT
2E
Signed
BGE
2C
Signed
BLS
23
Unsigned
BLO/BCS
25
Unsigned
BNE
26
Unsigned
BHI
22
Unsigned
BHS/BCC
24
Unsigned
BCC
24
Simple
BPL
2A
Simple
BVC
28
Simple
BNE
26
Simple
BRN
21
Unconditional
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CALL
Operation:
Description:
CALL
Call Subroutine in Expanded Memory
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ M(SP) : M(SP+1)
(SP) – $0001 ⇒ SP; (PPAGE) ⇒ M(SP)
page ⇒ PPAGE; Subroutine Address ⇒ PC
Sets up conditions to return to normal program flow, then transfers control
to a subroutine in expanded memory. Uses the address of the instruction
following the CALL as a return address. For code compatibility, CALL also
executes correctly in devices that do not have expanded memory capability.
Decrements the SP by two, then stores the return address on the stack. The
SP points to the high-order byte of the return address.
Decrements the SP by one, then stacks the current memory page value
from the PPAGE register on the stack.
Writes a new page value supplied by the instruction to PPAGE and transfers
control to the subroutine.
In indexed-indirect modes, the subroutine address and the PPAGE value
are fetched from memory in the order M high byte, M low byte, and new
PPAGE value.
Expanded-memory subroutines must be terminated by an RTC instruction,
which restores the return address and PPAGE value from the stack.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
CALL opr16a, page
CALL oprx0_xysp, page
CALL oprx9,xysp, page
CALL oprx16,xysp, page
CALL [D,xysp]
CALL [oprx16,xysp]
Access Detail
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
4A
4B
4B
4B
4B
4B
hh
xb
xb
xb
xb
xb
ll pg
pg
ff pg
ee ff pg
ee ff
gnSsPPP
gnSsPPP
gnSsPPP
fgnSsPPP
fIignSsPPP
fIignSsPPP
M68HC12
gnfSsPPP
gnfSsPPP
gnfSsPPP
fgnfSsPPP
fIignSsPPP
fIignSsPPP
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CBA
Operation:
Description:
CCR Details:
Compare Accumulators
CBA
(A) – (B)
Compares the content of accumulator A to the content of accumulator B and
sets the condition codes, which may then be used for arithmetic and logical
conditional branches. The contents of the accumulators are not changed.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • B7 • R7 + A7 • B7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • B7 + B7 • R7 + R7 • A7
Set if there was a borrow from the MSB of the result; cleared
otherwise
Source Form
CBA
Address
Mode
INH
Access Detail
Object Code
HCS12
18 17
OO
M68HC12
OO
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CLC
Operation:
Description:
CLC
Clear Carry
0 ⇒ C bit
Clears the C status bit. This instruction is assembled as ANDCC #$FE. The
ANDCC instruction can be used to clear any combination of bits in the CCR
in one operation.
CLC can be used to set up the C bit prior to a shift or rotate instruction
involving the C bit.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
0
C: 0; cleared
Source Form
CLC
translates to... ANDCC #$FE
Address
Mode
IMM
Access Detail
Object Code
HCS12
10 FE
P
M68HC12
P
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CLI
Operation:
Description:
CLI
Clear Interrupt Mask
0 ⇒ I bit
Clears the I mask bit. This instruction is assembled as ANDCC #$EF. The
ANDCC instruction can be used to clear any combination of bits in the CCR
in one operation.
When the I bit is cleared, interrupts are enabled. There is a 1-cycle (bus
clock) delay in the clearing mechanism for the I bit so that, if interrupts were
previously disabled, the next instruction after a CLI will always be executed,
even if there was an interrupt pending prior to execution of the CLI
instruction.
S
X
H
I
N
Z
V
C
–
–
–
0
–
–
–
–
CCR Details:
I:
0; cleared
Source Form
CLI
translates to... ANDCC #$EF
Address
Mode
IMM
Access Detail
Object Code
HCS12
10 EF
P
M68HC12
P
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CLR
Operation:
Description:
CCR Details:
0⇒M
All bits in memory location M are cleared to 0.
S
X
H
I
N
Z
V
C
–
–
–
–
0
1
0
0
N:
Z:
V:
C:
Source Form
CLR opr16a
CLR oprx0_xysp
CLR oprx9,xysp
CLR oprx16,xysp
CLR [D,xysp]
CLR [oprx16,xysp]
CLR
Clear Memory
0; cleared
1; set
0; cleared
0; cleared
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
79
69
69
69
69
69
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PwO
Pw
PwO
PwP
PIfw
PIPw
M68HC12
wOP
Pw
PwO
PwP
PIfPw
PIPPw
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CLRA
Operation:
Description:
CCR Details:
0⇒A
All bits in accumulator A are cleared to 0.
S
X
H
I
N
Z
V
C
–
–
–
–
0
1
0
0
N:
Z:
V:
C:
Source Form
CLRA
CLRA
Clear A
0; cleared
1; set
0; cleared
0; cleared
Address
Mode
INH
Access Detail
Object Code
HCS12
87
O
M68HC12
O
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CLRB
Operation:
Description:
CCR Details:
0⇒B
All bits in accumulator B are cleared to 0.
S
X
H
I
N
Z
V
C
–
–
–
–
0
1
0
0
N:
Z:
V:
C:
Source Form
CLRB
CLRB
Clear B
0; cleared
1; set
0; cleared
0; cleared
Address
Mode
INH
Access Detail
Object Code
HCS12
C7
O
M68HC12
O
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CLV
Operation:
Description:
Clear Two’s Complement Overflow Bit
CLV
0 ⇒ V bit
Clears the V status bit. This instruction is assembled as ANDCC #$FD. The
ANDCC instruction can be used to clear any combination of bits in the CCR
in one operation.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
0
–
V: 0; cleared
Source Form
CLV
translates to... ANDCC #$FD
Address
Mode
IMM
Access Detail
Object Code
HCS12
10 FD
P
M68HC12
P
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CMPA
Operation:
Description:
CCR Details:
CMPA
Compare A
(A) – (M)
Compares the content of accumulator A to the content of memory location
M and sets the condition codes, which may then be used for arithmetic and
logical conditional branching. The contents of A and location M are not
changed.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if there was a borrow from the MSB of the result; cleared
otherwise
Source Form
CMPA #opr8i
CMPA opr8a
CMPA opr16a
CMPA oprx0_xysp
CMPA oprx9,xysp
CMPA oprx16,xysp
CMPA [D,xysp]
CMPA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
81
91
B1
A1
A1
A1
A1
A1
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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CMPB
Operation:
Description:
CCR Details:
CMPB
Compare B
(B) – (M)
Compares the content of accumulator B to the content of memory location
M and sets the condition codes, which may then be used for arithmetic and
logical conditional branching. The contents of B and location M are not
changed.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: B7 • M7 • R7 + B7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: B7 • M7 + M7 • R7 + R7 • B7
Set if there was a borrow from the MSB of the result; cleared
otherwise
Source Form
CMPB #opr8i
CMPB opr8a
CMPB opr16a
CMPB oprx0_xysp
CMPB oprx9,xysp
CMPB oprx16,xysp
CMPB [D,xysp]
CMPB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C1
D1
F1
E1
E1
E1
E1
E1
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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153
COM
Operation:
Description:
CCR Details:
(M) = $FF – (M) ⇒ M
Replaces the content of memory location M with its one’s complement.
Each bit of M is complemented. Immediately after a COM operation on
unsigned values, only the BEQ, BNE, LBEQ, and LBNE branches can be
expected to perform consistently. After operation on two’s complement
values, all signed branches are available.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
1
N:
Z:
V:
C:
Source Form
COM opr16a
COM oprx0_xysp
COM oprx9,xysp
COM oprx16,xysp
COM [D,xysp]
COM [oprx16,xysp]
COM
Complement Memory
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
0; cleared
1; set (for M6800 compatibility)
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
71
61
61
61
61
61
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Freescale Semiconductor
COMA
Operation:
Description:
CCR Details:
(A) = $FF – (A) ⇒ A
Replaces the content of accumulator A with its one’s complement. Each bit
of A is complemented. Immediately after a COM operation on unsigned
values, only the BEQ, BNE, LBEQ, and LBNE branches can be expected to
perform consistently. After operation on two’s complement values, all
signed branches are available.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
1
N:
Z:
V:
C:
Source Form
COMA
COMA
Complement A
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
0; cleared
1; set (for M6800 compatibility)
Address
Mode
INH
Access Detail
Object Code
HCS12
41
0
M68HC12
0
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155
COMB
Operation:
Description:
CCR Details:
(B) = $FF – (B) ⇒ B
Replaces the content of accumulator B with its one’s complement. Each bit
of B is complemented. Immediately after a COM operation on unsigned
values, only the BEQ, BNE, LBEQ, and LBNE branches can be expected to
perform consistently. After operation on two’s complement values, all
signed branches are available.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
1
N:
Z:
V:
C:
Source Form
COMB
COMB
Complement B
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
0; cleared
1; set (for M6800 compatibility)
Address
Mode
INH
Access Detail
Object Code
HCS12
51
0
M68HC12
0
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Freescale Semiconductor
CPD
Operation:
Description:
CCR Details:
Compare Double Accumulator
CPD
(A : B) – (M : M + 1)
Compares the content of double accumulator D with a 16-bit value at the
address specified and sets the condition codes accordingly. The compare is
accomplished internally by a 16-bit subtract of (M : M + 1) from D without
modifying either D or (M : M + 1).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if the absolute value of the content of memory is larger than the
absolute value of the accumulator; cleared otherwise
Source Form
CPD #opr16i
CPD opr8a
CPD opr16a
CPD oprx0_xysp
CPD oprx9,xysp
CPD oprx16,xysp
CPD [D,xysp]
CPD [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
8C
9C
BC
AC
AC
AC
AC
AC
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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157
CPS
Operation:
Description:
CCR Details:
CPS
Compare Stack Pointer
(SP) – (M : M + 1)
Compares the content of the SP with a 16-bit value at the address specified,
and sets the condition codes accordingly. The compare is accomplished
internally by doing a 16-bit subtract of (M : M + 1) from the SP without
modifying either the SP or (M : M + 1).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: S15 • M15 • R15 + S15 • M15 • R15
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: S15 • M15 + M15 • R15 + R15 • S15
Set if the absolute value of the content of memory is larger than the
absolute value of the SP; cleared otherwise
Source Form
CPS #opr16i
CPS opr8a
CPS opr16a
CPS oprx0_xysp
CPS oprx9,xysp
CPS oprx16,xysp
CPS [D,xysp]
CPS [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
8F
9F
BF
AF
AF
AF
AF
AF
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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Freescale Semiconductor
CPX
Operation:
Description:
CCR Details:
CPX
Compare Index Register X
(X) – (M : M + 1)
Compares the content of index register X with a 16-bit value at the address
specified and sets the condition codes accordingly. The compare is
accomplished internally by a 16-bit subtract of (M : M + 1) from index register
X without modifying either index register X or (M : M + 1).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: X15 • M15 • R15 + X15 • M15 • R15
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: X15 • M15 + M15 • R15 + R15 • X15
Set if the absolute value of the content of memory is larger than the
absolute value of the index register; cleared otherwise
Source Form
CPX #opr16i
CPX opr8a
CPX opr16a
CPX oprx0_xysp
CPX oprx9,xysp
CPX oprx16,xysp
CPX [D,xysp]
CPX [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
8E
9E
BE
AE
AE
AE
AE
AE
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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159
CPY
Operation:
Description:
CCR Details:
CPY
Compare Index Register Y
(Y) – (M : M + 1)
Compares the content of index register Y to a 16-bit value at the address
specified and sets the condition codes accordingly. The compare is
accomplished internally by a 16-bit subtract of (M : M + 1) from Y without
modifying either Y or (M : M + 1).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: Y15 • M15 • R15 + Y15 • M15 • R15
Set if two’s complement overflow resulted from the operation;
cleared otherwise
C: Y15 • M15 + M15 • R15 + R15 • Y15
Set if the absolute value of the content of memory is larger than the
absolute value of the index register; cleared otherwise
Source Form
CPY #opr16i
CPY opr8a
CPY opr16a
CPY oprx0_xysp
CPY oprx9,xysp
CPY oprx16,xysp
CPY [D,xysp]
CPY [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
8D
9D
BD
AD
AD
AD
AD
AD
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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Freescale Semiconductor
DAA
Description:
DAA adjusts the content of accumulator A and the state of the C status bit
to represent the correct binary-coded-decimal sum and the associated carry
when a BCD calculation has been performed. To execute DAA, the content
of accumulator A, the state of the C status bit, and the state of the H status
bit must all be the result of performing an ABA, ADD, or ADC on BCD
operands, with or without an initial carry.
The table shows DAA operation for all legal combinations of input operands.
Columns 1 through 4 represent the results of ABA, ADC, or ADD operations
on BCD operands. The correction factor in column 5 is added to the
accumulator to restore the result of an operation on two BCD operands to a
valid BCD value and to set or clear the C bit. All values are in hexadecimal.
1
Initial
C Bit Value
0
0
0
0
0
0
1
1
1
CCR Details:
DAA
2
Value
of A[7:4]
0–9
0–8
0–9
A–F
9–F
A–F
0–2
0–2
0–3
3
Initial
H Bit Value
0
0
1
0
0
1
0
0
1
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
?
∆
N:
Z:
V:
C:
Source Form
DAA
Decimal Adjust A
4
Value
of A[3:0]
0–9
A–F
0–3
0–9
A–F
0–3
0–9
A–F
0–3
5
Correction
Factor
00
06
06
60
66
66
60
66
66
6
Corrected
C Bit Value
0
0
0
1
1
1
1
1
1
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
Undefined
Represents BCD carry. See bit table
Address
Mode
INH
Access Detail
Object Code
HCS12
18 07
OfO
M68HC12
OfO
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161
DBEQ
Operation:
Description:
Decrement and Branch if Equal to Zero
DBEQ
(Counter) – 1 ⇒ Counter
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC
Subtract one from the specified counter register A, B, D, X, Y, or SP. If the
counter register has reached zero, execute a branch to the specified relative
destination. The DBEQ instruction is encoded into three bytes of machine
code including the 9-bit relative offset (–256 to +255 locations from the start
of the next instruction).
IBEQ and TBEQ instructions are similar to DBEQ except that the counter is
incremented or tested rather than being decremented. Bits 7 and 6 of the
instruction postbyte are used to determine which operation is to be
performed.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
DBEQ abdxys, rel9
REL
Access Detail
Object Code(1)
HCS12
04 lb rr
M68HC12
PPP/PPO
PPP
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero
(DBEQ – 0) or not zero (DBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 would be 0:0
for DBEQ.
Count
Register
Bits 2:0
A
B
000
001
DBEQ A, rel9
DBEQ B, rel9
04 00 rr
04 01 rr
04 10 rr
04 11 rr
D
X
Y
SP
100
101
110
111
DBEQ D, rel9
DBEQ X, rel9
DBEQ Y, rel9
DBEQ SP, rel9
04
04
04
04
04
04
04
04
Source Form
Object Code
Object Code
(If Offset is Positive) (If Offset is Negative)
04
05
06
07
rr
rr
rr
rr
14
15
16
17
rr
rr
rr
rr
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Freescale Semiconductor
Glossary
DBNE
Operation:
Description:
Decrement and Branch if Not Equal to Zero
DBNE
(Counter) – 1 ⇒ Counter
If (Counter) not = 0, then (PC) + $0003 + Rel ⇒ PC
Subtract one from the specified counter register A, B, D, X, Y, or SP. If the
counter register has not been decremented to zero, execute a branch to the
specified relative destination. The DBNE instruction is encoded into three
bytes of machine code including a 9-bit relative offset (–256 to +255
locations from the start of the next instruction).
IBNE and TBNE instructions are similar to DBNE except that the counter is
incremented or tested rather than being decremented. Bits 7 and 6 of the
instruction postbyte are used to determine which operation is to be
performed.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
DBNE abdxys, rel9
REL
Access Detail
Object Code(1)
HCS12
04 lb rr
M68HC12
PPP/PPO
PPP
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (DBEQ – 0)
or not zero (DBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 would be 0:0 for DBNE.
Count
Register
Bits 2:0
A
B
000
001
DBNE A, rel9
DBNE B, rel9
04 20 rr
04 21 rr
04 30 rr
04 31 rr
D
X
Y
SP
100
101
110
111
DBNE D, rel9
DBNE X, rel9
DBNE Y, rel9
DBNE SP, rel9
04
04
04
04
04
04
04
04
Source Form
Object Code
Object Code
(If Offset is Positive) (If Offset is Negative)
24
25
26
27
rr
rr
rr
rr
34
35
36
37
rr
rr
rr
rr
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163
Instruction Glossary
DEC
Operation:
Description:
DEC
Decrement Memory
(M) – $01 ⇒ M
Subtract one from the content of memory location M.
The N, Z, and V status bits are set or cleared according to the results of the
operation. The C status bit is not affected by the operation, thus allowing the
DEC instruction to be used as a loop counter in multiple-precision
computations.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: Set if there was a two’s complement overflow as a result of the
operation; cleared otherwise. Two’s complement overflow occurs if
and only if (M) was $80 before the operation.
Source Form
DEC opr16a
DEC oprx0_xysp
DEC oprx9,xysp
DEC oprx16,xysp
DEC [D,xysp]
DEC [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code(1)
HCS12
73
63
63
63
63
63
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (DBEQ – 0)
or not zero (DBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 would be 0:0 for DBNE.
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Freescale Semiconductor
Glossary
DECA
Operation:
Description:
DECA
Decrement A
(A) – $01 ⇒ A
Subtract one from the content of accumulator A.
The N, Z, and V status bits are set or cleared according to the results of the
operation. The C status bit is not affected by the operation, thus allowing the
DEC instruction to be used as a loop counter in multiple-precision
computations.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: Set if there was a two’s complement overflow as a result of the
operation; cleared otherwise. Two’s complement overflow occurs if
and only if (A) was $80 before the operation.
Source Form
DECA
Address
Mode
INH
Access Detail
Object Code
HCS12
43
O
M68HC12
O
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165
Instruction Glossary
DECB
Operation:
Description:
DECB
Decrement B
(B) – $01 ⇒ B
Subtract one from the content of accumulator B.
The N, Z, and V status bits are set or cleared according to the results of the
operation. The C status bit is not affected by the operation, thus allowing the
DEC instruction to be used as a loop counter in multiple-precision
computations.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: Set if there was a two’s complement overflow as a result of the
operation; cleared otherwise. Two’s complement overflow occurs if
and only if (B) was $80 before the operation.
Source Form
DECB
Address
Mode
INH
Access Detail
Object Code
HCS12
53
O
M68HC12
O
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Freescale Semiconductor
Glossary
DES
Operation:
Description:
CCR Details:
Decrement Stack Pointer
DES
(SP) – $0001 ⇒ SP
Subtract one from the SP. This instruction assembles to LEAS –1,SP. The
LEAS instruction does not affect condition codes as DEX or DEY
instructions do.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
DES
translates to... LEAS –1,SP
Address
Mode
IDX
Access Detail
Object Code
HCS12
1B 9F
Pf
M68HC12
PP(1)
1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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167
Instruction Glossary
DEX
Operation:
Description:
DEX
Decrement Index Register X
(X) – $0001 ⇒ X
Subtract one from index register X. LEAX –1,X can produce the same result,
but LEAX does not affect the Z bit. Although the LEAX instruction is more
flexible, DEX requires only one byte of object code.
Only the Z bit is set or cleared according to the result of this operation.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z: Set if result is $0000; cleared otherwise
Source Form
DEX
Address
Mode
INH
Access Detail
Object Code
HCS12
09
O
M68HC12
O
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Freescale Semiconductor
Glossary
DEY
Operation:
Description:
DEY
Decrement Index Register Y
(Y) – $0001 ⇒ Y
Subtract one from index register Y. LEAY –1,Y can produce the same result,
but LEAY does not affect the Z bit. Although the LEAY instruction is more
flexible, DEY requires only one byte of object code.
Only the Z bit is set or cleared according to the result of this operation.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z: Set if result is $0000; cleared otherwise
Source Form
DEY
Address
Mode
INH
Access Detail
Object Code
HCS12
03
O
M68HC12
O
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169
Instruction Glossary
EDIV
Operation:
Description:
CCR Details:
Extended Divide 32-Bit by 16-Bit
(Unsigned)
EDIV
(Y : D) ÷ (X) ⇒ Y; Remainder ⇒ D
Divides a 32-bit unsigned dividend by a 16-bit divisor, producing a 16-bit
unsigned quotient and an unsigned 16-bit remainder. All operands and
results are located in CPU registers. If an attempt to divide by zero is made,
C is set and the states of the N, Z, and V bits in the CCR are undefined. In
case of an overflow or a divide by zero, the contents of the registers D and
Y do not change.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Undefined after overflow or division by zero
Z: Set if result is $0000; cleared otherwise
Undefined after overflow or division by zero
V: Set if the result was > $FFFF; cleared otherwise Undefined after
division by zero
C: Set if divisor was $0000; cleared otherwise
Source Form
EDIV
Address
Mode
INH
Access Detail
Object Code
HCS12
11
ffffffffffO
M68HC12
ffffffffffO
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Freescale Semiconductor
Glossary
EDIVS
Operation:
Description:
CCR Details:
EDIVS
Extended Divide 32-Bit by 16-Bit
(Signed)
(Y : D) ÷ (X) ⇒ Y; Remainder ⇒ D
Divides a signed 32-bit dividend by a 16-bit signed divisor, producing a
signed 16-bit quotient and a signed 16-bit remainder. All operands and
results are located in CPU registers. If an attempt to divide by zero is made,
C is set and the states of the N, Z, and V bits in the CCR are undefined. In
case of an overflow or a divide by zero, the contents of the registers D and
Y do not change.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Undefined after overflow or division by zero
Z: Set if result is $0000; cleared otherwise
Undefined after overflow or division by zero
V: Set if the result was > $7FFF or < $8000; cleared otherwise
Undefined after division by zero
C: Set if divisor was $0000; cleared otherwise
Indicates division by zero
Source Form
EDIVS
Address
Mode
INH
Access Detail
Object Code
HCS12
18 14
OffffffffffO
M68HC12
OffffffffffO
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Instruction Glossary
Extended Multiply and Accumulate
(Signed)
16-Bit by 16-Bit to 32-Bit
EMACS
Operation:
Description:
CCR Details:
EMACS
(M(X) : M(X+1)) × (M(Y) : M(Y+1)) + (M ~ M+3) ⇒ M ~ M+3
A 16-bit value is multiplied by a 16-bit value to produce a 32-bit intermediate
result. This 32-bit intermediate result is then added to the content of a 32-bit
accumulator in memory. EMACS is a signed integer operation. All operands
and results are located in memory. When the EMACS instruction is
executed, the first source operand is fetched from an address pointed to by
X, and the second source operand is fetched from an address pointed to by
index register Y. Before the instruction is executed, the X and Y index
registers must contain values that point to the most significant bytes of the
source operands. The most significant byte of the 32-bit result is specified
by an extended address supplied with the instruction.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00000000; cleared otherwise
V: M31 • I31 • R31 + M31 • I31 • R31
Set if result > $7FFFFFFF (+ overflow) or
< $80000000 (– underflow)
Indicates two’s complement overflow
C: M15 • I15 + I15 • R15 + R15 • M15
Set if there was a carry from bit 15 of the result; cleared otherwise
Indicates a carry from low word to high word of the result occurred
Source Form(1)
EMACS opr16a
Address
Mode
Special
Access Detail
Object Code
HCS12
18 12 hh ll
ORROfffRRfWWP
M68HC12
ORROfffRRfWWP
1. opr16a is an extended address specification. Both X and Y point to source operands.
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Freescale Semiconductor
Glossary
Place Larger of Two
Unsigned 16-Bit Values
in Accumulator D
EMAXD
Operation:
Description:
EMAXD
MAX ((D), (M : M + 1)) ⇒ D
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves the
larger of the two values in D. The Z status bit is set when the result of the
subtraction is zero (the values are equal), and the C status bit is set when
the subtraction requires a borrow (the value in memory is larger than the
value in the accumulator). When C = 1, the value in D has been replaced by
the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the largest value in a list of values.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = D – M : M + 1)
Source Form
EMAXD oprx0_xysp
EMAXD oprx9,xysp
EMAXD oprx16,xysp
EMAXD [D,xysp]
EMAXD [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
1A
1A
1A
1A
1A
xb
xb ff
xb ee ff
xb
xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
M68HC12
ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP
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173
Instruction Glossary
Place Larger of Two
Unsigned 16-Bit Values
in Memory
EMAXM
Operation:
Description:
EMAXM
MAX ((D), (M : M + 1)) ⇒ M : M + 1
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves the
larger of the two values in the memory location. The Z status bit is set when
the result of the subtraction is zero (the values are equal), and the C status
bit is set when the subtraction requires a borrow (the value in memory is
larger than the value in the accumulator). When C = 0, the value in D has
replaced the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = D – M : M + 1)
Source Form
EMAXM oprx0_xysp
EMAXM oprx9,xysp
EMAXM oprx16,xysp
EMAXM [D,xysp]
EMAXM [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
1E
1E
1E
1E
1E
xb
xb ff
xb ee ff
xb
xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
M68HC12
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
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Freescale Semiconductor
Glossary
Place Smaller of Two
Unsigned 16-Bit Values
in Accumulator D
EMIND
Operation:
Description:
EMIND
MIN ((D), (M : M + 1)) ⇒ D
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger, and leaves the
smaller of the two values in D. The Z status bit is set when the result of the
subtraction is zero (the values are equal), and the C status bit is set when
the subtraction requires a borrow (the value in memory is larger than the
value in the accumulator). When C = 0, the value in D has been replaced by
the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the smallest value in a list of values.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = D – M : M + 1)
Source Form
EMIND oprx0_xysp
EMIND oprx9,xysp
EMIND oprx16,xysp
EMIND [D,xysp]
EMIND [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
1B
1B
1B
1B
1B
xb
xb ff
xb ee ff
xb
xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
M68HC12
ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP
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175
Instruction Glossary
Place Smaller of Two
Unsigned 16-Bit Values
in Memory
EMINM
Operation:
Description:
EMINM
MIN ((D), (M : M + 1)) ⇒ M : M + 1
Subtracts an unsigned 16-bit value in memory from an unsigned 16-bit
value in double accumulator D to determine which is larger and leaves the
smaller of the two values in the memory location. The Z status bit is set
when the result of the subtraction is zero (the values are equal), and the C
status bit is set when the subtraction requires a borrow (the value in memory
is larger than the value in the accumulator). When C = 1, the value in D has
replaced the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = D – M : M + 1)
Source Form
EMINM oprx0_xysp
EMINM oprx9,xysp
EMINM oprx16,xysp
EMINM [D,xysp]
EMINM [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
1F
1F
1F
1F
1F
xb
xb ff
xb ee ff
xb
xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
M68HC12
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
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Freescale Semiconductor
Glossary
EMUL
Operation:
Description:
Extended Multiply
16-Bit by 16-Bit (Unsigned)
EMUL
(D) × (Y) ⇒ Y : D
An unsigned 16-bit value is multiplied by an unsigned 16-bit value to
produce an unsigned 32-bit result. The first source operand must be loaded
into 16-bit double accumulator D and the second source operand must be
loaded into index register Y before executing the instruction. When the
instruction is executed, the value in D is multiplied by the value in Y. The
upper 16-bits of the 32-bit result are stored in Y and the low-order 16-bits of
the result are stored in D.
The C status bit can be used to round the high-order 16 bits of the result.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
∆
N: Set if the MSB of the result is set; cleared otherwise
Z: Set if result is $00000000; cleared otherwise
C: Set if bit 15 of the result is set; cleared otherwise
Source Form
EMUL
Address
Mode
INH
Access Detail
Object Code
HCS12
13
ffO
M68HC12
ffO
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177
Instruction Glossary
A
EMULS
Operation:
Description:
Extended Multiply
16-Bit by 16-Bit (Signed)
EMULS
(D) × (Y) ⇒ Y : D
A signed 16-bit value is multiplied by a signed 16-bit value to produce a
signed 32-bit result. The first source operand must be loaded into 16-bit
double accumulator D, and the second source operand must be loaded into
index register Y before executing the instruction. When the instruction is
executed, D is multiplied by the value Y. The 16 high-order bits of the 32-bit
result are stored in Y and the 16 low-order bits of the result are stored in D.
The C status bit can be used to round the high-order 16 bits of the result.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
∆
N: Set if the MSB of the result is set; cleared otherwise
Z: Set if result is $00000000; cleared otherwise
C: Set if bit 15 of the result is set; cleared otherwise
Source Form
EMULS
Address
Mode
INH
Access Detail
Object Code
HCS12
18 13
OfO
OffO(1)
M68HC12
OfO
1. EMULS has an extra free cycle if it is followed by another PAGE TWO instruction.
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Freescale Semiconductor
Glossary
EORA
Operation:
Description:
CCR Details:
EORA
Exclusive OR A
(A) ⊕ (M) ⇒ A
Performs the logical exclusive OR between the content of accumulator A
and the content of memory location M. The result is placed in A. Each bit of
A after the operation is the logical exclusive OR of the corresponding bits of
M and A before the operation.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
EORA #opr8i
EORA opr8a
EORA opr16a
EORA oprx0_xysp
EORA oprx9,xysp
EORA oprx16,xysp
EORA [D,xysp]
EORA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
88
98
B8
A8
A8
A8
A8
A8
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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179
Instruction Glossary
EORB
Operation:
Description:
CCR Details:
EORB
Exclusive OR B
(B) ⊕ (M) ⇒ B
Performs the logical exclusive OR between the content of accumulator B
and the content of memory location M. The result is placed in A. Each bit of
A after the operation is the logical exclusive OR of the corresponding bits of
M and B before the operation.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
EORB #opr8i
EORB opr8a
EORB opr16a
EORB oprx0_xysp
EORB oprx9,xysp
EORB oprx16,xysp
EORB [D,xysp]
EORB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C8
D8
F8
E8
E8
E8
E8
E8
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Freescale Semiconductor
Glossary
ETBL
Operation:
Description:
Extended Table Lookup and Interpolate
ETBL
(M : M + 1) + [(B) × ((M + 2 : M + 3) – (M : M + 1))] ⇒ D
ETBL linearly interpolates one of 256 result values that fall between each
pair of data entries in a lookup table stored in memory. Data entries in the
table represent the y values of endpoints of equally-spaced line segments.
Table entries and the interpolated result are 16-bit values. The result is
stored in the D accumulator.
Before executing ETBL, an index register points to the table entry
corresponding to the x value (X1 that is closest to, but less than or equal to,
the desired lookup point (XL, YL). This defines the left end of a line segment
and the right end is defined by the next data entry in the table. Prior to
execution, accumulator B holds a binary fraction (radix left of MSB)
representing the ratio of (XL–X1) ÷ (X2–X1).
The 16-bit unrounded result is calculated using the following expression:
D = Y1 + [(B) × (Y2 – Y1)]
Where:
(B) = (XL – X1) ÷ (X2 – X1)
Y1 = 16-bit data entry pointed to by <effective address>
Y2 = 16-bit data entry pointed to by <effective address> + 2
The intermediate value [(B) × (Y2 – Y1)] produces a 24-bit result with the
radix point between bits 7 and 8. Any indexed addressing mode, except
indirect modes or 9-bit and 16-bit offset modes, can be used to identify the
first data point (X1,Y1). The second data point is the next table entry.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
∆(1)
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
C: Set if result can be rounded up; cleared otherwise
1. C-bit was undefined in original M68HC12
Source Form
ETBL oprx0_xysp
Address
Mode
IDX
Access Detail
Object Code
HCS12
18 3F xb
ORRffffffP
M68HC12
ORRffffffP
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181
Instruction Glossary
EXG
EXG
Exchange Register Contents
Operation:
See table
Description:
Exchanges the contents of registers specified in the instruction as shown
below. Note that the order in which exchanges between 8-bit and 16-bit
registers are specified affects the high byte of the 16-bit registers differently.
Exchanges of D with A or B are ambiguous. Cases involving TMP2 and
TMP3 are reserved for Freescale use, so some assemblers may not permit
their use, but it is possible to generate these cases by using DC.B or DC.W
assembler directives.
S
CCR Details:
X
H
I
N
Z
V
C
Or:
–
–
–
–
–
–
–
–
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
None affected, unless the CCR is the destination register. Condition codes
take on the value of the corresponding source bits, except that the X mask
bit cannot change from 0 to 1. Software can leave the X bit set, leave it
cleared, or change it from 1 to 0, but it can be set only in response to any
reset or by recognition of an XIRQ interrupt.
Address
Mode
Source Form
EXG abcdxys,abcdxys
INH
Access Detail
Object Code(1)
HCS12
B7 eb
M68HC12
P
P
1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent
the low-order destination digit (bit 3 is a don’t care). Values are in hexadecimal.
8
9
A
B
0
A⇔A
B⇔A
CCR ⇔ A
1
A⇔B
B⇔B
CCR ⇔ B
2
A ⇔ CCR
B ⇔ CCR
CCR ⇔ CCR
3
4
5
6
7
$00:A ⇒ TMP2 $00:B ⇒ TMP2 $00:CCR ⇒ TMP2
TMP2L ⇒ A
TMP2L ⇒ B
TMP2L ⇒ CCR
$00:CCR ⇒ D
$00:A ⇒ D
$00:B ⇒ D
B ⇒ CCR
$00:A ⇒ X
$00:B ⇒ X
$00:CCR ⇒ X
XL ⇒ A
XL ⇒ B
XL ⇒ CCR
$00:A ⇒ Y
$00:B ⇒ Y
$00:CCR ⇒ Y
YL ⇒ A
YL ⇒ B
YL ⇒ CCR
$00:A ⇒ SP
$00:B ⇒ SP
$00:CCR ⇒ SP
SPL ⇒ A
SPL ⇒ B
SPL ⇒ CCR
C
D
E
F
TMP3L ⇒ A
B⇒A
XL ⇒ A
YL ⇒ A
SPL ⇒ A
$00:A ⇒ TMP3
A⇒B
$00:A ⇒ X
$00:A ⇒ Y
$00:A ⇒ SP
TMP3L ⇒ B
B⇒B
XL ⇒ B
YL ⇒ B
SPL ⇒ B
$FF:B ⇒ TMP3
$FF ⇒ A
$FF:B ⇒ X
$FF:B ⇒ Y
$FF:B ⇒ SP
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
$FF:CCR ⇒ TMP3 $FF:CCR ⇒ D $FF:CCR ⇒ X $FF:CCR ⇒ Y $FF:CCR ⇒ SP
TMP3 ⇔ TMP2
D ⇔ TMP2
X ⇔ TMP2
Y ⇔ TMP2
SP ⇔ TMP2
TMP3 ⇔ D
D⇔D
X⇔D
Y⇔D
SP ⇔ D
TMP3 ⇔ X
D⇔X
X⇔X
Y⇔X
SP ⇔ X
TMP3 ⇔ Y
D⇔Y
X⇔Y
Y⇔Y
SP ⇔ Y
TMP3 ⇔ SP
D ⇔ SP
X ⇔ SP
Y ⇔ SP
SP ⇔ SP
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Freescale Semiconductor
Glossary
FDIV
Operation:
Description:
FDIV
Fractional Divide
(D) ÷ (X) ⇒ X; Remainder ⇒ D
Divides an unsigned 16-bit numerator in double accumulator D by an
unsigned 16-bit denominator in index register X, producing an unsigned
16-bit quotient in X and an unsigned 16-bit remainder in D. If both the
numerator and the denominator are assumed to have radix points in the
same positions, the radix point of the quotient is to the left of bit 15. The
numerator must be less than the denominator. In the case of overflow
(denominator is less than or equal to the numerator) or division by zero, the
quotient is set to $FFFF, and the remainder is indeterminate.
FDIV is equivalent to multiplying the numerator by 216 and then performing
32 by 16-bit integer division. The result is interpreted as a binary-weighted
fraction, which resulted from the division of a 16-bit integer by a larger 16-bit
integer. A result of $0001 corresponds to 0.000015, and $FFFF
corresponds to 0.9998. The remainder of an IDIV instruction can be
resolved into a binary-weighted fraction by an FDIV instruction. The
remainder of an FDIV instruction can be resolved into the next 16 bits of
binary-weighted fraction by another FDIV instruction.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
∆
∆
Z: Set if quotient is $0000; cleared otherwise
V: 1 if X ≤ D
Set if the denominator was less than or equal to the numerator;
cleared otherwise
C: X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise
Source Form
FDIV
Address
Mode
INH
Access Detail
Object Code
HCS12
18 11
OffffffffffO
M68HC12
OffffffffffO
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Instruction Glossary
IBEQ
Operation:
Description:
IBEQ
Increment and Branch if Equal to Zero
(Counter) + 1 ⇒ Counter
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC
Add one to the specified counter register A, B, D, X, Y, or SP. If the counter
register has reached zero, branch to the specified relative destination. The
IBEQ instruction is encoded into three bytes of machine code including a
9-bit relative offset (–256 to +255 locations from the start of the next
instruction).
DBEQ and TBEQ instructions are similar to IBEQ except that the counter is
decremented or tested rather than being incremented. Bits 7 and 6 of the
instruction postbyte are used to determine which operation is to be
performed.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
IBEQ abdxys, rel9
REL
Access Detail
Object Code(1)
HCS12
04 lb rr
M68HC12
PPP/PPO
PPP
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (IBEQ –
0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 1:0 for IBEQ.
Count
Bits 2:0
Register
Source Form
Object Code
(If Offset is Positive)
Object Code
(If Offset is Negative)
A
B
000
001
IBEQ A, rel9
IBEQ B, rel9
04 80 rr
04 81 rr
04 90 rr
04 91 rr
D
X
Y
SP
100
101
110
111
IBEQ D, rel9
IBEQ X, rel9
IBEQ Y, rel9
IBEQ SP, rel9
04
04
04
04
04
04
04
04
84
85
86
87
rr
rr
rr
rr
94
95
96
97
rr
rr
rr
rr
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Freescale Semiconductor
Glossary
IBNE
Operation:
Description:
IBNE
Increment and Branch if Not Equal to Zero
(Counter) + 1 ⇒ Counter
If (Counter) not = 0, then (PC) + $0003 + Rel ⇒ PC
Add one to the specified counter register A, B, D, X, Y, or SP. If the counter
register has not been incremented to zero, branch to the specified relative
destination. The IBNE instruction is encoded into three bytes of machine
code including a 9-bit relative offset (–256 to +255 locations from the start
of the next instruction).
DBNE and TBNE instructions are similar to IBNE except that the counter is
decremented or tested rather than being incremented. Bits 7 and 6 of the
instruction postbyte are used to determine which operation is to be
performed.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
IBNE abdxys, rel9
REL
Access Detail
Object Code(1)
HCS12
04 lb rr
M68HC12
PPP/PPO
PPP
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (IBEQ –
0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 1:0 for IBNE.
Count
Bits 2:0
Register
Source Form
Object Code
(If Offset is Positive)
Object Code
(If Offset is Negative)
A
B
000
001
IBNE A, rel9
IBNE B, rel9
04 A0 rr
04 A1 rr
04 B0 rr
04 B1 rr
D
X
Y
SP
100
101
110
111
IBNE D, rel9
IBNE X, rel9
IBNE Y, rel9
IBNE SP, rel9
04
04
04
04
04
04
04
04
A4
A5
A6
A7
rr
rr
rr
rr
B4
B5
B6
B7
rr
rr
rr
rr
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Instruction Glossary
IDIV
Operation:
Description:
CCR Details:
IDIV
Integer Divide
(D) ÷ (X) ⇒ X; Remainder ⇒ D
Divides an unsigned 16-bit dividend in double accumulator D by an
unsigned 16-bit divisor in index register X, producing an unsigned 16-bit
quotient in X, and an unsigned 16-bit remainder in D. If both the divisor and
the dividend are assumed to have radix points in the same positions, the
radix point of the quotient is to the right of bit 0. In the case of division by
zero, C is set, the quotient is set to $FFFF, and the remainder is
indeterminate.
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
0
∆
Z: Set if quotient is $0000; cleared otherwise
V: 0; cleared
C: X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise
Source Form
IDIV
Address
Mode
INH
Access Detail
Object Code
HCS12
18 10
OffffffffffO
M68HC12
OffffffffffO
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Freescale Semiconductor
Glossary
IDIVS
Operation:
Description:
IDIVS
Integer Divide (Signed)
(D) ÷ (X) ⇒ X; Remainder ⇒ D
Performs signed integer division of a signed 16-bit numerator in double
accumulator D by a signed 16-bit denominator in index register X, producing
a signed 16-bit quotient in X, and a signed 16-bit remainder in D. If division
by zero is attempted, the values in D and X are not changed, C is set, and
the values of the N, Z, and V status bits are undefined.
Other than division by zero, which is not legal and causes the C status bit to
be set, the only overflow case is:
$8000
–32,768
------------------ = --------------------- = +32,768
$FFFF
–1
But the highest positive value that can be represented in a 16-bit two’s
complement number is 32,767 ($7FFF).
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Undefined after overflow or division by zero
Z: Set if quotient is $0000; cleared otherwise
Undefined after overflow or division by zero
V: Set if the result was > $7FFF or < $8000; cleared otherwise
Undefined after division by zero
C: X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0
Set if denominator was $0000; cleared otherwise
Source Form
IDIVS
Address
Mode
INH
Access Detail
Object Code
HCS12
18 15
OffffffffffO
M68HC12
OffffffffffO
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187
Instruction Glossary
INC
Operation:
Description:
INC
Increment Memory
(M) + $01 ⇒ M
Add one to the content of memory location M.
The N, Z and V status bits are set or cleared according to the results of the
operation. The C status bit is not affected by the operation, thus allowing the
INC instruction to be used as a loop counter in multiple-precision
computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on two’s
complement values, all signed branches are available.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: Set if there is a two’s complement overflow as a result of the
operation; cleared otherwise. Two’s complement overflow occurs if
and only if (M) was $7F before the operation.
Source Form
INC opr16a
INC oprx0_xysp
INC oprx9,xysp
INC oprx16,xysp
INC [D,xysp]
INC [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
72
62
62
62
62
62
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Freescale Semiconductor
Glossary
INCA
Operation:
Description:
INCA
Increment A
(A) + $01 ⇒ A
Add one to the content of accumulator A.
The N, Z, and V status bits are set or cleared according to the results of the
operation. The C status bit is not affected by the operation, thus allowing the
INC instruction to be used as a loop counter in multiple-precision
computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on two’s
complement values, all signed branches are available.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: Set if there is a two’s complement overflow as a result of the
operation; cleared otherwise. Two’s complement overflow occurs if
and only if (A) was $7F before the operation.
Source Form
INCA
Address
Mode
INH
Access Detail
Object Code
HCS12
42
O
M68HC12
O
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Freescale Semiconductor
189
Instruction Glossary
INCB
Operation:
Description:
INCB
Increment B
(B) + $01 ⇒ B
Add one to the content of accumulator B.
The N, Z, and V status bits are set or cleared according to the results of the
operation. The C status bit is not affected by the operation, thus allowing the
INC instruction to be used as a loop counter in multiple-precision
computations.
When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE
branches can be expected to perform consistently. When operating on two’s
complement values, all signed branches are available.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: Set if there is a two’s complement overflow as a result of the
operation; cleared otherwise. Two’s complement overflow occurs if
and only if (B) was $7F before the operation.
Source Form
INCB
Address
Mode
INH
Access Detail
Object Code
HCS12
52
O
M68HC12
O
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Freescale Semiconductor
Glossary
INS
Operation:
Description:
CCR Details:
INS
Increment Stack Pointer
(SP) + $0001 ⇒ SP
Add one to the SP. This instruction is assembled to LEAS 1,SP. The LEAS
instruction does not affect condition codes as an INX or INY instruction
would.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
INS
translates to... LEAS 1,SP
Address
Mode
IDX
Access Detail
Object Code
HCS12
1B 81
Pf
M68HC12
PP(1)
1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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Instruction Glossary
INX
Operation:
Description:
INX
Increment Index Register X
(X) + $0001 ⇒ X
Add one to index register X. LEAX 1,X can produce the same result but
LEAX does not affect the Z status bit. Although the LEAX instruction is more
flexible, INX requires only one byte of object code.
INX operation affects only the Z status bit.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z: Set if result is $0000; cleared otherwise
Source Form
INX
Address
Mode
INH
Access Detail
Object Code
HCS12
08
O
M68HC12
O
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Freescale Semiconductor
Glossary
INY
Operation:
Description:
INY
Increment Index Register Y
(Y) + $0001 ⇒ Y
Add one to index register Y. LEAY 1,Y can produce the same result but
LEAY does not affect the Z status bit. Although the LEAY instruction is more
flexible, INY requires only one byte of object code.
INY operation affects only the Z status bit.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
∆
–
–
Z: Set if result is $0000; cleared otherwise
Source Form
INY
Address
Mode
INH
Access Detail
Object Code
HCS12
02
O
M68HC12
O
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Instruction Glossary
JMP
Operation:
Description:
CCR Details:
Source Form
JMP opr16a
JMP oprx0_xysp
JMP oprx9,xysp
JMP oprx16,xysp
JMP [D,xysp]
JMP [oprx16,xysp]
JMP
Jump
Effective Address ⇒ PC
Jumps to the instruction stored at the effective address. The effective
address is obtained according to the rules for extended or indexed
addressing.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
06
05
05
05
05
05
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
M68HC12
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
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Freescale Semiconductor
Glossary
JSR
Operation:
Description:
JSR
Jump to Subroutine
(SP) – $0002 ⇒ SP
RTNH : RTNL ⇒ M(SP) : M(SP + 1)
Subroutine Address ⇒ PC
Sets up conditions to return to normal program flow, then transfers control
to a subroutine. Uses the address of the instruction following the JSR as a
return address.
Decrements the SP by two to allow the two bytes of the return address to be
stacked.
Stacks the return address. The SP points to the high order byte of the return
address.
Calculates an effective address according to the rules for extended, direct,
or indexed addressing.
Jumps to the location determined by the effective address.
Subroutines are normally terminated with an RTS instruction, which
restores the return address from the stack.
CCR Details:
Source Form
JSR opr8a
JSR opr16a
JSR oprx0_xysp
JSR oprx9,xysp
JSR oprx16,xysp
JSR [D,xysp]
JSR [oprx16,xysp]
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
17
16
15
15
15
15
15
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
SPPP
SPPP
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
M68HC12
PPPS
PPPS
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
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Instruction Glossary
LBCC
Operation:
Long Branch if Carry Cleared
(Same as LBHS)
LBCC
If C = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 0.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBCC rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 24 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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Freescale Semiconductor
Glossary
LBCS
Operation:
Long Branch if Carry Set
(Same as LBLO)
LBCS
If C = 1, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the C status bit and branches if C = 1.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBCS rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 25 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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Instruction Glossary
LBEQ
Operation:
LBEQ
Long Branch if Equal
If Z = 1, (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 1.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBEQ rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 27 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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Freescale Semiconductor
Glossary
LBGE
Operation:
Long Branch if Greater Than or Equal to Zero
LBGE
If N ⊕ V = 0, (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers, if (Accumulator) ≥ Memory), then
branch
Description:
LBGE can be used to branch after subtracting or comparing signed two’s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is greater than or equal to the value in M. After CBA or SBA, the branch
occurs if the value in B is greater than or equal to the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBGE rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 2C qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
199
Instruction Glossary
LBGT
Operation:
LBGT
Long Branch if Greater Than Zero
If Z + (N ⊕ V) = 0, then (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers, If (Accumulator) > (Memory), then
branch
Description:
LBGT can be used to branch after subtracting or comparing signed two’s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is greater than or equal to the value in M. After CBA or SBA, the branch
occurs if the value in B is greater than or equal to the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBGT rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 2E qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
200
Freescale Semiconductor
Glossary
LBHI
Operation:
Long Branch if Higher
LBHI
If C + Z = 0, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) > (Memory), then branch
Description:
LBHI can be used to branch after subtracting or comparing unsigned values.
After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB,
or SUBD, the branch occurs if the CPU register value is greater than the
value in M. After CBA or SBA, the branch occurs if the value in B is greater
than the value in A. LBHI should not be used for branching after instructions
that do not affect the C bit, such as increment, decrement, load, store, test,
clear, or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBHI rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 22 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
201
Instruction Glossary
LBHS
Operation:
Long Branch if Higher or Same
(Same as LBCC)
LBHS
If C = 0, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) ≥ (Memory), then branch
Description:
LBHS can be used to branch after subtracting or comparing unsigned
values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA,
SUBB, or SUBD, the branch occurs if the CPU register value is greater than
or equal to the value in M. After CBA or SBA, the branch occurs if the value
in B is greater than or equal to the value in A. LBHS should not be used for
branching after instructions that do not affect the C bit, such as increment,
decrement, load, store, test, clear, or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBHS rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 24 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
202
Freescale Semiconductor
Glossary
LBLE
Operation:
Long Branch if Less Than or Equal to Zero
LBLE
If Z + (N ⊕ V) = 1, then (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers, if (Accumulator) ≤ (Memory), then
branch.
Description:
LBLE can be used to branch after subtracting or comparing signed two’s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is less than or equal to the value in M. After CBA or SBA, the branch occurs
if the value in B is less than or equal to the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBLE rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 2F qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
203
Instruction Glossary
LBLO
Operation:
LBLO
Long Branch if Lower
(Same as LBCS)
If C = 1, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) < (Memory), then branch
Description:
LBLO can be used to branch after subtracting or comparing unsigned
values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SUBA, SUBB, or
SUBD, the branch occurs if the CPU register value is less than the value in
M. After CBA or SBA, the branch occurs if the value in B is less than the
value in A. LBLO should not be used for branching after instructions that do
not affect the C bit, such as increment, decrement, load, store, test, clear,
or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBLO rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 25 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
204
Freescale Semiconductor
Glossary
LBLS
Operation:
Long Branch if Lower or Same
LBLS
If C + Z = 1, then (PC) + $0004 + Rel ⇒ PC
For unsigned binary numbers, if (Accumulator) ≤ (Memory), then branch
Description:
LBLS can be used to branch after subtracting or comparing unsigned
values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA,
SUBB, or SUBD, the branch occurs if the CPU register value is less than or
equal to the value in M. After CBA or SBA, the branch occurs if the value in
B is less than or equal to the value in A. LBLS should not be used for
branching after instructions that do not affect the C bit, such as increment,
decrement, load, store, test, clear, or complement.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBLS rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 23 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
205
Instruction Glossary
LBLT
Operation:
Long Branch if Less Than Zero
LBLT
If N ⊕ V = 1, (PC) + $0004 + Rel ⇒ PC
For signed two’s complement numbers, if (Accumulator) < (Memory), then
branch
Description:
LBLT can be used to branch after subtracting or comparing signed two-s
complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,
SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value
is less than the value in M. After CBA or SBA, the branch occurs if the value
in B is less than the value in A.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBLT rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 2D qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
206
Freescale Semiconductor
Glossary
LBMI
Operation:
LBMI
Long Branch if Minus
If N = 1, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 1.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBMI rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 2B qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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207
Instruction Glossary
LBNE
Operation:
Long Branch if Not Equal to Zero
LBNE
If Z = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the Z status bit and branches if Z = 0.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBNE rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 26 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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Freescale Semiconductor
Glossary
LBPL
Operation:
LBPL
Long Branch if Plus
If N = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the N status bit and branches if N = 0.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBPL rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 2A qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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209
Instruction Glossary
LBRA
Operation:
Description:
Long Branch Always
LBRA
(PC) + $0004 + Rel ⇒ PC
Unconditional branch to an address calculated as shown in the expression.
Rel is a relative offset stored as a two’s complement number in the second
and third bytes of machine code corresponding to the long branch
instruction.
Execution time is longer when a conditional branch is taken than when it is
not, because the instruction queue must be refilled before execution
resumes at the new address. Since the LBRA branch condition is always
satisfied, the branch is always taken, and the instruction queue must always
be refilled, so execution time is always the larger value.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBRA rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 20 qq rr
OPPP
M68HC12
OPPP
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Freescale Semiconductor
Glossary
LBRN
Operation:
Description:
Long Branch Never
LBRN
(PC) + $0004 ⇒ PC
Never branches. LBRN is effectively a 4-byte NOP that requires three
cycles to execute. LBRN is included in the instruction set to provide a
complement to the LBRA instruction. The instruction is useful during
program debug, to negate the effect of another branch instruction without
disturbing the offset byte. A complement for LBRA is also useful in compiler
implementations.
Execution time is longer when a conditional branch is taken than when it is
not, because the instruction queue must be refilled before execution
resumes at the new address. Since the LBRN branch condition is never
satisfied, the branch is never taken, and the queue does not need to be
refilled, so execution time is always the smaller value.
CCR Details:
Source Form
LBRN rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 21 qq rr
OPO
M68HC12
OPO
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Freescale Semiconductor
211
Instruction Glossary
LBVC
Operation:
Long Branch if Overflow Cleared
LBVC
If V = 0, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 0.
LBVC causes a branch when a previous operation on two’s complement
binary values does not cause an overflow. That is, when LBVC follows a
two’s complement operation, a branch occurs when the result of the
operation is valid.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBVC rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 28 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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Freescale Semiconductor
Glossary
LBVS
Operation:
Long Branch if Overflow Set
LBVS
If V = 1, then (PC) + $0004 + Rel ⇒ PC
Simple branch
Description:
Tests the V status bit and branches if V = 1.
LBVS causes a branch when a previous operation on two’s complement
binary values causes an overflow. That is, when LBVS follows a two’s
complement operation, a branch occurs when the result of the operation is
invalid.
See 3.8 Relative Addressing Mode for details of branch execution.
CCR Details:
Source Form
LBVS rel16
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
REL
Access Detail
Object Code
HCS12
18 29 qq rr
OPPP/OPO(1)
M68HC12
OPPP/OPO(1)
1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles
if the branch is not taken.
Test
r>m
r≥m
r=m
r≤m
r<m
r>m
r≥m
r=m
r≤m
r<m
Carry
Negative
Overflow
r=0
Always
Branch
Mnemonic
Opcode
LBGT
18 2E
LBGE
18 2C
LBEQ
18 27
LBLE
18 2F
LBLT
18 2D
LBHI
18 22
LBHS/LBCC
18 24
LBEQ
18 27
LBLS
18 23
LBLO/LBCS
18 25
LBCS
18 25
LBMI
18 2B
LBVS
18 29
LBEQ
18 27
LBRA
18 20
Boolean
Test
Z + (N ⊕ V) = 0
r≤m
N⊕V=0
r<m
Z=1
r≠m
Z + (N ⊕ V) = 1
r>m
N⊕V=1
r≥m
C+Z=0
r≤m
C=0
r<m
Z=1
r≠m
C+Z=1
r>m
C=1
r≥m
C=1
No Carry
N=1
Plus
V=1
No Overflow
Z=1
r≠0
—
Never
Complementary Branch
Mnemonic
Opcode
Comment
LBLE
18 2F
Signed
LBLT
18 2D
Signed
LBNE
18 26
Signed
LBGT
18 2E
Signed
LBGE
18 2C
Signed
LBLS
18 23
Unsigned
LBLO/LBCS
18 25
Unsigned
LBNE
18 26
Unsigned
LBHI
18 22
Unsigned
LBHS/LBCC
18 24
Unsigned
LBCC
18 24
Simple
LBPL
18 2A
Simple
LBVC
18 28
Simple
LBNE
18 26
Simple
LBRN
18 21
Unconditional
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Freescale Semiconductor
213
Instruction Glossary
LDAA
Operation:
Description:
CCR Details:
LDAA
Load Accumulator A
(M) ⇒ A
Loads the content of memory location M into accumulator A. The condition
codes are set according to the data.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
LDAA #opr8i
LDAA opr8a
LDAA opr16a
LDAA oprx0_xysp
LDAA oprx9,xysp
LDAA oprx16,xysp
LDAA [D,xysp]
LDAA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
86
96
B6
A6
A6
A6
A6
A6
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Freescale Semiconductor
Glossary
LDAB
Operation:
Description:
CCR Details:
LDAB
Load Accumulator B
(M) ⇒ B
Loads the content of memory location M into accumulator B. The condition
codes are set according to the data.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
LDAB #opr8i
LDAB opr8a
LDAB opr16a
LDAB oprx0_xysp
LDAB oprx9,xysp
LDAB oprx16,xysp
LDAB [D,xysp]
LDAB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C6
D6
F6
E6
E6
E6
E6
E6
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Freescale Semiconductor
215
Instruction Glossary
LDD
Operation:
Description:
CCR Details:
LDD
Load Double Accumulator
(M : M+1) ⇒ A : B
Loads the contents of memory locations M and M+1 into double
accumulator D. The condition codes are set according to the data. The
information from M is loaded into accumulator A, and the information from
M+1 is loaded into accumulator B.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
LDD #opr16i
LDD opr8a
LDD opr16a
LDD oprx0_xysp
LDD oprx9,xysp
LDD oprx16,xysp
LDD [D,xysp]
LDD [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
CC
DC
FC
EC
EC
EC
EC
EC
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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Freescale Semiconductor
Glossary
LDS
Operation:
Description:
CCR Details:
LDS
Load Stack Pointer
(M : M+1) ⇒ SP
Loads the most significant byte of the SP with the content of memory
location M, and loads the least significant byte of the SP with the content of
the next byte of memory at M+1.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
LDS #opr16i
LDS opr8a
LDS opr16a
LDS oprx0_xysp
LDS oprx9,xysp
LDS oprx16,xysp
LDS [D,xysp]
LDS [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
CF
DF
FF
EF
EF
EF
EF
EF
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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217
Instruction Glossary
LDX
Operation:
Description:
CCR Details:
LDX
Load Index Register X
(M : M+1) ⇒ X
Loads the most significant byte of index register X with the content of
memory location M, and loads the least significant byte of X with the content
of the next byte of memory at M+1.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
CE
DE
FE
EE
EE
EE
EE
EE
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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Freescale Semiconductor
Glossary
LDY
Operation:
Description:
CCR Details:
LDY
Load Index Register Y
(M : M+1) ⇒ Y
Loads the most significant byte of index register Y with the content of
memory location M, and loads the least significant byte of Y with the content
of the next memory location at M+1.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
LDY #opr16i
LDY opr8a
LDY opr16a
LDY oprx0_xysp
LDY oprx9,xysp
LDY oprx16,xysp
LDY [D,xysp]
LDY [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
CD
DD
FD
ED
ED
ED
ED
ED
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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219
Instruction Glossary
LEAS
Operation:
Description:
Load Stack Pointer with Effective Address
LEAS
Effective Address ⇒ SP
Loads the stack pointer with an effective address specified by the program.
The effective address can be any indexed addressing mode operand
address except an indirect address. Indexed addressing mode operand
addresses are formed by adding an optional constant supplied by the
program or an accumulator value to the current value in X, Y, SP, or PC.
See 3.9 Indexed Addressing Modes for more details.
LEAS does not alter condition code bits. This allows stack modification
without disturbing CCR bits changed by recent arithmetic operations.
Operation is a bit more complex when LEAS is used with auto-increment or
auto-decrement operand specifications and the SP is the referenced index
register. The index register is loaded with what would have gone out to the
address bus in the case of a load index instruction. In the case of a
pre-increment or pre-decrement, the modification is made before the index
register is loaded. In the case of a post-increment or post-decrement,
modification would have taken effect after the address went out on the
address bus, so post-modification does not affect the content of the index
register.
In the unusual case where LEAS involves two different index registers and
post-increment or post-decrement, both index registers are modified as
demonstrated by the following example. Consider the instruction LEAS
4,Y+. First S is loaded with the value of Y, then Y is incremented by 4.
CCR Details:
Source Form
LEAS oprx0_xysp
LEAS oprx9,xysp
LEAS oprx16,xysp
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
IDX
IDX1
IDX2
Access Detail
Object Code
HCS12
1B xb
1B xb ff
1B xb ee ff
Pf
PO
PP
M68HC12
PP(1)
PO
PP
1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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Freescale Semiconductor
Glossary
LEAX
Operation:
Description:
Load X with Effective Address
LEAX
Effective Address ⇒ X
Loads index register X with an effective address specified by the program.
The effective address can be any indexed addressing mode operand
address except an indirect address. Indexed addressing mode operand
addresses are formed by adding an optional constant supplied by the
program or an accumulator value to the current value in X, Y, SP, or PC.
See 3.9 Indexed Addressing Modes for more details.
Operation is a bit more complex when LEAX is used with auto-increment or
auto-decrement operand specifications and index register X is the
referenced index register. The index register is loaded with what would have
gone out to the address bus in the case of a load indexed instruction. In the
case of a pre-increment or pre-decrement, the modification is made before
the index register is loaded. In the case of a post-increment or
post-decrement, modification would have taken effect after the address
went out on the address bus, so post-modification does not affect the
content of the index register.
In the unusual case where LEAX involves two different index registers and
post-increment and post-decrement, both index registers are modified as
demonstrated by the following example. Consider the instruction LEAX
4,Y+. First X is loaded with the value of Y, then Y is incremented by 4.
CCR Details:
Source Form
LEAX oprx0_xysp
LEAX oprx9,xysp
LEAX oprx16,xysp
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
IDX
IDX1
IDX2
Access Detail
Object Code
HCS12
1A xb
1A xb ff
1A xb ee ff
Pf
PO
PP
M68HC12
PP(1)
PO
PP
1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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Instruction Glossary
LEAY
Operation:
Description:
Load Y with Effective Address
LEAY
Effective Address ⇒ Y
Loads index register Y with an effective address specified by the program.
The effective address can be any indexed addressing mode operand
address except an indirect address. Indexed addressing mode operand
addresses are formed by adding an optional constant supplied by the
program or an accumulator value to the current value in X, Y, SP, or PC.
See 3.9 Indexed Addressing Modes for more details.
Operation is a bit more complex when LEAY is used with auto-increment or
auto-decrement operand specifications and index register Y is the
referenced index register. The index register is loaded with what would have
gone out to the address bus in the case of a load indexed instruction. In the
case of a pre-increment or pre-decrement, the modification is made before
the index register is loaded. In the case of a post-increment or
post-decrement, modification would have taken effect after the address
went out on the address bus, so post-modification does not affect the
content of the index register.
In the unusual case where LEAY involves two different index registers and
post-increment and post-decrement, both index registers are modified as
demonstrated by the following example. Consider the instruction LEAY
4,X+. First Y is loaded with the value of X, then X is incremented by 4.
CCR Details:
Source Form
LEAY oprx0_xysp
LEAY oprx9,xysp
LEAY oprx16,xysp
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
IDX
IDX1
IDX2
Access Detail
Object Code
HCS12
19 xb
19 xb ff
19 xb ee ff
Pf
PO
PP
M68HC12
PP(1)
PO
PP
1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this
instruction.
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Freescale Semiconductor
Glossary
LSL
LSL
Logical Shift Left Memory
(Same as ASL)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
0
Shifts all bits of the memory location M one place to the left. Bit 0 is loaded
with 0. The C status bit is loaded from the most significant bit of M.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: M7
Set if the LSB of M was set before the shift; cleared otherwise
Source Form
LSL opr16a
LSL oprx0_xysp
LSL oprx9,xysp
LSL oprx16,xysp
LSL [D,xysp]
LSL [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
78
68
68
68
68
68
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Instruction Glossary
LSLA
LSLA
Logical Shift Left A
(Same as ASLA)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
0
Shifts all bits of accumulator A one place to the left. Bit 0 is loaded with 0.
The C status bit is loaded from the most significant bit of A.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: A7
Set if the LSB of A was set before the shift; cleared otherwise
Source Form
LSLA
Address
Mode
INH
Access Detail
Object Code
HCS12
48
O
M68HC12
O
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Freescale Semiconductor
Glossary
LSLB
LSLB
Logical Shift Left B
(Same as ASLB)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
0
Shifts all bits of accumulator B one place to the left. Bit 0 is loaded with 0.
The C status bit is loaded from the most significant bit of B.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: B7
Set if the LSB of B was set before the shift; cleared otherwise
Source Form
LSLB
Address
Mode
INH
Access Detail
Object Code
HCS12
58
O
M68HC12
O
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Instruction Glossary
LSLD
LSLD
Logical Shift Left Double
(Same as ASLD)
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
b7 – – – – – – b0
Accumulator A
Accumulator B
0
Shifts all bits of double accumulator D one place to the left. Bit 0 is loaded
with 0. The C status bit is loaded from the most significant bit of accumulator
A.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: D15
Set if the MSB of D was set before the shift; cleared otherwise
Source Form
LSLD
Address
Mode
INH
Access Detail
Object Code
HCS12
59
O
M68HC12
O
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Freescale Semiconductor
Glossary
LSR
LSR
Logical Shift Right Memory
Operation:
0
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of memory location M one place to the right. Bit 7 is loaded with
0. The C status bit is loaded from the least significant bit of M.
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N: 0; cleared
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: M0
Set if the LSB of M was set before the shift; cleared otherwise
Source Form
LSR opr16a
LSR oprx0_xysp
LSR oprx9,xysp
LSR oprx16,xysp
LSR [D,xysp]
LSR [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
74
64
64
64
64
64
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Instruction Glossary
LSRA
LSRA
Logical Shift Right A
Operation:
0
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of accumulator A one place to the right. Bit 7 is loaded with 0.
The C status bit is loaded from the least significant bit of A.
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
C
N: 0; cleared
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: A0
Set if the LSB of A was set before the shift; cleared otherwise
Source Form
LSRA
Address
Mode
INH
Access Detail
Object Code
HCS12
44
O
M68HC12
O
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Freescale Semiconductor
Glossary
LSRB
LSRB
Logical Shift Right B
Operation:
0
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of accumulator B one place to the right. Bit 7 is loaded with 0.
The C status bit is loaded from the least significant bit of B.
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N: 0; cleared
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: B0
Set if the LSB of B was set before the shift; cleared otherwise
Source Form
LSRB
Address
Mode
INH
Access Detail
Object Code
HCS12
54
O
M68HC12
O
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Instruction Glossary
LSRD
LSRD
Logical Shift Right Double
Operation:
0
b7 – – – – – – b0
b7 – – – – – – b0
Accumulator A
Description:
CCR Details:
C
Accumulator B
Shifts all bits of double accumulator D one place to the right. D15 (MSB of
A) is loaded with 0. The C status bit is loaded from D0 (LSB of B).
S
X
H
I
N
Z
V
C
–
–
–
–
0
∆
∆
∆
N: 0; cleared
Z: Set if result is $0000; cleared otherwise
V: D0
Set if, after the shift operation, C is set; cleared otherwise
C: D0
Set if the LSB of D was set before the shift; cleared otherwise
Source Form
LSRD
Address
Mode
INH
Access Detail
Object Code
HCS12
49
O
M68HC12
O
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Freescale Semiconductor
Glossary
MAXA
Operation:
Description:
Place Larger of Two Unsigned 8-Bit Values
in Accumulator A
MAXA
MAX ((A), (M)) ⇒ A
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit value
in accumulator A to determine which is larger and leaves the larger of the
two values in A. The Z status bit is set when the result of the subtraction is
zero (the values are equal), and the C status bit is set when the subtraction
requires a borrow (the value in memory is larger than the value in the
accumulator). When C = 1, the value in A has been replaced by the value in
memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the largest value in a list of values.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = A – M)
Source Form
MAXA oprx0_xysp
MAXA oprx9,xysp
MAXA oprx16,xysp
MAXA [D,xysp]
MAXA [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
18
18
18
18
18
xb
xb ff
xb ee ff
xb
xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
M68HC12
OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP
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Instruction Glossary
MAXM
Operation:
Description:
Place Larger of Two Unsigned 8-Bit Values
in Memory
MAXM
MAX ((A), (M)) ⇒ M
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit value
in accumulator A to determine which is larger and leaves the larger of the
two values in the memory location. The Z status bit is set when the result of
the subtraction is zero (the values are equal), and the C status bit is set
when the subtraction requires a borrow (the value in memory is larger than
the value in the accumulator). When C = 0, the value in accumulator A has
replaced the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = A – M)
Source Form
MAXM oprx0_xysp
MAXM oprx9,xysp
MAXM oprx16,xysp
MAXM [D,xysp]
MAXM [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
1C
1C
1C
1C
1C
xb
xb ff
xb ee ff
xb
xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
M68HC12
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
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Freescale Semiconductor
Glossary
MEM
Operation:
Description:
MEM
Determine Grade of Membership
(Fuzzy Logic)
Grade of Membership ⇒ M(Y)
(Y) + $0001 ⇒ Y
(X) + $0004 ⇒ X
Before executing MEM, initialize A, X, and Y. Load A with the current crisp
value of a system input variable. Load Y with the fuzzy input RAM location
where the grade of membership is to be stored. Load X with the first address
of a 4-byte data structure that describes a trapezoidal membership function.
The data structure consists of:
•
Point_1 — The x-axis starting point for the leading side (at MX)
•
Point_2 — The x-axis position of the rightmost point (at MX+1)
•
Slope_1 — The slope of the leading side (at MX+2)
•
Slope_2 — The slope of the trailing side (at MX+3); the right side
slopes up and to the left from point_2
A slope_1 or slope_2 value of $00 is a special case in which the
membership function either starts with a grade of $FF at input = point_1, or
ends with a grade of $FF at input = point_2 (infinite slope).
During execution, the value of A remains unchanged. X is incremented by
four and Y is incremented by one.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
?
–
?
?
?
?
H, N, Z, V, and C may be altered by this instruction.
Source Form
MEM
Address
Mode
Special
Access Detail
Object Code
01
HCS12
M68HC12
RRfOw
RRfOw
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Instruction Glossary
Place Smaller of Two
Unsigned 8-Bit Values
in Accumulator A
MINA
Operation:
Description:
MINA
MIN ((A), (M)) ⇒ A
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit value
in accumulator A to determine which is larger, and leaves the smaller of the
two values in accumulator A. The Z status bit is set when the result of the
subtraction is zero (the values are equal), and the C status bit is set when
the subtraction requires a borrow (the value in memory is larger than the
value in the accumulator). When C = 0, the value in accumulator A has been
replaced by the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand. Auto increment/decrement variations of indexed
addressing facilitate finding the smallest value in a list of values.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = A – M)
Source Form
MINA oprx0_xysp
MINA oprx9,xysp
MINA oprx16,xysp
MINA [D,xysp]
MINA [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
19
19
19
19
19
xb
xb ff
xb ee ff
xb
xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
M68HC12
OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP
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Freescale Semiconductor
Glossary
Place Smaller of Two
Unsigned 8-Bit Values
in Memory
MINM
Operation:
Description:
MINM
MIN ((A), (M)) ⇒ M
Subtracts an unsigned 8-bit value in memory from an unsigned 8-bit value
in accumulator A to determine which is larger and leaves the smaller of the
two values in the memory location. The Z status bit is set when the result of
the subtraction is zero (the values are equal), and the C status bit is set
when the subtraction requires a borrow (the value in memory is larger than
the value in the accumulator). When C = 1, the value in accumulator A has
replaced the value in memory.
The unsigned value in memory is accessed by means of indexed
addressing modes, which allow a great deal of flexibility in specifying the
address of the operand.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Condition codes reflect internal subtraction (R = A – M)
Source Form
MINM oprx0_xysp
MINM oprx9,xysp
MINM oprx16,xysp
MINM [D,xysp]
MINM [oprx16,xysp]
Access Detail
Address
Mode
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Object Code
HCS12
18
18
18
18
18
1D
1D
1D
1D
1D
xb
xb ff
xb ee ff
xb
xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
M68HC12
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
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Instruction Glossary
MOVB
Operation:
Description:
Move a Byte of Data
from One Memory Location to Another
MOVB
(M1) ⇒ M2
Moves the content of one memory location to another memory location. The
content of the source memory location is not changed.
Move instructions use separate addressing modes to access the source and
destination of a move. The following combinations of addressing modes are
supported: IMM–EXT, IMM–IDX, EXT–EXT, EXT–IDX, IDX–EXT, and
IDX–IDX. IDX operands allow indexed addressing mode specifications that
fit in a single postbyte including 5-bit constant, accumulator offsets, and
auto increment/decrement modes. Nine-bit and 16-bit constant offsets
would require additional extension bytes and are not allowed. Indexed
indirect modes (for example [D,r]) are also not allowed.
There are special considerations when using PC-relative addressing with
move instructions. These are discussed in 3.10 Instructions Using
Multiple Modes.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form(1)
MOVB #opr8, opr16a
MOVB #opr8i, oprx0_xysp
MOVB opr16a, opr16a
MOVB opr16a, oprx0_xysp
MOVB oprx0_xysp, opr16a
MOVB oprx0_xysp, oprx0_xysp
Access Detail
Address
Mode
IMM–EXT
IMM–IDX
EXT–EXT
EXT–IDX
IDX–EXT
IDX–IDX
Object Code
HCS12
18
18
18
18
18
18
0B
08
0C
09
0D
0A
ii
xb
hh
xb
xb
xb
hh
ii
ll
hh
hh
xb
ll
hh ll
ll
ll
OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO
M68HC12
OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO
1. The first operand in the source code statement specifies the source for the move.
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Glossary
MOVW
Operation:
Description:
Move a Word of Data
from One Memory Location to Another
MOVW
(M : M + 11) ⇒ M : M + 12
Moves the content of one 16-bit location in memory to another 16-bit
location in memory. The content of the source memory location is not
changed.
Move instructions use separate addressing modes to access the source and
destination of a move. The following combinations of addressing modes are
supported: IMM–EXT, IMM–IDX, EXT–EXT, EXT–IDX, IDX–EXT, and
IDX–IDX. IDX operands allow indexed addressing mode specifications that
fit in a single postbyte including 5-bit constant, accumulator offsets, and
auto increment/decrement modes. Nine-bit and 16-bit constant offsets
would require additional extension bytes and are not allowed. Indexed
indirect modes (for example [D,r]) are also not allowed.
There are special considerations when using PC-relative addressing with
move instructions. These are discussed in 3.10 Instructions Using
Multiple Modes.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form(1)
MOVW #opr16i, opr16a
MOVW #opr16i, oprx0_xysp
MOVW opr16a, opr16a
MOVW opr16a, oprx0_xysp
MOVW oprx0_xysp, opr16a
MOVW oprx0_xysp, oprx0_xysp
Access Detail
Address
Mode
IMM–EXT
IMM–IDX
EXT–EXT
EXT–IDX
IDX–EXT
IDX–IDX
Object Code
HCS12
18
18
18
18
18
18
03
00
04
01
05
02
jj
xb
hh
xb
xb
xb
kk
jj
ll
hh
hh
xb
hh ll
kk
hh ll
ll
ll
OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO
M68HC12
OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO
1. The first operand in the source code statement specifies the source for the move.
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Instruction Glossary
MUL
Operation:
Description:
CCR Details:
Multiply
8-Bit by 8-Bit (Unsigned)
MUL
(A) × (B) ⇒ A : B
Multiplies the 8-bit unsigned binary value in accumulator A by the 8-bit
unsigned binary value in accumulator B and places the 16-bit unsigned
result in double accumulator D. The carry flag allows rounding the most
significant byte of the result through the sequence MUL, ADCA #0.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
∆
C: R7
Set if bit 7 of the result (B bit 7) is set; cleared otherwise
Source Form
MUL
Address
Mode
INH
Access Detail
Object Code
HCS12
12
O
M68HC12
ffO
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Glossary
NEG
Operation:
Description:
CCR Details:
Negate Memory
NEG
0 – (M) = (M) + 1 ⇒ M
Replaces the content of memory location M with its two’s complement (the
value $80 is left unchanged).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise.
Z: Set if result is $00; cleared otherwise.
V: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if there is a two’s complement overflow from the implied
subtraction from zero; cleared otherwise. Two’s complement
overflow occurs if and only if (M) = $80
C: R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared
otherwise. Set in all cases except when (M) = $00.
Source Form
NEG opr16a
NEG oprx0_xysp
NEG oprx9,xysp
NEG oprx16,xysp
NEG [D,xysp]
NEG [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
70
60
60
60
60
60
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Instruction Glossary
NEGA
Operation:
Description:
CCR Details:
NEGA
Negate A
0 – (A) = (A) + 1 ⇒ A
Replaces the content of accumulator A with its two’s complement (the value
$80 is left unchanged).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if there is a two’s complement overflow from the implied
subtraction from zero; cleared otherwise
Two’s complement overflow occurs if and only if (A) = $80
C: R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared
otherwise
Set in all cases except when (A) = $00
Source Form
NEGA
Address
Mode
INH
Access Detail
Object Code
HCS12
40
O
M68HC12
O
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Glossary
NEGB
Operation:
Description:
CCR Details:
NEGB
Negate B
0 – (B) = (B) + 1 ⇒ B
Replaces the content of accumulator B with its two’s complement (the value
$80 is left unchanged).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0
Set if there is a two’s complement overflow from the implied
subtraction from zero; cleared otherwise
Two’s complement overflow occurs if and only if (B) = $80
C: R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0
Set if there is a borrow in the implied subtraction from zero; cleared
otherwise
Set in all cases except when (B) = $00
Source Form
NEGB
Address
Mode
INH
Access Detail
Object Code
HCS12
50
O
M68HC12
O
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Instruction Glossary
NOP
Operation:
Description:
CCR Details:
Source Form
NOP
NOP
Null Operation
No operation
This single-byte instruction increments the PC and does nothing else. No
other CPU registers are affected. NOP is typically used to produce a time
delay, although some software disciplines discourage CPU
frequency-based time delays. During debug, NOP instructions are
sometimes used to temporarily replace other machine code instructions,
thus disabling the replaced instruction(s).
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
A7
O
M68HC12
O
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Glossary
ORAA
Operation:
Description:
CCR Details:
ORAA
Inclusive OR A
(A) + (M) ⇒ A
Performs bitwise logical inclusive OR between the content of accumulator A
and the content of memory location M and places the result in A. Each bit of
A after the operation is the logical inclusive OR of the corresponding bits of
M and of A before the operation.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
ORAA #opr8i
ORAA opr8a
ORAA opr16a
ORAA oprx0_xysp
ORAA oprx9,xysp
ORAA oprx16,xysp
ORAA [D,xysp]
ORAA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
8A
9A
BA
AA
AA
AA
AA
AA
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Instruction Glossary
ORAB
Operation:
Description:
CCR Details:
ORAB
Inclusive OR B
(B) + (M) ⇒ B
Performs bitwise logical inclusive OR between the content of accumulator B
and the content of memory location M. The result is placed in B. Each bit of
B after the operation is the logical inclusive OR of the corresponding bits of
M and of B before the operation.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
ORAB #opr8i
ORAB opr8a
ORAB opr16a
ORAB oprx0_xysp
ORAB oprx9,xysp
ORAB oprx16,xysp
ORAB [D,xysp]
ORAB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
CA
DA
FA
EA
EA
EA
EA
EA
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Glossary
ORCC
Operation:
Description:
CCR Details:
Logical OR CCR with Mask
ORCC
(CCR) + (M) ⇒ CCR
Performs bitwise logical inclusive OR between the content of memory
location M and the content of the CCR and places the result in the CCR.
Each bit of the CCR after the operation is the logical OR of the
corresponding bits of M and of CCR before the operation. To set one or
more bits, set the corresponding bit of the mask equal to 1. Bits
corresponding to 0s in the mask are not changed by the ORCC operation.
S
X
H
I
N
Z
V
C
⇑
–
⇑
⇑
⇑
⇑
⇑
⇑
Condition code bits are set if the corresponding bit was 1 before the
operation or if the corresponding bit in the instruction-provided mask is 1.
The X interrupt mask cannot be set by any software instruction.
Source Form
ORCC #opr8i
Address
Mode
IMM
Access Detail
Object Code
HCS12
14 ii
P
M68HC12
P
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Instruction Glossary
PSHA
Operation:
Description:
Push A onto Stack
PSHA
(SP) – $0001 ⇒ SP
(A) ⇒ M(SP)
Stacks the content of accumulator A. The stack pointer is decremented by
one. The content of A is then stored at the address the SP points to.
Push instructions are commonly used to save the contents of one or more
CPU registers at the start of a subroutine. Complementary pull instructions
can be used to restore the saved CPU registers just before returning from
the subroutine.
CCR Details:
Source Form
PSHA
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
36
Os
M68HC12
Os
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Glossary
PSHB
Operation:
Description:
Push B onto Stack
PSHB
(SP) – $0001 ⇒ SP
(B) ⇒ M(SP)
Stacks the content of accumulator B. The stack pointer is decremented by
one. The content of B is then stored at the address the SP points to.
Push instructions are commonly used to save the contents of one or more
CPU registers at the start of a subroutine. Complementary pull instructions
can be used to restore the saved CPU registers just before returning from
the subroutine.
CCR Details:
Source Form
PSHB
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
37
Os
M68HC12
Os
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Instruction Glossary
PSHC
Operation:
Description:
Push CCR onto Stack
PSHC
(SP) – $0001 ⇒ SP
(CCR) ⇒ M(SP)
Stacks the content of the condition codes register. The stack pointer is
decremented by one. The content of the CCR is then stored at the address
to which the SP points.
Push instructions are commonly used to save the contents of one or more
CPU registers at the start of a subroutine. Complementary pull instructions
can be used to restore the saved CPU registers just before returning from
the subroutine.
CCR Details:
Source Form
PSHC
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
39
Os
M68HC12
Os
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Glossary
PSHD
Operation:
Description:
Push Double Accumulator onto Stack
PSHD
(SP) – $0002 ⇒ SP
(A : B) ⇒ M(SP) : M(SP+1)
Stacks the content of double accumulator D. The stack pointer is
decremented by two, then the contents of accumulators A and B are stored
at the location to which the SP points.
After PSHD executes, the SP points to the stacked value of accumulator A.
This stacking order is the opposite of the order in which A and B are stacked
when an interrupt is recognized. The interrupt stacking order is
backward-compatible with the M6800, which had no 16-bit accumulator.
Push instructions are commonly used to save the contents of one or more
CPU registers at the start of a subroutine. Complementary pull instructions
can be used to restore the saved CPU registers just before returning from
the subroutine.
CCR Details:
Source Form
PSHD
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
3B
OS
M68HC12
OS
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Instruction Glossary
PSHX
Operation:
Description:
Push Index Register X onto Stack
PSHX
(SP) – $0002 ⇒ SP
(XH : XL) ⇒ M(SP) : M(SP+1)
Stacks the content of index register X. The stack pointer is decremented by
two. The content of X is then stored at the address to which the SP points.
After PSHX executes, the SP points to the stacked value of the high-order
half of X.
Push instructions are commonly used to save the contents of one or more
CPU registers at the start of a subroutine. Complementary pull instructions
can be used to restore the saved CPU registers just before returning from
the subroutine.
CCR Details:
Source Form
PSHX
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
34
OS
M68HC12
OS
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Glossary
PSHY
Operation:
Description:
Push Index Register Y onto Stack
PSHY
(SP) – $0002 ⇒ SP
(YH : YL) ⇒ M(SP) : M(SP+1)
Stacks the content of index register Y. The stack pointer is decremented by
two. The content of Y is then stored at the address to which the SP points.
After PSHY executes, the SP points to the stacked value of the high-order
half of Y.
Push instructions are commonly used to save the contents of one or more
CPU registers at the start of a subroutine. Complementary pull instructions
can be used to restore the saved CPU registers just before returning from
the subroutine.
CCR Details:
Source Form
PSHY
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
35
OS
M68HC12
OS
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Instruction Glossary
PULA
Operation:
Description:
Pull A from Stack
PULA
(M(SP)) ⇒ A
(SP) + $0001 ⇒ SP
Accumulator A is loaded from the address indicated by the stack pointer.
The SP is then incremented by one.
Pull instructions are commonly used at the end of a subroutine, to restore
the contents of CPU registers that were pushed onto the stack before
subroutine execution.
CCR Details:
Source Form
PULA
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
32
ufO
M68HC12
ufO
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Glossary
PULB
Operation:
Description:
Pull B from Stack
PULB
(M(SP)) ⇒ B
(SP) + $0001 ⇒ SP
Accumulator B is loaded from the address indicated by the stack pointer.
The SP is then incremented by one.
Pull instructions are commonly used at the end of a subroutine, to restore
the contents of CPU registers that were pushed onto the stack before
subroutine execution.
CCR Details:
Source Form
PULB
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
33
ufO
M68HC12
ufO
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Instruction Glossary
PULC
Operation:
Description:
Pull Condition Code Register from Stack
PULC
(M(SP)) ⇒ CCR
(SP) + $0001 ⇒ SP
The condition code register is loaded from the address indicated by the
stack pointer. The SP is then incremented by one.
Pull instructions are commonly used at the end of a subroutine to restore the
contents of CPU registers that were pushed onto the stack before
subroutine execution.
CCR Details:
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
Condition codes take on the value pulled from the stack, except that the X
mask bit cannot change from 0 to 1. Software can leave the X bit set, leave
it cleared, or change it from 1 to 0, but it can be set only by a reset or by
recognition of an XIRQ interrupt.
Source Form
PULC
Address
Mode
INH
Access Detail
Object Code
HCS12
38
ufO
M68HC12
ufO
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Glossary
PULD
Operation:
Description:
Pull Double Accumulator from Stack
PULD
(M(SP) : M(SP+1)) ⇒ A : B
(SP) + $0002 ⇒ SP
Double accumulator D is loaded from the address indicated by the stack
pointer. The SP is then incremented by two.
The order in which A and B are pulled from the stack is the opposite of the
order in which A and B are pulled when an RTI instruction is executed. The
interrupt stacking order for A and B is backward-compatible with the M6800,
which had no 16-bit accumulator.
Pull instructions are commonly used at the end of a subroutine to restore the
contents of CPU registers that were pushed onto the stack before
subroutine execution.
CCR Details:
Source Form
PULD
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
3A
UfO
M68HC12
UfO
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Instruction Glossary
PULX
Operation:
Description:
Pull Index Register X from Stack
PULX
(M(SP) : M(SP+1)) ⇒ XH : XL
(SP) + $0002 ⇒ SP
Index register X is loaded from the address indicated by the stack pointer.
The SP is then incremented by two.
Pull instructions are commonly used at the end of a subroutine to restore the
contents of CPU registers that were pushed onto the stack before
subroutine execution.
CCR Details:
Source Form
PULX
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
30
UfO
M68HC12
UfO
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Glossary
PULY
Operation:
Description:
Pull Index Register Y from Stack
PULY
(M(SP) : M(SP+1)) ⇒ YH : YL
(SP) + $0002 ⇒ SP
Index register Y is loaded from the address indicated by the stack pointer.
The SP is then incremented by two.
Pull instructions are commonly used at the end of a subroutine to restore the
contents of CPU registers that were pushed onto the stack before
subroutine execution.
CCR Details:
Source Form
PULY
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
31
UfO
M68HC12
UfO
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Instruction Glossary
REV
Operation:
Description:
REV
Fuzzy Logic Rule Evaluation
MIN-MAX Rule Evaluation
Performs an unweighted evaluation of a list of rules, using fuzzy input values
to produce fuzzy outputs. REV can be interrupted, so it does not adversely
affect interrupt latency.
The REV instruction uses an 8-bit offset from a base address stored in index
register Y to determine the address of each fuzzy input and fuzzy output. For
REV to execute correctly, each rule in the knowledge base must consist of
a table of 8-bit antecedent offsets followed by a table of 8-bit consequent
offsets. The value $FE marks boundaries between antecedents and
consequents and between successive rules. The value $FF marks the end
of the rule list. REV can evaluate any number of rules with any number of
inputs and outputs.
Beginning with the address pointed to by the first rule antecedent, REV
evaluates each successive fuzzy input value until it encounters an $FE
separator. Operation is similar to that of a MINA instruction. The smallest
input value is the truth value of the rule. Then, beginning with the address
pointed to by the first rule consequent, the truth value is compared to each
successive fuzzy output value until another $FE separator is encountered;
if the truth value is greater than the current output value, it is written to the
output. Operation is similar to that of a MAXM instruction. Rules are
processed until an $FF terminator is encountered.
Before executing REV, perform these set up operations.
•
X must point to the first 8-bit element in the rule list.
•
Y must point to the base address for fuzzy inputs and fuzzy outputs.
•
A must contain the value $FF, and the CCR V bit must = 0.
(LDAA #$FF places the correct value in A and clears V.)
•
Clear fuzzy outputs to 0s.
Index register X points to the element in the rule list that is being evaluated.
X is automatically updated so that execution can resume correctly if the
instruction is interrupted. When execution is complete, X points to the next
address after the $FF separator at the end of the rule list.
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Glossary
REV
REV
Fuzzy Logic Rule Evaluation
(Continued)
Index register Y points to the base address for the fuzzy inputs and fuzzy
outputs. The value in Y does not change during execution.
Accumulator A holds intermediate results. During antecedent processing, a
MIN function compares each fuzzy input to the value stored in A, and writes
the smaller of the two to A. When all antecedents have been evaluated, A
contains the smallest input value. This is the truth value used during
consequent processing. Accumulator A must be initialized to $FF for the
MIN function to evaluate the inputs of the first rule correctly. For subsequent
rules, the value $FF is written to A when an $FE marker is encountered. At
the end of execution, accumulator A holds the truth value for the last rule.
The V status bit signals whether antecedents (0) or consequents (1) are
being processed. V must be initialized to 0 for processing to begin with the
antecedents of the first rule. Once execution begins, the value of V is
automatically changed as $FE separators are encountered. At the end of
execution, V should equal 1, because the last element before the $FF end
marker should be a rule consequent. If V is equal to 0 at the end of
execution, the rule list is incorrect.
Fuzzy outputs must be cleared to $00 before processing begins in order for
the MAX algorithm used during consequent processing to work correctly.
Residual output values would cause incorrect comparison.
Refer to Section 9. Fuzzy Logic Support for details.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
?
–
?
?
∆
?
V: 1; Normally set, unless rule structure is erroneous
H, N, Z, and C may be altered by this instruction
Source Form
REV
(replace comma if interrupted)
Address
Mode
Special
Access Detail(1)
Object Code
HCS12
18 3A
Orf(t,tx)O
ff + Orf(t,
M68HC12
Orf(t,tx)O
ff + Orf(t,
1. The 3-cycle loop in parentheses is executed once for each element in the rule list. When an interrupt occurs, there is a
2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or
consequent being processed at the time of the interrupt.
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Instruction Glossary
REVW
Operation:
Description:
Fuzzy Logic Rule Evaluation (Weighted)
REVW
MIN-MAX Rule Evaluation with Optional Rule Weighting
REVW performs either weighted or unweighted evaluation of a list of rules,
using fuzzy inputs to produce fuzzy outputs. REVW can be interrupted, so it
does not adversely affect interrupt latency.
For REVW to execute correctly, each rule in the knowledge base must
consist of a table of 16-bit antecedent pointers followed by a table of 16-bit
consequent pointers. The value $FFFE marks boundaries between
antecedents and consequents, and between successive rules. The value
$FFFF marks the end of the rule list. REVW can evaluate any number of
rules with any number of inputs and outputs.
Setting the C status bit enables weighted evaluation. To use weighted
evaluation, a table of 8-bit weighting factors, one per rule, must be stored in
memory. Index register Y points to the weighting factors.
Beginning with the address pointed to by the first rule antecedent, REVW
evaluates each successive fuzzy input value until it encounters an $FFFE
separator. Operation is similar to that of a MINA instruction. The smallest
input value is the truth value of the rule. Next, if weighted evaluation is
enabled, a computation is performed, and the truth value is modified. Then,
beginning with the address pointed to by the first rule consequent, the truth
value is compared to each successive fuzzy output value until another
$FFFE separator is encountered; if the truth value is greater than the current
output value, it is written to the output. Operation is similar to that of a MAXM
instruction. Rules are processed until an $FFFF terminator is encountered.
Perform these set up operations before execution:
•
X must point to the first 16-bit element in the rule list.
•
A must contain the value $FF, and the CCR V bit must = 0
(LDAA #$FF places the correct value in A and clears V).
•
Clear fuzzy outputs to 0s.
•
Set or clear the CCR C bit. When weighted evaluation is enabled,
Y must point to the first item in a table of 8-bit weighting factors.
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Glossary
REVW
Fuzzy Logic Rule Evaluation (Weighted)
(Continued)
REVW
Index register X points to the element in the rule list that is being evaluated.
X is automatically updated so that execution can resume correctly if the
instruction is interrupted. When execution is complete, X points to the
address after the $FFFF separator at the end of the rule list.
Index register Y points to the weighting factor being used. Y is automatically
updated so that execution can resume correctly if the instruction is
interrupted. When execution is complete, Y points to the last weighting
factor used. When weighting is not used (C = 0), Y is not changed.
Accumulator A holds intermediate results. During antecedent processing, a
MIN function compares each fuzzy input to the value stored in A and writes
the smaller of the two to A. When all antecedents have been evaluated, A
contains the smallest input value. For unweighted evaluation, this is the
truth value used during consequent processing. For weighted evaluation,
the value in A is multiplied by the quantity (Rule Weight + 1) and the upper
eight bits of the result replace the content of A. Accumulator A must be
initialized to $FF for the MIN function to evaluate the inputs of the first rule
correctly. For subsequent rules, the value $FF is automatically written to A
when an $FFFE marker is encountered. At the end of execution,
accumulator A holds the truth value for the last rule.
The V status bit signals whether antecedents (0) or consequents (1) are
being processed. V must be initialized to 0 for processing to begin with the
antecedents of the first rule. Once execution begins, the value of V is
automatically changed as $FFFE separators are encountered. At the end of
execution, V should equal 1, because the last element before the $FF end
marker should be a rule consequent. If V is equal to 0 at the end of
execution, the rule list is incorrect.
Fuzzy outputs must be cleared to $00 before processing begins in order for
the MAX algorithm used during consequent processing to work correctly.
Residual output values would cause incorrect comparison.
Refer to Section 9. Fuzzy Logic Support for details.
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Instruction Glossary
REVW
CCR Details:
REVW
Fuzzy Logic Rule Evaluation (Weighted)
(Concluded)
S
X
H
I
N
Z
V
C
–
–
?
–
?
?
∆
!
V: 1; Normally set, unless rule structure is erroneous
C: Selects weighted (1) or unweighted (0) rule evaluation
H, N, Z, and C may be altered by this instruction
Source Form
REVW
(add 2 at end of ins if wts)
(replace comma if interrupted)
Address
Mode
Special
Access Detail(1)
Object Code
HCS12
18 3B
ORf(t,Tx)O
(r,RfRf)
ffff + ORf(t,
M68HC12
ORf(tTx)O
(r,RfRf)
ffff + ORf(t,
1. The 3-cycle loop in parentheses expands to five cycles for separators when weighting is enabled. The loop is executed
once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry
sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the
interrupt.
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Glossary
ROL
Rotate Left Memory
ROL
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of memory location M one place to the left. Bit 0 is loaded from
the C status bit. The C bit is loaded from the most significant bit of M. Rotate
operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit to
the left, the sequence ASL LOW, ROL MID, ROL HIGH could be used where
LOW, MID and HIGH refer to the low-order, middle and high-order bytes of
the 24-bit value, respectively.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: M7
Set if the MSB of M was set before the shift; cleared otherwise
Source Form
ROL opr16a
ROL oprx0_xysp
ROL oprx9,xysp
ROL oprx16,xysp
ROL [D,xysp]
ROL [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
75
65
65
65
65
65
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Instruction Glossary
ROLA
ROLA
Rotate Left A
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of accumulator A one place to the left. Bit 0 is loaded from the
C status bit. The C bit is loaded from the most significant bit of A. Rotate
operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit to
the left, the sequence ASL LOW, ROL MID, and ROL HIGH could be used
where LOW, MID, and HIGH refer to the low-order, middle, and high-order
bytes of the 24-bit value, respectively.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: A7
Set if the MSB of A was set before the shift; cleared otherwise
Source Form
ROLA
Address
Mode
INH
Access Detail
Object Code
HCS12
45
O
M68HC12
O
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Glossary
ROLB
ROLB
Rotate Left B
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of accumulator B one place to the left. Bit 0 is loaded from the
C status bit. The C bit is loaded from the most significant bit of B. Rotate
operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit to
the left, the sequence ASL LOW, ROL MID, and ROL HIGH could be used
where LOW, MID, and HIGH refer to the low-order, middle and high-order
bytes of the 24-bit value, respectively.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: B7
Set if the MSB of B was set before the shift; cleared otherwise
Source Form
ROLB
Address
Mode
INH
Access Detail
Object Code
HCS12
55
O
M68HC12
O
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Instruction Glossary
ROR
ROR
Rotate Right Memory
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of memory location M one place to the right. Bit 7 is loaded
from the C status bit. The C bit is loaded from the least significant bit of M.
Rotate operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit to
the right, the sequence LSR HIGH, ROR MID, and ROR LOW could be used
where LOW, MID, and HIGH refer to the low-order, middle, and high-order
bytes of the 24-bit value, respectively.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: M0
Set if the LSB of M was set before the shift; cleared otherwise
Source Form
ROR opr16a
ROR oprx0_xysp
ROR oprx9,xysp
ROR oprx16,xysp
ROR [D,xysp]
ROR [oprx16,xysp]
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
76
66
66
66
66
66
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
M68HC12
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
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Glossary
RORA
RORA
Rotate Right A
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of accumulator A one place to the right. Bit 7 is loaded from the
C status bit. The C bit is loaded from the least significant bit of A. Rotate
operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit to
the right, the sequence LSR HIGH, ROR MID, and ROR LOW could be used
where LOW, MID, and HIGH refer to the low-order, middle, and high-order
bytes of the 24-bit value, respectively.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: A0
Set if the LSB of A was set before the shift; cleared otherwise
Source Form
RORA
Address
Mode
INH
Access Detail
Object Code
HCS12
46
O
M68HC12
O
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Instruction Glossary
RORB
RORB
Rotate Right B
Operation:
C
Description:
CCR Details:
b7 – – – – – – b0
C
Shifts all bits of accumulator B one place to the right. Bit 7 is loaded from the
C status bit. The C bit is loaded from the least significant bit of B. Rotate
operations include the carry bit to allow extension of shift and rotate
operations to multiple bytes. For example, to shift a 24-bit value one bit to
the right, the sequence LSR HIGH, ROR MID, and ROR LOW could be used
where LOW, MID, and HIGH refer to the low-order, middle and high-order
bytes of the 24-bit value, respectively.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: N ⊕ C = [N • C] + [N • C] (for N and C after the shift)
Set if (N is set and C is cleared) or (N is cleared and C is set);
cleared otherwise (for values of N and C after the shift)
C: B0
Set if the LSB of B was set before the shift; cleared otherwise
Source Form
RORB
Address
Mode
INH
Access Detail
Object Code
HCS12
56
O
M68HC12
O
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Glossary
RTC
Operation:
Description:
CCR Details:
Source Form
RTC
RTC
Return from Call
(M(SP)) ⇒ PPAGE
(SP) + $0001 ⇒ SP
(M(SP) : M(SP+1)) ⇒ PCH : PCL
(SP) + $0002 ⇒ SP
Terminates subroutines in expanded memory invoked by the CALL
instruction. Returns execution flow from the subroutine to the calling
program. The program overlay page (PPAGE) register and the return
address are restored from the stack; program execution continues at the
restored address. For code compatibility purposes, CALL and RTC also
execute correctly in devices that do not have expanded memory capability.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
0A
uUnfPPP
M68HC12
uUnPPP
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Instruction Glossary
RTI
Operation:
Description:
RTI
Return from Interrupt
(M(SP)) ⇒ CCR; (SP) + $0001 ⇒ SP
(M(SP) : M(SP+1)) ⇒ B : A; (SP) + $0002 ⇒ SP
(M(SP) : M(SP+1)) ⇒ XH : XL; (SP) + $0004 ⇒ SP
(M(SP) : M(SP+1)) ⇒ PCH : PCL; (SP) – $0002 ⇒ SP
(M(SP) : M(SP+1)) ⇒ YH : YL; (SP) + $0004 ⇒ SP
Restores system context after interrupt service processing is completed.
The condition codes, accumulators B and A, index register X, the PC, and
index register Y are restored to a state pulled from the stack. The X mask
bit may be cleared as a result of an RTI instruction, but cannot be set if it
was cleared prior to execution of the RTI instruction.
If another interrupt is pending when RTI has finished restoring registers from
the stack, the SP is adjusted to preserve stack content, and the new vector
is fetched. This operation is functionally identical to the same operation in
the M68HC11, where registers actually are re-stacked, but is faster.
CCR Details:
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
Condition codes take on the value pulled from the stack, except that the X
mask bit cannot change from 0 to 1. Software can leave the X bit set, leave
it cleared, or change it from 1 to 0, but it can be set only by a reset or by
recognition of an XIRQ interrupt.
Source Form
RTI
(with interrupt pending)
Address
Mode
INH
Access Detail
Object Code
HCS12
0B
uUUUUPPP
uUUUUfVfPPP
M68HC12
uUUUUPPP
uUUUUVfPPP
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Glossary
RTS
Operation:
Description:
CCR Details:
Source Form
RTS
RTS
Return from Subroutine
(M(SP) : M(SP+1)) ⇒ PCH : PCL; (SP) + $0002 ⇒ SP
Restores context at the end of a subroutine. Loads the program counter with
a 16-bit value pulled from the stack and increments the stack pointer by two.
Program execution continues at the address restored from the stack.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
3D
HCS12
M68HC12
UfPPP
UfPPP
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Instruction Glossary
SBA
Operation:
Description:
CCR Details:
Subtract Accumulators
SBA
(A) – (B) ⇒ A
Subtracts the content of accumulator B from the content of accumulator A
and places the result in A. The content of B is not affected. For subtraction
instructions, the C status bit represents a borrow.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • B7 • R7 + A7 • B7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • B7 + B7 • R7 + R7 • A7
Set if the absolute value of B is larger than the absolute value of A;
cleared otherwise
Source Form
SBA
Address
Mode
INH
Access Detail
Object Code
HCS12
18 16
OO
M68HC12
OO
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Glossary
SBCA
Operation:
Description:
CCR Details:
Subtract with Carry from A
SBCA
(A) – (M) – C ⇒ A
Subtracts the content of memory location M and the value of the C status bit
from the content of accumulator A. The result is placed in A. For subtraction
instructions, the C status bit represents a borrow.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if the absolute value of the content of memory plus previous
carry is larger than the absolute value of the accumulator; cleared
otherwise
Source Form
SBCA #opr8i
SBCA opr8a
SBCA opr16a
SBCA oprx0_xysp
SBCA oprx9,xysp
SBCA oprx16,xysp
SBCA [D,xysp]
SBCA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
82
92
B2
A2
A2
A2
A2
A2
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Instruction Glossary
SBCB
Operation:
Description:
CCR Details:
Subtract with Carry from B
SBCB
(B) – (M) – C ⇒ B
Subtracts the content of memory location M and the value of the C status bit
from the content of accumulator B. The result is placed in B. For subtraction
instructions, the C status bit represents a borrow.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: B7 • M7 • R7 + B7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: B7 • M7 + M7 • R7 + R7 • B7
Set if the absolute value of the content of memory plus previous
carry is larger than the absolute value of the accumulator; cleared
otherwise
Source Form
SBCB #opr8i
SBCB opr8a
SBCB opr16a
SBCB oprx0_xysp
SBCB oprx9,xysp
SBCB oprx16,xysp
SBCB [D,xysp]
SBCB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C2
D2
F2
E2
E2
E2
E2
E2
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Glossary
SEC
Operation:
Description:
SEC
Set Carry
1 ⇒ C bit
Sets the C status bit. This instruction is assembled as ORCC #$01. The
ORCC instruction can be used to set any combination of bits in the CCR in
one operation.
SEC can be used to set up the C bit prior to a shift or rotate instruction
involving the C bit.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
1
C: 1; set
Source Form
SEC
translates to... ORCC #$01
Address
Mode
IMM
Access Detail
Object Code
HCS12
14 01
P
M68HC12
P
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Instruction Glossary
SEI
Operation:
Description:
CCR Details:
SEI
Set Interrupt Mask
1 ⇒ I bit
Sets the I mask bit. This instruction is assembled as ORCC #$10. The
ORCC instruction can be used to set any combination of bits in the CCR in
one operation. When the I bit is set, all maskable interrupts are inhibited,
and the CPU will recognize only non-maskable interrupt sources or an SWI.
S
X
H
I
N
Z
V
C
–
–
–
1
–
–
–
–
I:
Source Form
SEI
translates to... ORCC #$10
1; set
Address
Mode
IMM
Access Detail
Object Code
HCS12
14 10
P
M68HC12
P
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Glossary
SEV
Operation:
Description:
CCR Details:
Set Two’s Complement Overflow Bit
SEV
1 ⇒ V bit
Sets the V status bit. This instruction is assembled as ORCC #$02. The
ORCC instruction can be used to set any combination of bits in the CCR in
one operation.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
1
–
V: 1; set
Source Form
SEV
translates to... ORCC #$02
Address
Mode
IMM
Access Detail
Object Code
HCS12
14 02
P
M68HC12
P
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Instruction Glossary
SEX
Operation:
Description:
CCR Details:
SEX
Sign Extend into 16-Bit Register
If r1 bit 7 = 0, then $00 : (r1) ⇒ r2
If r1 bit 7 = 1, then $FF : (r1) ⇒ r2
This instruction is an alternate mnemonic for the TFR r1,r2 instruction,
where r1 is an 8-bit register and r2 is a 16-bit register. The result in r2 is the
16-bit sign extended representation of the original two’s complement
number in r1. The content of r1 is unchanged in all cases except that of SEX
A,D (D is A : B).
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
SEX abc,dxys
Access Detail
Object Code(1)
HCS12
INH
B7 eb
M68HC12
P
P
1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent
the low-order destination digit (MSB is a don’t care). Values are in hexadecimal.
0
1
2
3
sex:A ⇒ TMP2
sex:B ⇒ TMP2
sex:CCR ⇒ TMP2
4
sex:A ⇒ D
SEX A,D
sex:B ⇒ D
SEX B,D
sex:CCR ⇒ D
SEX CCR,D
5
sex:A ⇒ X
SEX A,X
sex:B ⇒ X
SEX B,X
sex:CCR ⇒ X
SEX CCR,X
6
sex:A ⇒ Y
SEX A,Y
sex:B ⇒ Y
SEX B,Y
sex:CCR ⇒ Y
SEX CCR,Y
7
sex:A ⇒ SP
SEX A,SP
sex:B ⇒ SP
SEX B,SP
sex:CCR ⇒ SP
SEX CCR,SP
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Glossary
STAA
Operation:
Description:
CCR Details:
STAA
Store Accumulator A
(A) ⇒ M
Stores the content of accumulator A in memory location M. The content of
A is unchanged.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
STAA opr8a
STAA opr16a
STAA oprx0_xysp
STAA oprx9,xysp
STAA oprx16,xysp
STAA [D,xysp]
STAA [oprx16,xysp]
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
5A
7A
6A
6A
6A
6A
6A
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
M68HC12
Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw
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Instruction Glossary
STAB
Operation:
Description:
CCR Details:
STAB
Store Accumulator B
(B) ⇒ M
Stores the content of accumulator B in memory location M. The content of
B is unchanged.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
STAB opr8a
STAB opr16a
STAB oprx0_xysp
STAB oprx9,xysp
STAB oprx16,xysp
STAB [D,xysp]
STAB [oprx16,xysp]
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
5B
7B
6B
6B
6B
6B
6B
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
M68HC12
Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw
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Glossary
STD
Operation:
Description:
CCR Details:
STD
Store Double Accumulator
(A : B) ⇒ M : M + 1
Stores the content of double accumulator D in memory location
M : M + 1. The content of D is unchanged.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
STD opr8a
STD opr16a
STD oprx0_xysp
STD oprx9,xysp
STD oprx16,xysp
STD [D,xysp]
STD [oprx16,xysp]
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
5C
7C
6C
6C
6C
6C
6C
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
M68HC12
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
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Instruction Glossary
STOP
Operation:
Description:
STOP
Stop Processing
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP+1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
Stop All Clocks
When the S control bit is set, STOP is disabled and operates like a 2-cycle
NOP instruction. When the S bit is cleared, STOP stacks CPU context,
stops all system clocks, and puts the device in standby mode.
Standby operation minimizes system power consumption. The contents of
registers and the states of I/O pins remain unchanged.
Asserting the RESET, XIRQ, or IRQ signals ends standby mode. Stacking
on entry to STOP allows the CPU to recover quickly when an interrupt is
used, provided a stable clock is applied to the device. If the system uses a
clock reference crystal that also stops during low-power mode, crystal
startup delay lengthens recovery time.
If XIRQ is asserted while the X mask bit = 0 (XIRQ interrupts enabled),
execution resumes with a vector fetch for the XIRQ interrupt. If the X mask
bit = 1 (XIRQ interrupts disabled), a 2-cycle recovery sequence including an
O cycle is used to adjust the instruction queue and the stack-pointer, and
execution continues with the next instruction after STOP.
CCR Details:
Source Form
STOP (entering STOP)
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
18 3E
HCS12
M68HC12
OOSSSSsf
OOSSSfSs
(exiting STOP)
fVfPPP
(continue)
ff
fO
(if STOP disabled)
OO
OO
fVfPPP
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Glossary
STS
Operation:
Description:
CCR Details:
STS
Store Stack Pointer
(SPH : SPL) ⇒ M : M + 1
Stores the content of the stack pointer in memory. The most significant byte
of the SP is stored at the specified address, and the least significant byte of
the SP is stored at the next higher byte address (the specified address plus
one).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
STS opr8a
STS opr16a
STS oprx0_xysp
STS oprx9,xysp
STS oprx16,xysp
STS [D,xysp]
STS [oprx16,xysp]
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
5F
7F
6F
6F
6F
6F
6F
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
M68HC12
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
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Instruction Glossary
STX
Operation:
Description:
CCR Details:
STX
Store Index Register X
(XH : XL) ⇒ M : M + 1
Stores the content of index register X in memory. The most significant byte
of X is stored at the specified address, and the least significant byte of X is
stored at the next higher byte address (the specified address plus one).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
STX opr8a
STX opr16a
STX oprx0_xysp
STX oprx9,xysp
STX oprx16,xysp
STX [D,xysp]
STX [oprx16,xysp]
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
5E
7E
6E
6E
6E
6E
6E
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
M68HC12
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
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Glossary
STY
Operation:
Description:
CCR Details:
STY
Store Index Register Y
(YH : YL) ⇒ M : M + 1
Stores the content of index register Y in memory. The most significant byte
of Y is stored at the specified address, and the least significant byte of Y is
stored at the next higher byte address (the specified address plus one).
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: 0; cleared
Source Form
STY opr8a
STY opr16a
STY oprx0_xysp
STY oprx9,xysp
STY oprx16,xysp
STY [D,xysp]
STY [oprx16,xysp]
Address
Mode
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
5D
7D
6D
6D
6D
6D
6D
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
M68HC12
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
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Instruction Glossary
SUBA
Operation:
Description:
CCR Details:
SUBA
Subtract A
(A) – (M) ⇒ A
Subtracts the content of memory location M from the content of accumulator
A, and places the result in A. For subtraction instructions, the C status bit
represents a borrow.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: A7 • M7 • R7 + A7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: A7 • M7 + M7 • R7 + R7 • A7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Source Form
SUBA #opr8i
SUBA opr8a
SUBA opr16a
SUBA oprx0_xysp
SUBA oprx9,xysp
SUBA oprx16,xysp
SUBA [D,xysp]
SUBA [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
80
90
B0
A0
A0
A0
A0
A0
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Glossary
SUBB
Operation:
Description:
CCR Details:
SUBB
Subtract B
(B) – (M) ⇒ B
Subtracts the content of memory location M from the content of accumulator
B and places the result in B. For subtraction instructions, the C status bit
represents a borrow.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: B7 • M7 • R7 + B7 • M7 • R7
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: B7 • M7 + M7 • R7 + R7 • B7
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Source Form
SUBB #opr8i
SUBB opr8a
SUBB opr16a
SUBB oprx0_xysp
SUBB oprx9,xysp
SUBB oprx16,xysp
SUBB [D,xysp]
SUBB [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
C0
D0
F0
E0
E0
E0
E0
E0
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Instruction Glossary
SUBD
Operation:
Description:
CCR Details:
Subtract Double Accumulator
SUBD
(A : B) – (M : M + 1) ⇒ A : B
Subtracts the content of memory location M : M + 1 from the content of
double accumulator D and places the result in D. For subtraction
instructions, the C status bit represents a borrow.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
∆
∆
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $0000; cleared otherwise
V: D15 • M15 • R15 + D15 • M15 • R15
Set if a two’s complement overflow resulted from the operation;
cleared otherwise
C: D15 • M15 + M15 • R15 + R15 • D15
Set if the value of the content of memory is larger than the value of
the accumulator; cleared otherwise
Source Form
SUBD #opr16i
SUBD opr8a
SUBD opr16a
SUBD oprx0_xysp
SUBD oprx9,xyssp
SUBD oprx16,xysp
SUBD [D,xysp]
SUBD [oprx16,xysp]
Address
Mode
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
83
93
B3
A3
A3
A3
A3
A3
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
M68HC12
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
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Glossary
SWI
Operation:
Description:
CCR Details:
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP+1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
1⇒I
(SWI Vector) ⇒ PC
Causes an interrupt without an external interrupt service request. Uses the
address of the next instruction after SWI as a return address. Stacks the
return address, index registers Y and X, accumulators B and A, and the
CCR, decrementing the SP before each item is stacked. The I mask bit is
then set, the PC is loaded with the SWI vector, and instruction execution
resumes at that location. SWI is not affected by the I mask bit. Refer to
Section 7. Exception Processing for more information.
S
X
H
I
N
Z
V
C
–
–
–
1
–
–
–
–
I:
Source Form
SWI
SWI
Software Interrupt
1; set
Address
Mode
INH
Access Detail
Object Code
HCS12
3F
VSPSSPSsP(1)
M68HC12
VSPSSPSsP(1)
1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A variation
of the sequence (VfPPP) is used for resets.
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Instruction Glossary
TAB
Operation:
Description:
CCR Details:
TAB
Transfer from Accumulator A
to Accumulator B
(A) ⇒ B
Moves the content of accumulator A to accumulator B. The former content
of B is lost; the content of A is not affected. Unlike the general transfer
instruction TFR A,B which does not affect condition codes, the TAB
instruction affects the N, Z, and V status bits for compatibility with
M68HC11.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
TAB
Address
Mode
INH
Access Detail
Object Code
HCS12
18 0E
OO
M68HC12
OO
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Glossary
TAP
Operation:
Description:
TAP
Transfer from Accumulator A
to Condition Code Register
(A) ⇒ CCR
Transfers the logic states of bits [7:0] of accumulator A to the corresponding
bit positions of the CCR. The content of A remains unchanged. The X mask
bit can be cleared as a result of a TAP, but cannot be set if it was cleared
prior to execution of the TAP. If the I bit is cleared, there is a 1-cycle delay
before the system allows interrupt requests. This prevents interrupts from
occurring between instructions in the sequences CLI, WAI and CLI, STOP.
This instruction is accomplished with the TFR A,CCR instruction. For
compatibility with the M68HC11, the mnemonic TAP is translated by the
assembler.
CCR Details:
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
Condition codes take on the value of the corresponding bit of accumulator
A, except that the X mask bit cannot change from 0 to 1. Software can leave
the X bit set, leave it cleared, or change it from 1 to 0, but it can only be set
by a reset or by recognition of an XIRQ interrupt.
Source Form
TAP translates to...
TFR A,CCR
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 02
P
M68HC12
P
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Instruction Glossary
TBA
Operation:
Description:
CCR Details:
TBA
Transfer from Accumulator B
to Accumulator A
(B) ⇒ A
Moves the content of accumulator B to accumulator A. The former content
of A is lost; the content of B is not affected. Unlike the general transfer
instruction TFR B,A, which does not affect condition codes, the TBA
instruction affects N, Z, and V for compatibility with M68HC11.
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
–
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
V: 0; cleared
Source Form
TBA
Address
Mode
INH
Access Detail
Object Code
HCS12
18 0F
OO
M68HC12
OO
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Glossary
TBEQ
Operation:
Description:
TBEQ
Test and Branch if Equal to Zero
If (Counter) = 0, then (PC) + $0003 + Rel ⇒ PC
Tests the specified counter register A, B, D, X, Y, or SP. If the counter
register is zero, branches to the specified relative destination. TBEQ is
encoded into three bytes of machine code including a 9-bit relative offset
(–256 to +255 locations from the start of the next instruction).
DBEQ and IBEQ instructions are similar to TBEQ, except that the counter is
decremented or incremented rather than simply being tested. Bits 7 and 6
of the instruction postbyte are used to determine which operation is to be
performed.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
TBEQ abdxys,rel9
REL
Access Detail
Object Code(1)
HCS12
04 lb rr
M68HC12
PPP/PPO
PPP
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (TBEQ – 0)
or not zero (TBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 0:1 for TBEQ.
Count
Bits 2:0
Register
Source Form
Object Code
(If Offset is Positive)
Object Code
(If Offset is Negative)
A
B
000
001
TBEQ A, rel9
TBEQ B, rel9
04 40 rr
04 41 rr
04 50 rr
04 51 rr
D
X
Y
SP
100
101
110
111
TBEQ D, rel9
TBEQ X, rel9
TBEQ Y, rel9
TBEQ SP, rel9
04
04
04
04
04
04
04
04
44
45
46
47
rr
rr
rr
rr
54
55
56
57
rr
rr
rr
rr
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Instruction Glossary
TBL
Operation:
Description:
TBL
Table Lookup and Interpolate
(M) + [(B) × ((M+1) – (M))] ⇒ A
Linearly interpolates one of 256 result values that fall between each pair of
data entries in a lookup table stored in memory. Data entries in the table
represent the Y values of endpoints of equally spaced line segments. Table
entries and the interpolated result are 8-bit values. The result is stored in
accumulator A.
Before executing TBL, an index register points to the table entry
corresponding to the X value (X1) that is closest to, but less than or equal
to, the desired lookup point (XL, YL). This defines the left end of a line
segment and the right end is defined by the next data entry in the table. Prior
to execution, accumulator B holds a binary fraction (radix point to left of
MSB), representing the ratio (XL–X1) ÷ (X2–X1).
The 8-bit unrounded result is calculated using the following expression:
A = Y1 + [(B) × (Y2 – Y1)]
Where
(B) = (XL – X1) ÷ (X2 – X1)
Y1 = 8-bit data entry pointed to by <effective address>
Y2 = 8-bit data entry pointed to by <effective address> + 1
The intermediate value [(B) × (Y2 – Y1)] produces a 16-bit result with the
radix point between bits 7 and 8. Any indexed addressing mode referenced
to X, Y, SP, or PC, except indirect modes or 9-bit and 16-bit offset modes,
can be used to identify the first data point (X1,Y1). The second data point is
the next table entry.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
–
∆(1)
1. C-bit was undefined in original M68HC12.
N: Set if MSB of result is set; cleared otherwise
Z: Set if result is $00; cleared otherwise
C: Set if result can be rounded up; cleared otherwise
Source Form
TBL oprx0_xysp
Address
Mode
IDX
Access Detail
Object Code
18 3D xb
HCS12
M68HC12
ORfffP
OrrffffP
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Glossary
TBNE
Operation:
Description:
TBNE
Test and Branch if Not Equal to Zero
If (Counter) ≠ 0, then (PC) + $0003 + Rel ⇒ PC
Tests the specified counter register A, B, D, X, Y, or SP. If the counter
register is not zero, branches to the specified relative destination. TBNE is
encoded into three bytes of machine code including a 9-bit relative offset
(–256 to +255 locations from the start of the next instruction).
DBNE and IBNE instructions are similar to TBNE, except that the counter is
decremented or incremented rather than simply being tested. Bits 7 and 6
of the instruction postbyte are used to determine which operation is to be
performed.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
TBNE abdxys,rel9
REL
Access Detail
Object Code(1)
HCS12
04 lb rr
M68HC12
PPP/PPO
PPP
1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (TBEQ –
0) or not zero (TBNE – 1) versions, and bit 4 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 0:1 for TBNE.
Count
Bits 2:0
Register
Source Form
Object Code
(If Offset is Positive)
Object Code
(If Offset is Negative)
A
B
000
001
TBNE A, rel9
TBNE B, rel9
04 60 rr
04 61 rr
04 70 rr
04 71 rr
D
X
Y
SP
100
101
110
111
TBNE D, rel9
TBNE X, rel9
TBNE Y, rel9
TBNE SP, rel9
04
04
04
04
04
04
04
04
64
65
66
67
rr
rr
rr
rr
74
75
76
77
rr
rr
rr
rr
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Instruction Glossary
TFR
TFR
Transfer Register Content
to Another Register
Operation:
See table.
Description:
Transfers the content of a source register to a destination register specified
in the instruction. The order in which transfers between 8-bit and 16-bit
registers are specified affects the high byte of the 16-bit registers differently.
Cases involving TMP2 and TMP3 are reserved for Freescale use, so some
assemblers may not permit their use. It is possible to generate these cases
by using DC.B or DC.W assembler directives.
S
CCR Details:
X
H
I
N
Z
V
C
Or:
–
–
–
–
–
–
–
–
S
X
H
I
N
Z
V
C
∆
⇓
∆
∆
∆
∆
∆
∆
None affected, unless the CCR is the destination register. Condition codes
take on the value of the corresponding source bits, except that the X mask
bit cannot change from 0 to 1. Software can leave the X bit set, leave it
cleared, or change it from 1 to 0, but it can be set only by a reset or by
recognition of an XIRQ interrupt.
Address
Mode
Source Form
TFR abcdxys,abcdxys
Access Detail
Object Code(1)
HCS12
INH
B7 eb
M68HC12
P
P
1. Legal coding for eb is summarized in the following table. Columns represent the high-order source digit. Rows represent
the low-order destination digit (MSB is a don’t-care). Values are in hexadecimal.
0
1
2
3
4
5
6
7
0
A⇒A
B⇒A
CCR ⇒ A
TMP3L ⇒ A
B⇒A
XL ⇒ A
YL ⇒ A
SPL ⇒ A
1
A⇒B
B⇒B
CCR ⇒ B
TMP3L ⇒ B
B⇒B
XL ⇒ B
YL ⇒ B
SPL ⇒ B
2
A ⇒ CCR
B ⇒ CCR
CCR ⇒ CCR
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
3
sex:A ⇒ TMP2
sex:B ⇒ TMP2
sex:CCR ⇒ TMP2
TMP3 ⇒ TMP2
D ⇒ TMP2
X ⇒ TMP2
Y ⇒ TMP2
SP ⇒ TMP2
sex:A ⇒ D
SEX A,D
sex:A ⇒ X
SEX A,X
sex:A ⇒ Y
SEX A,Y
sex:A ⇒ SP
SEX A,SP
sex:B ⇒ D
SEX B,D
sex:B ⇒ X
SEX B,X
sex:B ⇒ Y
SEX B,Y
sex:B ⇒ SP
SEX B,SP
sex:CCR ⇒ D
SEX CCR,D
sex:CCR ⇒ X
SEX CCR,X
sex:CCR ⇒ Y
SEX CCR,Y
sex:CCR ⇒ SP
SEX CCR,SP
TMP3 ⇒ D
D⇒D
X⇒D
Y⇒D
SP ⇒ D
TMP3 ⇒ X
D⇒X
X⇒X
Y⇒X
SP ⇒ X
TMP3 ⇒ Y
D⇒Y
X⇒Y
Y⇒Y
SP ⇒ Y
TMP3 ⇒ SP
D ⇒ SP
X ⇒ SP
Y ⇒ SP
SP ⇒ SP
4
5
6
7
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Glossary
TPA
Operation:
Description:
Transfer from Condition Code
Register to Accumulator A
TPA
(CCR) ⇒ A
Transfers the content of the condition code register to corresponding bit
positions of accumulator A. The CCR remains unchanged.
This mnemonic is implemented by the TFR CCR,A instruction. For
compatibility with the M68HC11, the mnemonic TPA is translated into the
TFR CCR,A instruction by the assembler.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
TPA
translates to... TFR CCR,A
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 20
P
M68HC12
P
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Instruction Glossary
TRAP
Operation:
Description:
TRAP
Unimplemented Opcode Trap
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP+1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
1⇒I
(Trap Vector) ⇒ PC
Traps unimplemented opcodes. There are opcodes in all 256 positions in
the page 1 opcode map, but only 54 of the 256 positions on page 2 of the
opcode map are used. If the CPU attempts to execute one of the
unimplemented opcodes on page 2, an opcode trap interrupt occurs.
Unimplemented opcode traps are essentially interrupts that share the
$FFF8:$FFF9 interrupt vector.
TRAP uses the next address after the unimplemented opcode as a return
address. It stacks the return address, index registers Y and X, accumulators
B and A, and the CCR, automatically decrementing the SP before each item
is stacked. The I mask bit is then set, the PC is loaded with the trap vector,
and instruction execution resumes at that location. This instruction is not
maskable by the I bit. Refer to Section 7. Exception Processing for more
information.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
1
–
–
–
–
I:
Source Form
TRAP trapnum
1; set
Access Detail
Address
Mode
Object Code
INH
tn(1)
HCS12
$18
OVSPSSPSsP
M68HC12
OfVSPSSPSsP
1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF.
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Glossary
TST
Operation:
Description:
TST
Test Memory
(M) – $00
Subtracts $00 from the content of memory location M and sets the condition
codes accordingly.
The subtraction is accomplished internally without modifying M.
The TST instruction provides limited information when testing unsigned
values. Since no unsigned value is less than zero, BLO and BLS have no
utility following TST. While BHI can be used after TST, it performs the same
function as BNE, which is preferred. After testing signed values, all signed
branches are available.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
0
N:
Z:
V:
C:
Source Form
TST opr16a
TST oprx0_xysp
TST oprx9,xysp
TST oprx16,xysp
TST [D,xysp]
TST [oprx16,xysp]
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
0; cleared
0; cleared
Address
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Access Detail
Object Code
HCS12
F7
E7
E7
E7
E7
E7
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
M68HC12
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
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Instruction Glossary
TSTA
Operation:
Description:
TSTA
Test A
(A) – $00
Subtracts $00 from the content of accumulator A and sets the condition
codes accordingly.
The subtraction is accomplished internally without modifying A.
The TSTA instruction provides limited information when testing unsigned
values. Since no unsigned value is less than zero, BLO and BLS have no
utility following TSTA. While BHI can be used after TST, it performs the
same function as BNE, which is preferred. After testing signed values, all
signed branches are available.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
0
N:
Z:
V:
C:
Source Form
TSTA
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
0; cleared
0; cleared
Address
Mode
INH
Access Detail
Object Code
HCS12
97
O
M68HC12
O
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Glossary
TSTB
Operation:
Description:
TSTB
Test B
(B) – $00
Subtracts $00 from the content of accumulator B and sets the condition
codes accordingly.
The subtraction is accomplished internally without modifying B.
The TSTB instruction provides limited information when testing unsigned
values. Since no unsigned value is less than zero, BLO and BLS have no
utility following TSTB. While BHI can be used after TST, it performs the
same function as BNE, which is preferred. After testing signed values, all
signed branches are available.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
∆
∆
0
0
N:
Z:
V:
C:
Source Form
TSTB
Set if MSB of result is set; cleared otherwise
Set if result is $00; cleared otherwise
0; cleared
0; cleared
Address
Mode
INH
Access Detail
Object Code
HCS12
D7
O
M68HC12
O
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Instruction Glossary
TSX
Operation:
Description:
CCR Details:
TSX
Transfer from Stack Pointer
to Index Register X
(SP) ⇒ X
This is an alternate mnemonic to transfer the stack pointer value to index
register X. The content of the SP remains unchanged. After a TSX
instruction, X points at the last value that was stored on the stack.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
TSX
translates to... TFR SP,X
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 75
P
M68HC12
P
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Glossary
TSY
Operation:
Description:
CCR Details:
TSY
Transfer from Stack Pointer
to Index Register Y
(SP) ⇒ Y
This is an alternate mnemonic to transfer the stack pointer value to index
register Y. The content of the SP remains unchanged. After a TSY
instruction, Y points at the last value that was stored on the stack.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
TSY
translates to... TFR SP,Y
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 76
P
M68HC12
P
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Instruction Glossary
TXS
Operation:
Description:
CCR Details:
TXS
Transfer from Index Register X
to Stack Pointer
(X) ⇒ SP
This is an alternate mnemonic to transfer index register X value to the stack
pointer. The content of X is unchanged.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
TXS
translates to... TFR X,SP
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 57
P
M68HC12
P
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Glossary
TYS
Operation:
Description:
CCR Details:
TYS
Transfer from Index Register Y
to Stack Pointer
(Y) ⇒ SP
This is an alternate mnemonic to transfer index register Y value to the stack
pointer. The content of Y is unchanged.
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Source Form
TYS
translates to... TFR Y,SP
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 67
P
M68HC12
P
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Instruction Glossary
WAI
Operation:
Description:
WAI
Wait for Interrupt
(SP) – $0002 ⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))
(SP) – $0002 ⇒ SP; B : A⇒ (M(SP) : M(SP+1))
(SP) – $0001 ⇒ SP; CCR ⇒ (M(SP))
Stop CPU Clocks
Puts the CPU into a wait state. Uses the address of the instruction following
WAI as a return address. Stacks the return address, index registers Y and
X, accumulators B and A, and the CCR, decrementing the SP before each
item is stacked.
The CPU then enters a wait state for an integer number of bus clock cycles.
During the wait state, CPU clocks are stopped, but other MCU clocks can
continue to run. The CPU leaves the wait state when it senses an interrupt
that has not been masked.
Upon leaving the wait state, the CPU sets the appropriate interrupt mask
bit(s), fetches the vector corresponding to the interrupt sensed, and
instruction execution continues at the location the vector points to.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
Source Form
WAI (before interrupt)
WAI (when interrupt comes)
INH
Access Detail
Object Code
HCS12
M68HC12
OSSSSsf
OSSSfSsf
3E
fVfPPP
VfPPP
Although the WAI instruction itself does not alter the condition codes, the
interrupt that causes the CPU to resume processing also causes the I mask
bit (and the X mask bit, if the interrupt was XIRQ) to be set as the interrupt
vector is fetched.
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Glossary
WAV
Operation:
WAV
Weighted Average
Do until B = 0, leave SOP in Y : D, SOW in X
Partial Product = (M pointed to by X) × (M pointed to by Y)
Sum-of-Products (24-bit SOP) = Previous SOP + Partial Product
Sum-of-Weights (16-bit SOW) = Previous SOW + (M pointed to by Y)
(X) + $0001 ⇒ X; (Y) + $0001 ⇒ Y
(B) – $01 ⇒ B
Description:
Performs weighted average calculations on values stored in memory. Uses
indexed (X) addressing mode to reference one source operand list, and
indexed (Y) addressing mode to reference a second source operand list.
Accumulator B is used as a counter to control the number of elements to be
included in the weighted average.
For each pair of data points, a 24-bit sum of products (SOP) and a 16-bit
sum of weights (SOW) is accumulated in temporary registers. When B
reaches zero (no more data pairs), the SOP is placed in Y : D. The SOW is
placed in X. To arrive at the final weighted average, divide the content of Y
: D by X by executing an EDIV after the WAV.
This instruction can be interrupted. If an interrupt occurs during WAV
execution, the intermediate results (six bytes) are stacked in the order
SOW[15:0], SOP[15:0], $00:SOP[23:16] before the interrupt is processed. The
wavr pseudo-instruction is used to resume execution after an interrupt. The
mechanism is re-entrant. New WAV instructions can be started and
interrupted while a previous WAV instruction is interrupted.
This instruction is often used in fuzzy logic rule evaluation. Refer to Section
9. Fuzzy Logic Support for more information.
CCR Details:
S
X
H
I
N
Z
V
C
–
–
?
–
?
1
?
?
Z: 1; set
H, N, V and C may be altered by this instruction
Source Form
WAV
Address
Mode
Object Code
Special
18 3C
Access Detail(1)
HCS12
M68HC12
Of(frr,ffff)O
Off(frr,fffff)O
(replace comma if interrupted)
SSS + UUUrr
SSSf + UUUrr
1. The replace comma sequence in parentheses represents the loop for one iteration of SOP and SOW accumulation.
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Instruction Glossary
XGDX
Operation:
Description:
Exchange Double Accumulator
and Index Register X
XGDX
(D) ⇔ (X)
Exchanges the content of double accumulator D and the content of index
register X. For compatibility with the M68HC11, the XGDX instruction is
translated into an EXG D,X instruction by the assembler.
CCR Details:
Source Form
XGDX
translates to... EXG D,X
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 C5
P
M68HC12
P
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Glossary
XGDY
Operation:
Description:
Exchange Double Accumulator
and Index Register Y
XGDY
(D) ⇔ (Y)
Exchanges the content of double accumulator D and the content of index
register Y. For compatibility with the M68HC11, the XGDY instruction is
translated into an EXG D,Y instruction by the assembler.
CCR Details:
Source Form
XGDY
translates to... EXG D,Y
S
X
H
I
N
Z
V
C
–
–
–
–
–
–
–
–
Address
Mode
INH
Access Detail
Object Code
HCS12
B7 C6
P
M68HC12
P
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Instruction Glossary
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Reference Manual — S12CPUV2
Section 7. Exception Processing
7.1 Introduction
Exceptions are events that require processing outside the normal flow of
instruction execution. This section describes exceptions and the way each
is handled.
7.2 Types of Exceptions
Central processor unit (CPU12) exceptions include:
•
Resets
– Power-on reset and RESET pin
– Clock monitor reset
– COP watchdog reset
•
An unimplemented opcode trap
•
A software interrupt instruction (SWI)
•
Non-maskable (X-bit) interrupts
•
Maskable (I-bit) interrupts
Each exception has an associated 16-bit vector, which points to the memory
location where the routine that handles the exception is located. As shown
in Table 7-1, vectors are stored in the upper bytes of the standard 64-Kbyte
address map.
The six highest vector addresses are used for resets and unmaskable
interrupt sources. The remaining vectors are used for maskable interrupts.
All vectors must be programmed to point to the address of the appropriate
service routine.
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Table 7-1. CPU12 Exception Vector Map(1)
Vector Address
Source
$FFFE–$FFFF
System reset
$FFFC–$FFFD
Clock monitor reset
$FFFA–$FFFB
COP reset
$FFF8–$FFF9
Unimplemented opcode trap
$FFF6–$FFF7
Software interrupt instruction (SWI)
$FFF4–$FFF5
XIRQ signal
$FFF2–$FFF3
IRQ signal
$FF00–$FFF1
Device-specific interrupt sources (HCS12)
$FFC0–$FFF1
Device-specific interrupt sources (M68HC12)
1. See Device User Guide and Interrupt Block Guide for further details
The CPU12 can handle up to 128 exception vectors, but the number actually
used varies from device to device, and some vectors are reserved for
Freescale use. Refer to Device User Guide for more information.
Exceptions can be classified by the effect of the X and I interrupt mask bits
on recognition of a pending request.
•
Resets, the unimplemented opcode trap, and the SWI instruction are
not affected by the X and I mask bits.
•
Interrupt service requests from the XIRQ pin are inhibited when X =
1, but are not affected by the I bit.
•
All other interrupts are inhibited when I = 1.
7.3 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is serviced
first when simultaneous requests are made. Six sources are not maskable.
The remaining sources are maskable, and the device integration module
typically can change the relative priorities of maskable interrupts. Refer to
7.5 Interrupts for more detail concerning interrupt priority and servicing.
The priorities of the unmaskable sources are:
1.
2.
3.
4.
5.
6.
RESET pin or power-on reset (POR)
Clock monitor reset
Computer operating properly (COP) watchdog reset
Non-maskable interrupt request (XIRQ) signal
Unimplemented opcode trap
Software interrupt instruction (SWI)
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External reset and POR share the highest exception-processing priority,
followed by clock monitor reset, and then the on-chip watchdog reset.
The XIRQ interrupt is pseudo-non-maskable. After reset, the X bit in the
CCR is set, which inhibits all interrupt service requests from the XIRQ pin
until the X bit is cleared. The X bit can be cleared by a program instruction,
but program instructions cannot change X from 0 to 1. Once the X bit is
cleared, interrupt service requests made via the XIRQ pin become
non-maskable.
The unimplemented page 2 opcode trap (TRAP) and the SWI are special
cases. In one sense, these two exceptions have very low priority, because
any enabled interrupt source that is pending prior to the time exception
processing begins will take precedence. However, once the CPU begins
processing a TRAP or SWI, neither can be interrupted. Also, since these are
mutually exclusive instructions, they have no relative priority.
All remaining interrupts are subject to masking via the I bit in the CCR. Most
HCS12 microcontroller units (MCU) have an external IRQ pin, which is
assigned the highest I-bit interrupt priority and an internal periodic real-time
interrupt generator, which has the next highest priority. The other maskable
sources have default priorities that follow the address order of the interrupt
vectors — the higher the address, the higher the priority of the interrupt.
Other maskable interrupts are associated with on-chip peripherals such as
timers or serial ports. On the HCS12, logic in the device integration module
can give one I-masked source priority over other I-masked sources. Refer
to the documentation for the specific HCS12 derivative for more information.
7.4 Resets
M68HC12 devices perform resets with a combination of hardware and
software. Integration module circuitry determines the type of reset that has
occurred, performs basic system configuration, then passes control to the
CPU12. The CPU fetches a vector determined by the type of reset that has
occurred, jumps to the address pointed to by the vector, and begins to
execute code at that address.
The are four possible sources of reset are:
• Power-on reset (POR)
• External reset (RESET pin)
•
•
COP reset
Clock monitor reset
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Power-on reset (POR) and external reset share the same reset vector. The
computer operating properly (COP) reset and the clock monitor reset each
have a vector.
7.4.1 Power-On Reset
The HCS12 incorporate circuitry to detect a positive transition in the VDD
supply and initialize the device during cold starts, generally by asserting the
reset signal internally. The signal is typically released after a delay that
allows the device clock generator to stabilize.
7.4.2 External Reset
The MCU distinguishes between internal and external resets by sensing
how quickly the signal on the RESET pin rises to logic level 1 after it has
been asserted. When the MCU senses any of the four reset conditions,
internal circuitry drives the RESET signal low for N clock cycles, then
releases. M clock cycles later, the MCU samples the state of the signal
applied to the RESET pin. If the signal is still low, an external reset has
occurred. If the signal is high, reset is assumed to have been initiated
internally by either the COP system or the clock monitor.
7.4.3 COP Reset
The MCU includes a computer operating properly (COP) system to help
protect against software failures. When the COP is enabled, software must
write a particular code sequence to a specific address to keep a watchdog
timer from timing out. If software fails to execute the sequence properly, a
reset occurs.
7.4.4 Clock Monitor Reset
The clock monitor circuit uses an internal RC circuit to determine whether
clock frequency is above a predetermined limit. If clock frequency falls
below the limit when the clock monitor is enabled, a reset occurs.
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7.5 Interrupts
Each HCS12 device can recognize a number of interrupt sources. Each
source has a vector in the vector table. The XIRQ signal, the unimplemented
opcode trap, and the SWI instruction are non-maskable, and have a fixed
priority. The remaining interrupt sources can be masked by the I bit. In most
devices, the external interrupt request pin is assigned the highest maskable
interrupt priority, and the internal periodic real-time interrupt generator has
the next highest priority. Other maskable interrupts are associated with
on-chip peripherals such as timers or serial ports. These maskable sources
have default priorities that follow the address order of the interrupt vectors.
The higher the vector address, the higher the priority of the interrupt. On The
HCS12, a device integration module incorporates logic that can give any
one maskable source priority over other maskable sources.
7.5.1 Non-Maskable Interrupt Request (XIRQ)
The XIRQ input is an updated version of the non-maskable interrupt (NMI)
input of earlier MCUs. The XIRQ function is disabled during system reset
and upon entering the interrupt service routine for an XIRQ interrupt.
During reset, both the I bit and the X bit in the CCR are set. This disables
maskable interrupts and interrupt service requests made by asserting the
XIRQ signal. After minimum system initialization, software can clear the X
bit using an instruction such as ANDCC #$BF. Software cannot set the X bit
from 0 to 1 once it has been cleared, and interrupt requests made via the
XIRQ pin become non-maskable. When a non-maskable interrupt is
recognized, both the X and I bits are set after context is saved. The X bit is
not affected by maskable interrupts. Execution of an return-from-interrupt
(RTI) instruction at the end of the interrupt service routine normally restores
the X and I bits to the pre-interrupt request state.
7.5.2 Maskable Interrupts
Maskable interrupt sources include on-chip peripheral systems and external
interrupt service requests. Interrupts from these sources are recognized
when the global interrupt mask bit (I) in the CCR is cleared. The default state
of the I bit out of reset is 1, but it can be written at any time.
The interrupt module manages maskable interrupt priorities. Typically, an
on-chip interrupt source is subject to masking by associated bits in control
registers in addition to global masking by the I bit in the CCR. Sources
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generally must be enabled by writing one or more bits in associated control
registers. There may be other interrupt-related control bits and flags, and
there may be specific register read-write sequences associated with
interrupt service. Refer to individual on-chip peripheral descriptions for
details.
7.5.3 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after the
I mask bit is cleared. When an interrupt service request is recognized, the
CPU responds at the completion of the instruction being executed. Interrupt
latency varies according to the number of cycles required to complete the
current instruction. Because the fuzzy logic rule evaluation (REV), fuzzy
logic rule evaluation weighted (REVW), and weighted average (WAV)
instructions can take many cycles to complete, they are designed so that
they can be interrupted. Instruction execution resumes when interrupt
execution is complete. When the CPU begins to service an interrupt, the
instruction queue is refilled, a return address is calculated, and then the
return address and the contents of the CPU registers are stacked as shown
in Table 7-2.
Table 7-2. Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP + 7
RTNH : RTNL
SP + 5
YH : YL
SP + 3
XH : XL
SP + 1
B:A
SP
CCR
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service
request caused the interrupt) is set to prevent other interrupts from
disrupting the interrupt service routine. Execution continues at the address
pointed to by the vector for the highest-priority interrupt that was pending at
the beginning of the interrupt sequence. At the end of the interrupt service
routine, an RTI instruction restores context from the stacked registers, and
normal program execution resumes.
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7.5.4 External Interrupts
External interrupt service requests are made by asserting an active-low
signal connected to the IRQ pin. Typically, control bits affect how the signal
is detected and recognized.
The I bit serves as the IRQ interrupt enable flag. When an IRQ interrupt is
recognized, the I bit is set to inhibit interrupts during the interrupt service
routine. Before other maskable interrupt requests can be recognized, the I
bit must be cleared. This is generally done by an RTI instruction at the end
of the service routine.
7.5.5 Return-from-Interrupt Instruction (RTI)
RTI is used to terminate interrupt service routines. RTI is an 8-cycle
instruction when no other interrupt is pending and 11 cycles (10 cycles in
M68HC12) when another interrupt is pending. In either case, the first five
cycles are used to restore (pull) the CCR, B:A, X, Y, and the return address
from the stack. If no other interrupt is pending at this point, three program
words are fetched to refill the instruction queue from the area of the return
address and processing proceeds from there.
If another interrupt is pending after registers are restored, a new vector is
fetched, and the stack pointer is adjusted to point at the CCR value that was
just recovered (SP = SP – 9). This makes it appear that the registers have
been stacked again. After the SP is adjusted, three program words are
fetched to refill the instruction queue, starting at the address the vector
points to. Processing then continues with execution of the instruction that is
now at the head of the queue.
7.6 Unimplemented Opcode Trap
The CPU12 has opcodes in all 256 positions in the page 1 opcode map, but
only 54 of the 256 positions on page 2 of the opcode map are used. If the
CPU attempts to execute one of the 202 unused opcodes on page 2, an
unimplemented opcode trap occurs. The 202 unimplemented opcodes are
essentially interrupts that share a common interrupt vector, $FFF8:$FFF9.
The CPU12 uses the next address after an unimplemented page 2 opcode
as a return address. This differs from the M68HC11 illegal opcode interrupt,
which uses the address of an illegal opcode as the return address. In the
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CPU12, the stacked return address can be used to calculate the address of
the unimplemented opcode for software-controlled traps.
7.7 Software Interrupt Instruction (SWI)
Execution of the SWI instruction causes an interrupt without an interrupt
service request. SWI is not inhibited by the global mask bits in the CCR, and
execution of SWI sets the I mask bit. Once an SWI interrupt begins,
maskable interrupts are inhibited until the I bit in the CCR is cleared. This
typically occurs when an RTI instruction at the end of the SWI service
routine restores context.
7.8 Exception Processing Flow
The first cycle in the exception processing flow for all CPU12 exceptions is
the same, regardless of the source of the exception. Between the first and
second cycles of execution, the CPU chooses one of three alternative
paths. The first path is for resets, the second path is for pending X or I
interrupts, and the third path is used for software interrupts (SWI) and
trapping unimplemented opcodes. The last two paths are virtually identical,
differing only in the details of calculating the return address. Refer to Figure
7-1 for the following discussion.
7.8.1 Vector Fetch
The first cycle of all exception processing, regardless of the cause, is a
vector fetch. The vector points to the address where exception processing
will continue. Exception vectors are stored in a table located at the top of the
memory map ($FFxx). The CPU cannot use the fetched vector until the third
cycle of the exception processing sequence.
During the vector fetch cycle, the CPU issues a signal that tells the interrupt
module to drive the vector address of the highest priority, pending exception
onto the system address bus (the CPU does not provide this address).
After the vector fetch, the CPU selects one of the three alternate execution
paths, depending upon the cause of the exception.
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START
OPCODE TRAP?
YES
NO
1.0 - V
YES
FETCH VECTOR
T.1 - f
INTERNAL CALCULATIONS
2.2 - S
PUSH RETURN ADDRESS
RESET?
NO
INTERRUPT?
NO
YES
2.0 - f
NO BUS ACCESS
2.1 - S
PUSH RETURN ADDRESS
SET S, X, AND I
ADDRESS OF INST THAT WOULD HAVE
EXECUTED IF NO INTERRUPT
ADDRESS OF INST AFTER SWI OR
UNIMPLEMENTED OPCODE
3.0 - P
3.1 - P
3.2 - P
FETCH PROGRAM WORD
FETCH PROGRAM WORD
FETCH PROGRAM WORD
START TO FILL INSTRUCTION QUEUE
START TO FILL INSTRUCTION QUEUE
START TO FILL INSTRUCTION QUEUE
4.0 - P
4.1 - S
PUSH Y
4.2 - S
PUSH Y
5.1 - S
PUSH X
5.2 - S
PUSH X
6.1 - P
FETCH PROGRAM WORD
6.2 - P
FETCH PROGRAM WORD
FETCH PROGRAM WORD
CONTINUE TO FILL INSTRUCTION
QUEUE
5.0 - P
FETCH PROGRAM WORD
FINISH FILLING INSTRUCTION QUEUE
END
CONTINUE TO FILL INST. QUEUE
TRANSFER B:A TO 16-BIT TEMP REG
CONTINUE TO FILL INST. QUEUE
TRANSFER B:A TO 16-BIT TEMP REG
7.1 - S
PUSH B:A
7.2 - S
PUSH B:A
8.1 - s
PUSH CCR (BYTE)
8.2 - s
PUSH CCR (BYTE)
SET I BIT
IF XIRQ, SET X BIT
SET I BIT
9.2 - P
9.1 - P
FETCH PROGRAM WORD
FETCH PROGRAM WORD
FINISH FILLING INSTRUCTION QUEUE
FINISH FILLING INSTRUCTION QUEUE
END
END
Figure 7-1. Exception Processing Flow Diagram
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7.8.2 Reset Exception Processing
If reset caused the exception, processing continues to cycle 2.0. This cycle
sets the S, X, and I bits in the CCR. Cycles 3.0 through 5.0 are program
word fetches that refill the instruction queue. Fetches start at the address
pointed to by the reset vector. When the fetches are completed, exception
processing ends, and the CPU starts executing the instruction at the head
of the instruction queue.
7.8.3 Interrupt and Unimplemented Opcode Trap Exception Processing
If an exception was not caused by a reset, a return address is calculated.
• Cycles 2.1and 2.2 are both S cycles (stack a 16-bit word), but the
CPU12 performs different return address calculations for each type of
exception.
– When an X- or I-related interrupt causes the exception, the return
address points to the next instruction that would have been
executed had processing not been interrupted.
– When an exception is caused by an SWI opcode or by an
unimplemented opcode (see 7.6 Unimplemented Opcode Trap),
the return address points to the next address after the opcode.
•
Once calculated, the return address is pushed onto the stack.
•
Cycles 3.1 through 9.1 are identical to cycles 3.2 through 9.2 for the
rest of the sequence, except for optional setting of the X mask bit
performed in cycle 8.1 (see below).
•
Cycle 3.1/3.2 is the first of three program word fetches that refill the
instruction queue.
•
Cycle 4.1/4.2 pushes Y onto the stack.
•
Cycle 5.1/5.2 pushes X onto the stack.
•
Cycle 6.1/6.2 is the second of three program word fetches that refill
the instruction queue. During this cycle, the contents of the A and B
accumulators are concatenated into a 16-bit word in the order B:A.
This makes register order in the stack frame the same as that of the
M68HC11, M6801, and the M6800.
•
Cycle 7.1/7.2 pushes the 16-bit word containing B:A onto the stack.
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•
Cycle 8.1/8.2 pushes the 8-bit CCR onto the stack, then updates the
mask bits.
– When an XIRQ interrupt causes an exception, both X and I are set,
which inhibits further interrupts during exception processing.
– When any other interrupt causes an exception, the I bit is set, but
the X bit is not changed.
•
Cycle 9.1/9.2 is the third of three program word fetches that refill the
instruction queue. It is the last cycle of exception processing. After this
cycle the CPU starts executing the first cycle of the instruction at the
head of the instruction queue.
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Reference Manual — S12CPUV2
Section 8.
Instruction Queue
8.1 Introduction
This section describes development and debug support features related to
the central processor unit (CPU12). Topics include:
•
Single-wire background debug interface
•
Hardware breakpoint system
•
Instruction queue operation and reconstruction
•
Instruction tagging
1 = Valid Data
TRACE — Trace Flag
Indicates when tracing is enabled. Firmware in the BDM ROM sets
TRACE in response to a TRACE1 command and TRACE is cleared upon
completion of the TRACE1 command. Do not attempt to write TRACE
directly with WRITE_BD_BYTE commands.
0 = Tracing not enabled
1 = TRACE1 command in progress
8.2 External Reconstruction of the Queue
The CPU12 uses an instruction queue to buffer program information and
increase instruction throughput. The HCS12 implements the queue
somewhat differently from the original M68HC12. The HCS12 queue
consists of three 16-bit stages while the M68HC12 queue consists of two
16-bit stages, plus a 16-bit holding latch. Program information is always
fetched in aligned 16-bit words. At least three bytes of program information
are available to the CPU when instruction execution begins. The holding
latch in the M68HC12 is used when a word of program information arrives
before the queue can advance.
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Because of the queue, program information is fetched a few cycles before it
is used by the CPU. Internally, the microcontroller unit (MCU) only needs to
buffer the fetched data. But, in order to monitor cycle-by-cycle CPU activity
externally, it is necessary to capture data and address to discern what is
happening in the instruction queue.
Two external pins, IPIPE1 and IPIPE0, provide time-multiplexed information
about data movement in the queue and instruction execution. The
instruction queue and cycle-by-cycle activity can be reconstructed in real
time or from trace history captured by a logic analyzer. However, neither
scheme can be used to stop the CPU12 at a specific instruction. By the time
an operation is visible outside the MCU, the instruction has already begun
execution. A separate instruction tagging mechanism is provided for this
purpose. A tag follows the information in the queue as the queue is
advanced. During debugging, the CPU enters active background debug
mode when a tagged instruction reaches the head of the queue, rather than
executing the tagged instruction. For more information about tagging, refer
to 8.6 Instruction Tagging.
8.3 Instruction Queue Status Signals
The IPIPE1 and IPIPE0 signals carry time-multiplexed information about
data movement and instruction execution during normal CPU operation.
The signals are available on two multifunctional device pins. During reset,
the pins are used as mode-select input signals MODA and MODB.
To reconstruct the queue, the information carried by the status signals must
be captured externally. In general, data movement and execution start
information are considered to be distinct 2-bit values, with the low-order bit
on IPIPE0 and the high-order bit on IPIPE1.
8.3.1 HCS12 Timing Detail
In the HCS12, data-movement information is available when E clock is high
or on falling edges of the E clock; execution-start information is available
when E clock is low or on rising edges of the E clock, as shown in
Figure 8-1. Data-movement information refers to data on the bus.
Execution-start information refers to the bus cycle that starts with that E-low
time and continues through the following E-high time. Table 8-1
summarizes the information encoded on the IPIPE1 and IPIPE0 pins.
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EX1 REFERS TO
THIS CYCLE
CYCLE 0
CYCLE 1
E CLOCK
ADDRESS
ADDR0
DATA
IPIPE[1:0]
ADDR1
DATA0
EX0
DM0
DATA1
EX1
DM1
DM0 REFERS TO DATA
CAPTURED AT THE END
OF CURRENT E-HIGH PERIOD
Figure 8-1. Queue Status Signal Timing (HCS12)
8.3.2 M68HC12 Timing Detail
In the M68HC12, data movement information is available on rising edges of
the E clock; execution start information is available on falling edges of the E
clock, as shown in Figure 8-2. Data movement information refers to data on
the bus at the previous falling edge of E. Execution information refers to the
bus cycle from the current falling edge to the next falling edge of E.
Table 8-1 summarizes the information encoded on the IPIPE1 and IPIPE0
pins.
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EX1 REFERS TO
THIS CYCLE
CYCLE 0
CYCLE 1
CYCLE 2
E CLOCK
ADDRESS
DATA
IPIPE[1:0]
ADDR0
ADDR1
DATA0
ADDR2
DATA1
EX1
DM0
DATA2
EX2
DM1
DM0 REFERS TO DATA
CAPTURED AT
PREVIOUS E FALL
Figure 8-2. Queue Status Signal Timing (M68HC12)
Table 8-1. IPIPE1 and IPIPE0 Decoding (HCS12 and M68HC12)
Mnemonic
Data Movement
Meaning
Capture at E Fall in HCS12 (E Rise in M68HC12)
0:0
—
No movement
0:1
LAT(1)
Latch data from bus
1:0
ALD
Advance queue and load from bus
1:1
ALL(1)
Advance queue and load from latch
Execution Start
Capture at E Rise in HCS12 (E Fall in M68HC12)
0:0
—
No start
0:1
INT
Start interrupt sequence
1:0
SEV
Start even instruction
1:1
SOD
Start odd instruction
1. The HCS12 implementation does not include a holding latch, so these data movement
codes are used only in the original M68HC12.
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8.3.3 Null (Code 0:0)
The 0:0 data movement state indicates that there was no data movement in
the instruction queue; the 0:0 execution start state indicates continuation of
an instruction or interrupt sequence (no new instruction or interrupt start).
8.3.4 LAT — Latch Data from Bus (Code 0:1)
This code is not used in the HCS12. In the M68HC12, fetched program
information has arrived, but the queue is not ready to advance. The
information is latched into a buffer. Later, when the queue does advance,
stage 1 is refilled from the buffer or from the data bus if the buffer is empty.
In some instruction sequences, there can be several latch cycles before the
queue advances. In these cases, the buffer is filled on the first latch event
and additional latch requests are ignored.
8.3.5 ALD — Advance and Load from Data Bus (Code 1:0)
The instruction queue is advanced by one word and stage one is refilled with
a word of program information from the data bus. The CPU requested the
information two bus cycles earlier but, due to access delays, the information
was not available until the E cycle referred to by the ALD code.
8.3.6 ALL — Advance and Load from Latch (Code 1:1)
This code is not used in the HCS12. In the M68HC12, the 2-stage instruction
queue is advanced by one word and stage one is refilled with a word of
program information from the buffer. The information was latched from the
data bus at the falling edge of a previous E cycle because the instruction
queue was not ready to advance when it arrived.
8.3.7 INT — Interrupt Sequence Start (Code 0:1)
The E cycle associated with this code is the first cycle of an interrupt
sequence. Normally, this cycle is a read of the interrupt vector. However, in
systems that have interrupt vectors in external memory and an 8-bit data
bus, this cycle reads the upper byte of the 16-bit interrupt vector.
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8.3.8 SEV — Start Instruction on Even Address (Code 1:0)
The E cycle associated with this code is the first cycle of the instruction in
the even (high order) half of the word at the head of the instruction queue.
The queue treats the $18 prebyte for instructions on page 2 of the opcode
map as a special 1-byte, 1-cycle instruction, except that interrupts are not
recognized at the boundary between the prebyte and the rest of the
instruction.
8.3.9 SOD — Start Instruction on Odd Address (Code 1:1)
The E cycle associated with this code is the first cycle of the instruction in
the odd (low order) half of the word at the head of the instruction queue. The
queue treats the $18 prebyte for instructions on page 2 of the opcode map
as a special 1-byte, 1-cycle instruction, except that interrupts are not
recognized at the boundary between the prebyte and the rest of the
instruction.
8.4 Queue Reconstruction (for HCS12)
The raw signals required for queue reconstruction are the address bus
(ADDR), the data bus (DATA), the system clock (E), and the queue status
signals (IPIPE1 and IPIPE2). An ALD data movement implies a read;
therefore, it is not necessary to capture the R/W signal. An E clock cycle
begins at a falling edge of E. Addresses and execution status must be
captured at the rising E edge in the middle of the cycle. Data and
data-movement status must be captured at the falling edge of E at the end
of the cycle. These captures can then be organized into records with one
record per E clock cycle.
Implementation details depend on the type of MCU and the mode of
operation. For instance, the data bus can be eight bits or 16 bits wide, and
nonmultiplexed or multiplexed. In all cases, the externally reconstructed
queue must use 16-bit words. Demultiplexing and assembly of 8-bit data
into 16-bit words is done before program information enters the real queue,
so it must also be done for the external reconstruction.
An example:
Systems with an 8-bit data bus and a program stored in external memory
require two cycles for each program word fetch. MCU bus-control logic
freezes the CPU clocks long enough to do two 8-bit accesses rather than
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a single 16-bit access, so the CPU sees only 16-bit words of program
information. To recover the 16-bit program words externally, latch the
data bus state at the falling edge of E when ADDR0 = 0, and gate the
outputs of the latch onto DATA[15:8] when an ALD cycle occurs. Since
the 8-bit data bus is connected to DATA[7:0], the 16-bit word on the data
lines corresponds to the ALD during the last half of the second 8-bit fetch,
which is always to an odd address. IPIPE[1:0] status signals indicate 0:0
for the second half of the E cycle corresponding to the first 8-bit fetch.
Some MCUs have address lines to support memory expansion beyond the
standard 64-Kbyte address space. When memory expansion is used,
expanded addresses must also be captured and maintained.
8.4.1 Queue Reconstruction Registers (for HCS12)
Queue reconstruction requires the following registers, which can be
implemented as software variables when previously captured trace data is
used, or as hardware latches in real time.
8.4.1.1 fetch_add Register
This register buffers the fetch address.
8.4.1.2 st1_add, st1_dat Registers
These registers contain address and data for the first stage of the
reconstructed instruction queue.
8.4.1.3 st2_add, st2_dat Registers
These registers contain address and data for the middle stage of the
reconstructed instruction queue.
8.4.1.4 st3_add, st3_dat Registers
These registers contain address and data for the final stage of the
reconstructed instruction queue. When the IPIPE[1:0] signals indicate the
execution status, the address and opcode can be found in these registers.
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8.4.2 Reconstruction Algorithm (for HCS12)
This section describes how to use IPIPE[1:0] signals and queue
reconstruction registers to reconstruct the queue.
Typically, the first few cycles of raw capture data are not useful because it
takes several cycles before an instruction propagates to the head of the
queue. During these first raw cycles, the only meaningful information
available is data movement signals. Information on the external address
and data buses during this setup time is still captured and propagated
through the reconstructed queue, but the information reflects the actions of
instructions that were fetched before data collection started.
In the special case of a reset, there is a five-cycle sequence (VfPPP) during
which the reset vector is fetched and the instruction queue is filled, before
execution of the first instruction begins. Due to the timing of the switchover
of the IPIPE[1:0] pins from their alternate function as mode-select inputs,
the status information on these two pins may be erroneous during the first
cycle or two after the release of reset. This is not a problem because the
status is correct in time for queue reconstruction logic to correctly replicate
the queue.
On an advance-and-load-from-data-bus (ALD) cycle, the information in the
instruction queue must advance by one stage. Whatever was in stage three
of the queue simply disappears. The previous contents of stage two go to
stage three, the previous contents of stage one go to stage two, and the
contents of fetch_add and data from the current cycle go to stage one.
Figure 8-3 shows the reset sequence and illustrates the relationship
between instruction cycle codes (VfPPP) and pipe status signals. One cycle
of the data bus is shown to indicate the relationship between the ALD data
movement code and the data value it refers to. The SEV execution start
code indicates that the reset vector pointed to an even address in this
example.
INSTRUCTION
CYCLE CODES
V
f
P
P
E CLOCK
DM
FIRST
USER
INSTRUCTION
P
DM
DM
EX
10
ALD
10
SEV
DATA BUS
IPIPE[1:0]
00
00
00
00
00
10
ALD
00
10
ALD
00
Figure 8-3. Reset Sequence for HCS12
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8.5 Queue Reconstruction (for M68HC12)
The raw signals required for queue reconstruction are the address bus
(ADDR), the data bus (DATA), the system clock (E), and the queue status
signals (IPIPE1 and IPIPE0). An E-clock cycle begins after an E fall.
Addresses and data movement status must be captured at the E rise in the
middle of the cycle. Data and execution start status must be captured at the
E fall at the end of the cycle. These captures can then be organized into
records with one record per E clock cycle.
Implementation details depend upon the type of device and the mode of
operation. For instance, the data bus can be eight bits or 16 bits wide, and
non-multiplexed or multiplexed. In all cases, the externally reconstructed
queue must use 16-bit words. Demultiplexing and assembly of 8-bit data
into 16-bit words is done before program information enters the real queue,
so it must also be done for the external reconstruction.
An example:
Systems with an 8-bit data bus and a program stored in external memory
require two cycles for each program word fetch. MCU bus control logic
freezes the CPU clocks long enough to do two 8-bit accesses rather than
a single 16-bit access, so the CPU sees only 16-bit words of program
information. To recover the 16-bit program words externally, latch the
data bus state at the falling edge of E when ADDR0 = 0, and gate the
outputs of the latch onto DATA[15:8] when a LAT or ALD cycle occurs.
Since the 8-bit data bus is connected to DATA[7:0], the 16-bit word on the
data lines corresponds to the ALD or LAT status indication at the E rise
after the second 8-bit fetch, which is always to an odd address. IPIPE1
and IPIPE0 status signals indicate 0:0 at the beginning (E fall) and middle
(E rise) of the first 8-bit fetch.
Some M68HC12 devices have address lines to support memory expansion
beyond the standard 64-Kbyte address space. When memory expansion is
used, expanded addresses must also be captured and maintained.
8.5.1 Queue Reconstruction Registers (for M68HC12)
Queue reconstruction requires these registers, which can be implemented
as software variables when previously captured trace data is used or as
hardware latches in real time.
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8.5.1.1 in_add, in_dat Registers
These registers contain the address and data from the previous external
bus cycle. Depending on how records are read and processed from the raw
capture information, it may be possible to simply read this information from
the raw capture data file when needed.
8.5.1.2 fetch_add, fetch_dat Registers
These registers buffer address and data for information that was fetched
before the queue was ready to advance.
8.5.1.3 st1_add, st1_dat Registers
These registers contain address and data for the first stage of the
reconstructed instruction queue.
8.5.1.4 st2_add, st2_dat Registers
These registers contain address and data for the final stage of the
reconstructed instruction queue. When the IPIPE1 and IPIPE0 signals
indicate that an instruction is starting to execute, the address and opcode
can be found in these registers.
8.5.2 Reconstruction Algorithm (for M68HC12)
This subsection describes in detail how to use IPIPE1 and IPIPE0 signals
and queue reconstruction registers to reconstruct the queue. An “is_full” flag
is used to indicate when the fetch_add and fetch_dat buffer registers
contain information. The use of the flag is explained more fully in
subsequent paragraphs.
Typically, the first few cycles of raw capture data are not useful because it
takes several cycles before an instruction propagates to the head of the
queue. During these first raw cycles, the only meaningful information
available are data movement signals. Information on the external address
and data buses during this setup time reflects the actions of instructions that
were fetched before data collection started.
In the special case of a reset, there is a 5-cycle sequence (VfPPP) during
which the reset vector is fetched and the instruction queue is filled, before
execution of the first instruction begins. Due to the timing of the switchover
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of the IPIPE1 and IPIPE0 pins from their alternate function as mode select
inputs, the status information on these two pins may be erroneous during
the first cycle or two after the release of reset. This is not a problem because
the status is correct in time for queue reconstruction logic to correctly
replicate the queue.
Before starting to reconstruct the queue, clear the is_full flag to indicate that
there is no meaningful information in the fetch_add and fetch_dat buffers.
Further movement of information in the instruction queue is based on the
decoded status on the IPIPE1 and IPIPE0 signals at the rising edges of E.
8.5.2.1 LAT Decoding
On a latch cycle (LAT), check the is_full flag. If and only if is_full = 0, transfer
the address and data from the previous bus cycle (in_add and in_dat) into
the fetch_add and fetch_dat registers, respectively. Then, set the is_full
flag. The usual reason for a latch request instead of an advance request is
that the previous instruction ended with a single aligned byte of program
information in the last stage of the instruction queue. Since the odd half of
this word still holds the opcode for the next instruction, the queue cannot
advance on this cycle. However, the cycle to fetch the next word of program
information has already started and the data is on its way.
8.5.2.2 ALD Decoding
On an advance-and-load-from-data-bus (ALD) cycle, the information in the
instruction queue must advance by one stage. Whatever was in stage 2 of
the queue is simply thrown away. The previous contents of stage 1 are
moved to stage 2, and the address and data from the previous cycle (in_add
and in_dat) are transferred into stage 1 of the instruction queue. Finally,
clear the is_full flag to indicate the buffer latch is ready for new data. Usually,
there would be no useful information in the fetch buffer when an ALD cycle
was encountered, but in the case of a change-of-flow, any data that was
there needs to be flushed out (by clearing the is_full flag).
8.5.2.3 ALL Decoding
On an advance-and-load-from-latch (ALL) cycle, the information in the
instruction queue must advance by one stage. Whatever was in stage 2 of
the queue is simply thrown away. The previous contents of stage 1 are
moved to stage 2, and the contents of the fetch buffer latch are transferred
into stage 1 of the instruction queue. One or more cycles preceding the ALL
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cycle will have been a LAT cycle. After updating the instruction queue, clear
the is_full flag to indicate the fetch buffer is ready for new information.
Figure 8-4 shows the reset sequence and illustrates the relationship
between instruction cycle codes (VfPPP) and pipe status signals. One cycle
of the data bus is shown to indicate the relationship between the ALD data
movement code and the data value it refers to. The SEV execution start
code indicates that the reset vector pointed to an even address in this
example.
INSTRUCTION
CYCLE CODES
V
f
P
P
P
DM
DM
EX
10
ALD
10
SEV
FIRST USER
INSTRUCTION
E CLOCK
DM
DATA BUS
IPIPE[1:0]
00
00
00
00
00
00
10
ALD
00
10
ALD
Figure 8-4. Reset Sequence for M68HC12
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8.6 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed
in real time or from trace history that was captured by a logic analyzer.
However, the reconstructed queue cannot be used to stop the CPU at a
specific instruction, because execution has already begun by the time an
operation is visible outside the MCU. A separate instruction tagging
mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
TAGHI signal shares the BKGD pin. Tagging information is latched on the
falling edge of ECLK, as shown in Figure 8-5.
TAGS ARE APPLIED TO PROGRAM INFORMATION
CAPTURED ON THIS E CLOCK TRANSITION
E CLOCK
LSTRB/TAGLO
TAGLO
VALID
LSTRB VALID
TAGHI
VALID
BKGD/TAGHI
Figure 8-5. Tag Input Timing
Table 8-2 shows the functions of the two independent tagging pins. The
presence of logic level 0 on either pin at the fall of ECLK tags (marks) the
associated byte of program information as it is read into the instruction
queue. Tagging is allowed in all modes. Tagging is disabled when BDM
becomes active.
Table 8-2. Tag Pin Function
TAGHI
TAGLO
Tag
1
1
No tag
1
0
Low byte
0
1
High byte
0
0
Both bytes
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In HCS12 and M68HC12 derivatives that have hardware breakpoint
capability, the breakpoint control logic and BDM control logic use the same
internal signals for instruction tagging. The CPU does not differentiate
between the two kinds of tags.
The tag follows program information as it advances through the queue.
When a tagged instruction reaches the head of the queue, the CPU enters
active background debug mode rather than executing the instruction.
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Reference Manual — S12CPUV2
Section 9. Fuzzy Logic Support
9.1 Introduction
The instruction set of the central processor unit (CPU12) is the first
instruction set to specifically address the needs of fuzzy logic. This section
describes the use of fuzzy logic in control systems, discusses the CPU12
fuzzy logic instructions, and provides examples of fuzzy logic programs.
The CPU12 includes four instructions that perform specific fuzzy logic tasks.
In addition, several other instructions are especially useful in fuzzy logic
programs. The overall C-friendliness of the instruction set also aids
development of efficient fuzzy logic programs.
This section explains the basic fuzzy logic algorithm for which the four fuzzy
logic instructions are intended. Each of the fuzzy logic instructions are then
explained in detail. Finally, other custom fuzzy logic algorithms are
discussed, with emphasis on use of other CPU12 instructions.
The four fuzzy logic instructions are:
• MEM (determine grade of membership), which evaluates trapezoidal
membership functions
• REV (fuzzy logic rule evaluation) and REVW (fuzzy logic rule
evaluation weighted), which perform unweighted or weighted
MIN-MAX rule evaluation
• WAV (weighted average), which performs weighted average
defuzzification on singleton output membership functions.
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Other instructions that are useful for custom fuzzy logic programs include:
• MINA (place smaller of two unsigned 8-bit values in accumulator A)
• EMIND (place smaller of two unsigned 16-bit values in
accumulator D)
• MAXM (place larger of two unsigned 8-bit values in memory)
• EMAXM (place larger of two unsigned 16-bit values in memory)
• TBL (table lookup and interpolate)
• ETBL (extended table lookup and interpolate)
• EMACS (extended multiply and accumulate signed 16-bit by 16-bit to
32-bit)
For higher resolution fuzzy programs, the fast extended precision math
instructions in the CPU12 are also beneficial. Flexible indexed addressing
modes help simplify access to fuzzy logic data structures stored as lists or
tabular data structures in memory.
The actual logic additions required to implement fuzzy logic support in the
CPU12 are quite small, so there is no appreciable increase in cost for the
typical user. A fuzzy inference kernel for the CPU12 requires one-fifth as
much code space and executes almost 50 times faster than a comparable
kernel implemented on a typical midrange microcontroller.
9.2 Fuzzy Logic Basics
This is an overview of basic fuzzy logic concepts. It can serve as a general
introduction to the subject, but that is not the main purpose. There are a
number of fuzzy logic programming strategies. This discussion
concentrates on the methods implemented in the CPU12 fuzzy logic
instructions. The primary goal is to provide a background for a detailed
explanation of the CPU12 fuzzy logic instructions.
In general, fuzzy logic provides for set definitions that have fuzzy
boundaries rather than the crisp boundaries of Aristotelian logic. These sets
can overlap so that, for a specific input value, one or more sets associated
with linguistic labels may be true to a degree at the same time. As the input
varies from the range of one set into the range of an adjacent set, the first
set becomes progressively less true while the second set becomes
progressively more true.
Fuzzy logic has membership functions which emulate human concepts like
“temperature is warm”; that is, conditions are perceived to have gradual
boundaries. This concept seems to be a key element of the human ability to
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solve certain types of complex problems that have eluded traditional control
methods.
Fuzzy sets provide a means of using linguistic expressions like
“temperature is warm” in rules which can then be evaluated with a high
degree of numerical precision and repeatability. This directly contradicts the
common misperception that fuzzy logic produces approximate results — a
specific set of input conditions always produces the same result, just as a
conventional control system does.
A microcontroller-based fuzzy logic control system has two parts:
•
A fuzzy inference kernel which is executed periodically to determine
system outputs based on current system inputs
•
A knowledge base which contains membership functions and rules
Figure 9-1 is a block diagram of this kind of fuzzy logic system.
KNOWLEDGE
BASE
INPUT
MEMBERSHIP
FUNCTIONS
SYSTEM
INPUTS
FUZZY
INFERENCE
KERNEL
FUZZIFICATION
…
RULE LIST
RULE EVALUATION
…
OUTPUT
MEMBERSHIP
FUNCTIONS
FUZZY INPUTS
(IN RAM)
FUZZY OUTPUTS
(IN RAM)
DEFUZZIFICATION
SYSTEM
OUTPUTS
Figure 9-1. Block Diagram of a Fuzzy Logic System
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The knowledge base can be developed by an application expert without any
microcontroller programming experience. Membership functions are simply
expressions of the expert’s understanding of the linguistic terms that
describe the system to be controlled. Rules are ordinary language
statements that describe the actions a human expert would take to solve the
application problem.
Rules and membership functions can be reduced to relatively simple data
structures (the knowledge base) stored in non-volatile memory. A fuzzy
inference kernel can be written by a programmer who does not know how
the application system works. The only thing the programmer needs to do
with knowledge base information is store it in the memory locations used by
the kernel.
One execution pass through the fuzzy inference kernel generates system
output signals in response to current input conditions. The kernel is
executed as often as needed to maintain control. If the kernel is executed
more often than needed, processor bandwidth and power are wasted;
delaying too long between passes can cause the system to get too far out
of control. Choosing a periodic rate for a fuzzy control system is the same
as it would be for a conventional control system.
9.2.1 Fuzzification (MEM)
During the fuzzification step, the current system input values are compared
against stored input membership functions to determine the degree to which
each label of each system input is true. This is accomplished by finding the
y-value for the current input value on a trapezoidal membership function for
each label of each system input. The MEM instruction in the CPU12
performs this calculation for one label of one system input. To perform the
complete fuzzification task for a system, several MEM instructions must be
executed, usually in a program loop structure.
Figure 9-2 shows a system of three input membership functions, one for
each label of the system input. The x-axis of all three membership functions
represents the range of possible values of the system input. The vertical line
through all three membership functions represents a specific system input
value. The y-axis represents degree of truth and varies from completely
false ($00 or 0 percent) to completely true ($FF or 100 percent). The y-value
where the vertical line intersects each of the membership functions, is the
degree to which the current input value matches the associated label for this
system input. For example, the expression “temperature is warm” is 25
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percent true ($40). The value $40 is stored to a random-access memory
(RAM) location and is called a fuzzy input (in this case, the fuzzy input for
“temperature is warm”). There is a RAM location for each fuzzy input (for
each label of each system input).
MEMBERSHIP FUNCTIONS
FOR TEMPERATURE
$FF
FUZZY INPUTS
HOT
$C0
$80
$40
TEMPERATURE IS HOT
$00
TEMPERATURE IS WARM
$40
TEMPERATURE IS COLD
$C0
$00
0°F
$FF
32°F
64°F
96°F
128°F
WARM
$C0
$80
$40
$00
0°F
32°F
64°F
96°F
128°F
$FF
COLD
$C0
$80
$40
$00
0°F
32°F
64°F
96°F
128°F
CURRENT
TEMPERATURE
IS 64°F
Figure 9-2. Fuzzification Using Membership Functions
When the fuzzification step begins, the current value of the system input is
in an accumulator of the CPU12, one index register points to the first
membership function definition in the knowledge base, and a second index
register points to the first fuzzy input in RAM. As each fuzzy input is
calculated by executing a MEM instruction, the result is stored to the fuzzy
input and both pointers are updated automatically to point to the locations
associated with the next fuzzy input. The MEM instruction takes care of
everything except counting the number of labels per system input and
loading the current value of any subsequent system inputs.
The end result of the fuzzification step is a table of fuzzy inputs representing
current system conditions.
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9.2.2 Rule Evaluation (REV and REVW)
Rule evaluation is the central element of a fuzzy logic inference program.
This step processes a list of rules from the knowledge base using current
fuzzy input values from RAM to produce a list of fuzzy outputs in RAM.
These fuzzy outputs can be thought of as raw suggestions for what the
system output should be in response to the current input conditions. Before
the results can be applied, the fuzzy outputs must be further processed, or
defuzzified, to produce a single output value that represents the combined
effect of all of the fuzzy outputs.
The CPU12 offers two variations of rule evaluation instructions. The REV
instruction provides for unweighted rules (all rules are considered to be
equally important). The REVW instruction is similar but allows each rule to
have a separate weighting factor which is stored in a separate parallel data
structure in the knowledge base. In addition to the weights, the two rule
evaluation instructions also differ in the way rules are encoded into the
knowledge base.
An understanding of the structure and syntax of rules is needed to
understand how a microcontroller performs the rule evaluation task. An
example of a typical rule is:
If temperature is warm and pressure is high, then heat is
(should be) off.
At first glance, it seems that encoding this rule in a compact form
understandable to the microcontroller would be difficult, but it is actually
simple to reduce the rule to a small list of memory pointers. The antecedent
portion of the rule is a statement of input conditions and the consequent
portion of the rule is a statement of output actions.
The antecedent portion of a rule is made up of one or more (in this case two)
antecedents connected by a fuzzy and operator. Each antecedent
expression consists of the name of a system input, followed by is, followed
by a label name. The label must be defined by a membership function in the
knowledge base. Each antecedent expression corresponds to one of the
fuzzy inputs in RAM. Since and is the only operator allowed to connect
antecedent expressions, there is no need to include these in the encoded
rule. The antecedents can be encoded as a simple list of pointers to (or
addresses of) the fuzzy inputs to which they refer.
The consequent portion of a rule is made up of one or more (in this case
one) consequents. Each consequent expression consists of the name of a
system output, followed by is, followed by a label name. Each consequent
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expression corresponds to a specific fuzzy output in RAM. Consequents for
a rule can be encoded as a simple list of pointers to (or addresses of) the
fuzzy outputs to which they refer.
The complete rules are stored in the knowledge base as a list of pointers or
addresses of fuzzy inputs and fuzzy outputs. For the rule evaluation logic to
work, there must be some means of knowing which pointers refer to fuzzy
inputs and which refer to fuzzy outputs. There also must be a way to know
when the last rule in the system has been reached.
•
One method of organization is to have a fixed number of rules with a
specific number of antecedents and consequents.
•
A second method, employed in Freescale Freeware M68HC11
kernels, is to mark the end of the rule list with a reserved value, and
use a bit in the pointers to distinguish antecedents from consequents.
•
A third method of organization, used in the CPU12, is to mark the end
of the rule list with a reserved value, and separate antecedents and
consequents with another reserved value. This permits any number
of rules, and allows each rule to have any number of antecedents and
consequents, subject to the limits imposed by availability of system
memory.
Each rule is evaluated sequentially, but the rules as a group are treated as
if they were all evaluated simultaneously. Two mathematical operations
take place during rule evaluation. The fuzzy and operator corresponds to
the mathematical minimum operation and the fuzzy or operation
corresponds to the mathematical maximum operation. The fuzzy and is
used to connect antecedents within a rule. The fuzzy or is implied between
successive rules. Before evaluating any rules, all fuzzy outputs are set to
zero (meaning not true at all). As each rule is evaluated, the smallest
(minimum) antecedent is taken to be the overall truth of the rule. This rule
truth value is applied to each consequent of the rule (by storing this value to
the corresponding fuzzy output) unless the fuzzy output is already larger
(maximum). If two rules affect the same fuzzy output, the rule that is most
true governs the value in the fuzzy output because the rules are connected
by an implied fuzzy or.
In the case of rule weighting, the truth value for a rule is determined as usual
by finding the smallest rule antecedent. Before applying this truth value to
the consequents for the rule, the value is multiplied by a fraction from zero
(rule disabled) to one (rule fully enabled). The resulting modified truth value
is then applied to the fuzzy outputs.
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The end result of the rule evaluation step is a table of suggested or “raw”
fuzzy outputs in RAM. These values were obtained by plugging current
conditions (fuzzy input values) into the system rules in the knowledge base.
The raw results cannot be supplied directly to the system outputs because
they may be ambiguous. For instance, one raw output can indicate that the
system output should be medium with a degree of truth of 50 percent while,
at the same time, another indicates that the system output should be low
with a degree of truth of 25 percent. The defuzzification step resolves these
ambiguities.
9.2.3 Defuzzification (WAV)
The final step in the fuzzy logic program combines the raw fuzzy outputs into
a composite system output. Unlike the trapezoidal shapes used for inputs,
the CPU12 typically uses singletons for output membership functions. As
with the inputs, the x-axis represents the range of possible values for a
system output. Singleton membership functions consist of the x-axis
position for a label of the system output. Fuzzy outputs correspond to the
y-axis height of the corresponding output membership function.
The WAV instruction calculates the numerator and denominator sums for
weighted average of the fuzzy outputs according to the formula:
n
∑ Si Fi
i=1
System Output = ----------------------n
Fi
∑
i=1
Where n is the number of labels of a system output, Si are the singleton
positions from the knowledge base, and Fi are fuzzy outputs from RAM. For
a common fuzzy logic program on the CPU12, n is eight or less (though this
instruction can handle any value to 255) and Si and Fi are 8-bit values. The
final divide is performed with a separate EDIV instruction placed
immediately after the WAV instruction.
Before executing WAV, an accumulator must be loaded with the number of
iterations (n), one index register must be pointed at the list of singleton
positions in the knowledge base, and a second index register must be
pointed at the list of fuzzy outputs in RAM. If the system has more than one
system output, the WAV instruction is executed once for each system
output.
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9.3 Example Inference Kernel
Figure 9-3 is a complete fuzzy inference kernel written in CPU12 assembly
language. Numbers in square brackets are cycle counts for an HCS12
device. The kernel uses two system inputs with seven labels each and one
system output with seven labels. The program assembles to 57 bytes. It
executes in about 20 µs at an 25-MHz bus rate. The basic structure can
easily be extended to a general-purpose system with a larger number of
inputs and outputs.
01
02
03
04
05
06
07
08
09
10
*
[2]
[2]
[3]
[1]
[5]
[3]
[3]
[1]
[5]
[3]
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FUZZIFY
LDX
LDY
LDAA
LDAB
MEM
DBNE
LDAA
LDAB
MEM
DBNE
#INPUT_MFS
#FUZ_INS
CURRENT_INS
#7
[1]
[2]
RULE_EVAL
[3]
[2]
[2]
[1]
[3n+4]
LDAB
CLR
DBNE
LDX
LDY
LDAA
REV
#7
1,Y+
b,RULE_EVAL
#RULE_START
#FUZ_INS
#$FF
;Loop count
;Clr a fuzzy out & inc ptr
;Loop to clr all fuzzy outs
;Point at first rule element
;Point at fuzzy ins and outs
;Init A (and clears V-bit)
;Process rule list
[2]
DEFUZ
[2]
[1]
[7b+4]
[11]
[1]
[3]
*
***** End
LDY
LDX
LDAB
WAV
EDIV
TFR
STAB
#FUZ_OUT
#SGLTN_POS
#7
;Point at fuzzy outputs
;Point at singleton positions
;7 fuzzy outs per COG output
;Calculate sums for wtd av
;Final divide for wtd av
;Move result to A:B
;Store system output
GRAD_LOOP
GRAD_LOOP1
B,GRAD_LOOP
CURRENT_INS+1
#7
B,GRAD_LOOP1
Y,D
COG_OUT
;Point at MF definitions
;Point at fuzzy input table
;Get first input value
;7 labels per input
;Evaluate one MF
;For 7 labels of 1 input
;Get second input value
;7 labels per input
;Evaluate one MF
;For 7 labels of 1 input
Figure 9-3. Fuzzy Inference Engine
Lines 1 to 3 set up pointers and load the system input value into the A
accumulator.
Line 4 sets the loop count for the loop in lines 5 and 6.
Lines 5 and 6 make up the fuzzification loop for seven labels of one system
input. The MEM instruction finds the y-value on a trapezoidal membership
function for the current input value, for one label of the current input, and
then stores the result to the corresponding fuzzy input. Pointers in X and Y
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are automatically updated by four and one so they point at the next
membership function and fuzzy input respectively.
Line 7 loads the current value of the next system input. Pointers in X and Y
already point to the right places as a result of the automatic update function
of the MEM instruction in line 5.
Line 8 reloads a loop count.
Lines 9 and 10 form a loop to fuzzify the seven labels of the second system
input. When the program drops to line 11, the Y index register is pointing at
the next location after the last fuzzy input, which is the first fuzzy output in
this system.
Line 11 sets the loop count to clear seven fuzzy outputs.
Lines 12 and 13 form a loop to clear all fuzzy outputs before rule evaluation
starts.
Line 14 initializes the X index register to point at the first element in the rule
list for the REV instruction.
Line 15 initializes the Y index register to point at the fuzzy inputs and outputs
in the system. The rule list (for REV) consists of 8-bit offsets from this base
address to particular fuzzy inputs or fuzzy outputs. The special value $FE is
interpreted by REV as a marker between rule antecedents and
consequents.
Line 16 initializes the A accumulator to the highest 8-bit value in preparation
for finding the smallest fuzzy input referenced by a rule antecedent. The
LDAA #$FF instruction also clears the V-bit in the CPU12’s condition code
register so the REV instruction knows it is processing antecedents. During
rule list processing, the V bit is toggled each time an $FE is detected in the
list. The V bit indicates whether REV is processing antecedents or
consequents.
Line 17 is the REV instruction, a self-contained loop to process successive
elements in the rule list until an $FF character is found. For a system of 17
rules with two antecedents and one consequent each, the REV instruction
takes 259 cycles, but it is interruptible so it does not cause a long interrupt
latency.
Lines 18 through 20 set up pointers and an iteration count for the WAV
instruction.
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Line 21 is the beginning of defuzzification. The WAV instruction calculates
a sum-of-products and a sum-of-weights.
Line 22 completes defuzzification. The EDIV instruction performs a 32-bit by
16-bit divide on the intermediate results from WAV to get the weighted
average.
Line 23 moves the EDIV result into the double accumulator.
Line 24 stores the low 8-bits of the defuzzification result.
This example inference program shows how easy it is to incorporate fuzzy
logic into general applications using the CPU12. Code space and execution
time are no longer serious factors in the decision to use fuzzy logic. The next
section begins a much more detailed look at the fuzzy logic instructions of
the CPU12.
9.4 MEM Instruction Details
This section provides a more detailed explanation of the membership
function evaluation instruction (MEM), including details about abnormal
special cases for improperly defined membership functions.
9.4.1 Membership Function Definitions
Figure 9-4 shows how a normal membership function is specified in the
CPU12. Typically, a software tool is used to input membership functions
graphically, and the tool generates data structures for the target processor
and software kernel. Alternatively, points and slopes for the membership
functions can be determined and stored in memory with define-constant
assembler directives.
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GRAPHICAL REPRESENTATION
$FF
$E0
$C0
DEGREE
OF
TRUTH
$A0
$80
slope_2
$60
$40
slope_1
point_1
point_2
$20
$00
$00
$10
$20
$30
$40
$50
$60
$70
$80
$90
$A0
$B0
$C0
$D0
$E0
$F0
$FF
INPUT RANGE
MEMORY REPRESENTATION
ADDR
$40
X-POSITION OF point_1
ADDR+1
$D0
X-POSITION OF point_2
ADDR+2
$08
slope_1 ($FF/(X-POS OF SATURATION – point_1))
ADDR+3
$04
slope_2 ($FF/(point_2 – X-POS OF SATURATION))
Figure 9-4. Defining a Normal Membership Function
An internal CPU algorithm calculates the y-value where the current input
intersects a membership function. This algorithm assumes the membership
function obeys some common-sense rules. If the membership function
definition is improper, the results may be unusual. See 9.4.2 Abnormal
Membership Function Definitions for a discussion of these cases.
These rules apply to normal membership functions.
•
$00 ≤ point1 < $FF
•
$00 < point2 ≤ $FF
•
point1 < point2
•
The sloping sides of the trapezoid meet at or above $FF.
Each system input such as temperature has several labels such as cold,
cool, normal, warm, and hot. Each label of each system input must have a
membership function to describe its meaning in an unambiguous numerical
way. Typically, there are three to seven labels per system input, but there is
no practical restriction on this number as far as the fuzzification step is
concerned.
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9.4.2 Abnormal Membership Function Definitions
In the CPU12, it is possible (and proper) to define “crisp” membership
functions. A crisp membership function has one or both sides vertical
(infinite slope). Since the slope value $00 is not used otherwise, it is
assigned to mean infinite slope to the MEM instruction in the CPU12.
Although a good fuzzy development tool will not allow the user to specify an
improper membership function, it is possible to have program errors or
memory errors which result in erroneous abnormal membership functions.
Although these abnormal shapes do not correspond to any working
systems, understanding how the CPU12 treats these cases can be helpful
for debugging.
A close examination of the MEM instruction algorithm will show how such
membership functions are evaluated. Figure 9-5 is a complete flow diagram
for the execution of a MEM instruction. Each rectangular box represents one
CPU bus cycle. The number in the upper left corner corresponds to the cycle
number and the letter corresponds to the cycle type (refer to Section 6.
Instruction Glossary for details). The upper portion of the box includes
information about bus activity during this cycle (if any). The lower portion of
the box, which is separated by a dashed line, includes information about
internal CPU processes. It is common for several internal functions to take
place during a single CPU cycle (for example, in cycle 2, two 8-bit
subtractions take place and a flag is set based on the results).
Consider 4a: If (((Slope_2 = 0) or (Grade_2 > $FF)) and (flag_d12n = 0)).
The flag_d12n is zero as long as the input value (in accumulator A) is within
the trapezoid. Everywhere outside the trapezoid, one or the other delta term
will be negative, and the flag will equal one. Slope_2 equals zero indicates
the right side of the trapezoid has infinite slope, so the resulting grade
should be $FF everywhere in the trapezoid, including at point_2, as far as
this side is concerned. The term grade_2 greater than $FF means the value
is far enough into the trapezoid that the right sloping side of the trapezoid
has crossed above the $FF cutoff level and the resulting grade should be
$FF as far as the right sloping side is concerned. 4a decides if the value is
left of the right sloping side (Grade = $FF), or on the sloping portion of the
right side of the trapezoid (Grade = Grade_2). 4b could still override this
tentative value in grade.
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START
1-R
2-R
READ WORD @ 0,X — Point_1 AND Point_2
X=X+4
READ WORD @ –2,X — Slope_1 AND Slope_2
Y=Y+1
2a — Delta_1 = ACCA – Point_1
2b — Delta_2 = Point_2 – ACCA
2c — IF (Delta_1 OR Delta_2) < 0 THEN flag_d12n = 1 ELSE flag_d12n = 0
3-f
NO BUS ACCESS
3a — IF flag_d12n = 1 THEN Grade_1 = 0 ELSE Grade_1 = Slope_1 * Delta_1
3b — IF flag_d12n = 1 THEN Grade_2 = 0 ELSE Grade_2 = Slope_2 * Delta_2
4-O
IF MISALIGNED THEN READ PROGRAM WORD TO FILL INSTRUCTION QUEUE ELSE NO BUS ACCESS
4a — IF (((Slope_2 = 0) OR (Grade_2 > $FF)) AND (flag_d12n = 0)) THEN GRADE = $FF
ELSE GRADE = Grade_2
4b — IF (((Slope_1 = 0) OR (Grade_1 > $FF)) AND (flag_d12n = 0)) THEN GRADE = GRADE
ELSE GRADE = Grade_1
5-w
WRITE BYTE @ –1,Y — FUZZY INPUT RESULT (GRADE)
END
Figure 9-5. MEM Instruction Flow Diagram
In 4b, slope_1 is zero if the left side of the trapezoid has infinite slope
(vertical). If so, the result (grade) should be $FF at and to the right of point_1
everywhere within the trapezoid as far as the left side is concerned. The
grade_1 greater than $FF term corresponds to the input being to the right of
where the left sloping side passes the $FF cutoff level. If either of these
conditions is true, the result (grade) is left at the value it got from 4a. The
“else” condition in 4b corresponds to the input falling on the sloping portion
of the left side of the trapezoid (or possibly outside the trapezoid), so the
result is grade equal grade_1. If the input was outside the trapezoid,
flag_d12n would be one and grade_1 and grade_2 would have been forced
to $00 in cycle 3. The else condition of 4b would set the result to $00.
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The special cases shown here represent abnormal membership function
definitions. The explanations describe how the specific algorithm in the
CPU12 resolves these unusual cases. The results are not all intuitively
obvious, but rather fall out from the specific algorithm. Remember, these
cases should not occur in a normal system.
9.4.2.1 Abnormal Membership Function Case 1
This membership function is abnormal because the sloping sides cross
below the $FF cutoff level. The flag_d12n signal forces the membership
function to evaluate to $00 everywhere except from point_1 to point_2.
Within this interval, the tentative values for grade_1 and grade_2 calculated
in cycle 3 fall on the crossed sloping sides. In step 4a, grade gets set to the
grade_2 value, but in 4b this is overridden by the grade_1 value, which ends
up as the result of the MEM instruction. One way to say this is that the result
follows the left sloping side until the input passes point_2, where the result
goes to $00.
MEMORY DEFINITION: $60, $80, $04, $04; point_1, point_2, slope_1, slope_2
GRAPHICAL REPRESENTATION
P1
P2
HOW INTERPRETED
P1
P2
Figure 9-6. Abnormal Membership Function Case 1
If point_1 was to the right of point_2, flag_d12n would force the result to be
$00 for all input values. In fact, flag_d12n always limits the region of interest
to the space greater than or equal to point_1 and less than or equal to
point_2.
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9.4.2.2 Abnormal Membership Function Case 2
Like the previous example, the membership function in case 2 is abnormal
because the sloping sides cross below the $FF cutoff level, but the left
sloping side reaches the $FF cutoff level before the input gets to point_2. In
this case, the result follows the left sloping side until it reaches the $FF cutoff
level. At this point, the (grade_1 > $FF) term of 4b kicks in, making the
expression true so grade equals grade (no overwrite). The result from here
to point_2 becomes controlled by the “else” part of 4a (grade = grade_2),
and the result follows the right sloping side.
MEMORY DEFINITION: $60, $C0, $04, $04; point_1, point_2, slope_1, slope_2
GRAPHICAL REPRESENTATION
P1
P2
HOW INTERPRETED
P1
LEFT SIDE P2
CROSSES $FF
Figure 9-7. Abnormal Membership Function Case 2
9.4.2.3 Abnormal Membership Function Case 3
The membership function in case 3 is abnormal because the sloping sides
cross below the $FF cutoff level, and the left sloping side has infinite slope.
In this case, 4a is not true, so grade equals grade_2. 4b is true because
slope_1 is zero, so 4b does not overwrite grade.
MEMORY DEFINITION: $60, $80, $00, $04; point_1, point_2, slope_1, slope_2
GRAPHICAL REPRESENTATION
P1
P2
HOW INTERPRETED
P1
P2
Figure 9-8. Abnormal Membership Function Case 3
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9.5 REV and REVW Instruction Details
This section provides a more detailed explanation of the rule evaluation
instructions (REV and REVW). The data structures used to specify rules are
somewhat different for the weighted versus unweighted versions of the
instruction. One uses 8-bit offsets in the encoded rules, while the other uses
full 16-bit addresses. This affects the size of the rule data structure and
execution time.
9.5.1 Unweighted Rule Evaluation (REV)
This instruction implements basic min-max rule evaluation. CPU registers
are used for pointers and intermediate calculation results.
Since the REV instruction is essentially a list-processing instruction,
execution time is dependent on the number of elements in the rule list. The
REV instruction is interruptible (typically within three bus cycles), so it does
not adversely affect worst case interrupt latency. Since all intermediate
results and instruction status are held in stacked CPU registers, the interrupt
service code can even include independent REV and REVW instructions.
9.5.1.1 Set Up Prior to Executing REV
Some CPU registers and memory locations need to be set up prior to
executing the REV instruction. X and Y index registers are used as index
pointers to the rule list and the fuzzy inputs and outputs. The A accumulator
is used for intermediate calculation results and needs to be set to $FF
initially. The V condition code bit is used as an instruction status indicator to
show whether antecedents or consequents are being processed. Initially,
the V bit is cleared to zero to indicate antecedents are being processed. The
fuzzy outputs (working RAM locations) need to be cleared to $00. If these
values are not initialized before executing the REV instruction, results will
be erroneous.
The X index register is set to the address of the first element in the rule list
(in the knowledge base). The REV instruction automatically updates this
pointer so that the instruction can resume correctly if it is interrupted. After
the REV instruction finishes, X will point at the next address past the $FF
separator character that marks the end of the rule list.
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The Y index register is set to the base address for the fuzzy inputs and
outputs (in working RAM). Each rule antecedent is an unsigned 8-bit offset
from this base address to the referenced fuzzy input. Each rule consequent
is an unsigned 8-bit offset from this base address to the referenced fuzzy
output. The Y index register remains constant throughout execution of the
REV instruction.
The 8-bit A accumulator is used to hold intermediate calculation results
during execution of the REV instruction. During antecedent processing, A
starts out at $FF and is replaced by any smaller fuzzy input that is
referenced by a rule antecedent (MIN). During consequent processing, A
holds the truth value for the rule. This truth value is stored to any fuzzy
output that is referenced by a rule consequent, unless that fuzzy output is
already larger (MAX).
Before starting to execute REV, A must be set to $FF (the largest 8-bit
value) because rule evaluation always starts with processing of the
antecedents of the first rule. For subsequent rules in the list, A is
automatically set to $FF when the instruction detects the $FE marker
character between the last consequent of the previous rule and the first
antecedent of a new rule.
The instruction LDAA #$FF clears the V bit at the same time it initializes A
to $FF. This satisfies the REV setup requirement to clear the V bit as well
as the requirement to initialize A to $FF. Once the REV instruction starts, the
value in the V bit is automatically maintained as $FE separator characters
are detected.
The final requirement to clear all fuzzy outputs to $00 is part of the MAX
algorithm. Each time a rule consequent references a fuzzy output, that fuzzy
output is compared to the truth value for the current rule. If the current truth
value is larger, it is written over the previous value in the fuzzy output. After
all rules have been evaluated, the fuzzy output contains the truth value for
the most-true rule that referenced that fuzzy output.
After REV finishes, A will hold the truth value for the last rule in the rule list.
The V condition code bit should be one because the last element before the
$FF end marker should have been a rule consequent. If V is zero after
executing REV, it indicates the rule list was structured incorrectly.
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9.5.1.2 Interrupt Details
The REV instruction includes a 3-cycle processing loop for each byte in the
rule list (including antecedents, consequents, and special separator
characters). Within this loop, a check is performed to see if any qualified
interrupt request is pending. If an interrupt is detected, the current CPU
registers are stacked and the interrupt is honored. When the interrupt
service routine finishes, an RTI instruction causes the CPU to recover its
previous context from the stack, and the REV instruction is resumed as if it
had not been interrupted.
The stacked value of the program counter (PC), in case of an interrupted
REV instruction, points to the REV instruction rather than the instruction that
follows. This causes the CPU to try to execute a new REV instruction upon
return from the interrupt. Since the CPU registers (including the V bit in the
condition codes register) indicate the current status of the interrupted REV
instruction, this effectively causes the rule evaluation operation to resume
from where it left off.
9.5.1.3 Cycle-by-Cycle Details for REV
The central element of the REV instruction is a 3-cycle loop that is executed
once for each byte in the rule list. There is a small amount of housekeeping
activity to get this loop started as REV begins and a small sequence to end
the instruction. If an interrupt comes, there is a special small sequence to
save CPU status on the stack before honoring the requested interrupt.
Figure 9-9 is a REV instruction flow diagram. Each rectangular box
represents one CPU clock cycle. Decision blocks and connecting arrows
are considered to take no time at all. The letters in the small rectangles in
the upper left corner of each bold box correspond to execution cycle codes
(refer to Section 6. Instruction Glossary for details). Lower case letters
indicate a cycle where 8-bit or no data is transferred. Upper case letters
indicate cycles where 16-bit or no data is transferred.
When a value is read from memory, it cannot be used by the CPU until the
second cycle after the read takes place. This is due to access and
propagation delays.
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START
1.0 - O
2.0 - r
READ PROGRAM WORD IF $18 MISALIGNED
READ BYTE @ 0,X (RULE ELEMENT Rx)
X = X + 1 POINT AT NEXT RULE ELEMENT
3.0 - f
NO BUS ACCESS
4.0 - t
UPDATE RX WITH VALUE READ IN CYC 2 OR 5
IF Rx $FE OR $FF
THEN READ BYTE @ Rx,Y (FUZZY IN OR OUT Fy)
ELSE NO BUS ACCESS
IF Rx = $FE & V WAS 1, RESET ACCA TO $FF
IF Rx = $FE TOGGLE V-BIT
YES
INTERRUPT PENDING?
NO
5.0 - t
$FF
Rx = $FF, OTHER?
5.2 - f
NO BUS ACCESS
ADJUST PC TO POINT AT CURRENT REV INSTRUCTION
OTHER
READ BYTE @ 0,X (RULE ELEMENT Rx)
X = X + 1 POINT AT NEXT RULE ELEMENT
6.2 - f
NO BUS ACCESS
ADJUST X = X – 1
CONTINUE TO INTERRUPT STACKING
1 (MAX)
V-BIT
0 (MIN)
6.0 - x
NO BUS ACCESS
UPDATE Fy WITH VALUE READ IN CYC 4.0
IF Rx $FE THEN A = MIN(A, Fy)
ELSE A = A (NO CHANGE TO A)
NO
6.1 - x
UPDATE FY WITH VALUE READ IN CYC 4.0
IF Rx $FE OR $FF, AND ACCA > Fy
THEN WRITE BYTE @ Rx,Y
ELSE NO BUS ACCESS
Rx = $FF (END OF RULES)?
YES
7.0 - O
READ PROGRAM WORD IF $3A MISALIGNED
END
Figure 9-9. REV Instruction Flow Diagram
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Since there is more than one flow path through the REV instruction, cycle
numbers have a decimal place. This decimal place indicates which of
several possible paths is being used. The CPU normally moves forward by
one digit at a time within the same flow (flow number is indicated after the
decimal point in the cycle number). There are two exceptions possible to this
orderly sequence through an instruction. The first is a branch back to an
earlier cycle number to form a loop as in 6.0 to 4.0. The second type of
sequence change is from one flow to a parallel flow within the same
instruction such as 4.0 to 5.2, which occurs if the REV instruction senses an
interrupt. In this second type of sequence branch, the whole number
advances by one and the flow number changes to a new value (the digit
after the decimal point).
In cycle 1.0, the CPU12 does an optional program word access to replace
the $18 prebyte of the REV instruction. Notice that cycle 7.0 is also an O
type cycle. One or the other of these will be a program word fetch, while the
other will be a free cycle where the CPU does not access the bus. Although
the $18 page prebyte is a required part of the REV instruction, it is treated
by the CPU12 as a somewhat separate single cycle instruction.
Rule evaluation begins at cycle 2.0 with a byte read of the first element in
the rule list. Usually this would be the first antecedent of the first rule, but the
REV instruction can be interrupted, so this could be a read of any byte in the
rule list. The X index register is incremented so it points to the next element
in the rule list. Cycle 3.0 is needed to satisfy the required delay between a
read and when data is valid to the CPU. Some internal CPU housekeeping
activity takes place during this cycle, but there is no bus activity. By cycle
4.0, the rule element that was read in cycle 2.0 is available to the CPU.
Cycle 4.0 is the first cycle of the main three cycle rule evaluation loop.
Depending upon whether rule antecedents or consequents are being
processed, the loop will consist of cycles 4.0, 5.0, 6.0, or the sequence 4.0,
5.0, 6.1. This loop is executed once for every byte in the rule list, including
the $FE separators and the $FF end-of-rules marker.
At each cycle 4.0, a fuzzy input or fuzzy output is read, except during the
loop passes associated with the $FE and $FF marker bytes, where no bus
access takes place during cycle 4.0. The read access uses the Y index
register as the base address and the previously read rule byte (Rx) as an
unsigned offset from Y. The fuzzy input or output value read here will be
used during the next cycle 6.0 or 6.1. Besides being used as the offset from
Y for this read, the previously read Rx is checked to see if it is a separator
character ($FE). If Rx was $FE and the V bit was one, this indicates a switch
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from processing consequents of one rule to starting to process antecedents
of the next rule. At this transition, the A accumulator is initialized to $FF to
prepare for the min operation to find the smallest fuzzy input. Also, if Rx is
$FE, the V bit is toggled to indicate the change from antecedents to
consequents, or consequents to antecedents.
During cycle 5.0, a new rule byte is read unless this is the last loop pass,
and Rx is $FF (marking the end of the rule list). This new rule byte will not
be used until cycle 4.0 of the next pass through the loop.
Between cycle 5.0 and 6.x, the V-bit is used to decide which of two paths to
take. If V is zero, antecedents are being processed and the CPU progresses
to cycle 6.0. If V is one, consequents are being processed and the CPU
goes to cycle 6.1.
During cycle 6.0, the current value in the A accumulator is compared to the
fuzzy input that was read in the previous cycle 4.0, and the lower value is
placed in the A accumulator (min operation). If Rx is $FE, this is the
transition between rule antecedents and rule consequents, and this min
operation is skipped (although the cycle is still used). No bus access takes
place during cycle 6.0 but cycle 6.x is considered an x type cycle because it
could be a byte write (cycle 6.1) or a free cycle (cycle 6.0 or 6.1 with Rx =
$FE or $FF).
If an interrupt arrives while the REV instruction is executing, REV can break
between cycles 4.0 and 5.0 in an orderly fashion so that the rule evaluation
operation can resume after the interrupt has been serviced. Cycles 5.2 and
6.2 are needed to adjust the PC and X index register so the REV operation
can recover after the interrupt. PC is adjusted backward in cycle 5.2 so it
points to the currently running REV instruction. After the interrupt, rule
evaluation will resume, but the values that were stored on the stack for index
registers, accumulator A, and CCR will cause the operation to pick up where
it left off. In cycle 6.2, the X index register is adjusted backward by one
because the last rule byte needs to be re-fetched when the REV instruction
resumes.
After cycle 6.2, the REV instruction is finished, and execution would
continue to the normal interrupt processing flow.
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9.5.2 Weighted Rule Evaluation (REVW)
This instruction implements a weighted variation of min-max rule evaluation.
The weighting factors are stored in a table with one 8-bit entry per rule. The
weight is used to multiply the truth value of the rule (minimum of all
antecedents) by a value from zero to one to get the weighted result. This
weighted result is then applied to the consequents, just as it would be for
unweighted rule evaluation.
Since the REVW instruction is essentially a list-processing instruction,
execution time is dependent on the number of rules and the number of
elements in the rule list. The REVW instruction is interruptible (typically
within three to five bus cycles), so it does not adversely affect worst case
interrupt latency. Since all intermediate results and instruction status are
held in stacked CPU registers, the interrupt service code can even include
independent REV and REVW instructions.
The rule structure is different for REVW than for REV. For REVW, the rule
list is made up of 16-bit elements rather than 8-bit elements. Each
antecedent is represented by the full 16-bit address of the corresponding
fuzzy input. Each rule consequent is represented by the full address of the
corresponding fuzzy output.
The markers separating antecedents from consequents are the reserved
16-bit value $FFFE, and the end of the last rule is marked by the reserved
16-bit value $FFFF. Since $FFFE and $FFFF correspond to the addresses
of the reset vector, there would never be a fuzzy input or output at either of
these locations.
9.5.2.1 Set Up Prior to Executing REVW
Some CPU registers and memory locations need to be set up prior to
executing the REVW instruction. X and Y index registers are used as index
pointers to the rule list and the list of rule weights. The A accumulator is used
for intermediate calculation results and needs to be set to $FF initially. The
V condition code bit is used as an instruction status indicator that shows
whether antecedents or consequents are being processed. Initially the V bit
is cleared to zero to indicate antecedents are being processed. The C
condition code bit is used to indicate whether rule weights are to be used (1)
or not (0). The fuzzy outputs (working RAM locations) need to be cleared to
$00. If these values are not initialized before executing the REVW
instruction, results will be erroneous.
The X index register is set to the address of the first element in the rule list
(in the knowledge base). The REVW instruction automatically updates this
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pointer so that the instruction can resume correctly if it is interrupted. After
the REVW instruction finishes, X will point at the next address past the
$FFFF separator word that marks the end of the rule list.
The Y index register is set to the starting address of the list of rule weights.
Each rule weight is an 8-bit value. The weighted result is the truncated upper
eight bits of the 16-bit result, which is derived by multiplying the minimum
rule antecedent value ($00–$FF) by the weight plus one ($001–$100). This
method of weighting rules allows an 8-bit weighting factor to represent a
value between zero and one inclusive.
The 8-bit A accumulator is used to hold intermediate calculation results
during execution of the REVW instruction. During antecedent processing, A
starts out at $FF and is replaced by any smaller fuzzy input that is
referenced by a rule antecedent. If rule weights are enabled by the C
condition code bit equal one, the rule truth value is multiplied by the rule
weight just before consequent processing starts. During consequent
processing, A holds the truth value (possibly weighted) for the rule. This
truth value is stored to any fuzzy output that is referenced by a rule
consequent, unless that fuzzy output is already larger (MAX).
Before starting to execute REVW, A must be set to $FF (the largest 8-bit
value) because rule evaluation always starts with processing of the
antecedents of the first rule. For subsequent rules in the list, A is
automatically set to $FF when the instruction detects the $FFFE marker
word between the last consequent of the previous rule, and the first
antecedent of a new rule.
Both the C and V condition code bits must be set up prior to starting a REVW
instruction. Once the REVW instruction starts, the C bit remains constant
and the value in the V bit is automatically maintained as $FFFE separator
words are detected.
The final requirement to clear all fuzzy outputs to $00 is part of the MAX
algorithm. Each time a rule consequent references a fuzzy output, that fuzzy
output is compared to the truth value (weighted) for the current rule. If the
current truth value is larger, it is written over the previous value in the fuzzy
output. After all rules have been evaluated, the fuzzy output contains the
truth value for the most-true rule that referenced that fuzzy output.
After REVW finishes, A will hold the truth value (weighted) for the last rule
in the rule list. The V condition code bit should be one because the last
element before the $FFFF end marker should have been a rule consequent.
If V is zero after executing REVW, it indicates the rule list was structured
incorrectly.
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9.5.2.2 Interrupt Details
The REVW instruction includes a 3-cycle processing loop for each word in
the rule list (this loop expands to five cycles between antecedents and
consequents to allow time for the multiplication with the rule weight). Within
this loop, a check is performed to see if any qualified interrupt request is
pending. If an interrupt is detected, the current CPU registers are stacked
and the interrupt is honored. When the interrupt service routine finishes, an
RTI instruction causes the CPU to recover its previous context from the
stack, and the REVW instruction is resumed as if it had not been interrupted.
The stacked value of the program counter (PC), in case of an interrupted
REVW instruction, points to the REVW instruction rather than the instruction
that follows. This causes the CPU to try to execute a new REVW instruction
upon return from the interrupt. Since the CPU registers (including the C bit
and V bit in the condition codes register) indicate the current status of the
interrupted REVW instruction, this effectively causes the rule evaluation
operation to resume from where it left off.
9.5.2.3 Cycle-by-Cycle Details for REVW
The central element of the REVW instruction is a 3-cycle loop that is
executed once for each word in the rule list. For the special case pass
(where the $FFFE separator word is read between the rule antecedents and
the rule consequents, and weights are enabled by the C bit equal one), this
loop takes five cycles. There is a small amount of housekeeping activity to
get this loop started as REVW begins and a small sequence to end the
instruction. If an interrupt comes, there is a special small sequence to save
CPU status on the stack before the interrupt is serviced.
Figure 9-10 is a detailed flow diagram for the REVW instruction. Each
rectangular box represents one CPU clock cycle. Decision blocks and
connecting arrows are considered to take no time at all. The letters in the
small rectangles in the upper left corner of each bold box correspond to the
execution cycle codes (refer to Section 6. Instruction Glossary for
details). Lower case letters indicate a cycle where 8-bit or no data is
transferred. Upper case letters indicate cycles where 16-bit data could be
transferred.
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START
1.0 - O
READ PROGRAM WORD IF $18 MISALIGNED
2.0 - R
READ WORD @ 0,X (RULE ELEMENT Rx)
X = X + 2 POINT AT NEXT RULE ELEMENT
3.0 - f
NO BUS ACCESS
TMP2 = Y – 1 (WEIGHT POINTER KEPT IN TMP2)
UPDATE Rx WITH VALUE READ IN CYC 2 OR 5
4.0 - t
IF Rx = $FFFF
THEN NO BUS ACCESS
IF Rx = $FFFE
IF V = 0, THEN TMP2 = TMP2 + 1
IF V = 0 AND C = 1,
THEN READ RULE WEIGHT @,TMP2
ELSE NO BUS ACCESS
IF Rx = OTHER
THEN READ BYTE @,Rx FUZZY IN/OUT FRx
TOGGLE V BIT; IF V NOW 0, A = $FF
NO
5.0 - T
INTERRUPT PENDING?
IF Rx $FFFF
THEN READ RULE WORD @,X0
5.3 - f
6.3 - f
MIN
OR DEFAULT
MIN/MAX/MUL?
NO BUS ACCESS
ADJUST PC TO POINT AT CURRENT REVW INSTRUCTION
X0 = X, X = X0 + 2
MUL
V=C=1 and Rx=$FFFE
MAX
V = 1 & RX $FFFE or $FFFF
6.1 - x
YES
IF A > FRx WRITE A TO Rx
ELSE NO BUS ACCESS
NO BUS ACCESS
ADJUST X = X – 2 POINTER TO RULE LIST
7.3 - f
NO BUS ACCESS
IF (Rx = $FFFE OR $FFFE) AND V = 0
THEN TMP2 = TMP2 – 1
8.3 - f
NO BUS ACCESS
Y = TMP2 + 1
6.0 - x
NO BUS ACCESS
CONTINUE TO INTERRUPT STACKING
A = MIN(A, FRx)
6.2 - f
NO
Rx = $FFFF (END OF RULES)?
YES
7.0 - O
BEGIN MULTIPLY OF (wt + 1) * A fi A : B
7.2 - R
READ PROGRAM WORD IF $3B MISALIGNED
ADJUST PC TO POINT AT NEXT INSTRUCTION
IF C = 1 (WEIGHTS ENABLED), Y = TMP2 + 1
NO BUS ACCESS
READ RULE WORD @,X0
CONTINUE MULTIPLY
8.2 - f
NO BUS ACCESS
FINISH MULTIPLY
END
Figure 9-10. REVW Instruction Flow Diagram
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In cycle 2.0, the first element of the rule list (a 16-bit address) is read from
memory. Due to propagation delays, this value cannot be used for
calculations until two cycles later (cycle 4.0). The X index register, which is
used to access information from the rule list, is incremented by two to point
at the next element of the rule list.
The operations performed in cycle 4.0 depend on the value of the word read
from the rule list. $FFFE is a special token that indicates a transition from
antecedents to consequents or from consequents to antecedents of a new
rule. The V bit can be used to decide which transition is taking place, and V
is toggled each time the $FFFE token is detected. If V was zero, a change
from antecedents to consequents is taking place, and it is time to apply
weighting (provided it is enabled by the C bit equal one). The address in
TMP2 (derived from Y) is used to read the weight byte from memory. In this
case, there is no bus access in cycle 5.0, but the index into the rule list is
updated to point to the next rule element.
The old value of X (X0) is temporarily held on internal nodes, so it can be
used to access a rule word in cycle 7.2. The read of the rule word is timed
to start two cycles before it will be used in cycle 4.0 of the next loop pass.
The actual multiply takes place in cycles 6.2 through 8.2. The 8-bit weight
from memory is incremented (possibly overflowing to $100) before the
multiply, and the upper eight bits of the 16-bit internal result is used as the
weighted result. By using weight+1, the result can range from 0.0 times A to
1.0 times A. After 8.2, flow continues to the next loop pass at cycle 4.0.
At cycle 4.0, if Rx is $FFFE and V was one, a change from consequents to
antecedents of a new rule is taking place, so accumulator A must be
reinitialized to $FF. During processing of rule antecedents, A is updated with
the smaller of A, or the current fuzzy input (cycle 6.0). Cycle 5.0 is usually
used to read the next rule word and update the pointer in X. This read is
skipped if the current Rx is $FFFF (end of rules mark). If this is a weight
multiply pass, the read is delayed until cycle 7.2. During processing of
consequents, cycle 6.1 is used to optionally update a fuzzy output if the
value in accumulator A is larger.
After all rules have been processed, cycle 7.0 is used to update the PC to
point at the next instruction. If weights were enabled, Y is updated to point
at the location that immediately follows the last rule weight.
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9.6 WAV Instruction Details
The WAV instruction performs weighted average calculations used in
defuzzification. The pseudo-instruction wavr is used to resume an
interrupted weighted average operation. WAV calculates the numerator and
denominator sums using:
n
∑ Si Fi
i=1
System Output = ----------------------n
Fi
∑
i=1
Where n is the number of labels of a system output, Si are the singleton
positions from the knowledge base, and Fi are fuzzy outputs from RAM. Si
and Fi are 8-bit values. The 8-bit B accumulator holds the iteration count n.
Internal temporary registers hold intermediate sums, 24 bits for the
numerator and 16 bits for the denominator. This makes this instruction
suitable for n values up to 255 although eight is a more typical value. The
final long division is performed with a separate EDIV instruction immediately
after the WAV instruction. The WAV instruction returns the numerator and
denominator sums in the correct registers for the EDIV. (EDIV performs the
unsigned division Y = Y : D / X; remainder in D.)
Execution time for this instruction depends on the number of iterations
(labels for the system output). WAV is interruptible so that worst case
interrupt latency is not affected by the execution time for the complete
weighted average operation. WAV includes initialization for the 24-bit and
16-bit partial sums so the first entry into WAV looks different than a resume
from interrupt operation. The CPU12 handles this difficulty with a
pseudo-instruction (wavr), which is specifically intended to resume an
interrupted weighted average calculation. Refer to 9.6.3 Cycle-by-Cycle
Details for WAV and wavr for more detail.
9.6.1 Set Up Prior to Executing WAV
Before executing the WAV instruction, index registers X and Y and
accumulator B must be set up. Index register X is a pointer to the Si
singleton list. X must have the address of the first singleton value in the
knowledge base. Index register Y is a pointer to the fuzzy outputs Fi. Y must
have the address of the first fuzzy output for this system output. B is the
iteration count n. The B accumulator must be set to the number of labels for
this system output.
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9.6.2 WAV Interrupt Details
The WAV instruction includes a 7-cycle processing loop for each label of the
system output (8 cycles in M68HC12). Within this loop, the CPU checks
whether a qualified interrupt request is pending. If an interrupt is detected,
the current values of the internal temporary registers for the 24-bit and 16-bit
sums are stacked, the CPU registers are stacked, and the interrupt is
serviced.
A special processing sequence is executed when an interrupt is detected
during a weighted average calculation. This exit sequence adjusts the PC
so that it points to the second byte of the WAV object code ($3C), before the
PC is stacked. Upon return from the interrupt, the $3C value is interpreted
as a wavr pseudo-instruction. The wavr pseudo-instruction causes the CPU
to execute a special WAV resumption sequence. The wavr recovery
sequence adjusts the PC so that it looks like it did during execution of the
original WAV instruction, then jumps back into the WAV processing loop. If
another interrupt occurs before the weighted average calculation finishes,
the PC is adjusted again as it was for the first interrupt. WAV can be
interrupted any number of times, and additional WAV instructions can be
executed while a WAV instruction is interrupted.
9.6.3 Cycle-by-Cycle Details for WAV and wavr
The WAV instruction is unusual in that the logic flow has two separate entry
points. The first entry point is the normal start of a WAV instruction. The
second entry point is used to resume the weighted average operation after
a WAV instruction has been interrupted. This recovery operation is called
the wavr pseudo-instruction.
Figure 9-12 is a flow diagram of the WAV instruction in the HCS12,
including the wavr pseudo-instruction. Figure 9-12 is a flow diagram of the
WAV instruction in the M68HC12, including the wavr pseudo-instruction.
Each rectangular box in these figures represents one CPU clock cycle.
Decision blocks and connecting arrows are considered to take no time at all.
The letters in the small rectangles in the upper left corner of the boxes
correspond to execution cycle codes (refer to Section 6. Instruction
Glossary for details). Lower case letters indicate a cycle where 8-bit or no
data is transferred. Upper case letters indicate cycles where 16-bit data
could be transferred.
The cycle-by-cycle description provided here refers to the HCS12 flow in
Figure 9-11. In terms of cycle-by-cycle bus activity, the $18 page select
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prebyte is treated as a special 1-byte instruction. In cycle 1.0 of the WAV
instruction, one word of program information will be fetched into the
instruction queue if the $18 is located at an odd address. If the $18 is at an
even address, the instruction queue cannot advance so there is no bus
access in this cycle.
wavr
WAV
1.0 - O
2.0 - f
READ PROGRAM WORD IF $18 MISALIGNED
NO BUS ACCESS
TMP1 = TMP2 = TMP3 = $0000
3.0 - f
1.1 - U
READ WORD @ 0,SP (UNSTACK TMP1)
SP = SP + 2
2.1 - U
READ WORD @ 0,SP (UNSTACK TMP2)
SP = SP + 2
NO BUS ACCESS
B = B – 1 DECREMENT ITERATION COUNTER
3.1 - U
READ WORD @ 0,SP (UNSTACK TMP3)
SP = SP + 2
4.0 - f
READ BYTE @ 0,Y (FUZZY OUTPUT Fi)
4.1 - r
READ BYTE @ –1,Y (FUZZY OUTPUT Fi)
5.1 - r
READ BYTE @ –1,X (SINGLETON Si)
6.1 - S
WRITE WORD @ –2,SP (STACK TMP3)
Y = Y + 1 point at next fuzzy output
5.0 - r
READ BYTE @ 0,X (SINGLETON Si)
X = X + 1 POINT AT NEXT SINGLETON
YES
INTERRUPT PENDING?
NO
6.0 - f
NO BUS ACCESS
TMP3 = TMP3 + Fi
7.0 - f
SP = SP – 2
7.1 - S
NO BUS ACCESS
START MULTIPLY, PPROD = Si*Fi
8.0 - f
8.1 - S
NO BUS ACCESS
FINISH MULTIPLY, TMP2 = TMP2 + PPROD
9.0 - f
WRITE WORD @ –2,SP (STACK TMP2)
SP = SP – 2
WRITE WORD @ –2,SP (STACK TMP1)
SP = SP – 2
ADJUST PC TO POINT AT $3C wavr PSEUDO-OPCODE
NO BUS ACCESS
TMP1 = TMP1 + (CARRY FROM PPROD ADD)
CONTINUE TO INTERRUPT STACKING
NO
B = 0?
YES
10.0 - O
READ PROGRAM WORD IF $3C MISALIGNED
ADJUST PC TO POINT AT NEXT INSTRUCTION
Y : D = TMP1 : TMP2; X = TMP3
END
Figure 9-11. WAV and wavr Instruction Flow Diagram (for HCS12)
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WAV
wavr
1.0 - O
READ PROGRAM WORD IF $18 MISALIGNED
2.0 - f
NO BUS ACCESS
3.0 - f
NO BUS ACCESS
2.1 - U
READ WORD @ 0,SP (UNSTACK TMP3)
SP = SP + 2
TMP1 = TMP2 = TMP3 = $0000
3.1 - U
READ WORD @ 0,SP (UNSTACK TMP2)
SP = SP + 2
4.0 - f
4.1 - U
NO BUS ACCESS
B = B – 1 DECREMENT ITERATION COUNTER
5.0 - r
READ WORD @ 0,SP (UNSTACK TMP1)
SP = SP + 2
READ BYTE @ 0,Y (FUZZY OUTPUT Fi)
5.1 - r
READ BYTE @ –1,Y (FUZZY OUTPUT Fi)
6.1 - r
READ BYTE @ –1,X (SINGLETON Si)
7.1 - S
WRITE WORD @ –2,SP (STACK TMP1)
Y = Y + 1 point at next fuzzy output
6.0 - r
READ BYTE @ 0,X (SINGLETON Si)
X = X + 1 POINT AT NEXT SINGLETON
YES
INTERRUPT PENDING?
NO
7.0 - f
NO BUS ACCESS
TMP1 = TMP1 + Fi
8.0 - f
SP = SP – 2
8.1 - S
NO BUS ACCESS
START MULTIPLY PPROD = Si*Fi
9.0 - f
SP = SP – 2
9.1 - S
NO BUS ACCESS
CONTINUE MULTIPLY
10.0 - f
WRITE WORD @ –2,SP (STACK TMP3)
SP = SP – 2
ADJUST PC TO POINT AT $3C wavr PSEUDO-OPCODE
NO BUS ACCESS
FINISH MULTIPLY, TMP2 = TMP2 + PPROD
11.0 - f
WRITE WORD @ –2,SP (STACK TMP2)
10.1 - f
NO BUS ACCESS
NO BUS ACCESS
TMP3 = TMP3 + (CARRY FROM PPROD ADD)
NO
CONTINUE TO INTERRUPT STACKING
B = 0?
YES
12.0 - O
READ PROGRAM WORD IF $3C MISALIGNED
ADJUST PC TO POINT AT NEXT INSTRUCTION
Y : D = TMP3 : TMP2; X = TMP1
END
Figure 9-12. WAV and wavr Instruction Flow Diagram (for M68HC12)
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In cycle 2.0, three internal 16-bit temporary registers are cleared in
preparation for summation operations, but there is no bus access. The WAV
instruction maintains a 32-bit sum-of-products in TMP1 : TMP2 and a 16-bit
sum-of-weights in TMP3. By keeping these sums inside the CPU, bus
accesses are reduced and the WAV operation is optimized for high speed.
Cycles 3.0 through 9.0 form the 7-cycle main loop for WAV. The value in the
8-bit B accumulator is used to count the number of loop iterations. B is
decremented at the top of the loop in cycle 3.0, and the test for zero is
located at the bottom of the loop after cycle 9.0. Cycle 4.0 and 5.0 are used
to fetch the 8-bit operands for one iteration of the loop. X and Y index
registers are used to access these operands. The index registers are
incremented as the operands are fetched. Cycle 6.0 is used to accumulate
the current fuzzy output into TMP3. Cycles 7.0 through 9.0 are used to
perform the eight by eight multiply of Fi times Si, and accumulate this result
into TMP1 : TMP2. Even though the sum-of-products will not exceed 24 bits,
the sum is maintained in the 32-bit combined TMP1 : TMP2 register
because it is easier to use existing 16-bit operations than it would be to
create a new smaller operation to handle the high order bits of this sum.
Since the weighted average operation could be quite long, it is made to be
interruptible. The usual longest latency path is from very early in cycle 6.0,
through cycle 9.0, to the top of the loop to cycle 3.0, through cycle 5.0 to the
interrupt check.
If the WAV instruction is interrupted, the internal temporary registers TMP3,
TMP2, and TMP1 need to be stored on the stack so the operation can be
resumed. Since the WAV instruction included initialization in cycle 2.0, the
recovery path after an interrupt needs to be different. The wavr
pseudo-instruction has the same opcode as WAV, but it is on the first page
of the opcode map so there is no page prebyte ($18) like there is for WAV.
When WAV is interrupted, the PC is adjusted to point at the second byte of
the WAV object code, so that it will be interpreted as the wavr
pseudo-instruction on return from the interrupt, rather than the WAV
instruction. During the recovery sequence, the PC is readjusted in case
another interrupt comes before the weighted average operation finishes.
The resume sequence includes recovery of the temporary registers from the
stack (1.1 through 3.1), and reads to get the operands for the current
iteration. The normal WAV flow is then rejoined at cycle 6.0.
Upon normal completion of the instruction (cycle 10.0), the PC is adjusted
so it points to the next instruction. The results are transferred from the TMP
registers into CPU registers in such a way that the EDIV instruction can be
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used to divide the sum-of-products by the sum-of-weights. TMP1 : TMP2 is
transferred into Y : D and TMP3 is transferred into X.
9.7 Custom Fuzzy Logic Programming
The basic fuzzy logic inference techniques described earlier are suitable for
a broad range of applications, but some systems may require
customization. The built-in fuzzy instructions use 8-bit resolution and some
systems may require finer resolution. The rule evaluation instructions only
support variations of MIN-MAX rule evaluation and other methods have
been discussed in fuzzy logic literature. The weighted average of singletons
is not the only defuzzification technique. The CPU12 has several
instructions and addressing modes that can be helpful when developing
custom fuzzy logic systems.
9.7.1 Fuzzification Variations
The MEM instruction supports trapezoidal membership functions and
several other varieties, including membership functions with vertical sides
(infinite slope sides). Triangular membership functions are a subset of
trapezoidal functions. Some practitioners refer to s-, z-, and π-shaped
membership functions. These refer to a trapezoid butted against the right
end of the x-axis, a trapezoid butted against the left end of the x-axis, and a
trapezoidal membership function that isn’t butted against either end of the
x-axis, respectively. Many other membership function shapes are possible,
if memory space and processing bandwidth are sufficient.
Tabular membership functions offer complete flexibility in shape and very
fast evaluation time. However, tables take a very large amount of memory
space (as many as 256 bytes per label of one system input). The excessive
size to specify tabular membership functions makes them impractical for
most microcontroller-based fuzzy systems. The CPU12 instruction set
includes two instructions (TBL and ETBL) for lookup and interpolation of
compressed tables.
The TBL instruction uses 8-bit table entries (y-values) and returns an 8-bit
result. The ETBL instruction uses 16-bit table entries (y-values) and returns
a 16-bit result. A flexible indexed addressing mode is used to identify the
effective address of the data point at the beginning of the line segment, and
the data value for the end point of the line segment is the next consecutive
memory location (byte for TBL and word for ETBL). In both cases, the B
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accumulator represents the ratio of (the x-distance from the beginning of the
line segment to the lookup point) to (the x-distance from the beginning of the
line segment to the end of the line segment). B is treated as an 8-bit binary
fraction with radix point left of the MSB, so each line segment can effectively
be divided into 256 pieces. During execution of the TBL or ETBL instruction,
the difference between the end point y-value and the beginning point
y-value (a signed byte-TBL or word-ETBL) is multiplied by the B
accumulator to get an intermediate delta-y term. The result is the y-value of
the beginning point, plus this signed intermediate delta-y value.
Because indexed addressing mode is used to identify the starting point of
the line segment of interest, there is a great deal of flexibility in constructing
tables. A common method is to break the x-axis range into 256 equal width
segments and store the y value for each of the resulting 257 endpoints. The
16-bit D accumulator is then used as the x input to the table. The upper eight
bits (A) is used as a coarse lookup to find the line segment of interest, and
the lower eight bits (B) is used to interpolate within this line segment.
In the program sequence
LDX
#TBL_START
LDD
DATA_IN
TBL
A,X
The notation A,X causes the TBL instruction to use the Ath line segment in
the table. The low-order half of D (B) is used by TBL to calculate the exact
data value from this line segment. This type of table uses only 257 entries
to approximate a table with 16 bits of resolution. This type of table has the
disadvantage of equal width line segments, which means just as many
points are needed to describe a flat portion of the desired function as are
needed for the most active portions.
Another type of table stores x:y coordinate pairs for the endpoints of each
linear segment. This type of table may reduce the table storage space
compared to the previous fixed-width segments because flat areas of the
functions can be specified with a single pair of endpoints. This type of table
is a little harder to use with the CPU12 TBL and ETBL instructions because
the table instructions expect y-values for segment endpoints to be in
consecutive memory locations.
Consider a table made up of an arbitrary number of x:y coordinate pairs,
where all values are eight bits. The table is entered with the x-coordinate of
the desired point to lookup in the A accumulator. When the table is exited,
the corresponding y-value is in the A accumulator. Figure 9-13 shows one
way to work with this type of table.
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BEGIN
FIND_LOOP
LDY
CMPA
#TABLE_START-2
2,+Y
;setup initial table pointer
;find first Xn > XL
;(auto pre-inc Y by 2)
BLS
FIND_LOOP
;loop if XL .le. Xn
* on fall thru, XB@-2,Y YB@-1,Y XE@0,Y and YE@1,Y
TFR
D,X
;save XL in high half of X
CLRA
;zero upper half of D
LDAB
0,Y
;D = 0:XE
SUBB
-2,Y
;D = 0:(XE-XB)
EXG
D,X
;X = (XE-XB).. D = XL:junk
SUBA
-2,Y
;A = (XL-XB)
EXG
A,D
;D = 0:(XL-XB), uses trick of EXG
FDIV
;X reg = (XL-XB)/(XE-XB)
EXG
D,X
;move fractional result to A:B
EXG
A,B
;byte swap - need result in B
TSTA
;check for rounding
BPL
NO_ROUND
INCB
;round B up by 1
NO_ROUND
LDAA
1,Y
;YE
PSHA
;put on stack for TBL later
LDAA
-1,Y
;YB
PSHA
;now YB@0,SP and YE@1,SP
TBL
2,SP+
;interpolate and deallocate
;stack temps
Figure 9-13. Endpoint Table Handling
The basic idea is to find the segment of interest, temporarily build a
1-segment table of the correct format on the stack, then use TBL with stack
relative indexed addressing to interpolate. The most difficult part of the
routine is calculating the proportional distance from the beginning of the
segment to the lookup point versus the width of the segment
((XL–XB)/(XE–XB)). With this type of table, this calculation must be done at
run time. In the previous type of table, this proportional term is an inherent
part (the lowest order bits) of the data input to the table.
Some fuzzy theorists have suggested membership functions should be
shaped like normal distribution curves or other mathematical functions. This
may be correct, but the processing requirements to solve for an intercept on
such a function would be unacceptable for most microcontroller-based fuzzy
systems. Such a function could be encoded into a table of one of the
previously described types.
For many common systems, the thing that is most important about
membership function shape is that there is a gradual transition from
non-membership to membership as the system input value approaches the
central range of the membership function.
Examine the human problem of stopping a car at an intersection. Rules such
as “If intersection is close and speed is fast, apply brakes” might be used.
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The meaning (reflected in membership function shape and position) of the
labels “close” and “fast” will be different for a teenager than they are for a
grandmother, but both can accomplish the goal of stopping. It makes
intuitive sense that the exact shape of a membership function is much less
important than the fact that it has gradual boundaries.
9.7.2 Rule Evaluation Variations
The REV and REVW instructions expect fuzzy input and fuzzy output values
to be 8-bit values. In a custom fuzzy inference program, higher resolution
may be desirable (although this is not a common requirement). The CPU12
includes variations of minimum and maximum operations that work with the
fuzzy MIN-MAX inference algorithm. The problem with the fuzzy inference
algorithm is that the min and max operations need to store their results
differently, so the min and max instructions must work differently or more
than one variation of these instructions is needed.
The CPU12 has MIN and MAX instructions for 8- or 16-bit operands, where
one operand is in an accumulator and the other is a referenced memory
location. There are separate variations that replace the accumulator or the
memory location with the result. While processing rule antecedents in a
fuzzy inference program, a reference value must be compared to each of
the referenced fuzzy inputs, and the smallest input must end up in an
accumulator. The instruction
EMIND
2,X+
;process one rule antecedent
automates the central operations needed to process rule antecedents. The
E stands for extended, so this instruction compares 16-bit operands. The D
at the end of the mnemonic stands for the D accumulator, which is both the
first operand for the comparison and the destination of the result. The 2,X+
is an indexed addressing specification that says X points to the second
operand for the comparison and it will be post-incremented by 2 to point at
the next rule antecedent.
When processing rule consequents, the operand in the accumulator must
remain constant (in case there is more than one consequent in the rule), and
the result of the comparison must replace the referenced fuzzy output in
RAM. To do this, use the instruction
EMAXM
2,X+
;process one rule consequent
The M at the end of the mnemonic indicates that the result will replace the
referenced memory operand. Again, indexed addressing is used. These two
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instructions would form the working part of a 16-bit resolution fuzzy
inference routine.
There are many other methods of performing inference, but none of these
are as widely used as the min-max method. Since the CPU12 is a
general-purpose microcontroller, the programmer has complete freedom to
program any algorithm desired. A custom programmed algorithm would
typically take more code space and execution time than a routine that used
the built-in REV or REVW instructions.
9.7.3 Defuzzification Variations
Other CPU12 instructions can help with custom defuzzification routines in
two main areas:
•
The first case is working with operands that are more than eight bits.
•
The second case involves using an entirely different approach than
weighted average of singletons.
The primary part of the WAV instruction is a multiply and accumulate
operation to get the numerator for the weighted average calculation. When
working with operands as large as 16 bits, the EMACS instruction could at
least be used to automate the multiply and accumulate function. The CPU12
has extended math capabilities, including the EMACS instruction which
uses 16-bit input operands and accumulates the sum to a 32-bit memory
location and 32-bit by 16-bit divide instructions.
One benefit of the WAV instruction is that both a sum of products and a sum
of weights are maintained, while the fuzzy output operand is only accessed
from memory once. Since memory access time is such a significant part of
execution time, this provides a speed advantage compared to conventional
instructions.
The weighted average of singletons is the most commonly used technique
in microcontrollers because it is computationally less difficult than most
other methods. The simplest method is called max defuzzification, which
simply uses the largest fuzzy output as the system result. However, this
approach does not take into account any other fuzzy outputs, even when
they are almost as true as the chosen max output. Max defuzzification is not
a good general choice because it only works for a subset of fuzzy logic
applications.
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373
The CPU12 is well suited for more computationally challenging algorithms
than weighted average. A 32-bit by 16-bit divide instruction takes 11 or 12
25-MHz cycles for unsigned or signed variations. A 16-bit by 16-bit multiply
with a 32-bit result takes only three 25-MHz cycles. The EMACS instruction
uses 16-bit operands and accumulates the result in a 32-bit memory
location, taking only 12 25-MHz cycles per iteration, including accessing all
operands from memory and storing the result to memory.
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Reference Manual — S12CPUV2
Appendix A. Instruction Reference
A.1 Introduction
This appendix provides quick references for the instruction set, opcode
map, and encoding.
A
0 7
B
15
D
0
8-BIT ACCUMULATORS A AND B
OR
16-BIT DOUBLE ACCUMULATOR D
15
X
0
INDEX REGISTER X
15
Y
0
INDEX REGISTER Y
15
SP
0
STACK POINTER
15
PC
0
PROGRAM COUNTER
7
S X H I N Z V C
0
CONDITION CODE REGISTER
CARRY
OVERFLOW
ZERO
NEGATIVE
MASK (DISABLE) IRQ INTERRUPTS
HALF-CARRY
(USED IN BCD ARITHMETIC)
MASK (DISABLE) XIRQ INTERRUPTS
RESET OR XIRQ SET X,
INSTRUCTIONS MAY CLEAR X
BUT CANNOT SET X
STOP DISABLE (IGNORE STOP OPCODES)
RESET DEFAULT IS 1
Figure A-1. Programming Model
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375
A.2 Stack and Memory Layout
SP BEFORE
INTERRUPT
SP +9
HIGHER ADDRESSES
RTNLO
RTNHI
YLO
YHI
XLO
XHI
A
B
SP AFTER
INTERRUPT
CCR
LOWER ADDRESSES
STACK UPON ENTRY TO SERVICE ROUTINE
IF SP WAS ODD BEFORE INTERRUPT
STACK UPON ENTRY TO SERVICE ROUTINE
IF SP WAS EVEN BEFORE INTERRUPT
SP +8
RTNLO
SP +9
SP +9
SP +6
YLO
RTNHI
SP +7
SP +7
RTNHI
RTNLO
SP +8
SP +4
XLO
YHI
SP +5
SP +5
YHI
YLO
SP +6
SP +2
A
XHI
SP +3
SP +4
XHI
XLO
SP +4
SP
CCR
B
SP +1
SP +1
B
A
SP +2
SP –1
SP –1
CCR
SP
SP –2
SP +10
A.3 Interrupt Vector Locations
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFC0–$FFF1 (M68HC12)
$FF00–$FFF1 (HCS12)
Power-On (POR) or External Reset
Clock Monitor Reset
Computer Operating Properly (COP Watchdog Reset
Unimplemented Opcode Trap
Software Interrupt Instruction (SWI)
XIRQ
IRQ
Device-Specific Interrupt Sources
Device-Specific Interrupt Sources
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A.4 Notation Used in Instruction Set Summary
CPU Register Notation
Accumulator A — A or a
Accumulator B — B or b
Accumulator D — D or d
Index Register X — X or x
Index Register Y — Y or y
Stack Pointer — SP, sp, or s
Program Counter — PC, pc, or p
Condition Code Register — CCR or c
Explanation of Italic Expressions in Source Form Column
abc — A or B or CCR
abcdxys — A or B or CCR or D or X or Y or SP. Some assemblers also allow T2 or T3.
abd — A or B or D
abdxys — A or B or D or X or Y or SP
dxys — D or X or Y or SP
msk8 — 8-bit mask, some assemblers require # symbol before value
opr8i — 8-bit immediate value
opr16i — 16-bit immediate value
opr8a — 8-bit address used with direct address mode
opr16a — 16-bit address value
oprx0_xysp — Indexed addressing postbyte code:
oprx3,–xys Predecrement X or Y or SP by 1 . . . 8
oprx3,+xys Preincrement X or Y or SP by 1 . . . 8
oprx3,xys– Postdecrement X or Y or SP by 1 . . . 8
oprx3,xys+ Postincrement X or Y or SP by 1 . . . 8
oprx5,xysp 5-bit constant offset from X or Y or SP or PC
abd,xysp Accumulator A or B or D offset from X or Y or SP or PC
oprx3 — Any positive integer 1 . . . 8 for pre/post increment/decrement
oprx5 — Any integer in the range –16 . . . +15
oprx9 — Any integer in the range –256 . . . +255
oprx16 — Any integer in the range –32,768 . . . 65,535
page — 8-bit value for PPAGE, some assemblers require # symbol before this value
rel8 — Label of branch destination within –128 to +127 locations
rel9 — Label of branch destination within –256 to +255 locations
rel16 — Any label within 64K memory space
trapnum — Any 8-bit integer in the range $30-$39 or $40-$FF
xys — X or Y or SP
xysp — X or Y or SP or PC
Operators
+ — Addition
– —
• —
Subtraction
Logical AND
+ — Logical OR (inclusive)
Continued on next page
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Operators (continued)
⊕ — Logical exclusive OR
× —
÷ —
Multiplication
M —
: —
Negation. One’s complement (invert each bit of M)
⇒ —
⇔ —
Division
Concatenate
Example: A : B means the 16-bit value formed by concatenating 8-bit accumulator A
with 8-bit accumulator B.
A is in the high-order position.
Transfer
Example: (A) ⇒ M means the content of accumulator A is transferred to memory
location M.
Exchange
Example: D ⇔ X means exchange the contents of D with those of X.
Address Mode Notation
INH — Inherent; no operands in object code
IMM — Immediate; operand in object code
DIR — Direct; operand is the lower byte of an address from $0000 to $00FF
EXT — Operand is a 16-bit address
REL — Two’s complement relative offset; for branch instructions
IDX — Indexed (no extension bytes); includes:
5-bit constant offset from X, Y, SP, or PC
Pre/post increment/decrement by 1 . . . 8
Accumulator A, B, or D offset
IDX1 — 9-bit signed offset from X, Y, SP, or PC; 1 extension byte
IDX2 — 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes
[IDX2] — Indexed-indirect; 16-bit offset from X, Y, SP, or PC
[D, IDX] — Indexed-indirect; accumulator D offset from X, Y, SP, or PC
Machine Coding
dd — 8-bit direct address $0000 to $00FF. (High byte assumed to be $00).
ee — High-order byte of a 16-bit constant offset for indexed addressing.
eb — Exchange/Transfer post-byte. See Table A-5 on page 399.
ff — Low-order eight bits of a 9-bit signed constant offset for indexed addressing,
or low-order byte of a 16-bit constant offset for indexed addressing.
hh — High-order byte of a 16-bit extended address.
ii — 8-bit immediate data value.
jj — High-order byte of a 16-bit immediate data value.
kk — Low-order byte of a 16-bit immediate data value.
lb — Loop primitive (DBNE) post-byte. See Table A-6 on page 400.
ll — Low-order byte of a 16-bit extended address.
mm — 8-bit immediate mask value for bit manipulation instructions.
Set bits indicate bits to be affected.
pg — Program page (bank) number used in CALL instruction.
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qq — High-order byte of a 16-bit relative offset for long branches.
tn — Trap number $30–$39 or $40–$FF.
rr — Signed relative offset $80 (–128) to $7F (+127).
Offset relative to the byte following the relative offset byte, or
low-order byte of a 16-bit relative offset for long branches.
xb — Indexed addressing post-byte. See Table A-3 on page 397
and Table A-4 on page 398.
Access Detail
Each code letter except (,), and comma equals one CPU cycle. Uppercase = 16-bit
operation and lowercase = 8-bit operation. For complex sequences see the CPU12
Reference Manual (CPU12RM/AD) for more detailed information.
f
g
I
i
n
O
P
r
R
s
S
w
W
u
U
V
t
T
x
()
,
— Free cycle, CPU doesn’t use bus
— Read PPAGE internally
— Read indirect pointer (indexed indirect)
— Read indirect PPAGE value (CALL indirect only)
— Write PPAGE internally
— Optional program word fetch (P) if instruction is misaligned and has
an odd number of bytes of object code — otherwise, appears as
a free cycle (f); Page 2 prebyte treated as a separate 1-byte instruction
— Program word fetch (always an aligned-word read)
— 8-bit data read
— 16-bit data read
— 8-bit stack write
— 16-bit stack write
— 8-bit data write
— 16-bit data write
— 8-bit stack read
— 16-bit stack read
— 16-bit vector fetch (always an aligned-word read)
— 8-bit conditional read (or free cycle)
— 16-bit conditional read (or free cycle)
— 8-bit conditional write (or free cycle)
— Indicate a microcode loop
— Indicates where an interrupt could be honored
Special Cases
PPP/P — Short branch, PPP if branch taken, P if not
OPPP/OPO — Long branch, OPPP if branch taken, OPO if not
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Condition Codes Columns
– — Status bit not affected by operation.
0 — Status bit cleared by operation.
1 — Status bit set by operation.
∆ — Status bit affected by operation.
⇓ — Status bit may be cleared or remain set, but is not set by operation.
⇑ — Status bit may be set or remain cleared, but is not cleared by operation.
? — Status bit may be changed by operation but the final state is not defined.
! — Status bit used for a special purpose.
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Table A-1. Instruction Set Summary (Sheet 1 of 14)
Source Form
Operation
Addr.
Mode
Machine
Coding (hex)
Access Detail
HCS12
M68HC12
SXHI
NZVC
OO – – ∆ – ∆ ∆ ∆ ∆
ABA
(A) + (B) ⇒ A
Add Accumulators A and B
INH
18 06
OO
ABX
(B) + (X) ⇒ X
Translates to LEAX B,X
IDX
1A E5
Pf
PP1
––––
––––
ABY
(B) + (Y) ⇒ Y
Translates to LEAY B,Y
IDX
19 ED
Pf
PP1
––––
––––
ADCA #opr8i
ADCA opr8a
ADCA opr16a
ADCA oprx0_xysp
ADCA oprx9,xysp
ADCA oprx16,xysp
ADCA [D,xysp]
ADCA [oprx16,xysp]
(A) + (M) + C ⇒ A
Add with Carry to A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
89
99
B9
A9
A9
A9
A9
A9
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P ––∆– ∆∆∆∆
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
ADCB #opr8i
ADCB opr8a
ADCB opr16a
ADCB oprx0_xysp
ADCB oprx9,xysp
ADCB oprx16,xysp
ADCB [D,xysp]
ADCB [oprx16,xysp]
(B) + (M) + C ⇒ B
Add with Carry to B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C9
D9
F9
E9
E9
E9
E9
E9
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P ––∆– ∆∆∆∆
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
ADDA #opr8i
ADDA opr8a
ADDA opr16a
ADDA oprx0_xysp
ADDA oprx9,xysp
ADDA oprx16,xysp
ADDA [D,xysp]
ADDA [oprx16,xysp]
(A) + (M) ⇒ A
Add without Carry to A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8B
9B
BB
AB
AB
AB
AB
AB
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P ––∆– ∆∆∆∆
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
ADDB #opr8i
ADDB opr8a
ADDB opr16a
ADDB oprx0_xysp
ADDB oprx9,xysp
ADDB oprx16,xysp
ADDB [D,xysp]
ADDB [oprx16,xysp]
(B) + (M) ⇒ B
Add without Carry to B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CB
DB
FB
EB
EB
EB
EB
EB
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P ––∆– ∆∆∆∆
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
ADDD #opr16i
ADDD opr8a
ADDD opr16a
ADDD oprx0_xysp
ADDD oprx9,xysp
ADDD oprx16,xysp
ADDD [D,xysp]
ADDD [oprx16,xysp]
(A:B) + (M:M+1) ⇒ A:B
Add 16-Bit to D (A:B)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C3
D3
F3
E3
E3
E3
E3
E3
jj
dd
hh
xb
xb
xb
xb
xb
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆∆∆
ANDA #opr8i
ANDA opr8a
ANDA opr16a
ANDA oprx0_xysp
ANDA oprx9,xysp
ANDA oprx16,xysp
ANDA [D,xysp]
ANDA [oprx16,xysp]
(A) • (M) ⇒ A
Logical AND A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
84
94
B4
A4
A4
A4
A4
A4
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
ANDB #opr8i
ANDB opr8a
ANDB opr16a
ANDB oprx0_xysp
ANDB oprx9,xysp
ANDB oprx16,xysp
ANDB [D,xysp]
ANDB [oprx16,xysp]
(B) • (M) ⇒ B
Logical AND B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C4
D4
F4
E4
E4
E4
E4
E4
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
ANDCC #opr8i
(CCR) • (M) ⇒ CCR
Logical AND CCR with Memory
IMM
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
kk
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
10 ii
P
P ⇓⇓⇓⇓ ⇓⇓⇓⇓
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
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Table A-1. Instruction Set Summary (Sheet 2 of 14)
Source Form
ASL opr16a
ASL oprx0_xysp
ASL oprx9,xysp
ASL oprx16,xysp
ASL [D,xysp]
ASL [oprx16,xysp]
ASLA
ASLB
Addr.
Mode
Operation
0
b0
b7
C
Arithmetic Shift Left
Arithmetic Shift Left Accumulator A
Arithmetic Shift Left Accumulator B
ASLD
Machine
Coding (hex)
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
78
68
68
68
68
68
48
58
INH
59
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
77
67
67
67
67
67
47
57
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
Access Detail
SXHI
NZVC
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆∆
O
––––
∆∆∆∆
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆∆
PPP/P1
PPP/P1
––––
––––
rPwO
rPwP
rPwO
rPwP
frPwPO
rPOw
rPPw
rPOw
rPwP
frPwOP
––––
∆∆0–
HCS12
M68HC12
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O
0
C
b7 A b0 b7
Arithmetic Shift Left Double
B
b0
ASR opr16a
ASR oprx0_xysp
ASR oprx9,xysp
ASR oprx16,xysp
ASR [D,xysp]
ASR [oprx16,xysp]
ASRA
ASRB
b7
Arithmetic Shift Right
BCC rel8
Branch if Carry Clear (if C = 0)
REL
24 rr
BCLR opr8a, msk8
BCLR opr16a, msk8
BCLR oprx0_xysp, msk8
BCLR oprx9,xysp, msk8
BCLR oprx16,xysp, msk8
(M) • (mm) ⇒ M
Clear Bit(s) in Memory
DIR
EXT
IDX
IDX1
IDX2
4D
1D
0D
0D
0D
BCS rel8
Branch if Carry Set (if C = 1)
REL
25 rr
PPP/P1
PPP/P1
––––
––––
PPP/P1
––––
––––
b0
C
Arithmetic Shift Right Accumulator A
Arithmetic Shift Right Accumulator B
hh
xb
xb
xb
xb
xb
dd
hh
xb
xb
xb
ll
ff
ee ff
ee ff
mm
ll mm
mm
ff mm
ee ff mm
BEQ rel8
Branch if Equal (if Z = 1)
REL
27 rr
PPP/P1
BGE rel8
Branch if Greater Than or Equal
(if N ⊕ V = 0) (signed)
REL
2C rr
PPP/P1
PPP/P1
––––
––––
BGND
Place CPU in Background Mode
see CPU12 Reference Manual
INH
00
VfPPP
VfPPP
––––
––––
BGT rel8
Branch if Greater Than
(if Z + (N ⊕ V) = 0) (signed)
REL
2E rr
PPP/P1
PPP/P1
––––
––––
BHI rel8
Branch if Higher
(if C + Z = 0) (unsigned)
REL
22 rr
PPP/P1
PPP/P1
––––
––––
BHS rel8
Branch if Higher or Same
(if C = 0) (unsigned)
same function as BCC
REL
24 rr
PPP/P1
PPP/P1
––––
––––
BITA #opr8i
BITA opr8a
BITA opr16a
BITA oprx0_xysp
BITA oprx9,xysp
BITA oprx16,xysp
BITA [D,xysp]
BITA [oprx16,xysp]
(A) • (M)
Logical AND A with Memory
Does not change Accumulator or Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
85
95
B5
A5
A5
A5
A5
A5
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
BITB #opr8i
BITB opr8a
BITB opr16a
BITB oprx0_xysp
BITB oprx9,xysp
BITB oprx16,xysp
BITB [D,xysp]
BITB [oprx16,xysp]
(B) • (M)
Logical AND B with Memory
Does not change Accumulator or Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C5
D5
F5
E5
E5
E5
E5
E5
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
BLE rel8
Branch if Less Than or Equal
(if Z + (N ⊕ V) = 1) (signed)
REL
2F rr
PPP/P1
PPP/P1
––––
––––
BLO rel8
Branch if Lower
(if C = 1) (unsigned)
same function as BCS
REL
25 rr
PPP/P1
PPP/P1
––––
––––
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
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Table A-1. Instruction Set Summary (Sheet 3 of 14)
Source Form
Operation
Addr.
Mode
Machine
Coding (hex)
Access Detail
HCS12
M68HC12
SXHI
NZVC
BLS rel8
Branch if Lower or Same
(if C + Z = 1) (unsigned)
REL
23 rr
PPP/P1
PPP/P1
––––
––––
BLT rel8
Branch if Less Than
(if N ⊕ V = 1) (signed)
REL
2D rr
PPP/P1
PPP/P1
––––
––––
BMI rel8
Branch if Minus (if N = 1)
REL
2B rr
PPP/P1
PPP/P1
1
––––
––––
BNE rel8
Branch if Not Equal (if Z = 0)
REL
26 rr
PPP/P
PPP/P1
––––
––––
BPL rel8
Branch if Plus (if N = 0)
REL
2A rr
PPP/P1
PPP/P1
––––
––––
BRA rel8
Branch Always (if 1 = 1)
REL
20 rr
PPP
PPP
––––
––––
BRCLR opr8a, msk8, rel8
Branch if (M) • (mm) = 0
BRCLR opr16a, msk8, rel8
(if All Selected Bit(s) Clear)
BRCLR oprx0_xysp, msk8, rel8
BRCLR oprx9,xysp, msk8, rel8
BRCLR oprx16,xysp, msk8, rel8
DIR
EXT
IDX
IDX1
IDX2
4F
1F
0F
0F
0F
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
rPPP
rfPPP
rPPP
rffPPP
frPffPPP
––––
––––
BRN rel8
REL
21 rr
P
P
––––
––––
DIR
EXT
IDX
IDX1
IDX2
4E
1E
0E
0E
0E
dd mm rr
hh ll mm rr
xb mm rr
xb ff mm rr
xb ee ff mm rr
rPPP
rfPPP
rPPP
rfPPP
PrfPPP
rPPP
rfPPP
rPPP
rffPPP
frPffPPP
––––
––––
DIR
EXT
IDX
IDX1
IDX2
4C
1C
0C
0C
0C
dd mm
hh ll mm
xb mm
xb ff mm
xb ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
rPOw
rPPw
rPOw
rPwP
frPwOP
––––
∆∆0–
PPPS
––––
––––
Branch Never (if 1 = 0)
BRSET opr8, msk8, rel8
Branch if (M) • (mm) = 0
BRSET opr16a, msk8, rel8
(if All Selected Bit(s) Set)
BRSET oprx0_xysp, msk8, rel8
BRSET oprx9,xysp, msk8, rel8
BRSET oprx16,xysp, msk8, rel8
BSET opr8, msk8
BSET opr16a, msk8
BSET oprx0_xysp, msk8
BSET oprx9,xysp, msk8
BSET oprx16,xysp, msk8
(M) + (mm) ⇒ M
Set Bit(s) in Memory
dd mm rr
hh ll mm rr
xb mm rr
xb ff mm rr
xb ee ff mm rr
BSR rel8
(SP) – 2 ⇒ SP; RTNH:RTNL ⇒ M(SP):M(SP+1)
Subroutine address ⇒ PC
Branch to Subroutine
REL
07 rr
SPPP
BVC rel8
Branch if Overflow Bit Clear (if V = 0)
REL
28 rr
PPP/P1
PPP/P1
––––
––––
29 rr
PPP/P1
PPP/P1
––––
––––
gnfSsPPP
gnfSsPPP
gnfSsPPP
fgnfSsPPP
fIignSsPPP
fIignSsPPP
––––
––––
BVS rel8
Branch if Overflow Bit Set (if V = 1)
CALL opr16a, page
CALL oprx0_xysp, page
CALL oprx9,xysp, page
CALL oprx16,xysp, page
CALL [D,xysp]
CALL [oprx16, xysp]
(SP) – 2 ⇒ SP; RTNH:RTNL ⇒ M(SP):M(SP+1)
(SP) – 1 ⇒ SP; (PPG) ⇒ M(SP);
pg ⇒ PPAGE register; Program address ⇒ PC
Call subroutine in extended memory
(Program may be located on another
expansion memory page.)
REL
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
4A
4B
4B
4B
4B
4B
hh
xb
xb
xb
xb
xb
ll pg
pg
ff pg
ee ff pg
ee ff
gnSsPPP
gnSsPPP
gnSsPPP
fgnSsPPP
fIignSsPPP
fIignSsPPP
Indirect modes get program address
and new pg value based on pointer.
CBA
(A) – (B)
Compare 8-Bit Accumulators
INH
18 17
OO
OO
––––
∆∆∆∆
CLC
0⇒C
Translates to ANDCC #$FE
IMM
10 FE
P
P
––––
–––0
CLI
0⇒I
Translates to ANDCC #$EF
(enables I-bit interrupts)
IMM
10 EF
P
P
–––0
––––
CLR opr16a
CLR oprx0_xysp
CLR oprx9,xysp
CLR oprx16,xysp
CLR [D,xysp]
CLR [oprx16,xysp]
CLRA
CLRB
0⇒M
wOP
Pw
PwO
PwP
PIfPw
PIPPw
O
O
––––
0100
CLV
0⇒V
Translates to ANDCC #$FD
P
––––
––0–
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆∆∆
0⇒A
0⇒B
Clear Memory Location
Clear Accumulator A
Clear Accumulator B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
IMM
79
69
69
69
69
69
87
C7
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
PwO
Pw
PwO
PwP
PIfw
PIPw
O
O
P
10 FD
Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
CMPA #opr8i
CMPA opr8a
CMPA opr16a
CMPA oprx0_xysp
CMPA oprx9,xysp
CMPA oprx16,xysp
CMPA [D,xysp]
CMPA [oprx16,xysp]
(A) – (M)
Compare Accumulator A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
81
91
B1
A1
A1
A1
A1
A1
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
383
Table A-1. Instruction Set Summary (Sheet 4 of 14)
Source Form
CMPB #opr8i
CMPB opr8a
CMPB opr16a
CMPB oprx0_xysp
CMPB oprx9,xysp
CMPB oprx16,xysp
CMPB [D,xysp]
CMPB [oprx16,xysp]
COM opr16a
COM oprx0_xysp
COM oprx9,xysp
COM oprx16,xysp
COM [D,xysp]
COM [oprx16,xysp]
COMA
COMB
Operation
(B) – (M)
Compare Accumulator B with Memory
(M) ⇒ M equivalent to $FF – (M) ⇒ M
1’s Complement Memory Location
(A) ⇒ A
Complement Accumulator A
(B) ⇒ B
Complement Accumulator B
CPD #opr16i
CPD opr8a
CPD opr16a
CPD oprx0_xysp
CPD oprx9,xysp
CPD oprx16,xysp
CPD [D,xysp]
CPD [oprx16,xysp]
(A:B) – (M:M+1)
Compare D to Memory (16-Bit)
CPS #opr16i
CPS opr8a
CPS opr16a
CPS oprx0_xysp
CPS oprx9,xysp
CPS oprx16,xysp
CPS [D,xysp]
CPS [oprx16,xysp]
(SP) – (M:M+1)
Compare SP to Memory (16-Bit)
CPX #opr16i
CPX opr8a
CPX opr16a
CPX oprx0_xysp
CPX oprx9,xysp
CPX oprx16,xysp
CPX [D,xysp]
CPX [oprx16,xysp]
(X) – (M:M+1)
Compare X to Memory (16-Bit)
CPY #opr16i
CPY opr8a
CPY opr16a
CPY oprx0_xysp
CPY oprx9,xysp
CPY oprx16,xysp
CPY [D,xysp]
CPY [oprx16,xysp]
(Y) – (M:M+1)
Compare Y to Memory (16-Bit)
DAA
Adjust Sum to BCD
Decimal Adjust Accumulator A
DBEQ abdxys, rel9
(cntr) – 1⇒ cntr
if (cntr) = 0, then Branch
else Continue to next instruction
Addr.
Mode
Machine
Coding (hex)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C1
D1
F1
E1
E1
E1
E1
E1
ii
dd
hh
xb
xb
xb
xb
xb
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
71
61
61
61
61
61
41
51
hh
xb
xb
xb
xb
xb
ll
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8C
9C
BC
AC
AC
AC
AC
AC
jj
dd
hh
xb
xb
xb
xb
xb
kk
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8F
9F
BF
AF
AF
AF
AF
AF
jj
dd
hh
xb
xb
xb
xb
xb
kk
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8E
9E
BE
AE
AE
AE
AE
AE
jj
dd
hh
xb
xb
xb
xb
xb
kk
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8D
9D
BD
AD
AD
AD
AD
AD
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
Access Detail
HCS12
M68HC12
SXHI
NZVC
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆∆∆
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆01
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆∆∆
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆∆∆
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆∆∆
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆∆∆
18 07
OfO
OfO
––––
∆∆?∆
REL
(9-bit)
04 lb rr
PPP (branch)
PPO (no
branch)
PPP
––––
––––
REL
(9-bit)
04 lb rr
PPP (branch)
PPO (no
branch)
PPP
––––
––––
INH
Decrement Counter and Branch if = 0
(cntr = A, B, D, X, Y, or SP)
DBNE abdxys, rel9
(cntr) – 1 ⇒ cntr
If (cntr) not = 0, then Branch;
else Continue to next instruction
Decrement Counter and Branch if ≠ 0
(cntr = A, B, D, X, Y, or SP)
S12CPUV2 Reference Manual, Rev. 4.0
384
Freescale Semiconductor
Table A-1. Instruction Set Summary (Sheet 5 of 14)
Source Form
DEC opr16a
DEC oprx0_xysp
DEC oprx9,xysp
DEC oprx16,xysp
DEC [D,xysp]
DEC [oprx16,xysp]
DECA
DECB
Operation
(M) – $01 ⇒ M
Decrement Memory Location
(A) – $01 ⇒ A
(B) – $01 ⇒ B
Decrement A
Decrement B
Addr.
Mode
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
Machine
Coding (hex)
73
63
63
63
63
63
43
53
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
Access Detail
HCS12
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
SXHI
NZVC
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆–
PP1
––––
––––
M68HC12
DES
(SP) – $0001 ⇒ SP
Translates to LEAS –1,SP
IDX
1B 9F
Pf
DEX
(X) – $0001 ⇒ X
Decrement Index Register X
INH
09
O
O
––––
–∆––
DEY
(Y) – $0001 ⇒ Y
Decrement Index Register Y
INH
03
O
O
––––
–∆––
EDIV
(Y:D) ÷ (X) ⇒ Y Remainder ⇒ D
32 by 16 Bit ⇒ 16 Bit Divide (unsigned)
INH
11
ffffffffffO
ffffffffffO
––––
∆∆∆∆
EDIVS
(Y:D) ÷ (X) ⇒ Y Remainder ⇒ D
32 by 16 Bit ⇒ 16 Bit Divide (signed)
INH
18 14
OffffffffffO
OffffffffffO
––––
∆∆∆∆
EMACS opr16a 2
(M(X):M(X+1)) × (M(Y):M(Y+1)) + (M~M+3) ⇒ M~M+3
Special
18 12 hh ll
ORROfffRRfWWP
ORROfffRRfWWP
––––
∆∆∆∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
1A
1A
1A
1A
1A
xb
xb ff
xb ee ff
xb
xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP
––––
∆∆∆∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
1E
1E
1E
1E
1E
xb
xb ff
xb ee ff
xb
xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
––––
∆∆∆∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
1B
1B
1B
1B
1B
xb
xb ff
xb ee ff
xb
xb ee ff
ORPf
ORPO
OfRPP
OfIfRPf
OfIPRPf
ORfP
ORPO
OfRPP
OfIfRfP
OfIPRfP
––––
∆∆∆∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
1F
1F
1F
1F
1F
xb
xb ff
xb ee ff
xb
xb ee ff
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
ORPW
ORPWO
OfRPWP
OfIfRPW
OfIPRPW
––––
∆∆∆∆
16 by 16 Bit ⇒ 32 Bit
Multiply and Accumulate (signed)
EMAXD oprx0_xysp
EMAXD oprx9,xysp
EMAXD oprx16,xysp
EMAXD [D,xysp]
EMAXD [oprx16,xysp]
MAX((D), (M:M+1)) ⇒ D
MAX of 2 Unsigned 16-Bit Values
EMAXM oprx0_xysp
EMAXM oprx9,xysp
EMAXM oprx16,xysp
EMAXM [D,xysp]
EMAXM [oprx16,xysp]
MAX((D), (M:M+1)) ⇒ M:M+1
MAX of 2 Unsigned 16-Bit Values
EMIND oprx0_xysp
EMIND oprx9,xysp
EMIND oprx16,xysp
EMIND [D,xysp]
EMIND [oprx16,xysp]
MIN((D), (M:M+1)) ⇒ D
MIN of 2 Unsigned 16-Bit Values
EMINM oprx0_xysp
EMINM oprx9,xysp
EMINM oprx16,xysp
EMINM [D,xysp]
EMINM [oprx16,xysp]
MIN((D), (M:M+1)) ⇒ M:M+1
MIN of 2 Unsigned 16-Bit Values
EMUL
(D) × (Y) ⇒ Y:D
16 by 16 Bit Multiply (unsigned)
INH
13
ffO
ffO
––––
∆∆–∆
EMULS
(D) × (Y) ⇒ Y:D
16 by 16 Bit Multiply (signed)
INH
18 13
OfO
OfO
––––
∆∆–∆
(A) ⊕ (M) ⇒ A
Exclusive-OR A with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
EORA #opr8i
EORA opr8a
EORA opr16a
EORA oprx0_xysp
EORA oprx9,xysp
EORA oprx16,xysp
EORA [D,xysp]
EORA [oprx16,xysp]
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
N, Z, V and C status bits reflect result of
internal compare ((D) – (M:M+1))
(if followed by page 2 instruction)
OffO
OfO
88
98
B8
A8
A8
A8
A8
A8
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
Notes:
1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
2. opr16a is an extended address specification. Both X and Y point to source operands.
EORB #opr8i
EORB opr8a
EORB opr16a
EORB oprx0_xysp
EORB oprx9,xysp
EORB oprx16,xysp
EORB [D,xysp]
EORB [oprx16,xysp]
(B) ⊕ (M) ⇒ B
Exclusive-OR B with Memory
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C8
D8
F8
E8
E8
E8
E8
E8
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
385
Table A-1. Instruction Set Summary (Sheet 6 of 14)
Source Form
ETBL oprx0_xysp
Operation
(M:M+1)+ [(B)×((M+2:M+3) – (M:M+1))] ⇒ D
16-Bit Table Lookup and Interpolate
Addr.
Mode
IDX
Machine
Coding (hex)
18 3F xb
Access Detail
HCS12
ORRffffffP
M68HC12
ORRffffffP
SXHI
NZVC
––––
∆∆–∆
?
C Bit is undefined
in HC12
Initialize B, and index before ETBL.
<ea> points at first table entry (M:M+1)
and B is fractional part of lookup value
(no indirect addr. modes or extensions allowed)
EXG abcdxys,abcdxys
(r1) ⇔ (r2) (if r1 and r2 same size) or
$00:(r1) ⇒ r2 (if r1=8-bit; r2=16-bit) or
(r1low) ⇔ (r2) (if r1=16-bit; r2=8-bit)
INH
B7 eb
P
P
––––
––––
18 11
OffffffffffO
OffffffffffO
––––
–∆∆∆
r1 and r2 may be
A, B, CCR, D, X, Y, or SP
FDIV
(D) ÷ (X) ⇒ X; Remainder ⇒ D
16 by 16 Bit Fractional Divide
INH
IBEQ abdxys, rel9
(cntr) + 1⇒ cntr
If (cntr) = 0, then Branch
else Continue to next instruction
REL
(9-bit)
04 lb rr
PPP (branch)
PPO (no
branch)
PPP
––––
––––
REL
(9-bit)
04 lb rr
PPP (branch)
PPO (no
branch)
PPP
––––
––––
Increment Counter and Branch if = 0
(cntr = A, B, D, X, Y, or SP)
IBNE abdxys, rel9
(cntr) + 1⇒ cntr
if (cntr) not = 0, then Branch;
else Continue to next instruction
Increment Counter and Branch if ≠ 0
(cntr = A, B, D, X, Y, or SP)
IDIV
(D) ÷ (X) ⇒ X; Remainder ⇒ D
16 by 16 Bit Integer Divide (unsigned)
INH
18 10
OffffffffffO
OffffffffffO
––––
–∆0∆
IDIVS
(D) ÷ (X) ⇒ X; Remainder ⇒ D
16 by 16 Bit Integer Divide (signed)
INH
18 15
OffffffffffO
OffffffffffO
––––
∆∆∆∆
INC opr16a
INC oprx0_xysp
INC oprx9,xysp
INC oprx16,xysp
INC [D,xysp]
INC [oprx16,xysp]
INCA
INCB
(M) + $01 ⇒ M
Increment Memory Byte
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆–
INS
(SP) + $0001 ⇒ SP
Translates to LEAS 1,SP
IDX
1B 81
Pf
PP1
––––
––––
INX
(X) + $0001 ⇒ X
Increment Index Register X
INH
08
O
O
––––
–∆––
INY
(Y) + $0001 ⇒ Y
Increment Index Register Y
INH
02
O
O
––––
–∆––
JMP opr16a
JMP oprx0_xysp
JMP oprx9,xysp
JMP oprx16,xysp
JMP [D,xysp]
JMP [oprx16,xysp]
Routine address ⇒ PC
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
06
05
05
05
05
05
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
––––
––––
SPPP
SPPP
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
PPPS
PPPS
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
––––
––––
(A) + $01 ⇒ A
(B) + $01 ⇒ B
Increment Acc. A
Increment Acc. B
Jump
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
72
62
62
62
62
62
42
52
hh
xb
xb
xb
xb
xb
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
JSR opr8a
JSR opr16a
JSR oprx0_xysp
JSR oprx9,xysp
JSR oprx16,xysp
JSR [D,xysp]
JSR [oprx16,xysp]
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
Subroutine address ⇒ PC
LBCC rel16
Long Branch if Carry Clear (if C = 0)
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Jump to Subroutine
REL
17
16
15
15
15
15
15
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
18 24 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
OPPP/OPO1
––––
––––
LBCS rel16
Long Branch if Carry Set (if C = 1)
REL
18 25 qq rr
OPPP/OPO1
LBEQ rel16
Long Branch if Equal (if Z = 1)
REL
18 27 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBGE rel16
Long Branch Greater Than or Equal
(if N ⊕ V = 0) (signed)
REL
18 2C qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
S12CPUV2 Reference Manual, Rev. 4.0
386
Freescale Semiconductor
Table A-1. Instruction Set Summary (Sheet 7 of 14)
Source Form
Operation
Addr.
Mode
Machine
Coding (hex)
Access Detail
HCS12
M68HC12
SXHI
NZVC
LBGT rel16
Long Branch if Greater Than
(if Z + (N ⊕ V) = 0) (signed)
REL
18 2E qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBHI rel16
Long Branch if Higher
(if C + Z = 0) (unsigned)
REL
18 22 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBHS rel16
Long Branch if Higher or Same
(if C = 0) (unsigned)
same function as LBCC
REL
18 24 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBLE rel16
Long Branch if Less Than or Equal
(if Z + (N ⊕ V) = 1) (signed)
REL
18 2F qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBLO rel16
Long Branch if Lower
(if C = 1) (unsigned)
same function as LBCS
REL
18 25 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBLS rel16
Long Branch if Lower or Same
(if C + Z = 1) (unsigned)
REL
18 23 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBLT rel16
Long Branch if Less Than
(if N ⊕ V = 1) (signed)
REL
18 2D qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBMI rel16
Long Branch if Minus (if N = 1)
REL
18 2B qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBNE rel16
Long Branch if Not Equal (if Z = 0)
REL
18 26 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBPL rel16
Long Branch if Plus (if N = 0)
REL
18 2A qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBRA rel16
Long Branch Always (if 1=1)
REL
18 20 qq rr
OPPP
OPPP
––––
––––
LBRN rel16
Long Branch Never (if 1 = 0)
REL
18 21 qq rr
OPO
OPO
––––
––––
LBVC rel16
Long Branch if Overflow Bit Clear (if V=0)
REL
18 28 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LBVS rel16
Long Branch if Overflow Bit Set (if V = 1)
REL
18 29 qq rr
OPPP/OPO1
OPPP/OPO1
––––
––––
LDAA #opr8i
LDAA opr8a
LDAA opr16a
LDAA oprx0_xysp
LDAA oprx9,xysp
LDAA oprx16,xysp
LDAA [D,xysp]
LDAA [oprx16,xysp]
(M) ⇒ A
Load Accumulator A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
86
96
B6
A6
A6
A6
A6
A6
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
LDAB #opr8i
LDAB opr8a
LDAB opr16a
LDAB oprx0_xysp
LDAB oprx9,xysp
LDAB oprx16,xysp
LDAB [D,xysp]
LDAB [oprx16,xysp]
(M) ⇒ B
Load Accumulator B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C6
D6
F6
E6
E6
E6
E6
E6
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
LDD #opr16i
LDD opr8a
LDD opr16a
LDD oprx0_xysp
LDD oprx9,xysp
LDD oprx16,xysp
LDD [D,xysp]
LDD [oprx16,xysp]
(M:M+1) ⇒ A:B
Load Double Accumulator D (A:B)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CC
DC
FC
EC
EC
EC
EC
EC
jj
dd
hh
xb
xb
xb
xb
xb
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆0–
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆0–
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆0–
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
kk
ll
ff
ee ff
ee ff
Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
LDS #opr16i
LDS opr8a
LDS opr16a
LDS oprx0_xysp
LDS oprx9,xysp
LDS oprx16,xysp
LDS [D,xysp]
LDS [oprx16,xysp]
(M:M+1) ⇒ SP
Load Stack Pointer
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysp
LDX oprx9,xysp
LDX oprx16,xysp
LDX [D,xysp]
LDX [oprx16,xysp]
(M:M+1) ⇒ X
Load Index Register X
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CF
DF
FF
EF
EF
EF
EF
EF
jj
dd
hh
xb
xb
xb
xb
xb
kk
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CE
DE
FE
EE
EE
EE
EE
EE
jj
dd
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
387
Table A-1. Instruction Set Summary (Sheet 8 of 14)
Source Form
Addr.
Mode
Operation
Machine
Coding (hex)
Access Detail
HCS12
SXHI
NZVC
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆0–
M68HC12
LDY #opr16i
LDY opr8a
LDY opr16a
LDY oprx0_xysp
LDY oprx9,xysp
LDY oprx16,xysp
LDY [D,xysp]
LDY [oprx16,xysp]
(M:M+1) ⇒ Y
Load Index Register Y
LEAS oprx0_xysp
LEAS oprx9,xysp
LEAS oprx16,xysp
Effective Address ⇒ SP
Load Effective Address into SP
IDX
IDX1
IDX2
1B xb
1B xb ff
1B xb ee ff
Pf
PO
PP
PP1
PO
PP
––––
––––
LEAX oprx0_xysp
LEAX oprx9,xysp
LEAX oprx16,xysp
Effective Address ⇒ X
Load Effective Address into X
IDX
IDX1
IDX2
1A xb
1A xb ff
1A xb ee ff
Pf
PO
PP
PP1
PO
PP
––––
––––
LEAY oprx0_xysp
LEAY oprx9,xysp
LEAY oprx16,xysp
Effective Address ⇒ Y
Load Effective Address into Y
IDX
IDX1
IDX2
19 xb
19 xb ff
19 xb ee ff
Pf
PO
PP
PP1
PO
PP
––––
––––
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
78
68
68
68
68
68
48
58
rPwO
rPw
rPwO
frPPw
fIfrPw
fIPrPw
O
O
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆∆
INH
59
O
––––
∆∆∆∆
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
74
64
64
64
64
64
44
54
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
0∆∆∆
INH
49
O
––––
0∆∆∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP
––––
∆∆∆∆
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
––––
∆∆∆∆
RRfOw
––?–
????
LSL opr16a
LSL oprx0_xysp
LSL oprx9,xysp
LSL oprx16,xysp
LSL [D,xysp]
LSL [oprx16,xysp]
LSLA
LSLB
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
0
b7
C
Logical Shift Left
same function as ASL
b0
Logical Shift Accumulator A to Left
Logical Shift Accumulator B to Left
LSLD
CD
DD
FD
ED
ED
ED
ED
ED
jj
dd
hh
xb
xb
xb
xb
xb
hh
xb
xb
xb
xb
xb
kk
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
O
0
b0
b7 A
b7
B
C
Logical Shift Left D Accumulator
same function as ASLD
LSR opr16a
LSR oprx0_xysp
LSR oprx9,xysp
LSR oprx16,xysp
LSR [D,xysp]
LSR [oprx16,xysp]
LSRA
LSRB
b0
0
b7
Logical Shift Right
b0
C
Logical Shift Accumulator A to Right
Logical Shift Accumulator B to Right
LSRD
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O
0
b0
A
b7
b7
B
Logical Shift Right D Accumulator
MAXA oprx0_xysp
MAXA oprx9,xysp
MAXA oprx16,xysp
MAXA [D,xysp]
MAXA [oprx16,xysp]
b0
C
MAX((A), (M)) ⇒ A
MAX of 2 Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
18
18
18
18
18
xb
xb ff
xb ee ff
xb
xb ee ff
Note 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.
MAXM oprx0_xysp
MAXM oprx9,xysp
MAXM oprx16,xysp
MAXM [D,xysp]
MAXM [oprx16,xysp]
MAX((A), (M)) ⇒ M
MAX of 2 Unsigned 8-Bit Values
MEM
µ (grade) ⇒ M(Y);
(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
Special
01
1C
1C
1C
1C
1C
xb
xb ff
xb ee ff
xb
xb ee ff
RRfOw
if (A) < P1 or (A) > P2 then µ = 0, else
µ = MIN[((A) – P1)×S1, (P2 – (A))×S2, $FF]
where:
A = current crisp input value;
X points at 4-byte data structure that describes a trapezoidal
membership function (P1, P2, S1, S2);
Y points at fuzzy input (RAM location).
See CPU12 Reference Manual for special cases.
S12CPUV2 Reference Manual, Rev. 4.0
388
Freescale Semiconductor
Table A-1. Instruction Set Summary (Sheet 9 of 14)
Source Form
Operation
Addr.
Mode
Machine
Coding (hex)
Access Detail
HCS12
M68HC12
SXHI
NZVC
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
19
19
19
19
19
xb
xb ff
xb ee ff
xb
xb ee ff
OrPf
OrPO
OfrPP
OfIfrPf
OfIPrPf
OrfP
OrPO
OfrPP
OfIfrfP
OfIPrfP
––––
∆∆∆∆
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
18
18
18
18
18
1D
1D
1D
1D
1D
xb
xb ff
xb ee ff
xb
xb ee ff
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
OrPw
OrPwO
OfrPwP
OfIfrPw
OfIPrPw
––––
∆∆∆∆
MOVB #opr8, opr16a1
(M1) ⇒ M2
MOVB #opr8i, oprx0_xysp1
Memory to Memory Byte-Move (8-Bit)
1
MOVB opr16a, opr16a
1
MOVB opr16a, oprx0_xysp
MOVB oprx0_xysp, opr16a1
MOVB oprx0_xysp, oprx0_xysp1
IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX
18
18
18
18
18
18
0B ii hh ll
08 xb ii
0C hh ll hh ll
09 xb hh ll
0D xb hh ll
0A xb xb
OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO
OPwP
OPwO
OrPwPO
OPrPw
OrPwP
OrPwO
––––
––––
MOVW #oprx16, opr16a1
(M:M+11) ⇒ M:M+12
MOVW #opr16i, oprx0_xysp1
Memory to Memory Word-Move (16-Bit)
1
MOVW opr16a, opr16a
1
MOVW opr16a, oprx0_xysp
MOVW oprx0_xysp, opr16a1
MOVW oprx0_xysp, oprx0_xysp1
IMM-EXT
IMM-IDX
EXT-EXT
EXT-IDX
IDX-EXT
IDX-IDX
18
18
18
18
18
18
03 jj kk hh ll
00 xb jj kk
04 hh ll hh ll
01 xb hh ll
05 xb hh ll
02 xb xb
OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO
OPWPO
OPPW
ORPWPO
OPRPW
ORPWP
ORPWO
––––
––––
INH
12
ffO
––––
–––∆
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
70
60
60
60
60
60
40
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
––––
∆∆∆∆
INH
50
MINA oprx0_xysp
MINA oprx9,xysp
MINA oprx16,xysp
MINA [D,xysp]
MINA [oprx16,xysp]
MIN((A), (M)) ⇒ A
MIN of 2 Unsigned 8-Bit Values
MINM oprx0_xysp
MINM oprx9,xysp
MINM oprx16,xysp
MINM [D,xysp]
MINM [oprx16,xysp]
MIN((A), (M)) ⇒ M
MIN of 2 Unsigned 8-Bit Values
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
N, Z, V and C status bits reflect result of
internal compare ((A) – (M)).
MUL
(A) × (B) ⇒ A:B
8 by 8 Unsigned Multiply
NEG opr16a
NEG oprx0_xysp
NEG oprx9,xysp
NEG oprx16,xysp
NEG [D,xysp]
NEG [oprx16,xysp]
NEGA
0 – (M) ⇒ M equivalent to (M) + 1 ⇒ M
Two’s Complement Negate
NEGB
NOP
ORAA #opr8i
ORAA opr8a
ORAA opr16a
ORAA oprx0_xysp
ORAA oprx9,xysp
ORAA oprx16,xysp
ORAA [D,xysp]
ORAA [oprx16,xysp]
0 – (A) ⇒ A equivalent to (A) + 1 ⇒ A
Negate Accumulator A
0 – (B) ⇒ B equivalent to (B) + 1 ⇒ B
Negate Accumulator B
No Operation
(A) + (M) ⇒ A
Logical OR A with Memory
O
hh
xb
xb
xb
xb
xb
INH
A7
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
8A
9A
BA
AA
AA
AA
AA
AA
ii
dd
hh
xb
xb
xb
xb
xb
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CA
DA
FA
EA
EA
EA
EA
EA
ii
dd
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
O
O
O
––––
––––
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆0–
Note 1. The first operand in the source code statement specifies the source for the move.
ORAB #opr8i
ORAB opr8a
ORAB opr16a
ORAB oprx0_xysp
ORAB oprx9,xysp
ORAB oprx16,xysp
ORAB [D,xysp]
ORAB [oprx16,xysp]
(B) + (M) ⇒ B
Logical OR B with Memory
ll
ff
ee ff
ee ff
ORCC #opr8i
(CCR) + M ⇒ CCR
Logical OR CCR with Memory
IMM
14 ii
P
PSHA
(SP) – 1 ⇒ SP; (A) ⇒ M(SP)
Push Accumulator A onto Stack
INH
36
Os
Os
––––
––––
PSHB
(SP) – 1 ⇒ SP; (B) ⇒ M(SP)
Push Accumulator B onto Stack
INH
37
Os
Os
––––
––––
PSHC
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
Push CCR onto Stack
INH
39
Os
Os
––––
––––
PSHD
(SP) – 2 ⇒ SP; (A:B) ⇒ M(SP):M(SP+1)
Push D Accumulator onto Stack
INH
3B
OS
OS
––––
––––
PSHX
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1)
Push Index Register X onto Stack
INH
34
OS
OS
––––
––––
PSHY
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1)
Push Index Register Y onto Stack
INH
35
OS
OS
––––
––––
P ⇑–⇑⇑ ⇑⇑⇑⇑
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
389
Table A-1. Instruction Set Summary (Sheet 10 of 14)
Source Form
Addr.
Mode
Operation
Machine
Coding (hex)
Access Detail
HCS12
M68HC12
SXHI
NZVC
PULA
(M(SP)) ⇒ A; (SP) + 1 ⇒ SP
Pull Accumulator A from Stack
INH
32
ufO
ufO
––––
––––
PULB
(M(SP)) ⇒ B; (SP) + 1 ⇒ SP
Pull Accumulator B from Stack
INH
33
ufO
ufO
––––
––––
PULC
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
Pull CCR from Stack
INH
38
ufO
ufO ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆
PULD
(M(SP):M(SP+1)) ⇒ A:B; (SP) + 2 ⇒ SP
Pull D from Stack
INH
3A
UfO
UfO
––––
––––
PULX
(M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 2 ⇒ SP
Pull Index Register X from Stack
INH
30
UfO
UfO
––––
––––
PULY
(M(SP):M(SP+1)) ⇒ YH:YL; (SP) + 2 ⇒ SP
Pull Index Register Y from Stack
INH
31
UfO
UfO
––––
––––
REV
MIN-MAX rule evaluation
Find smallest rule input (MIN).
Store to rule outputs unless fuzzy output is already larger
(MAX).
18 3A
Orf(t,tx)O
Orf(t,tx)O
––?–
??∆?
––?–
??∆!
Special
(exit + re-entry replaces comma
above if interrupted)
ff + Orf(t,
ff + Orf(t,
ORf(t,Tx)O
ORf(t,Tx)O
For rule weights see REVW.
Each rule input is an 8-bit offset from the base address in Y.
Each rule output is an 8-bit offset from the base address in Y.
$FE separates rule inputs from rule outputs. $FF terminates
the rule list.
REV may be interrupted.
REVW
MIN-MAX rule evaluation
Find smallest rule input (MIN),
Store to rule outputs unless fuzzy output is already larger
(MAX).
Special
18 3B
(loop to read weight if enabled)
(r,RfRf)
(r,RfRf)
(exit + re-entry replaces comma
above if interrupted)
Rule weights supported, optional.
ffff + ORf(t,
Each rule input is the 16-bit address of a fuzzy input. Each rule
output is the 16-bit address of a fuzzy output. The value $FFFE
separates rule inputs from rule outputs. $FFFF terminates the
rule list.
fff + ORf(t,
REVW may be interrupted.
ROL opr16a
ROL oprx0_xysp
ROL oprx9,xysp
ROL oprx16,xysp
ROL [D,xysp]
ROL [oprx16,xysp]
ROLA
ROLB
ROR opr16a
ROR oprx0_xysp
ROR oprx9,xysp
ROR oprx16,xysp
ROR [D,xysp]
ROR [oprx16,xysp]
RORA
RORB
b7
C
Rotate Memory Left through Carry
b0
Rotate A Left through Carry
Rotate B Left through Carry
b0
b7
C
Rotate Memory Right through Carry
Rotate A Right through Carry
Rotate B Right through Carry
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
75
65
65
65
65
65
45
55
hh
xb
xb
xb
xb
xb
ll
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
76
66
66
66
66
66
46
56
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
ff
ee ff
ee ff
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆∆
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
rOPw
rPw
rPOw
frPPw
fIfrPw
fIPrPw
O
O
––––
∆∆∆∆
uUnPPP
––––
––––
RTC
(M(SP)) ⇒ PPAGE; (SP) + 1 ⇒ SP;
(M(SP):M(SP+1)) ⇒ PCH:PCL;
(SP) + 2 ⇒ SP
Return from Call
INH
0A
uUnfPPP
RTI
(M(SP)) ⇒ CCR; (SP) + 1 ⇒ SP
(M(SP):M(SP+1)) ⇒ B:A; (SP) + 2 ⇒ SP
(M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 4 ⇒ SP
(M(SP):M(SP+1)) ⇒ PCH:PCL; (SP) – 2 ⇒ SP
(M(SP):M(SP+1)) ⇒ YH:YL; (SP) + 4 ⇒ SP
Return from Interrupt
INH
0B
uUUUUPPP
(M(SP):M(SP+1)) ⇒ PCH:PCL;
(SP) + 2 ⇒ SP
Return from Subroutine
INH
RTS
uUUUUPPP ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆
(with interrupt pending)
uUUUUVfPPP
3D
UfPPP
uUUUUfVfPPP
UfPPP
––––
––––
S12CPUV2 Reference Manual, Rev. 4.0
390
Freescale Semiconductor
Table A-1. Instruction Set Summary (Sheet 11 of 14)
Source Form
Operation
Addr.
Mode
Machine
Coding (hex)
SBA
(A) – (B) ⇒ A
Subtract B from A
SBCA #opr8i
SBCA opr8a
SBCA opr16a
SBCA oprx0_xysp
SBCA oprx9,xysp
SBCA oprx16,xysp
SBCA [D,xysp]
SBCA [oprx16,xysp]
(A) – (M) – C ⇒ A
Subtract with Borrow from A
SBCB #opr8i
SBCB opr8a
SBCB opr16a
SBCB oprx0_xysp
SBCB oprx9,xysp
SBCB oprx16,xysp
SBCB [D,xysp]
SBCB [oprx16,xysp]
(B) – (M) – C ⇒ B
Subtract with Borrow from B
SEC
1⇒C
Translates to ORCC #$01
IMM
14 01
SEI
1 ⇒ I; (inhibit I interrupts)
Translates to ORCC #$10
IMM
SEV
1⇒V
Translates to ORCC #$02
SEX abc,dxys
$00:(r1) ⇒ r2 if r1, bit 7 is 0 or
$FF:(r1) ⇒ r2 if r1, bit 7 is 1
INH
Access Detail
HCS12
SXHI
NZVC
OO
––––
∆∆∆∆
M68HC12
18 16
OO
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
82
92
B2
A2
A2
A2
A2
A2
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆∆∆
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C2
D2
F2
E2
E2
E2
E2
E2
ii
dd
hh
xb
xb
xb
xb
xb
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆∆∆
P
P
––––
–––1
14 10
P
P
–––1
––––
IMM
14 02
P
P
––––
––1–
INH
B7 eb
P
P
––––
––––
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw
––––
∆∆0–
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
Pw
wOP
Pw
PwO
PwP
PIfPw
PIPPw
––––
∆∆0–
PW
PWO
PW
PWO
PWP
PIfW
PIPW
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
––––
∆∆0–
––––
––––
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
Sign Extend 8-bit r1 to 16-bit r2
r1 may be A, B, or CCR
r2 may be D, X, Y, or SP
Alternate mnemonic for TFR r1, r2
STAA opr8a
STAA opr16a
STAA oprx0_xysp
STAA oprx9,xysp
STAA oprx16,xysp
STAA [D,xysp]
STAA [oprx16,xysp]
(A) ⇒ M
Store Accumulator A to Memory
STAB opr8a
STAB opr16a
STAB oprx0_xysp
STAB oprx9,xysp
STAB oprx16,xysp
STAB [D,xysp]
STAB [oprx16,xysp]
(B) ⇒ M
Store Accumulator B to Memory
STD opr8a
STD opr16a
STD oprx0_xysp
STD oprx9,xysp
STD oprx16,xysp
STD [D,xysp]
STD [oprx16,xysp]
(A) ⇒ M, (B) ⇒ M+1
Store Double Accumulator
STOP
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP);
STOP All Clocks
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5A
7A
6A
6A
6A
6A
6A
dd
hh
xb
xb
xb
xb
xb
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5B
7B
6B
6B
6B
6B
6B
dd
hh
xb
xb
xb
xb
xb
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5C
7C
6C
6C
6C
6C
6C
dd
hh
xb
xb
xb
xb
xb
INH
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
(entering STOP)
18 3E
OOSSSSsf
OOSSSfSs
(exiting STOP)
fVfPPP
fVfPPP
(continue)
ff
fO
Registers stacked to allow quicker recovery by interrupt.
If S control bit = 1, the STOP instruction is disabled and acts
like a two-cycle NOP.
(if STOP disabled)
OO
OO
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
391
Table A-1. Instruction Set Summary (Sheet 12 of 14)
Source Form
Operation
STS opr8a
STS opr16a
STS oprx0_xysp
STS oprx9,xysp
STS oprx16,xysp
STS [D,xysp]
STS [oprx16,xysp]
(SPH:SPL) ⇒ M:M+1
Store Stack Pointer
STX opr8a
STX opr16a
STX oprx0_xysp
STX oprx9,xysp
STX oprx16,xysp
STX [D,xysp]
STX [oprx16,xysp]
(XH:XL) ⇒ M:M+1
Store Index Register X
STY opr8a
STY opr16a
STY oprx0_xysp
STY oprx9,xysp
STY oprx16,xysp
STY [D,xysp]
STY [oprx16,xysp]
(YH:YL) ⇒ M:M+1
Store Index Register Y
SUBA #opr8i
SUBA opr8a
SUBA opr16a
SUBA oprx0_xysp
SUBA oprx9,xysp
SUBA oprx16,xysp
SUBA [D,xysp]
SUBA [oprx16,xysp]
(A) – (M) ⇒ A
Subtract Memory from Accumulator A
SUBB #opr8i
SUBB opr8a
SUBB opr16a
SUBB oprx0_xysp
SUBB oprx9,xysp
SUBB oprx16,xysp
SUBB [D,xysp]
SUBB [oprx16,xysp]
(B) – (M) ⇒ B
Subtract Memory from Accumulator B
SUBD #opr16i
SUBD opr8a
SUBD opr16a
SUBD oprx0_xysp
SUBD oprx9,xysp
SUBD oprx16,xysp
SUBD [D,xysp]
SUBD [oprx16,xysp]
(D) – (M:M+1) ⇒ D
Subtract Memory from D (A:B)
SWI
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
1 ⇒ I; (SWI Vector) ⇒ PC
Software Interrupt
Addr.
Mode
Machine
Coding (hex)
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5F
7F
6F
6F
6F
6F
6F
dd
hh
xb
xb
xb
xb
xb
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5E
7E
6E
6E
6E
6E
6E
dd
hh
xb
xb
xb
xb
xb
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5D
7D
6D
6D
6D
6D
6D
dd
hh
xb
xb
xb
xb
xb
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
80
90
B0
A0
A0
A0
A0
A0
ii
dd
hh
xb
xb
xb
xb
xb
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C0
D0
F0
E0
E0
E0
E0
E0
ii
dd
hh
xb
xb
xb
xb
xb
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
83
93
B3
A3
A3
A3
A3
A3
jj
dd
hh
xb
xb
xb
xb
xb
INH
3F
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
ll
ff
ee ff
ee ff
kk
ll
ff
ee ff
ee ff
Access Detail
HCS12
M68HC12
SXHI
NZVC
PW
PWO
PW
PWO
PWP
PIfW
PIPW
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
––––
∆∆0–
PW
PWO
PW
PWO
PWP
PIfW
PIPW
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
––––
∆∆0–
PW
PWO
PW
PWO
PWP
PIfW
PIPW
PW
WOP
PW
PWO
PWP
PIfPW
PIPPW
––––
∆∆0–
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆∆∆
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rfP
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
––––
∆∆∆∆
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
OP
RfP
ROP
RfP
RPO
fRPP
fIfRfP
fIPRfP
––––
∆∆∆∆
VSPSSPSsP*
–––1
––––
VfPPP
11–1
––––
OO
––––
∆∆0–
VSPSSPSsP*
(for Reset)
VfPPP
*The CPU also uses the SWI microcode sequence for hardware interrupts and unimplemented opcode traps. Reset uses the VfPPP variation of this sequence.
TAB
(A) ⇒ B
Transfer A to B
INH
18 0E
OO
TAP
(A) ⇒ CCR
Translates to TFR A , CCR
INH
B7 02
P
TBA
(B) ⇒ A
Transfer B to A
INH
18 0F
OO
TBEQ abdxys,rel9
If (cntr) = 0, then Branch;
else Continue to next instruction
04 lb rr
PPP (branch)
PPO (no
branch)
REL
(9-bit)
P ∆⇓∆∆ ∆∆∆∆
OO
––––
∆∆0–
PPP
––––
––––
Test Counter and Branch if Zero
(cntr = A, B, D, X,Y, or SP)
S12CPUV2 Reference Manual, Rev. 4.0
392
Freescale Semiconductor
Table A-1. Instruction Set Summary (Sheet 13 of 14)
Source Form
TBL oprx0_xysp
Operation
(M) + [(B) × ((M+1) – (M))] ⇒ A
8-Bit Table Lookup and Interpolate
Addr.
Mode
IDX
Machine
Coding (hex)
18 3D xb
Access Detail
HCS12
M68HC12
ORfffP
OrrffffP
SXHI
NZVC
––––
∆∆–∆
?
C Bit is undefined
in HC12
Initialize B, and index before TBL.
<ea> points at first 8-bit table entry (M) and B is fractional part
of lookup value.
(no indirect addressing modes or extensions allowed)
TBNE abdxys,rel9
REL
(9-bit)
If (cntr) not = 0, then Branch;
else Continue to next instruction
04 lb rr
PPP (branch)
PPO (no
branch)
B7 eb
P
PPP
––––
P
––––
––––
Test Counter and Branch if Not Zero
(cntr = A, B, D, X,Y, or SP)
TFR abcdxys,abcdxys
(r1) ⇒ r2 or
$00:(r1) ⇒ r2 or
(r1[7:0]) ⇒ r2
INH
––––
or
∆⇓∆∆ ∆∆∆∆
Transfer Register to Register
r1 and r2 may be A, B, CCR, D, X, Y, or SP
TPA
(CCR) ⇒ A
Translates to TFR CCR ,A
INH
B7 20
P
TRAP trapnum
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP)
1 ⇒ I; (TRAP Vector) ⇒ PC
INH
18 tn
tn = $30–$39
or
$40–$FF
OVSPSSPSsP
F7
E7
E7
E7
E7
E7
97
D7
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
O
O
P
––––
––––
OfVSPSSPSsP
–––1
––––
rOP
rfP
rPO
frPP
fIfrfP
fIPrfP
O
O
––––
∆∆00
Unimplemented opcode trap
TST opr16a
TST oprx0_xysp
TST oprx9,xysp
TST oprx16,xysp
TST [D,xysp]
TST [oprx16,xysp]
TSTA
TSTB
(M) – 0
Test Memory for Zero or Minus
TSX
(SP) ⇒ X
Translates to TFR SP,X
INH
B7 75
P
P
––––
––––
TSY
(SP) ⇒ Y
Translates to TFR SP,Y
INH
B7 76
P
P
––––
––––
TXS
(X) ⇒ SP
Translates to TFR X,SP
INH
B7 57
P
P
––––
––––
TYS
(Y) ⇒ SP
Translates to TFR Y,SP
INH
B7 67
P
P
––––
––––
WAI
(SP) – 2 ⇒ SP;
RTNH:RTNL ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (YH:YL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (XH:XL) ⇒ M(SP):M(SP+1);
(SP) – 2 ⇒ SP; (B:A) ⇒ M(SP):M(SP+1);
(SP) – 1 ⇒ SP; (CCR) ⇒ M(SP);
WAIT for interrupt
INH
3E
OSSSSsf
OSSSfSsf
––––
(A) – 0
(B) – 0
Test A for Zero or Minus
Test B for Zero or Minus
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
hh
xb
xb
xb
xb
xb
ll
ff
ee ff
ee ff
fVfPPP
––––
or
(after interrupt)
VfPPP
–––1
––––
or
–1–1
––––
S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
393
Table A-1. Instruction Set Summary (Sheet 14 of 14)
Source Form
WAV
Addr.
Mode
Operation
B
∑ Si Fi ⇒ Y:D
B
and
i=1
Special
Machine
Coding (hex)
18 3C
∑ Fi ⇒ X
Access Detail
HCS12
M68HC12
Of(frr,ffff)O
Off(frr,fffff)O
SXHI
NZVC
––?–
?∆??
––?–
?∆??
(add if interrupt)
i=1
SSS + UUUrr,
SSSf + UUUrr
UUUrr,ffff
(frr,ffff)O
UUUrrfffff
(frr,fffff)O
Calculate Sum of Products and Sum of Weights for Weighted
Average Calculation
Initialize B, X, and Y before WAV. B specifies number of elements. X points at first element in Si list. Y points at first element in Fi list.
All Si and Fi elements are 8-bits.
If interrupted, six extra bytes of stack used for
intermediate values
wavr
see WAV
pseudoinstruction
Resume executing an interrupted WAV instruction (recover intermediate results from stack rather than initializing them to
zero)
XGDX
(D) ⇔ (X)
Translates to EXG D, X
INH
B7 C5
P
P
––––
––––
XGDY
(D) ⇔ (Y)
Translates to EXG D, Y
INH
B7 C6
P
P
––––
––––
Special
3C
(exit + re-entry replaces comma
above if interrupted)
SSS + UUUrr,
SSSf + UUUrr
S12CPUV2 Reference Manual, Rev. 4.0
394
Freescale Semiconductor
Freescale Semiconductor
Table A-2. CPU12 Opcode Map (Sheet 1 of 2)
00
†5 10
BGND
IH
01
1 IM
5 11
MEM
IH
02
EDIV
INY
DEY
loop
EMUL
S12CPUV2 Reference Manual, Rev. 4.0
JMP
JMP
3 EX
4 17
BSR
2 DI
1 18
INX
DEX
RTC
BVS
BPL
BCLR
BRCLR
BRCLR
4-6 EX
wavr
RTS
2 IH
3/1 3E
WAI
SWI
2 IH
BCLR
ROR
BRCLR
4 DI
ROR
2-4 EX
3-6 77
ASR
1 ID
1 68
ASR
2-4 EX
3-6 78
ASL
1 ID
1 69
ASL
2-4 EX
‡2-4 79
CLR
1 ID
2 6A
CLR
2-4 EX
‡2-4 7A
STAA
2 ID
2 6B
STAA
2-4 EX
‡2-4 7B
STAB
2 ID
2 6C
STAB
2-4 EX
‡2-4 7C
STD
2 ID
2 6D
STD
2-4 EX
‡2-4 7D
STY
2 ID
2 6E
STX
4 DI
4 5F
ROL
2-4 EX
3-6 76
1 ID
1 67
STY
3 DI
4 5E
BRSET
1 DI
ROL
STD
3 DI
4 5D
LSR
2-4 EX
3-6 75
1 ID
1 66
STAB
2-5 DI
4 5C
BSET
1 DI
9 4F
LSR
STAA
CALL
DEC
2-4 EX
3-6 74
1 ID
1 65
ASLD
1 IH
‡7 5A
CALL
1 DI
‡†7 4E
2 IH
3/1 3F
BLE
5 RL
LSRD
1 DI
5 4D
DEC
ASLB
1 IH
1 59
INC
2-4 EX
3-6 73
1 ID
1 64
ASRB
1 IH
1 58
ASLA
1 ID
‡+5 4C
2 SP
3/1 3D
BGT
5 RL
5 2F
ASRA
1 EX
4 DI
2 4B ‡7-10 5B
PSHD
INC
RORB
1 IH
1 57
COM
2-4 EX
3-6 72
1 ID
1 63
ROLB
1 IH
1 56
RORA
1 IH
3 4A
PULD
BLT
4 RL
5 2E
ROLA
1 IH
2 49
PSHC
BGE
BRSET
4-6 EX
‡4-6 1F
PULC
COM
LSRB
1 IH
1 55
1 IH
3 48
2 IH
3/1 3C
4 RL
4 2D
BCLR
3-5 EX
‡4-6 1E
BRSET
BMI
BSET
PSHB
2 IH
3/1 3B
2-4 RL
4 2C
LSRA
STY
2-4 EX
‡2-4 7E
STX
2 ID
2 6F
STS
STX
2-4 EX
‡2-4 7F
STS
2 ID
4 80
NEG
2-4 EX
3-6 71
1 ID
1 62
DECB
1 IH
1 54
1 IH
2 47
2 IH
3/1 3A
2-4 RL
2 2B
3-5 EX
4-6 1D
PSHA
2 IH
3/1 39
2-4 RL
2 2A
LEAS
1 ID
4-6 1C
BSET
ID
BVC
DECA
1 IH
2 46
2 IH
3/1 38
- RL
2 29
LEAX
1 ID
†8 1B
RTI
ID
0F
BEQ
LEAY
1 ID
‡7 1A
PSHY
1 ID
1 61
INCB
1 IH
1 53
1 IH
2 45
2 IH
3/1 37
2 RL
- 28
1 1 19
IH
0A
ID
0D
BNE
Page 2
IH
09
PSHX
2 IH
3/1 36
3 RL
4 27
JSR
RL
08
IH
0C
BCS
INCA
3-6 70
NEG
COMB
1 IH
1 52
1 IH
2 44
2 IH
3/1 35
2-4 RL
4 26
JSR
EX
07
IH
0B
BCC
JSR
2-4 ID
3 16
PULB
2 IH
3/1 34
2 RL
4-7 25
COMA
1 IH
3 43
1 60
NEGB
1 IH
1 51
1 IH
3 42
PULA
BLS
ORCC
PULY
2 IH
3/1 33
1 RL
1 24
3 IM
3-6 15
ID
06
BHI
1 50
NEGA
1 IH
3 41
2 IH
3/1 32
1 RL
3 23
1 IH
3 14
*
RL
05
BRN
MUL
3 40
PULX
2 IH
1 31
1 RL
‡1 22
1 IH
1 13
IH
04
3 30
BRA
2 RL
11 21
1 IH
1 12
IH
03
ID
0E
1 20
ANDCC
STS
2-4 EX
SUBA
3 IM
4 81
CMPA
3 IM
4 82
SBCA
3 IM
4 83
SUBD
3 IM
4 84
ANDA
3 IM
4 85
1 90
SUBA
2 DI
1 91
CMPA
2 DI
1 92
SBCA
2 DI
2 93
SUBD
3 DI
1 94
ANDA
2 DI
1 95
BITA
3 IM
4 86
LDAA
3 IM
4 87
CLRA
3 IH
4 88
EORA
3 IM
3 89
ADCA
3 IM
3 8A
ORAA
3 IM
3 8B
ADDA
3 IM
3 8C
LDAA
2 DI
1 97
TSTA
1 IH
1 98
EORA
2 DI
1 99
ADCA
2 DI
1 9A
ORAA
2 DI
1 9B
ADDA
2 DI
2 9C
CPY
3 IM
3 8E
CPX
3 DI
2 9F
CPS
3 IM
CPS
3 DI
CPX
2-4 EX
3-6 BF
CPS
2 ID
LDAB
3 IM
1 C7
CLRB
2 IH
3 C8
EORB
3 IM
3 C9
ADCB
3 IM
3 CA
ORAB
3 IM
3 CB
ADDB
3 IM
3 CC
CPS
2-4 EX
1 D0
SUBB
2 DI
1 D1
CMPB
2 DI
1 D2
SBCB
2 DI
2 D3
ADDD
3 DI
1 D4
ANDB
2 DI
1 D5
BITB
2 DI
1 D6
LDAB
2 DI
1 D7
EORB
2 DI
1 D9
ADCB
2 DI
1 DA
ORAB
2 DI
1 DB
ADDB
2 DI
2 DC
LDX
3 IM
3 CF
LDS
3 DI
Key to Table A-2
395
Opcode
Mnemonic
Address Mode
00
5
Number of HCS12 cycles (‡ indicates HC12 different)
I
Number of bytes
BGND
IH
3
3
LDX
2-4 EX
3-6 FF
LDS
2 ID
3
3
LDY
2-4 EX
3-6 FE
LDX
2 ID
3 EF
3
3
LDD
2-4 EX
3-6 FD
LDY
2 ID
3 EE
3
3
ADDB
2-4 EX
3-6 FC
LDD
2 ID
3 ED
3
3
ORAB
2-4 EX
3-6 FB
ADDB
2 ID
3 EC
3
3
ADCB
2-4 EX
3-6 FA
ORAB
2 ID
3 EB
3
3
EORB
2-4 EX
3-6 F9
ADCB
2 ID
3 EA
3
3
TST
2-4 EX
3-6 F8
EORB
2 ID
3 E9
3
3
LDAB
2-4 EX
3-6 F7
TST
1 ID
3 E8
3
3
BITB
2-4 EX
3-6 F6
LDAB
2 ID
1 E7
3
3
ANDB
2-4 EX
3-6 F5
BITB
2 ID
3 E6
3
3
ADDD
2-4 EX
3-6 F4
ANDB
2 ID
3 E5
3
3
SBCB
2-4 EX
3-6 F3
ADDD
2 ID
3 E4
3
3
CMPB
2-4 EX
3-6 F2
SBCB
2 ID
3 E3
3
SUBB
2-4 EX
3-6 F1
CMPB
2 ID
3 E2
LDX
3 DI
2 DF
LDS
3 IM
2 ID
3 E1
LDY
3 DI
2 DE
3-6 F0
SUBB
LDD
3 DI
2 DD
LDY
3 IM
3 CE
3 E0
TSTB
1 IH
1 D8
LDD
3 IM
3 CD
CPY
2-4 EX
3-6 BE
CPX
2 ID
3 AF
CPD
2-4 EX
3-6 BD
CPY
2 ID
3 AE
ADDA
2-4 EX
3-6 BC
CPD
2 ID
3 AD
ORAA
2-4 EX
3-6 BB
ADDA
2 ID
3 AC
ADCA
2-4 EX
3-6 BA
ORAA
2 ID
3 AB
EORA
2-4 EX
3-6 B9
ADCA
2 ID
3 AA
BITB
3 IM
3 C6
TFR/EXG
1 IH
3-6 B8
EORA
2 ID
3 A9
ANDB
3 IM
3 C5
LDAA
2-4 EX
1 B7
NOP
1 IH
3 A8
ADDD
3 IM
3 C4
BITA
2-4 EX
3-6 B6
LDAA
2 ID
1 A7
SBCB
3 IM
3 C3
ANDA
2-4 EX
3-6 B5
BITA
2 ID
3 A6
CMPB
3 IM
3 C2
SUBD
2-4 EX
3-6 B4
ANDA
2 ID
3 A5
3 IM
3 C1
SBCA
2-4 EX
3-6 B3
SUBD
2 ID
3 A4
SUBB
CMPA
2-4 EX
3-6 B2
SBCA
2 ID
3 A3
3 C0
SUBA
2-4 EX
3-6 B1
CMPA
2 ID
3 A2
CPY
3 DI
2 9E
CPX
3 IM
3 8F
2 ID
3 A1
CPD
3 DI
2 9D
3-6 B0
SUBA
BITA
2 DI
1 96
CPD
3 IM
3 8D
3 A0
3
3
LDS
2-4 EX
3
396
Table A-2. CPU12 Opcode Map (Sheet 2 of 2)
00
4 10
MOVW
IM-ID
01
MOVW
4 30
12 20
IDIV
5 IH
5 11
LBRA
2 RL
12 21
FDIV
4 IH
3 31
LBRN
EX-ID
02
MOVW
MOVW
EX-EX
05
MOVW
S12CPUV2 Reference Manual, Rev. 4.0
ID-EX
06
EMULS
6 IH
6 14
EDIVS
6 IH
5 15
IDIVS
SBA
2 IH
3 17
DAA
IH
08
MOVB
IM-ID
09
MOVB
EX-ID
0A
MOVB
ID-ID
0B
MOVB
IM-EX
0C
MOVB
EX-EX
0D
MOVB
Freescale Semiconductor
ID-EX
0E
TAB
IH
0F
TBA
IH
CBA
2 IH
4 18
MAXA
4 ID
5 19
MINA
5 ID
5 1A
EMAXD
4 ID
4 1B
MAXM
6 ID
5 1D
EMINM
2 ID
REVW
WAV
4 SP
4/3 3D
TBL
4 ID
4/3 3E
ETBL
4 ID
TRAP
3 IH
TRAP
2 IH
TRAP
2 IH
TRAP
2 IH
TRAP
2 IH
TRAP
2 IH
TRAP
2 IH
10 AF
TRAP
2 IH
TRAP
2 IH
10 CF
TRAP
2 IH
2
10
TRAP
2 IH
10 FF
TRAP
2 IH
2
10
TRAP
2 IH
10 FE
TRAP
2 IH
10 EF
2
10
TRAP
2 IH
10 FD
TRAP
2 IH
10 EE
TRAP
2 IH
10 DF
TRAP
2 IH
TRAP
2 IH
10 DE
2
10
TRAP
2 IH
10 FC
TRAP
2 IH
10 ED
2
10
TRAP
2 IH
10 FB
TRAP
2 IH
10 EC
TRAP
2 IH
10 DD
TRAP
2 IH
10 CE
TRAP
2 IH
10 BF
TRAP
2 IH
TRAP
2 IH
10 BE
TRAP
2 IH
10 CD
TRAP
2 IH
10 DC
2
10
TRAP
2 IH
10 FA
TRAP
2 IH
10 EB
2
10
TRAP
2 IH
10 F9
TRAP
2 IH
10 EA
TRAP
2 IH
10 DB
TRAP
2 IH
10 CC
TRAP
2 IH
10 BD
TRAP
2 IH
10 AE
TRAP
2 IH
10 9F
TRAP
2 IH
10 AD
TRAP
2 IH
10 9E
TRAP
2 IH
10 8F
TRAP
2 IH
10 9D
TRAP
2 IH
10 8E
TRAP
2 IH
10 7F
TRAP
2 IH
10 8D
TRAP
2 IH
10 7E
TRAP
2 IH
10 6F
TRAP
2 IH
10 7D
TRAP
2 IH
10 6E
TRAP
2 IH
10 5F
TRAP
2 IH
10 6D
TRAP
2 IH
10 5E
TRAP
2 IH
10 4F
TRAP
2 IH
10 5D
TRAP
3 IH
‡8 4E
STOP
4 IH
4/3 3F
LBLE
3-5 RL
TRAP
TRAP
2 IH
10 BC
TRAP
2 IH
10 CB
TRAP
2 IH
10 DA
2
10
TRAP
2 IH
10 F8
TRAP
2 IH
10 E9
2
10
TRAP
2 IH
10 F7
TRAP
2 IH
10 E8
TRAP
2 IH
10 D9
TRAP
2 IH
10 CA
TRAP
2 IH
10 BB
TRAP
2 IH
10 AC
TRAP
2 IH
10 BA
TRAP
2 IH
10 AB
TRAP
2 IH
10 9C
TRAP
2 IH
10 AA
TRAP
2 IH
10 9B
TRAP
2 IH
10 8C
TRAP
2 IH
10 9A
TRAP
2 IH
10 8B
TRAP
2 IH
10 7C
TRAP
2 IH
10 8A
TRAP
2 IH
10 7B
TRAP
2 IH
10 6C
TRAP
2 IH
10 7A
TRAP
2 IH
10 6B
TRAP
2 IH
10 5C
TRAP
2 IH
10 6A
TRAP
2 IH
10 5B
TRAP
2 IH
‡6 4D
TRAP
2 IH
10 5A
TRAP
4 SP
2 IH
4/3 3C ‡†7B 4C
LBGT
3-5 RL
4-7 2F
TRAP
2 IH
†3n 4A
REV
LBLT
3-5 RL
4-7 2E
EMAXM
2 ID
2 1F
TRAP
TRAP
2 IH
10 C9
TRAP
2 IH
10 D8
2
10
TRAP
2 IH
10 F6
TRAP
2 IH
10 E7
2
10
TRAP
2 IH
10 F5
TRAP
2 IH
10 E6
TRAP
2 IH
10 D7
TRAP
2 IH
10 C8
TRAP
2 IH
10 B9
TRAP
2 IH
10 C7
TRAP
2 IH
10 B8
TRAP
2 IH
10 A9
TRAP
2 IH
10 B7
TRAP
2 IH
10 A8
TRAP
2 IH
10 99
TRAP
2 IH
10 A7
TRAP
2 IH
10 98
TRAP
2 IH
10 89
TRAP
2 IH
10 97
TRAP
2 IH
10 88
TRAP
2 IH
10 79
TRAP
2 IH
10 87
TRAP
2 IH
10 78
TRAP
2 IH
10 69
TRAP
2 IH
10 77
TRAP
2 IH
10 68
TRAP
2 IH
10 59
TRAP
2 IH
10 67
TRAP
2 IH
10 58
TRAP
2 IH
10 49
4 SP
2 IH
4/3 3B †5n/3n 4B
LBGE
3-5 RL
D4-7 2D
MINM
5 ID
2 1E
TRAP
TRAP
2 IH
10 57
TRAP
2 IH
10 48
4 IH
4/3 3A
LBMI
3-5 RL
4-7 2C
TRAP
2 IH
10 47
TRAP
LBPL
3-5 RL
4-7 2B
EMIND
5 ID
6 1C
TRAP
TRAP
2 IH
10 D6
2
10
TRAP
2 IH
10 F4
TRAP
2 IH
10 E5
2
10
TRAP
2 IH
10 F3
TRAP
2 IH
10 E4
TRAP
2 IH
10 D5
TRAP
2 IH
10 C6
TRAP
2 IH
10 D4
TRAP
2 IH
10 C5
TRAP
2 IH
10 B6
TRAP
2 IH
10 C4
TRAP
2 IH
10 B5
TRAP
2 IH
10 A6
TRAP
2 IH
10 B4
TRAP
2 IH
10 A5
TRAP
2 IH
10 96
TRAP
2 IH
10 A4
TRAP
2 IH
10 95
TRAP
2 IH
10 86
TRAP
2 IH
10 94
TRAP
2 IH
10 85
TRAP
2 IH
10 76
TRAP
2 IH
10 84
TRAP
2 IH
10 75
TRAP
2 IH
10 66
TRAP
2 IH
10 74
TRAP
2 IH
10 65
TRAP
2 IH
10 56
TRAP
2 IH
10 64
TRAP
2 IH
10 55
TRAP
2 IH
10 46
4 IH
4/3 39
LBVS
3-5 RL
4-7 2A
TRAP
TRAP
2 IH
10 54
TRAP
2 IH
10 45
4 IH
4/3 38
LBVC
3-5 RL
4-7 29
TRAP
4 IH
4/3 37
LBEQ
2 RL
4-7 28
TRAP
2 IH
10 44
4 IH
4/3 36
LBNE
2 RL
2 27
TRAP
2
10
TRAP
2 IH
10 F2
TRAP
2 IH
10 E3
10
TRAP
2 IH
10 F1
TRAP
2 IH
10 E2
TRAP
2 IH
10 D3
10 F0
TRAP
2 IH
10 E1
TRAP
2 IH
10 D2
TRAP
2 IH
10 C3
10 E0
TRAP
2 IH
10 D1
TRAP
2 IH
10 C2
TRAP
2 IH
10 B3
10 D0
TRAP
2 IH
10 C1
TRAP
2 IH
10 B2
TRAP
2 IH
10 A3
10 C0
TRAP
2 IH
10 B1
TRAP
2 IH
10 A2
TRAP
2 IH
10 93
10 B0
TRAP
2 IH
10 A1
TRAP
2 IH
10 92
TRAP
2 IH
10 83
10 A0
TRAP
2 IH
10 91
TRAP
2 IH
10 82
TRAP
2 IH
10 73
10 90
TRAP
2 IH
10 81
TRAP
2 IH
10 72
TRAP
2 IH
10 63
10 80
TRAP
2 IH
10 71
TRAP
2 IH
10 62
TRAP
2 IH
10 53
10 70
TRAP
2 IH
10 61
TRAP
2 IH
10 52
TRAP
2 IH
10 43
4 IH
4/3 35
LBCS
2 RL
2 26
TRAP
IH
33
10 60
TRAP
2 IH
10 51
TRAP
2 IH
10 42
4 IH
4/3 34
LBCC
2 RL
12 25
5 IH
2 16
ABA
IH
07
LBLS
2 RL
12 24
IH
32
10 50
TRAP
2 IH
10 41
TRAP
5 IH
2 RL
4
5 12
13 22
4/3
MOVW EMACS
LBHI
4 RL
ID-ID
4 SP
4
03
5 13
3 23
4/3
IM-EX
04
10 40
TRAP
2
10
TRAP
2 IH
2
* The opcode $04 (on sheet 1 of 2) corresponds to one of the loop primitive instructions DBEQ, DBNE, IBEQ, IBNE, TBEQ, or TBNE.
† Refer to instruction summary for more information.
‡ Refer to instruction summary for different HC12 cycle count.
Page 2: When the CPU encounters a page 2 opcode ($18 on page 1 of the opcode map), it treats the next byte of object code as a page 2 instruction opcode.
Freescale Semiconductor
Table A-3. Indexed Addressing Mode Postbyte Encoding (xb)
S12CPUV2 Reference Manual, Rev. 4.0
00
10
20
30
40
50
60
70
80
0,X
5b const
01
1,X
5b const
02
2,X
5b const
03
3,X
5b const
04
4,X
5b const
05
5,X
5b const
06
6,X
5b const
07
7,X
5b const
08
8,X
5b const
09
9,X
5b const
0A
10,X
5b const
0B
11,X
5b const
0C
12,X
5b const
0D
13,X
5b const
0E
14,X
5b const
0F
15,X
5b const
–16,X
5b const
11
–15,X
5b const
12
–14,X
5b const
13
–13,X
5b const
14
–12,X
5b const
15
–11,X
5b const
16
–10,X
5b const
17
–9,X
5b const
18
–8,X
5b const
19
–7,X
5b const
1A
–6,X
5b const
1B
–5,X
5b const
1C
–4,X
5b const
1D
–3,X
5b const
1E
–2,X
5b const
1F
–1,X
5b const
1,+X
pre-inc
21
2,+X
pre-inc
22
3,+X
pre-inc
23
4,+X
pre-inc
24
5,+X
pre-inc
25
6,+X
pre-inc
26
7,+X
pre-inc
27
8,+X
pre-inc
28
8,–X
pre-dec
29
7,–X
pre-dec
2A
6,–X
pre-dec
2B
5,–X
pre-dec
2C
4,–X
pre-dec
2D
3,–X
pre-dec
2E
2,–X
pre-dec
2F
1,–X
pre-dec
1,X+
post-inc
31
2,X+
post-inc
32
3,X+
post-inc
33
4,X+
post-inc
34
5,X+
post-inc
35
6,X+
post-inc
36
7,X+
post-inc
37
8,X+
post-inc
38
8,X–
post-dec
39
7,X–
post-dec
3A
6,X–
post-dec
3B
5,X–
post-dec
3C
4,X–
post-dec
3D
3,X–
post-dec
3E
2,X–
post-dec
3F
1,X–
post-dec
0,Y
5b const
41
1,Y
5b const
42
2,Y
5b const
43
3,Y
5b const
44
4,Y
5b const
45
5,Y
5b const
46
6,Y
5b const
47
7,Y
5b const
48
8,Y
5b const
49
9,Y
5b const
4A
10,Y
5b const
4B
11,Y
5b const
4C
12,Y
5b const
4D
13,Y
5b const
4E
14,Y
5b const
4F
15,Y
5b const
–16,Y
5b const
51
–15,Y
5b const
52
–14,Y
5b const
53
–13,Y
5b const
54
–12,Y
5b const
55
–11,Y
5b const
56
–10,Y
5b const
57
–9,Y
5b const
58
–8,Y
5b const
59
–7,Y
5b const
5A
–6,Y
5b const
5B
–5,Y
5b const
5C
–4,Y
5b const
5D
–3,Y
5b const
5E
–2,Y
5b const
5F
–1,Y
5b const
1,+Y
pre-inc
61
2,+Y
pre-inc
62
3,+Y
pre-inc
63
4,+Y
pre-inc
64
5,+Y
pre-inc
65
6,+Y
pre-inc
66
7,+Y
pre-inc
67
8,+Y
pre-inc
68
8,–Y
pre-dec
69
7,–Y
pre-dec
6A
6,–Y
pre-dec
6B
5,–Y
pre-dec
6C
4,–Y
pre-dec
6D
3,–Y
pre-dec
6E
2,–Y
pre-dec
6F
1,–Y
pre-dec
1,Y+
post-inc
71
2,Y+
post-inc
72
3,Y+
post-inc
73
4,Y+
post-inc
74
5,Y+
post-inc
75
6,Y+
post-inc
76
7,Y+
post-inc
77
8,Y+
post-inc
78
8,Y–
post-dec
79
7,Y–
post-dec
7A
6,Y–
post-dec
7B
5,Y–
post-dec
7C
4,Y–
post-dec
7D
3,Y–
post-dec
7E
2,Y–
post-dec
7F
1,Y–
post-dec
0,SP
5b const
81
1,SP
5b const
82
2,SP
5b const
83
3,SP
5b const
84
4,SP
5b const
85
5,SP
5b const
86
6,SP
5b const
87
7,SP
5b const
88
8,SP
5b const
89
9,SP
5b const
8A
10,SP
5b const
8B
11,SP
5b const
8C
12,SP
5b const
8D
13,SP
5b const
8E
14,SP
5b const
8F
15,SP
5b const
90
–16,SP
5b const
91
–15,SP
5b const
92
–14,SP
5b const
93
–13,SP
5b const
94
–12,SP
5b const
95
–11,SP
5b const
96
–10,SP
5b const
97
–9,SP
5b const
98
–8,SP
5b const
99
–7,SP
5b const
9A
–6,SP
5b const
9B
–5,SP
5b const
9C
–4,SP
5b const
9D
–3,SP
5b const
9E
–2,SP
5b const
9F
–1,SP
5b const
A0
1,+SP
pre-inc
A1
2,+SP
pre-inc
A2
3,+SP
pre-inc
A3
4,+SP
pre-inc
A4
5,+SP
pre-inc
A5
6,+SP
pre-inc
A6
7,+SP
pre-inc
A7
8,+SP
pre-inc
A8
8,–SP
pre-dec
A9
7,–SP
pre-dec
AA
6,–SP
pre-dec
AB
5,–SP
pre-dec
AC
4,–SP
pre-dec
AD
3,–SP
pre-dec
AE
2,–SP
pre-dec
AF
1,–SP
pre-dec
B0
1,SP+
post-inc
B1
2,SP+
post-inc
B2
3,SP+
post-inc
B3
4,SP+
post-inc
B4
5,SP+
post-inc
B5
6,SP+
post-inc
B6
7,SP+
post-inc
B7
8,SP+
post-inc
B8
8,SP–
post-dec
B9
7,SP–
post-dec
BA
6,SP–
post-dec
BB
5,SP–
post-dec
BC
4,SP–
post-dec
BD
3,SP–
post-dec
BE
2,SP–
post-dec
BF
1,SP–
post-dec
Key to Table A-3
postbyte (hex)
B0
#,REG
type
397
type offset used
source code syntax
C0
0,PC
5b const
C1
1,PC
5b const
C2
2,PC
5b const
C3
3,PC
5b const
C4
4,PC
5b const
C5
5,PC
5b const
C6
6,PC
5b const
C7
7,PC
5b const
C8
8,PC
5b const
C9
9,PC
5b const
CA
10,PC
5b const
CB
11,PC
5b const
CC
12,PC
5b const
CD
13,PC
5b const
CE
14,PC
5b const
CF
15,PC
5b const
D0
–16,PC
5b const
D1
–15,PC
5b const
D2
–14,PC
5b const
D3
–13,PC
5b const
D4
–12,PC
5b const
D5
–11,PC
5b const
D6
–10,PC
5b const
D7
–9,PC
5b const
D8
–8,PC
5b const
D9
–7,PC
5b const
DA
–6,PC
5b const
DB
–5,PC
5b const
DC
–4,PC
5b const
DD
–3,PC
5b const
DE
–2,PC
5b const
DF
–1,PC
5b const
E0
F0
n,X
9b const
E1
–n,X
9b const
E2
n,X
16b const
E3
[n,X]
16b indr
E4
A,X
A offset
E5
B,X
B offset
E6
D,X
D offset
E7
[D,X]
D indirect
E8
n,Y
9b const
E9
–n,Y
9b const
EA
n,Y
16b const
EB
[n,Y]
16b indr
EC
A,Y
A offset
ED
B,Y
B offset
EE
D,Y
D offset
EF
[D,Y]
D indirect
n,SP
9b const
F1
–n,SP
9b const
F2
n,SP
16b const
F3
[n,SP]
16b indr
F4
A,SP
A offset
F5
B,SP
B offset
F6
D,SP
D offset
F7
[D,SP]
D indirect
F8
n,PC
9b const
F9
–n,PC
9b const
FA
n,PC
16b const
FB
[n,PC]
16b indr
FC
A,PC
A offset
FD
B,PC
B offset
FE
D,PC
D offset
FF
[D,PC]
D indirect
Table A-4. Indexed Addressing Mode Summary
Postbyte
Code (xb)
Operand
Syntax
Comments
rr0nnnnn
,r
n,r
–n,r
5-bit constant offset
n = –16 to +15
rr can specify X, Y, SP, or PC
111rr0zs
n,r
–n,r
Constant offset (9- or 16-bit signed)
z- 0 = 9-bit with sign in LSB of postbyte (s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
rr1pnnnn
n,–r
n,+r
n,r–
n,r+
Auto predecrement, preincrement, postdecrement, or postincrement;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
111rr1aa
A,r
B,r
D,r
Accumulator offset (unsigned 8-bit or 16-bit)
aa - 00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
111rr011
[n,r]
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
111rr111
[D,r]
Accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
S12CPUV2 Reference Manual, Rev. 4.0
398
Freescale Semiconductor
Freescale Semiconductor
Table A-5. Transfer and Exchange Postbyte Encoding
TRANSFERS
⇓ LS
MS⇒
0
1
2
3
4
5
6
7
0
A⇒A
B⇒A
CCR ⇒ A
TMP3L ⇒ A
B⇒A
XL ⇒ A
YL ⇒ A
SPL ⇒ A
1
A⇒B
B⇒B
CCR ⇒ B
TMP3L ⇒ B
B⇒B
XL ⇒ B
YL ⇒ B
SPL ⇒ B
2
A ⇒ CCR
B ⇒ CCR
CCR ⇒ CCR
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
TMP3 ⇒ TMP2
D ⇒ TMP2
X ⇒ TMP2
Y ⇒ TMP2
SP ⇒ TMP2
sex:A ⇒ TMP2 sex:B ⇒ TMP2 sex:CCR ⇒ TMP2
3
S12CPUV2 Reference Manual, Rev. 4.0
4
sex:A ⇒ D
SEX A,D
sex:B ⇒ D
SEX B,D
sex:CCR ⇒ D
SEX CCR,D
TMP3 ⇒ D
D⇒D
X⇒D
Y⇒D
SP ⇒ D
5
sex:A ⇒ X
SEX A,X
sex:B ⇒ X
SEX B,X
sex:CCR ⇒ X
SEX CCR,X
TMP3 ⇒ X
D⇒X
X⇒X
Y⇒X
SP ⇒ X
6
sex:A ⇒ Y
SEX A,Y
sex:B ⇒ Y
SEX B,Y
sex:CCR ⇒ Y
SEX CCR,Y
TMP3 ⇒ Y
D⇒Y
X⇒Y
Y⇒Y
SP ⇒ Y
7
sex:A ⇒ SP
SEX A,SP
sex:B ⇒ SP
SEX B,SP
sex:CCR ⇒ SP
SEX CCR,SP
TMP3 ⇒ SP
D ⇒ SP
X ⇒ SP
Y ⇒ SP
SP ⇒ SP
EXCHANGES
⇓ LS
MS⇒
8
9
A
B
C
D
E
F
B⇒A
A⇒B
XL ⇒ A
$00:A ⇒ X
YL ⇒ A
$00:A ⇒ Y
SPL ⇒ A
$00:A ⇒ SP
B⇒B
$FF ⇒ A
XL ⇒ B
$FF:B ⇒ X
YL ⇒ B
$FF:B ⇒ Y
SPL ⇒ B
$FF:B ⇒ SP
0
A⇔A
B⇔A
CCR ⇔ A
TMP3L ⇒ A
$00:A ⇒ TMP3
1
A⇔B
B⇔B
CCR ⇔ B
TMP3L ⇒ B
$FF:B ⇒ TMP3
2
A ⇔ CCR
B ⇔ CCR
CCR ⇔ CCR
3
4
$00:A ⇒ TMP2 $00:B ⇒ TMP2 $00:CCR ⇒ TMP2
TMP2L ⇒ A
TMP2L ⇒ B
TMP2L ⇒ CCR
$00:CCR ⇒ D
$00:A ⇒ D
$00:B ⇒ D
B ⇒ CCR
TMP3L ⇒ CCR
B ⇒ CCR
XL ⇒ CCR
YL ⇒ CCR
SPL ⇒ CCR
$FF:CCR ⇒ TMP3 $FF:CCR ⇒ D $FF:CCR ⇒ X $FF:CCR ⇒ Y $FF:CCR ⇒ SP
TMP3 ⇔ TMP2
D ⇔ TMP2
X ⇔ TMP2
Y ⇔ TMP2
SP ⇔ TMP2
TMP3 ⇔ D
D⇔D
X⇔D
Y⇔D
SP ⇔ D
5
$00:A ⇒ X
XL ⇒ A
$00:B ⇒ X
XL ⇒ B
$00:CCR ⇒ X
XL ⇒ CCR
TMP3 ⇔ X
D⇔X
X⇔X
Y⇔X
SP ⇔ X
6
$00:A ⇒ Y
YL ⇒ A
$00:B ⇒ Y
YL ⇒ B
$00:CCR ⇒ Y
YL ⇒ CCR
TMP3 ⇔ Y
D⇔Y
X⇔Y
Y⇔Y
SP ⇔ Y
7
$00:A ⇒ SP
SPL ⇒ A
$00:B ⇒ SP
SPL ⇒ B
$00:CCR ⇒ SP
SPL ⇒ CCR
TMP3 ⇔ SP
D ⇔ SP
X ⇔ SP
Y ⇔ SP
SP ⇔ SP
TMP2 and TMP3 registers are for factory use only.
399
Table A-6. Loop Primitive Postbyte Encoding (lb)
00
A 10
DBEQ
A 20
DBEQ
(+)
(–)
01
(+)
(–)
02
(+)
12
—
—
03
D 14
04
DBEQ
D 24
DBEQ
(+)
(–)
05
(+)
(–)
06
DBNE
(+)
Y 16
TBEQ
(–)
Y 26
TBNE
(+)
Y 56
(–)
Y 66
(+)
Y 76
X B5
IBNE
(–)
Y 86
(–)
X A5
IBEQ
X
IBNE
(+)
Y 96
D
IBNE
(+)
X 95
IBEQ
D B4
IBNE
(–)
X 85
—
D A4
IBEQ
(+)
X 75
TBNE
(–)
Y 46
(–)
X 65
TBEQ
(+)
Y 36
(+)
X 55
B3
—
D 94
IBEQ
—
A3
—
D 84
TBNE
B2
—
93
—
D 74
TBNE
(–)
X 45
83
—
D 64
TBEQ
(+)
X 35
DBNE
D 54
TBEQ
(–)
X 25
DBEQ
D 44
DBNE
(+)
X 15
DBEQ
D 34
DBNE
73
—
(–)
A2
—
B
IBNE
(+)
92
—
B B1
IBNE
(–)
82
—
63
—
(+)
72
—
53
—
(–)
62
—
43
—
(+)
52
—
33
—
(–)
42
—
23
—
(+)
32
—
13
—
(–)
22
(–)
B A1
IBEQ
A
IBNE
(+)
B 91
IBEQ
A B0
IBNE
(–)
B 81
TBNE
A A0
IBEQ
(+)
B 71
TBNE
A 90
IBEQ
(–)
B 61
TBEQ
A 80
TBNE
(+)
B 51
TBEQ
A 70
TBNE
(–)
B 41
DBNE
A 60
TBEQ
(+)
B 31
DBNE
A 50
TBEQ
(–)
B 21
DBEQ
A 40
DBNE
(+)
B 11
DBEQ
A 30
DBNE
(–)
Y A6
Y B6
Y
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
IBEQ
IBNE
IBNE
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
07
SP 17
SP 27
SP 37
SP 47
SP 57
SP 67
SP 77
SP 87
SP 97
SP A7
SP B7
SP
DBEQ
DBEQ
DBNE
DBNE
TBEQ
TBEQ
TBNE
TBNE
IBEQ
IBEQ
IBNE
IBNE
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
Key to Table A-6
postbyte (hex)
(bit 3 is don’t care)
counter used
B0
A
_BEQ
(–)
branch condition
sign of 9-bit relative branch offset
(lower eight bits are an extension byte
following postbyte)
Table A-7. Branch/Complementary Branch
Branch
Test
Mnemonic
Opcode
Boolean
Test
r≤m
r>m
BGT
2E
Z + (N ⊕ V) = 0
r<m
r≥m
BGE
2C
N⊕V=0
r=m
BEQ
27
Z=1
r≠m
r>m
r≤m
BLE
2F
Z + (N ⊕ V) = 1
r≥m
r<m
BLT
2D
N⊕V=1
r>m
BHI
22
C+Z=0
r≤m
r≥m
BHS/BCC
24
C=0
r<m
r=m
BEQ
27
Z=1
r≠m
r≤m
BLS
23
C+Z=1
r>m
r<m
BLO/BCS
25
C=1
r≥m
Carry
BCS
25
C=1
No Carry
Negative
BMI
2B
N=1
Plus
Overflow
BVS
29
V=1
No Overflow
r=0
BEQ
27
Z=1
r≠0
Always
BRA
20
—
Never
For 16-bit offset long branches precede opcode with a $18 page prebyte.
Complementary Branch
Mnemonic
Opcode
BLE
2F
BLT
2D
BNE
26
BGT
2E
BGE
2C
BLS
23
BLO/BCS
25
BNE
26
BHI
22
BHS/BCC
24
BCC
24
BPL
2A
BVC
28
BNE
26
BRN
21
Comment
Signed
Signed
Signed
Signed
Signed
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Simple
Simple
Simple
Simple
Unconditional
S12CPUV2 Reference Manual, Rev. 4.0
400
Freescale Semiconductor
Table A-8. Hexadecimal to ASCII Conversion
Hex
ASCII
Hex
ASCII
Hex
ASCII
Hex
ASCII
$00
NUL
$20
SP space
$40
@
$60
` grave
$01
SOH
$21
!
$41
A
$61
a
$02
STX
$22
“ quote
$42
B
$62
b
$03
ETX
$23
#
$43
C
$63
c
$04
EOT
$24
$
$44
D
$64
d
$05
ENQ
$25
%
$45
E
$65
e
$06
ACK
$26
&
$46
F
$66
f
$07
BEL beep
$27
‘ apost.
$47
G
$67
g
$08
BS back
sp
$28
(
$48
H
$68
h
$09
HT tab
$29
)
$49
I
$69
i
$0A
LF
linefeed
$2A
*
$4A
J
$6A
j
$0B
VT
$2B
+
$4B
K
$6B
k
$0C
FF
$2C
, comma
$4C
L
$6C
l
$0D
CR return
$2D
$4D
M
$6D
m
$0E
SO
$2E
- dash
. period
$4E
N
$6E
n
$0F
SI
$2F
/
$4F
O
$6F
o
$10
DLE
$30
0
$50
P
$70
p
$11
DC1
$31
1
$51
Q
$71
q
$12
DC2
$32
2
$52
R
$72
r
$13
DC3
$33
3
$53
S
$73
s
$14
DC4
$34
4
$54
T
$74
t
$15
NAK
$35
5
$55
U
$75
u
$16
SYN
$36
6
$56
V
$76
v
$17
ETB
$37
7
$57
W
$77
w
$18
CAN
$38
8
$58
X
$78
x
$19
EM
$39
9
$59
Y
$79
y
$1A
SUB
$3A
:
$5A
Z
$7A
z
$1B
ESCAPE
$3B
;
$5B
[
$7B
{
$1C
FS
$3C
<
$5C
\
$7C
|
$1D
GS
$3D
=
$5D
]
$7D
}
$1E
RS
$3E
>
$5E
^
$7E
~
$1F
US
$3F
?
$5F
_ under
$7F
DEL
delete
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A.5 Hexadecimal to Decimal Conversion
To convert a hexadecimal number (up to four hexadecimal digits) to
decimal, look up the decimal equivalent of each hexadecimal digit in Table
A-9. The decimal equivalent of the original hexadecimal number is the sum
of the weights found in the table for all hexadecimal digits.
Table A-9. Hexadecimal to/from Decimal Conversion
15
15
12
4th Hex Digit
Hex
Decimal
0
0
1
4,096
2
8,192
3
12,288
4
5
6
7
8
9
A
B
C
D
E
F
16,384
20,480
24,576
28,672
32,768
36,864
40,960
45,056
49,152
53,248
57,344
61,440
Bit
11
8
8
3rd Hex Digit
Hex
Decimal
0
0
1
256
2
512
3
768
4
5
6
7
8
9
A
B
C
D
E
F
1,024
1,280
1,536
1,792
2,048
2,304
2,560
2,816
3,072
3,328
3,484
3,840
7
7
Bit
4 3
2nd Hex Digit
Hex
Decimal
0
0
1
16
2
32
3
48
4
5
6
7
8
9
A
B
C
D
E
F
64
80
96
112
128
144
160
176
192
208
224
240
0
0
1st Hex Digit
Hex
Decimal
0
0
1
1
2
2
3
3
4
5
6
7
8
9
A
B
C
D
E
F
4
5
6
7
8
9
10
11
12
13
14
15
A.6 Decimal to Hexadecimal Conversion
To convert a decimal number (up to 65,53510) to hexadecimal, find the
largest decimal number in Table A-9 that is less than or equal to the number
you are converting. The corresponding hexadecimal digit is the most
significant hexadecimal digit of the result. Subtract the decimal number
found from the original decimal number to get the remaining decimal value.
Repeat the procedure using the remaining decimal value for each
subsequent hexadecimal digit.
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Reference Manual — S12CPUV2
Appendix B. M68HC11 to CPU12 Upgrade Path
B.1 Introduction
This appendix discusses similarities and differences between the CPU12
and the M68HC11 CPU. In general, the CPU12 is a proper superset of the
M68HC11. Significant changes have been made to improve the efficiency
and capabilities of the CPU12 without eliminating compatibility and
familiarity for the large community of M68HC11 programmers.
B.2 CPU12 Design Goals
The primary goals of the CPU12 design were:
•
Absolute source code compatibility with the M68HC11
•
Same programming model
•
Same stacking operations
•
Upgrade to 16-bit architecture
•
Eliminate extra byte/extra cycle penalty for using index register Y
•
Improve performance
•
Improve compatibility with high-level languages
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B.3 Source Code Compatibility
Every M68HC11 instruction mnemonic and source code statement can be
assembled directly with a CPU12 assembler with no modifications.
The CPU12 supports all M68HC11 addressing modes and includes several
new variations of indexed addressing mode. CPU12 instructions affect
condition code bits in the same way as M68HC11 instructions.
CPU12 object code is similar to but not identical to M68HC11 object code.
Some primary objectives, such as the elimination of the penalty for using Y,
could not be achieved without object code differences. While the object
code has been changed, the majority of the opcodes are identical to those
of the M6800, which was developed more than 20 years earlier.
The CPU12 assembler automatically translates a few M68HC11 instruction
mnemonics into functionally equivalent CPU12 instructions. For example,
the CPU12 does not have an increment stack pointer (INS) instruction, so
the INS mnemonic is translated to LEAS 1,S. The CPU12 does provide
single-byte DEX, DEY, INX, and INY instructions because the LEAX and
LEAY instructions do not affect the condition codes, while the M68HC11
instructions update the Z bit according to the result of the decrement or
increment.
Table B-1 shows M68HC11 instruction mnemonics that are automatically
translated into equivalent CPU12 instructions. This translation is performed
by the assembler so there is no need to modify an old M68HC11 program
to assemble it for the CPU12. In fact, the M68HC11 mnemonics can be used
in new CPU12 programs.
Table B-1. Translated M68HC11 Mnemonics
M68HC11
Mnemonic
ABX
ABY
Equivalent
CPU12 Instruction
Comments
LEAX B,X
LEAY B,Y
Since CPU12 has accumulator offset indexing,
ABX and ABY are rarely used in new CPU12
programs. ABX is one byte on M68HC11 but
ABY is two bytes. The LEA substitutes are two
bytes.
Continued on next page
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Table B-1. Translated M68HC11 Mnemonics (Continued)
M68HC11
Mnemonic
Equivalent
CPU12 Instruction
Comments
CLC
CLI
CLV
SEC
SEI
SEV
ANDCC #$FE
ANDCC #$EF
ANDCC #$FD
ORCC #$01
ORCC #$10
ORCC #$02
ANDCC and ORCC now allow more control
over the CCR, including the ability to set or
clear multiple bits in a single instruction. These
instructions take one byte each on M68HC11
while the ANDCC and ORCC equivalents take
two bytes each.
DES
INS
LEAS –1,S
LEAS 1,S
Unlike DEX and INX, DES and INS did not
affect CCR bits in the M68HC11, so the LEAS
equivalents in CPU12 duplicate the function of
DES and INS. These instructions are one byte
on M68HC11 and two bytes on CPU12.
TAP
TPA
TSX
TSY
TXS
TYS
XGDX
XGDY
TFR A,CCR
TFR CCR,A
TFR S,X
TFR S,Y
TFR X,S
TFR Y,S
EXG D,X
EXG D,Y
The M68HC11 has a small collection of specific
transfer and exchange instructions. CPU12
expanded this to allow transfer or exchange
between any two CPU registers. For all but TSY
and TYS (which take two bytes on either CPU),
the CPU12 transfer/exchange costs one extra
byte compared to the M68HC11. The substitute
instructions execute in one cycle rather than
two.
All of the translations produce the same amount of or slightly more object
code than the original M68HC11 instructions. However, there are offsetting
savings in other instructions. Y-indexed instructions in particular assemble
into one byte less object code than the same M68HC11 instruction.
The CPU12 has a 2-page opcode map, rather than the 4-page M68HC11
map. This is largely due to redesign of the indexed addressing modes. Most
of pages 2, 3, and 4 of the M68HC11 opcode map are required because
Y-indexed instructions use different opcodes than X-indexed instructions.
Approximately two-thirds of the M68HC11 page 1 opcodes are unchanged
in CPU12, and some M68HC11 opcodes have been moved to page 1 of the
CPU12 opcode map. Object code for each of the moved instructions is one
byte smaller than object code for the equivalent M68HC11 instruction.
Table B-2 shows instructions that assemble to one byte less object code on
the CPU12.
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Table B-2. Instructions with Smaller Object Code
Instruction
DEY
INY
Comments
Page 2 opcodes in M68HC11 but page 1 in CPU12
INST n,Y
For values of n less than 16 (the majority of cases). Were on page 2,
now are on page 1. Applies to BSET, BCLR, BRSET, BRCLR, NEG,
COM, LSR, ROR, ASR, ASL, ROL, DEC, INC, TST, JMP, CLR,
SUB, CMP, SBC, SUBD, ADDD, AND, BIT, LDA, STA, EOR, ADC,
ORA, ADD, JSR, LDS, and STS. If X is the index reference and the
offset is greater than 15 (much less frequent than offsets of 0, 1, and
2), the CPU12 instruction assembles to one byte more of object code
than the equivalent M68HC11 instruction.
PSHY
PULY
Were on page 2, now are on page 1
LDY
STY
CPY
Were on page 2, now are on page 1
CPY n,Y
LDY n,Y
STY n,Y
For values of n less than 16 (the majority of cases); were on page 3,
now are on page 1
CPD
Was on page 2, 3, or 4, now on page 1. In the case of indexed with
offset greater than 15, CPU12 and M68HC11 object code are the
same size.
Instruction set changes offset each other to a certain extent. Programming
style also affects the rate at which instructions appear. As a test, the
BUFFALO monitor, an 8-Kbyte M68HC11 assembly code program, was
reassembled for the CPU12. The resulting object code is six bytes smaller
than the M68HC11 code. It is fair to conclude that M68HC11 code can be
reassembled with very little change in size.
The relative size of code for M68HC11 vs. code for CPU12 has also been
tested by rewriting several smaller programs from scratch. In these cases,
the CPU12 code is typically about 30 percent smaller. These savings are
mostly due to improved indexed addressing.
It seems useful to mention the results of size comparisons done on C
programs. A C program compiled for the CPU12 is about 30 percent smaller
than the same program compiled for the M68HC11. The savings are largely
due to better indexing.
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B.4 Programmer’s Model and Stacking
The CPU12 programming model and stacking order are identical to those of
the M68HC11.
B.5 True 16-Bit Architecture
The M68HC11 is a direct descendant of the M6800, one of the first
microprocessors, which was introduced in 1974. The M6800 was strictly an
8-bit machine, with 8-bit data buses and 8-bit instructions. As Freescale
devices evolved from the M6800 to the M68HC11, a number of 16-bit
instructions were added, but the data buses remained eight bits wide, so
these instructions were performed as sequences of 8-bit operations. The
CPU12 is a true 16-bit implementation, but it retains the ability to work with
the mostly 8-bit M68HC11 instruction set. The larger arithmetic logic unit
(ALU) of the CPU12 (it can perform some 20-bit operations) is used to
calculate 16-bit pointers and to speed up math operations.
B.5.1 Bus Structures
The CPU12 is a 16-bit processor with 16-bit data paths. Typical HCS12 and
M68HC12 devices have internal and external 16-bit data paths, but some
derivatives incorporate operating modes that allow for an 8-bit data bus, so
that a system can be built with low-cost 8-bit program memory. HCS12 and
M68HC12 MCUs include an on-chip integration module that manages the
external bus interface. When the CPU makes a 16-bit access to a resource
that is served by an 8-bit bus, the integration module performs two 8-bit
accesses, freezes the CPU clocks for part of the sequence, and assembles
the data into a 16-bit word. As far as the CPU is concerned, there is no
difference between this access and a 16-bit access to an internal resource
via the 16-bit data bus. This is similar to the way an M68HC11 can stretch
clock cycles to accommodate slow peripherals.
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B.5.2 Instruction Queue
The CPU12 has a 2-word instruction queue and a 16-bit holding buffer,
which sometimes acts as a third word for queueing program information. All
program information is fetched from memory as aligned 16-bit words, even
though there is no requirement for instructions to begin or end on even word
boundaries. There is no penalty for misaligned instructions. If a program
begins on an odd boundary (if the reset vector is an odd address), program
information is fetched to fill the instruction queue, beginning with the aligned
word at the next address below the misaligned reset vector. The instruction
queue logic starts execution with the opcode in the low-order half of this
word.
The instruction queue causes three bytes of program information (starting
with the instruction opcode) to be directly available to the CPU at the
beginning of every instruction. As it executes, each instruction performs
enough additional program fetches to refill the space it took up in the queue.
Alignment information is maintained by the logic in the instruction queue.
The CPU provides signals that tell the queue logic when to advance a word
of program information and when to toggle the alignment status.
The CPU is not aware of instruction alignment. The queue logic includes a
multiplexer that sorts out the information in the queue to present the opcode
and the next two bytes of information as CPU inputs. The multiplexer
determines whether the opcode is in the even or odd half of the word at the
head of the queue. Alignment status is also available to the ALU for address
calculations. The execution sequence for all instructions is independent of
the alignment of the instruction.
The only situation where alignment can affect the number of cycles an
instruction takes occurs in devices that have a narrow (8-bit) external data
bus and is related to optional program fetch cycles (O type cycles). O cycles
are always performed, but serve different purposes determined by
instruction size and alignment.
Each instruction includes one program fetch cycle for every two bytes of
object code. Instructions with an odd number of bytes can use an O cycle to
fetch an extra word of object code. If the queue is aligned at the start of an
instruction with an odd byte count, the last byte of object code shares a
queue word with the opcode of the next instruction. Since this word holds
part of the next instruction, the queue cannot advance after the odd byte
executes because the first byte of the next instruction would be lost. In this
case, the O cycle appears as a free cycle since the queue is not ready to
accept the next word of program information. If this same instruction had
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been misaligned, the queue would be ready to advance and the O cycle
would be used to perform a program word fetch.
In a single-chip system or in a system with the program in 16-bit memory,
both the free cycle and the program fetch cycle take one bus cycle. In a
system with the program in an external 8-bit memory, the O cycle takes one
bus cycle when it appears as a free cycle, but it takes two bus cycles when
used to perform a program fetch. In this case, the on-chip integration
module freezes the CPU clocks long enough to perform the cycle as two
smaller accesses. The CPU handles only 16-bit data, and is not aware that
the 16-bit program access is split into two 8-bit accesses.
To allow development systems to track events in the CPU12 instruction
queue, two status signals (IPIPE[1:0]) provide information about data
movement in the queue and about the start of instruction execution. A
development system can use this information along with address and data
information to externally reconstruct the queue. This representation of the
queue can also track both the data and address buses.
B.5.3 Stack Function
Both the M68HC11 and the CPU12 stack nine bytes for interrupts. Since this
is an odd number of bytes, there is no practical way to ensure that the stack
will stay aligned. To ensure that instructions take a fixed number of cycles
regardless of stack alignment, the internal RAM in M68HC12 MCUs is
designed to allow single cycle 16-bit accesses to misaligned addresses. As
long as the stack is located in this special RAM, stacking and unstacking
operations take the same amount of execution time, regardless of stack
alignment. If the stack is located in an external 16-bit RAM, a PSHX
instruction can take two or three cycles depending on the alignment of the
stack. This extra access time is transparent to the CPU because the
integration module freezes the CPU clocks while it performs the extra 8-bit
bus cycle required for a misaligned stack operation.
The CPU12 has a “last-used” stack rather than a “next-available” stack like
the M68HC11 CPU. That is, the stack pointer points to the last 16-bit stack
address used, rather than to the address of the next available stack location.
This generally has very little effect, because it is very unusual to access
stacked information using absolute addressing. The change allows a 16-bit
word of data to be removed from the stack without changing the value of the
SP twice.
To illustrate, consider the operation of a PULX instruction. With the
next-available M68HC11 stack, if the SP = $01F0 when execution begins,
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the sequence of operations is: SP = SP + 1; load X from $01F1:01F2; SP =
SP + 1; and the SP ends up at $01F2. With the last-used CPU12 stack, if
the SP = $01F0 when execution begins, the sequence is: load X from
$01F0:01F1; SP = SP + 2; and the SP again ends up at $01F2. The second
sequence requires one less stack pointer adjustment.
The stack pointer change also affects operation of the TSX and TXS
instructions. In the M68HC11, TSX increments the SP by one during the
transfer. This adjustment causes the X index to point to the last stack
location used. The TXS instruction operates similarly, except that it
decrements the SP by one during the transfer. CPU12 TSX and TXS
instructions are ordinary transfers — the CPU12 stack requires no
adjustment.
For ordinary use of the stack, such as pushes, pulls, and even
manipulations involving TSX and TXS, there are no differences in the way
the M68HC11 and the CPU12 stacks look to a programmer. However, the
stack change can affect a program algorithm in two subtle ways.
The LDS #$xxxx instruction is normally used to initialize the stack pointer at
the start of a program. In the M68HC11, the address specified in the LDS
instruction is the first stack location used. In the CPU12, however, the first
stack location used is one address lower than the address specified in the
LDS instruction. Since the stack builds downward, M68HC11 programs
reassembled for the CPU12 operate normally, but the program stack is one
physical address lower in memory.
In very uncommon situations, such as test programs used to verify CPU
operation, a program could initialize the SP, stack data, and then read the
stack via an extended mode read (it is normally improper to read stack data
from an absolute extended address). To make an M68HC11 source
program that contains such a sequence work on the CPU12, change either
the initial LDS #$xxxx or the absolute extended address used to read the
stack.
B.6 Improved Indexing
The CPU12 has significantly improved indexed addressing capability, yet
retains compatibility with the M68HC11. The one cycle and one byte cost of
doing Y-related indexing in the M68HC11 has been eliminated. In addition,
high-level language requirements, including stack relative indexing and the
ability to perform pointer arithmetic directly in the index registers, have been
accommodated.
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The M68HC11 has one variation of indexed addressing that works from X
or Y as the reference pointer. For X indexed addressing, an 8-bit unsigned
offset in the instruction is added to the index pointer to arrive at the address
of the operand for the instruction. A load accumulator instruction assembles
into two bytes of object code, the opcode and a 1-byte offset. Using Y as the
reference, the same instruction assembles into three bytes (a page prebyte,
the opcode, and a 1-byte offset.) Analysis of M68HC11 source code
indicates that the offset is most frequently zero and seldom greater than
four.
The CPU12 indexed addressing scheme uses a postbyte plus 0, 1, or 2
extension bytes after the instruction opcode. These bytes specify which
index register is used, determine whether an accumulator is used as the
offset, implement automatic pre/post increment/decrement of indices, and
allow a choice of 5-, 9-, or 16-bit signed offsets. This approach eliminates
the differences between X and Y register use and dramatically enhances
indexed addressing capabilities.
Major improvements that result from this new approach are:
•
Stack pointer can be used as an index register in all indexed
operations (very important for C compilers)
•
Program counter can be used as index register in all but auto inc/dec
modes
•
Accumulator offsets allowed using A, B, or D accumulators
•
Automatic pre- or post- increment or decrement by –8 to +8
•
5-bit, 9-bit, or 16-bit signed constant offsets (M68HC11 only
supported positive unsigned 8-bit offsets)
•
16-bit offset indexed-indirect and accumulator D offset
indexed-indirect
The change completely eliminates pages three and four of the M68HC11
opcode map and eliminates almost all instructions from page two of the
opcode map. For offsets of 0 to +15 from the X index register, the object
code is the same size as it was for the M68HC11. For offsets of 0 to +15
from the Y index register, the object code is one byte smaller than it was for
the M68HC11.
Table A-3 and Table A-4 summarize CPU12 indexed addressing mode
capabilities. Table A-6 shows how the postbyte is encoded.
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B.6.1 Constant Offset Indexing
The CPU12 offers three variations of constant offset indexing to optimize
the efficiency of object code generation.
The most common constant offset is 0. Offsets of 1, 2, 3, 4 are used fairly
often, but with less frequency than 0.
The 5-bit constant offset variation covers the most frequent indexing
requirements by including the offset in the postbyte. This reduces a load
accumulator indexed instruction to two bytes of object code, and matches
the object code size of the smallest M68HC11 indexed instructions, which
can only use X as the index register. The CPU12 can use X, Y, SP, or PC
as the index reference with no additional object code size cost.
The signed 9-bit constant offset indexing mode covers the same positive
range as the M68HC11 8-bit unsigned offset. The size was increased to
nine bits with the sign bit (ninth bit) included in the postbyte, and the
remaining 8 bits of the offset in a single extension byte.
The 16-bit constant offset indexing mode allows indexed access to the
entire normal 64-Kbyte address space. Since the address consists of 16
bits, the 16-bit offset can be regarded as a signed (–32,768 to +32,767) or
unsigned (0 to 65,535) value. In 16-bit constant offset mode, the offset is
supplied in two extension bytes after the opcode and postbyte.
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B.6.2 Auto-Increment Indexing
The CPU12 provides greatly enhanced auto increment and decrement
modes of indexed addressing. In the CPU12, the index modification may be
specified for before the index is used (pre-), or after the index is used (post-),
and the index can be incremented or decremented by any amount from one
to eight, independent of the size of the operand that was accessed. X, Y,
and SP can be used as the index reference, but this mode does not allow
PC to be the index reference (this would interfere with proper program
execution).
This addressing mode can be used to implement a software stack structure
or to manipulate data structures in lists or tables, rather than manipulating
bytes or words of data. Anywhere an M68HC11 program has an increment
or decrement index register operation near an indexed mode instruction, the
increment or decrement operation can be combined with the indexed
instruction with no cost in object code size, as shown in the following code
comparison.
18 A6 00
18 08
18 08
LDAA 0,Y
INY
INY
A6
71
LDAA
2,Y+
The M68HC11 object code requires seven bytes, while the CPU12 requires
only two bytes to accomplish the same functions. Three bytes of M68HC11
code were due to the page prebyte for each Y-related instruction ($18).
CPU12 post-increment indexing capability allowed the two INY instructions
to be absorbed into the LDAA indexed instruction. The replacement code is
not identical to the original 3-instruction sequence because the Z condition
code bit is affected by the M68HC11 INY instructions, while the Z bit in the
CPU12 would be determined by the value loaded into A.
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B.6.3 Accumulator Offset Indexing
This indexed addressing variation allows the programmer to use either an
8-bit accumulator (A or B) or the 16-bit D accumulator as the offset for
indexed addressing. This allows for a program-generated offset, which is
more difficult to achieve in the M68HC11. The following code compares the
M68HC11 and CPU12 operations.
C6 05
CE 10 00
3A
A6 00
5A
26 F7
LDAB
#$5
LOOP LDX #$1000
ABX
LDAA
0,X
|
DECB
BNE
LOOP
[2]
[3] C6 05
[3] CE 10 00
[4] A6 E5
[2] 04 31 FB
[3]
LDAB #$5
LDX #$1000
LOOP LDAA B,X
|
DBNE B,LOOP
[1]
[2]
[3]
[3]
The CPU12 object code is only one byte smaller, but the LDX # instruction
is outside the loop. It is not necessary to reload the base address in the
index register on each pass through the loop because the LDAA B,X
instruction does not alter the index register. This reduces the loop execution
time from 15 cycles to six cycles. This reduction, combined with the 25-MHz
bus speed of the HCS12 (M68HC12) Family, can have significant effects.
B.6.4 Indirect Indexing
The CPU12 allows some forms of indexed indirect addressing where the
instruction points to a location in memory where the address of the operand
is stored. This is an extra level of indirection compared to ordinary indexed
addressing. The two forms of indexed indirect addressing are 16-bit
constant offset indexed indirect and D accumulator indexed indirect. The
reference index register can be X, Y, SP, or PC as in other CPU12 indexed
addressing modes. PC-relative indirect addressing is one of the more
common uses of indexed indirect addressing. The indirect variations of
indexed addressing help in the implementation of pointers. D accumulator
indexed indirect addressing can be used to implement a runtime computed
GOTO function. Indirect addressing is also useful in high-level language
compilers. For instance, PC-relative indirect indexing can be used to
efficiently implement some C case statements.
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B.7 Improved Performance
The HCS12 uses a system-on-a-chip (SoC) design methodology and is
normally implemented in a 0.25µ FLASH process. HCS12 devices can
operate at up to 25 MHz and are designed to be migrated easily to faster,
smaller silicon process technologies as they are developed.
The M68HC12 improves on M68HC11 performance in several ways.
M68HC12 devices are designed using sub-micron design rules and
fabricated using advanced semiconductor processing, the same methods
used to manufacture the M68HC16 and M68300 Families of modular
microcontrollers. M68HC12 devices have a base bus speed of 8 MHz and
are designed to operate over a wide range of supply voltages.
The 16-bit wide architecture of the CPU12 also increases performance.
Beyond these obvious improvements, the CPU12 uses a reduced number
of cycles for many of its instructions, and a 20-bit ALU makes certain CPU12
math operations much faster.
B.7.1 Reduced Cycle Counts
No M68HC11 instruction takes less than two cycles, but the CPU12 has
more than 50 opcodes that take only one cycle. Some of the reduction
comes from the instruction queue, which ensures that several program
bytes are available at the start of each instruction. Other cycle reductions
occur because the CPU12 can fetch 16 bits of information at a time, rather
than eight bits at a time.
B.7.2 Fast Math
The CPU12 has some of the fastest math ever designed into a Freescale
general-purpose MCU. Much of the speed is due to a 20-bit ALU that can
perform two smaller operations simultaneously. The ALU can also perform
two operations in a single bus cycle in certain cases.
Table B-3 compares the speed of CPU12 and M68HC11 math instructions.
The CPU12 requires fewer cycles to perform an operation, and the cycle
time is considerably faster than that of the M68HC11.
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Table B-3. Comparison of Math Instruction Speeds
Instruction
Mnemonic
Math
Operation
M68HC11
1 Cycle = 250 ns
M68HC11
With Coprocessor
1 Cycle = 250 ns
CPU12
1 Cycle = 40 ns
(125 ns in M68HC12)
MUL
8 × 8 = 16
(signed)
10 cycles
—
3 cycles
EMUL
16 × 16 = 32
(unsigned)
—
20 cycles
3 cycles
EMULS
16 × 16 = 32
(signed)
—
20 cycles
3 cycles
IDIV
16 ÷ 16 = 16
(unsigned)
41 cycles
—
12 cycles
FDIV
16 ÷ 16 = 16
(fractional)
41 cycles
—
12 cycles
EDIV
32 ÷ 16 = 16
(unsigned)
—
33 cycles
11 cycles
EDIVS
32 ÷ 16 = 16
(signed)
—
37 cycles
12 cycles
IDIVS
16 ÷ 16 = 16
(signed)
—
—
12 cycles
EMACS
32 × (16 × 16) ⇒ 32
(signed MAC)
—
20 cycles
12 cycles
The IDIVS instruction is included specifically for C compilers, where
word-sized operands are divided to produce a word-sized result (unlike the
32 ÷ 16 = 16 EDIV). The EMUL and EMULS instructions place the result in
registers so a C compiler can choose to use only 16 bits of the 32-bit result.
B.7.3 Code Size Reduction
CPU12 assembly language programs written from scratch tend to be
30 percent smaller than equivalent programs written for the M68HC11. This
figure has been independently qualified by Freescale programmers and an
independent C compiler vendor. The major contributors to the reduction
appear to be improved indexed addressing and the universal
transfer/exchange instruction.
In some specialized areas, the reduction is much greater. A fuzzy logic
inference kernel requires about 250 bytes in the M68HC11, and the same
program for the CPU12 requires about 50 bytes. The CPU12 fuzzy logic
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instructions replace whole subroutines in the M68HC11 version. Table
lookup instructions also greatly reduce code space.
Other CPU12 code space reductions are more subtle. Memory-to- memory
moves are one example. The CPU12 move instruction requires almost as
many bytes as an equivalent sequence of M68HC11 instructions, but the
move operations themselves do not require the use of an accumulator. This
means that the accumulator often need not be saved and restored, which
saves instructions.
Arithmetic operations on index pointers are another example. The
M68HC11 usually requires that the content of the index register be moved
into accumulator D, where calculations are performed, then back to the
index register before indexing can take place. In the CPU12, the LEAS,
LEAX, and LEAY instructions perform arithmetic operations directly on the
index pointers. The pre-/post-increment/decrement variations of indexed
addressing also allow index modification to be incorporated into an existing
indexed instruction rather than performing the index modification as a
separate operation.
Transfer and exchange operations often allow register contents to be
temporarily saved in another register rather than having to save the
contents in memory. Some CPU12 instructions such as MIN and MAX
combine the actions of several M68HC11 instructions into a single
operation.
B.8 Additional Functions
The CPU12 incorporates a number of new instructions that provide added
functionality and code efficiency. Among other capabilities, these new
instructions allow efficient processing for fuzzy logic applications and
support subroutine processing in extended memory beyond the standard
64-Kbyte address map for M68HC12 devices incorporating this feature.
Table B-4 is a summary of these new instructions. Subsequent paragraphs
discuss significant enhancements.
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Table B-4. New M68HC12 Instructions (Sheet 1 of 2)
Mnemonic
Addressing Modes
Brief Functional Description
ANDCC
Immediate
AND CCR with mask (replaces CLC, CLI, and CLV)
BCLR
Extended
Bit(s) clear (added extended mode)
BGND
Inherent
Enter background debug mode, if enabled
BRCLR
Extended
Branch if bit(s) clear (added extended mode)
BRSET
Extended
Branch if bit(s) set (added extended mode)
BSET
Extended
Bit(s) set (added extended mode)
CALL
Extended, indexed
CPS
Immediate, direct,
extended, and indexed
DBNE
Relative
Decrement and branch if equal to zero (looping primitive)
DBEQ
Relative
Decrement and branch if not equal to zero (looping primitive)
EDIV
Inherent
Extended divide Y:D/X = Y(Q) and D(R) (unsigned)
EDIVS
Inherent
Extended divide Y:D/X = Y(Q) and D(R) (signed)
EMACS
Special
Multiply and accumulate 16 × 16 ⇒ 32 (signed)
EMAXD
Indexed
Maximum of two unsigned 16-bit values
EMAXM
Indexed
Maximum of two unsigned 16-bit values
EMIND
Indexed
Minimum of two unsigned 16-bit values
EMINM
Indexed
Minimum of two unsigned 16-bit values
EMUL
Special
Extended multiply 16 × 16 ⇒ 32; M(idx) ∗ D ⇒ Y:D
EMULS
Special
Extended multiply 16 × 16 ⇒ 32 (signed); M(idx) ∗ D ⇒ Y:D
ETBL
Special
Table lookup and interpolate (16-bit entries)
EXG
Inherent
Exchange register contents
IBEQ
Relative
Increment and branch if equal to zero (looping primitive)
IBNE
Relative
Increment and branch if not equal to zero (looping primitive)
IDIVS
Inherent
Signed integer divide D/X ⇒ X(Q) and D(R) (signed)
LBCC
Relative
Long branch if carry clear (same as LBHS)
LBCS
Relative
Long branch if carry set (same as LBLO)
LBEQ
Relative
Long branch if equal (Z=1)
LBGE
Relative
Long branch if greater than or equal to zero
LBGT
Relative
Long branch if greater than zero
LBHI
Relative
Long branch if higher
LBHS
Relative
Long branch if higher or same (same as LBCC)
LBLE
Relative
Long branch if less than or equal to zero
LBLO
Relative
Long branch if lower (same as LBCS)
LBLS
Relative
Long branch if lower or same
Similar to JSR except also stacks PPAGE value; with RTC
instruction, allows easy access to >64-Kbyte space
Compare stack pointer
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Table B-4. New M68HC12 Instructions (Sheet 2 of 2)
Mnemonic
Addressing Modes
Brief Functional Description
LBLT
Relative
Long branch if less than zero
LBMI
Relative
Long branch if minus
LBNE
Relative
Long branch if not equal to zero
LBPL
Relative
Long branch if plus
LBRA
Relative
Long branch always
LBRN
Relative
Long branch never
LBVC
Relative
Long branch if overflow clear
LBVS
Relative
Long branch if overflow set
LEAS
Indexed
Load stack pointer with effective address
LEAX
Indexed
Load X index register with effective address
LEAY
Indexed
Load Y index register with effective address
MAXA
Indexed
Maximum of two unsigned 8-bit values
MAXM
Indexed
Maximum of two unsigned 8-bit values
MEM
Special
Determine grade of fuzzy membership
MINA
Indexed
Minimum of two unsigned 8-bit values
MINM
Indexed
Minimum of two unsigned 8-bit values
MOVB(W)
Combinations of
immediate, extended,
and indexed
ORCC
Immediate
PSHC
Inherent
Push CCR onto stack
PSHD
Inherent
Push double accumulator onto stack
PULC
Inherent
Pull CCR contents from stack
PULD
Inherent
Pull double accumulator from stack
REV
Special
Fuzzy logic rule evaluation
REVW
Special
Fuzzy logic rule evaluation with weights
RTC
Inherent
Restore program page and return address from stack
used with CALL instruction, allows easy access to >64-Kbyte space
SEX
Inherent
Sign extend 8-bit register into 16-bit register
TBEQ
Relative
Test and branch if equal to zero (looping primitive)
TBL
Inherent
Table lookup and interpolate (8-bit entries)
TBNE
Relative
Test register and branch if not equal to zero (looping primitive)
TFR
Inherent
Transfer register contents to another register
WAV
Special
Weighted average (fuzzy logic support)
Move data from one memory location to another
OR CCR with mask (replaces SEC, SEI, and SEV)
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B.8.1 Memory-to-Memory Moves
The CPU12 has both 8- and 16-bit variations of memory-to-memory move
instructions. The source address can be specified with immediate,
extended, or indexed addressing modes. The destination address can be
specified by extended or indexed addressing mode. The indexed
addressing mode for move instructions is limited to modes that require no
extension bytes (9- and 16-bit constant offsets are not allowed), and indirect
indexing is not allowed for moves. This leaves 5-bit signed constant offsets,
accumulator offsets, and the automatic increment/decrement modes. The
following simple loop is a block move routine capable of moving up to 256
words of information from one memory area to another.
LOOP
DBNE
MOVW
2,X+ , 2,Y+
B,LOOP
;move a word and update pointers
;repeat B times
The move immediate to extended is a convenient way to initialize a register
without using an accumulator or affecting condition codes.
B.8.2 Universal Transfer and Exchange
The M68HC11 has only eight transfer instructions and two exchange
instructions. The CPU12 has a universal transfer/exchange instruction that
can be used to transfer or exchange data between any two CPU registers.
The operation is obvious when the two registers are the same size, but
some of the other combinations provide very useful results. For example
when an 8-bit register is transferred to a 16-bit register, a sign-extend
operation is performed. Other combinations can be used to perform a
zero-extend operation.
These instructions are used often in CPU12 assembly language programs.
Transfers can be used to make extra copies of data in another register, and
exchanges can be used to temporarily save data during a call to a routine
that expects data in a specific register. This is sometimes faster and
produces more compact object code than saving data to memory with
pushes or stores.
B.8.3 Loop Construct
The CPU12 instruction set includes a new family of six loop primitive
instructions. These instructions decrement, increment, or test a loop count
in a CPU register and then branch based on a zero or non-zero test result.
The CPU registers that can be used for the loop count are A, B, D, X, Y, or
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SP. The branch range is a 9-bit signed value (–512 to +511) which gives
these instructions twice the range of a short branch instruction.
B.8.4 Long Branches
All of the branch instructions from the M68HC11 are also available with
16-bit offsets which allows them to reach any location in the 64-Kbyte
address space.
B.8.5 Minimum and Maximum Instructions
Control programs often need to restrict data values within upper and lower
limits. The CPU12 facilitates this function with 8- and 16-bit versions of MIN
and MAX instructions. Each of these instructions has a version that stores
the result in either the accumulator or in memory.
For example, in a fuzzy logic inference program, rule evaluation consists of
a series of MIN and MAX operations. The min operation is used to
determine the smallest rule input (the running result is held in an
accumulator), and the max operation is used to store the largest rule truth
value (in an accumulator) or the previous fuzzy output value (in a RAM
location) to the fuzzy output in RAM. The following code demonstrates how
MIN and MAX instructions can be used to evaluate a rule with four inputs
and two outputs.
LDY
LDX
LDAA
MINA
MINA
MINA
MINA
MAXM
MAXM
#OUT1
#IN1
#$FF
1,X+
1,X+
1,X+
1,X+
1,Y+
1,Y+
;Point at first output
;Point at first input value
;start with largest 8-bit number in A
;A=MIN(A,IN1)
;A=MIN(A,IN2)
;A=MIN(A,IN3)
;A=MIN(A,IN4) so A holds smallest input
;OUT1=MAX(A,OUT1) and A is unchanged
;OUT1=MAX(A,OUT2) A still has min input
Before this sequence is executed, the fuzzy outputs must be cleared to
zeros (not shown). M68HC11 MIN or MAX operations are performed by
executing a compare followed by a conditional branch around a load or store
operation.
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These instructions can also be used to limit a data value prior to using it as
an input to a table lookup or other routine. Suppose a table is valid for input
values between $20 and $7F. An arbitrary input value can be tested against
these limits and be replaced by the largest legal value if it is too big, or the
smallest legal value if too small using the following two CPU12 instructions.
HILIMIT FCB
LOWLIMIT FCB
MINA
MAXA
$7F
$20
HILIMIT,PCR
LOWLIMIT,PCR
;comparison value needs to be in mem
;so it can be referenced via indexed
;A=MIN(A,$7F)
;A=MAX(A,$20)
;A now within the legal range $20 to $7F
The “,PCR” notation is also new for the CPU12. This notation indicates the
programmer wants an appropriate offset from the PC reference to the
memory location (HILIMIT or LOWLIMIT in this example), and then to
assemble this instruction into a PC-relative indexed MIN or MAX instruction.
B.8.6 Fuzzy Logic Support
The CPU12 includes four instructions (MEM, REV, REVW, and WAV)
specifically designed to support fuzzy logic programs. These instructions
have a very small impact on the size of the CPU and even less impact on
the cost of a complete MCU. At the same time, these instructions
dramatically reduce the object code size and execution time for a fuzzy logic
inference program. A kernel written for the M68HC11 required about 250
bytes and executed in about 750 milliseconds. The CPU12 kernel uses
about 50 bytes and executes in about 16 microseconds (in a 25-MHz
HCS12).
B.8.7 Table Lookup and Interpolation
The CPU12 instruction set includes two instructions (TBL and ETBL) for
lookup and interpolation of compressed tables. Consecutive table values
are assumed to be the x coordinates of the endpoints of a line segment. The
TBL instruction uses 8-bit table entries (y-values) and returns an 8-bit result.
The ETBL instruction uses 16-bit table entries (y-values) and returns a
16-bit result.
An indexed addressing mode is used to identify the effective address of the
data point at the beginning of the line segment, and the data value for the
end point of the line segment is the next consecutive memory location (byte
for TBL and word for ETBL). In both cases, the B accumulator represents
the ratio of (the x-distance from the beginning of the line segment to the
lookup point) to (the x-distance from the beginning of the line segment to the
end of the line segment). B is treated as an 8-bit binary fraction with radix
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point left of the MSB, so each line segment is effectively divided into 256
pieces. During execution of the TBL or ETBL instruction, the difference
between the end point y-value and the beginning point y-value (a signed
byte for TBL or a signed word for ETBL) is multiplied by the B accumulator
to get an intermediate delta-y term. The result is the y-value of the beginning
point, plus this signed intermediate delta-y value.
B.8.8 Extended Bit Manipulation
The M68HC11 CPU allows only direct or indexed addressing. This typically
causes the programmer to dedicate an index register to point at some
memory area such as the on-chip registers. The CPU12 allows all bit
manipulation instructions to work with direct, extended, or indexed
addressing modes.
B.8.9 Push and Pull D and CCR
The CPU12 includes instructions to push and pull the D accumulator and the
CCR. It is interesting to note that the order in which 8-bit accumulators A and
B are stacked for interrupts is the opposite of what would be expected for
the upper and lower bytes of the 16-bit D accumulator. The order used
originated in the M6800, an 8-bit microprocessor developed long before
anyone thought 16-bit single-chip devices would be made. The interrupt
stacking order for accumulators A and B is retained for code compatibility.
B.8.10 Compare SP
This instruction was added to the CPU12 instruction set to improve
orthogonality and high-level language support. One of the most important
requirements for C high-level language support is the ability to do arithmetic
on the stack pointer for such things as allocating local variable space on the
stack. The LEAS –5,SP instruction is an example of how the compiler could
easily allocate five bytes on the stack for local variables. LDX 5,SP+ loads
X with the value on the bottom of the stack and deallocates five bytes from
the stack in a single operation that takes only two bytes of object code.
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B.8.11 Support for Memory Expansion
Bank switching is a common method of expanding memory beyond the
64-Kbyte limit of a CPU with a 64-Kbyte address space, but there are some
known difficulties associated with bank switching. One problem is that
interrupts cannot take place during the bank switching operation. This
increases worst case interrupt latency and requires extra programming
space and execution time.
Some HCS12 and M68HC12 variants include a built-in bank switching
scheme that eliminates many of the problems associated with external
switching logic. The CPU12 includes CALL and return-from-call (RTC)
instructions that manage the interface to the bank-switching system. These
instructions are analogous to the JSR and RTS instructions, except that the
bank page number is saved and restored automatically during execution.
Since the page change operation is part of an uninterruptable instruction,
many of the difficulties associated with bank switching are eliminated. On
HCS12 and M68HC12 derivatives with expanded memory capability, bank
numbers are specified by on-chip control registers. Since the addresses of
these control registers may not be the same in all derivatives, the CPU12
has a dedicated control line to the on-chip integration module that indicates
when a memory-expansion register is being read or written. This allows the
CPU to access the PPAGE register without knowing the register address.
The indexed indirect versions of the CALL instruction access the address of
the called routine and the destination page value indirectly. For other
addressing mode variations of the CALL instruction, the destination page
value is provided as immediate data in the instruction object code. CALL
and RTC execute correctly in the normal 64-Kbyte address space, thus
providing for portable code.
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Appendix C. High-Level Language Support
C.1 Introduction
Many programmers are turning to high-level languages such as C as an
alternative to coding in native assembly languages. High-level language
(HLL) programming can improve productivity and produce code that is more
easily maintained than assembly language programs. The most serious
drawback to the use of HLL in MCUs has been the relatively large size of
programs written in HLL. Larger program ROM size requirements translate
into increased system costs.
This appendix identifies CPU12 instructions and addressing modes that
provide improved support for high-level language. C language examples are
provided to demonstrate how these features support efficient HLL structures
and concepts. Since the CPU12 instruction set is a superset of the
M68HC11 instruction set, some of the discussions use the M68HC11 as a
basis for comparison.
C.2 Data Types
The CPU12 supports the bit-sized data type with bit manipulation
instructions which are available in extended, direct, and indexed variations.
The char data type is a simple 8-bit value that is commonly used to specify
variables in a small microcontroller system because it requires less memory
space than a 16-bit integer (provided the variable has a range small enough
to fit into eight bits). The 16-bit CPU12 can easily handle 16-bit integer types
and the available set of conditional branches (including long branches)
allow branching based on signed or unsigned arithmetic results. Some of
the higher math functions allow for division and multiplication involving
32-bit values, although it is somewhat less common to use such long values
in a microcontroller system.
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The CPU12 has special sign extension instructions to allow easy
type-casting from smaller data types to larger ones, such as from char to
integer. This sign extension is automatically performed when an 8-bit value
is transferred to a 16-bit register.
C.3 Parameters and Variables
High-level languages make extensive use of the stack, both to pass
variables and for temporary and local storage. It follows that there should be
easy ways to push and pull each CPU register, stack pointer based indexing
should be allowed, and that direct arithmetic manipulation of the stack
pointer value should be allowed. The CPU12 instruction set provided for all
of these needs with improved indexed addressing, the addition of an LEAS
instruction, and the addition of push and pull instructions for the D
accumulator and the CCR.
C.3.1 Register Pushes and Pulls
The M68HC11 has push and pull instructions for A, B, X, and Y, but requires
separate 8-bit pushes and pulls of accumulators A and B to stack or unstack
the 16-bit D accumulator (the concatenated combination of A:B). The PSHD
and PULD instructions allow directly stacking the D accumulator in the
expected 16-bit order.
Adding PSHC and PULC improved orthogonality by completing the set of
stacking instructions so that any of the CPU registers can be pushed or
pulled. These instructions are also useful for preserving the CCR value
during a function call subroutine.
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C.3.2 Allocating and Deallocating Stack Space
The LEAS instruction can be used to allocate or deallocate space on the
stack for temporary variables:
LEAS
LEAS
–10,S
10,S
;Allocate space for 5 16-bit integers
;Deallocate space for 5 16-bit ints
The (de)allocation can even be combined with a register push or pull as in
this example:
LDX
8,S+
;Load return value and deallocate
X is loaded with the 16-bit integer value at the top of the stack, and the stack
pointer is adjusted up by eight to deallocate space for eight bytes worth of
temporary storage. Post-increment indexed addressing is used in this
example, but all four combinations of pre/post increment/decrement are
available (offsets from –8 to +8 inclusive, from X, Y, or SP). This form of
indexing can often be used to get an index (or stack pointer) adjustment for
free during an indexed operation (the instruction requires no more code
space or cycles than a zero-offset indexed instruction).
C.3.3 Frame Pointer
In the C language, it is common to have a frame pointer in addition to the
CPU stack pointer. The frame is an area of memory within the system stack
which is used for parameters and local storage of variables used within a
function subroutine. The following is a description of how a frame pointer
can be set up and used.
First, parameters (typically values in CPU registers) are pushed onto the
system stack prior to using a JSR or CALL to get to the function subroutine.
At the beginning of the called subroutine, the frame pointer of the calling
program is pushed onto the stack. Typically, an index register, such as X, is
used as the frame pointer, so a PSHX instruction would save the frame
pointer from the calling program.
Next, the called subroutine establishes a new frame pointer by executing a
TFR S,X. Space is allocated for local variables by executing an
LEAS –n,S, where n is the number of bytes needed for local variables.
Notice that parameters are at positive offsets from the frame pointer while
locals are at negative offsets. In the M68HC11, the indexed addressing
mode uses only positive offsets, so the frame pointer always points to the
lowest address of any parameter or local. After the function subroutine
finishes, calculations are required to restore the stack pointer to the
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mid-frame position between the locals and the parameters before returning
to the calling program. The CPU12 only requires execution of TFR X,S to
deallocate the local storage and return.
The concept of a frame pointer is supported in the CPU12 through a
combination of improved indexed addressing, universal transfer/exchange,
and the LEA instruction. These instructions work together to achieve more
efficient handling of frame pointers. It is important to consider the complete
instruction set as a complex system with subtle interrelationships rather
than simply examining individual instructions when trying to improve an
instruction set. Adding or removing a single instruction can have
unexpected consequences.
C.4 Increment and Decrement Operators
In C, the notation + + i or i – – is often used to form loop counters. Within
limited constraints, the CPU12 loop primitives can be used to speed up the
loop count and branch function.
The CPU12 includes a set of six basic loop control instructions which
decrement, increment, or test a loop count register, and then branch if it is
either equal to zero or not equal to zero. The loop count register can be A,
B, D, X, Y, or SP. A or B could be used if the loop count fits in an 8-bit char
variable; the other choices are all 16-bit registers. The relative offset for the
loop branch is a 9-bit signed value, so these instructions can be used with
loops as long as 256 bytes.
In some cases, the pre- or post-increment operation can be combined with
an indexed instruction to eliminate the cost of the increment operation. This
is typically done by post-compile optimization because the indexed
instruction that could absorb the increment/decrement operation may not be
apparent at compile time.
C.5 Higher Math Functions
In the CPU12, subtle characteristics of higher math operations such as
IDIVS and EMUL are arranged so a compiler can handle inputs and outputs
more efficiently.
The most apparent case is the IDIVS instruction, which divides two 16-bit
signed numbers to produce a 16-bit result. While the same function can be
accomplished with the EDIVS instruction (a 32 by 16 divide), doing so is
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much less efficient because extra steps are required to prepare inputs to the
EDIVS, and because EDIVS uses the Y index register. EDIVS uses a 32-bit
signed numerator and the C compiler would typically want to use a 16-bit
value (the size of an integer data type). The 16-bit C value would need to be
sign-extended into the upper 16 bits of the 32-bit EDIVS numerator before
the divide operation.
Operand size is also a potential problem in the extended multiply operations
but the difficulty can be minimized by putting the results in CPU registers.
Having higher precision math instructions is not necessarily a requirement
for supporting high-level language because these functions can be
performed as library functions. However, if an application requires these
functions, the code is much more efficient if the MCU can use native
instructions instead of relatively large, slow routines.
C.6 Conditional If Constructs
In the CPU12 instruction set, most arithmetic and data manipulation
instructions automatically update the condition code register, unlike other
architectures that only change condition codes during a few specific
compare instructions. The CPU12 includes branch instructions that perform
conditional branching based on the state of the indicators in the condition
codes register. Short branches use a single byte relative offset that allows
branching to a destination within about ±128 locations from the branch.
Long branches use a 16-bit relative offset that allows conditional branching
to any location in the 64-Kbyte map.
C.7 Case and Switch Statements
Case and switch statements (and computed GOTOs) can use PC-relative
indirect addressing to determine which path to take. Depending upon the
situation, cases can use either the constant offset variation or the
accumulator D offset variation of indirect indexed addressing.
C.8 Pointers
The CPU12 supports pointers by allowing direct arithmetic operations on
the 16-bit index registers (LEAS, LEAX, and LEAY instructions) and by
allowing indexed indirect addressing modes.
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C.9 Function Calls
Bank switching is a fairly common way of adapting a CPU with a 16-bit
address bus to accommodate more than 64 Kbytes of program memory
space. One of the most significant drawbacks of this technique has been the
requirement to mask (disable) interrupts while the bank page value was
being changed. Another problem is that the physical location of the bank
page register can change from one MCU derivative to another (or even due
to a change to mapping controls by a user program). In these situations, an
operating system program has to keep track of the physical location of the
page register. The CPU12 addresses both of these problems with the
uninterruptible CALL and return-from-call (RTC) instructions.
The CALL instruction is similar to a JSR instruction, except that the
programmer supplies a destination page value as part of the instruction.
When CALL executes, the old page value is saved on the stack and the new
page value is written to the bank page register. Since the CALL instruction
is uninterruptible, this eliminates the need to separately mask off interrupts
during the context switch.
The CPU12 has dedicated signal lines that allow the CPU to access the
bank page register without having to use an address in the normal 64-Kbyte
address space. This eliminates the need for the program to know where the
page register is physically located.
The RTC instruction is similar to the RTS instruction, except that RTC uses
the byte of information that was saved on the stack by the corresponding
CALL instruction to restore the bank page register to its old value. Although
a CALL/RTC pair can be used to access any function subroutine regardless
of the location of the called routine (on the current bank page or a different
page), it is most efficient to access some subroutines with JSR/RTS
instructions when the called subroutine is on the current page or in an area
of memory that is always visible in the 64-Kbyte map regardless of the bank
page selection.
Push and pull instructions can be used to stack some or all the CPU
registers during a function call. The CPU12 can push and pull any of the
CPU registers A, B, CCR, D, X, Y, or SP.
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C.10 Instruction Set Orthogonality
One helpful aspect of the CPU12 instruction set, orthogonality, is difficult to
quantify in terms of direct benefit to an HLL compiler. Orthogonality refers to
the regularity of the instruction set. A completely orthogonal instruction set
would allow any instruction to operate in any addressing mode, would have
identical code sizes and execution times for similar operations on different
registers, and would include both signed and unsigned versions of all
mathematical instructions. Greater regularity of the instruction set makes it
possible to implement compilers more efficiently, because operation is more
consistent, and fewer special cases must be handled.
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Index
A
ABA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Abbreviations for system resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ABX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ABY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Access details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94–99, 379
Accumulator offset indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Accumulator offset indexed indirect addressing mode . . . . . . . . . . . . . . . . . . . . . . 40
Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 35
B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 35
D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 35
ADCA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ADCB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADDA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADDB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADDD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Addition instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADDR mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 34
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ANDA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ANDB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ANDCC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Arithmetic shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ASL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ASLA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ASLB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ASLD instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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ASR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ASRA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ASRB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Asserted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
B
Background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 123
Base index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37–41
BCC instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
BCD instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 161
BCLR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
BCS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
BEQ instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
BGE instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
BGND instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 123
BGT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
BHI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
BHS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Binary-coded decimal instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 161
Bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .65, 119, 140, 423, 425
Mask operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43, 119, 137, 139, 140
Multiple addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Bit test instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 76, 127, 128, 137, 139
BITA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
BITB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Bit-condition branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 137, 139
BLE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
BLO instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
BLS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
BLT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
BMI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
BNE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Boolean logic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 109, 110
Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 156
Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179, 180
Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243, 244, 245
Negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239, 240, 241
BPL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
BRA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33, 51–53, 73, 429
Bit-condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53, 76, 137, 139
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Long . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52, 53, 75, 421
Loop primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53, 77, 400
Offset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74, 75, 76, 77
Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 53, 74
Signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Simple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 141
Summary of complementary branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 196
Taken/not-taken cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 99
Unary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Branch offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33–34
BRCLR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
BRN instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
BRSET instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
BSET instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
BSR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 141
Bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Bus structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
BVC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
BVS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Byte moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58, 236
Byte order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Byte-sized instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
C
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
C status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26, 66, 118, 120
CALL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44–??, 50, 78, 144, 424, 430
Case statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
CBA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
CCR (see Condition codes register)
Changes in execution flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49–53
CLC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Clear instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clear memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CLI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
CLR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CLRA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CLRB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
CLV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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CMPA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
CMPB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Code size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
COM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
COMA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
COMB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Compare instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Complement instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Computer operating properly (COP) watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Condition codes instructions . . . . . . . . . . . 84, 110, 245, 248, 254, 291, 297, 405, 423
Condition codes register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 23–27
C status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26, 66, 118, 120
H status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 161
I mask bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 110, 147, 276, 306, 313, 315
Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84, 110, 245, 276
N status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
S control bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 282
V status bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
X mask bit . . . . . . . . . . . . . . . . . . . . 25, 182, 254, 270, 282, 291, 296, 306, 313, 315
Z status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 121, 134
Conditional 16-bit read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Conditional 8-bit read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Conditional 8-bit write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Conserving power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 282, 306
Constant indirect indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Constant offset indexed addressing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 38
COP reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
CPD instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
CPS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
CPX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
CPY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Cycle code letters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
Cycle counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Cycle-by-cycle operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 379
D
DAA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
DATA mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 425
DBEQ instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162, 400
DBNE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163, 400
DEC instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DECA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DECB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
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Decrement instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Defuzzification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344, 364–368
DES instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DEX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DEY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Division instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64, 428
16-bit fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16-bit integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186, 187
32-bit extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170, 171
Double accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 22
E
EDIV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
EDIVS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Effective address . . . . . . . . . . . . . . . . . . . . . . . 29, 35, 83, 220, 221, 222, 417, 426–428
EMACS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 172
EMAXD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
EMAXM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174, 338
EMIND instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175, 338
EMINM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
EMUL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
EMULS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Enabling maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 147
EORA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
EORB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
ETBL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72, 181, 338
Even bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 311
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315, 317
Non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311, 313–314
Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 289, 318
Unimplemented opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311, 313, 317
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311, 318
Exchange instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57, 182, 417, 420
Postbyte encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Execution cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Execution time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EXG instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Expanded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 50, 424, 430
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Bank switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44, 78, 144, 269
Page registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 430
Extended addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Extended division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Extension byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
External queue reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
HCS12 queue reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
HCS12 reconstruction algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
HCS12 timing detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
M68HC12 queue reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
M68HC12 reconstruction algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
M68HC12 timing detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
F
Fast math. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
f-cycle (free cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
FDIV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64, 183
Fractional division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64, 183
Frame pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427, 428
Free cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
Fuzzy logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337–374
Antecedents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342, 372
Consequents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342, 372
Custom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Defuzzification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68, 344, 364–367
Fuzzification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67, 340, 369
Inference kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339, 345
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Instructions . . . . . . . . . . . . . . . . . . . . 67, 68, 233, 258–262, 307, 337, 347–367, 422
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361, 365–368
Knowledge base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340, 342, 372
Membership functions . . . . . . . . . . . . . . . . . . 67, 233, 338, 340, 347–352, 369–371
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68, 372
Rule evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67, 258–262, 342, 353–363, 372
Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340, 342, 372
Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Tabular membership functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72, 369
Weighted average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68, 307, 337, 344, 364–367
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G
g-cycle (read PPAGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
General purpose accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Global interrupt mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 313
H
H status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 161
Highest priority interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
High-level language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425–431
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425, 427, 429
Condition codes register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Expanded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Loop primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426, 427
I
I mask bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 110, 147, 276, 313
IBEQ instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184, 400
IBNE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185, 400
I-cycle (16-bit read indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
i-cycle (8-bit read indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
IDIV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
IDIVS instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187, 428
Immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
INCA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
INCB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Increment instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Index calculation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83, 417
Index manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Index registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 81, 83, 427
PC (as an index register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 36, 37, 94
SP (as an index register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22, 36, 37, 94
X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 36, 94
Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 36, 94
Indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 34–43, 397, 410–414
16-bit constant indirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
16-bit constant offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5-bit constant offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9-bit constant offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Accumulator direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Accumulator offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Auto increment/decrement indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Base index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37–41
Extension byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Limitations for BIT and MOV instructions . . . . . . . . . 119, 137, 139, 140, 236, 237
Postbyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Postbyte encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 397
Inference kernel, fuzzy logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Instruction pipe, see Instruction queue
Instruction queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28, 47, 323, 408
Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323–334
Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 323
Status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329, 332
Status signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 324–333
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 87, 381
Integer division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64, 186–187
Interrupt instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315–319
Enabling and disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 147, 276, 315
External . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
I mask bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 147, 276, 316
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 80, 147, 270, 276, 289, 298
Low-power stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 282
Maskable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 315
Non-maskable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 311–313, 315
Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 26, 80, 270, 317
Service routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 289, 318
Stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316, 376
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311, 317, 318
Wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 306
X mask bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 282, 306, 316
INX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
INY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
J
JMP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53, 194
JSR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 195
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Jump instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53, 78
K
Knowledge base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
L
Label. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LBCC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
LBCS instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
LBEQ instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
LBGE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
LBGT instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
LBHI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
LBHS instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
LBLE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
LBLO instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
LBLS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
LBLT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
LBMI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
LBNE instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LBPL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
LBRA instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
LBRN instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
LBVC instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LBVS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
LDAA instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
LDAB instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
LDD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
LDS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LDX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
LDY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
LEAS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220, 427, 429
Least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Least significant word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LEAX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221, 429
LEAY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222, 429
Legal label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Literal expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Logic level one . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Logic level zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop primitive instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53, 77, 400, 420, 428
Offset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Postbyte encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Low-power stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 282
LSL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66, 223
LSLA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
LSLB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
LSLD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
LSR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
LSRA instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
LSRB instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
LSRD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
M
M68HC11 compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 403–424
M68HC11 instruction mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 315
MAXA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Maximum instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70, 421
16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 174
8-bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231, 232
MAXM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232, 338
MEM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67, 233, 337, 347–352
Membership functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340, 347–352
Memory and addressing symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MINA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234, 338
Minimum instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70, 421
16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175, 176
8-bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234, 235
MINM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Misaligned instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Most significant word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MOVB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Move instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58, 236, 237, 417, 420
Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Multiple addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PC relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reference index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MOVW instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
MUL instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Multiple addressing modes
Bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Move instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Multiplication instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177, 178
8-bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Multiply and accumulate instructions . . . . . . . . . . . . . . . . . . . . . . . . .71, 172, 307, 373
N
N status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
n-cycle (write PPAGE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 379
NEG instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
NEGA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Negate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Negated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Negative integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
NEGB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 313, 315
NOP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 242
Notation
Branch taken/not taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99, 379
Changes in CCR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Cycle-by-cycle operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Memory and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Object code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 377
Source forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
System resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Null operation instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 242
Numeric range of branch offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 74–77
O
Object code notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
O-cycle (optional program word fetch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 96, 379
Odd bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Offset
Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33–34
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34–38
Opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395–396
Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 377
Optional cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 96, 379
ORAA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
ORAB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
ORCC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Orthogonality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
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Page 2 prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 96, 396
P-cycle (program word fetch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 379
Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pointer calculation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83, 220, 221, 222
Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Postbyte encoding
Exchange instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182, 399
Indexed addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 397
Loop primitive instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278, 296, 399
Post-decrement indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Post-increment indexed addressing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power conservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 282, 306
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Prebyte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 96, 396
Pre-decrement indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pre-increment indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Priority, exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 23, 35, 123
Program word access cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 379
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, 21, 407
Pseudo-non-maskable interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
PSHA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
PSHB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
PSHC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
PSHD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249, 426
PSHX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
PSHY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
PULA instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
PULB instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
PULC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254, 426
PULD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255, 426
Pull instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
PULX instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
PULY instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Push instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Q
Queue reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
HCS12 queue reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
HCS12 reconstruction algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
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HCS12 timing detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
M68HC12 queue reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
M68HC12 reconstruction algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
M68HC12 timing detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
R
R-cycle (16-bit data read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
r-cycle (8-bit data read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Read 16-bit data cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Read 8-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Read indirect pointer cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
Read indirect PPAGE value cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
Read PPAGE cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 379
Register designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Relative offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311, 313
Clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
External . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Return from call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Return from interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Return from subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
REV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 67, 258–259, 337, 342, 353–358, 372
REVW instruction . . . . . . . . . . . . . . . . . . . . . . . . . 67, 260–262, 337, 342, 359–363, 372
ROL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
ROLA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
ROLB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
ROR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
RORA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
RORB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Rotate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
RTC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 50, 78, 269, 424, 430
RTI instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26, 80, 270, 317
RTS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51, 271
S
S control bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 282
SBA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
SBCA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
SBCB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
S-cycle (16-bit stack write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
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s-cycle (8-bit stack write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
SEC instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
SEI instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting memory bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SEV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
SEX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57, 278
Shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Sign extension instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57, 278, 426
Signed branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Signed integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Signed multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Simple branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Source code compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, 404
Source form notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
STAA instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
STAB instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 409, 410
Stack 16-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Stack 8-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Stack operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 22, 35, 426
Compatibility with HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409–410
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 410
Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316, 376
Stack pointer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82, 423, 426
Standard CPU12 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
STOP continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
STOP disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 282
STOP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 85, 282
Store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
STX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
STY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
SUBA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
SUBB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
SUBD instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Subroutine instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 430
Expanded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50, 78, 144, 269, 430
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Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78, 141, 144, 195, 430
Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 271
Subtraction instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SWI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 289, 318
Switch statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Symbols and notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 377
T
TAB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table interpolation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72, 181, 294, 422
Tabular membership functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369–371
TAP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
TBA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
TBEQ instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293, 400
TBL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72, 294, 338, 369–370
TBNE instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295, 400
T-cycle (16-bit conditional read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
t-cycle (8-bit conditional read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Termination of interrupt service routines . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 270, 317
Termination of subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269, 271
Test instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TFR instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
TPA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57, 417, 420
Postbyte encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
TRAP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79, 298, 317, 396
TST instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
TSTA instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
TSTB instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
TSX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
TSY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Twos-complement form. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TXS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Types of instructions
Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Background and null . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Binary-coded decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Bit test and manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Boolean logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Clear, complement, and negate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Compare and test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Condition code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Decrement and increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Fuzzy logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Index manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Jump and subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Load and store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Loop primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Maximum and minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Multiplication and division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Multiply and accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Pointer and index calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Shift and rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Sign extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Stop and wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Transfer and exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
TYS instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
U
U-cycle (16-bit stack read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
u-cycle (8-bit stack read). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Unary branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Unimplemented opcode trap . . . . . . . . . . . . . . . . . . . . . . . . . . . .79, 298, 311, 313, 396
Unsigned branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73–75
Unsigned multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Unstack 16-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Unstack 8-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Unweighted rule evaluation . . . . . . . . . . . . . . . . . . . . . . . 258–259, 342, 353–358, 372
V
V status bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 84
V-cycle (vector fetch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Vector fetch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
Vectors, exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311, 318
W
WAI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 306
Wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 306
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
WAV instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68, 307, 337, 344, 364–368
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HCS12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
M68HC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
wavr pseudo-instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365–368
HCS12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
M68HC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
W-cycle (16-bit data write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
w-cycle (8-bit data write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Weighted average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Weighted rule evaluation . . . . . . . . . . . . . . . . . 260–262, 342, 353–355, 359–363, 372
Word moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58, 237
Write 16-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Write 8-bit data cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 379
Write PPAGE cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 379
X
X mask bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 182, 254, 270, 282, 291, 296, 306
x-cycle (8-bit conditional write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 379
XGDX instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
XGDY instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Z
Z status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 121, 134
Zero-page addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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How to Reach Us:
Home Page:
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<size-12>S12CPUV2
Rev. 4.0, 03/2006
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
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