Instruction Set Manual ht Instruction Set Manual Version 1.2, 12.97 tp :/ Se /ww m w ic .s on ie du me ct ns or .d / e/ for the C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers Version 1.2, 12.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C166 Family Microcontroller Instruction Set Manual Revision History: Version 1.2, 12.97 Previous Releases: Version 1.1, 09.95 03.94 Page Subjects 8 BFLD* code size corrected 35 ADDCB: spelling corrected 38 ASHR: "operation" corrected 43, 44 BFLD*: Note improved, format corrected 51 CALLI: "operation" corrected 67 EINIT: Syntax corrected 75 JBC: Condition flags corrected 77 JMPI: "operation" corrected 81 JNBS: Condition flags corrected 86, 87 MUL(U): Flag N corrected 95 PRIOR: "Operation" corrected 104 SCXT: Data Type added 108 SRVWDT: Syntax corrected We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] C166 Family Instruction Set Table of Contents Table of Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Short Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Semiconductor Group 4 Version 1.2, 12.97 C166 Family Instruction Set Introduction 30Mar98@15:00h 1 Introduction The Siemens family of 16-bit microcontrollers offers devices that provide various levels of peripheral performance and programmability. This allows to equip each specific application with the microcontroller that fits best to the required functionality and performance. Still the Siemens family concept provides an easy path to upgrade existing applications or to climb the next level of performance in order to realize a subsequent more sophisticated design. Two major characteristics enable this upgrade path to save and reuse almost all of the engineering efforts that have been made for previous designs: • All family members are based on the same basic architecture • All family members execute the same instructions (except for upgrades for new members) The fact that all members execute the same instructions (almost) saves knowhow with respect to the understanding of the controller itself and also with respect to the used tools (assembler, disassembler, compiler, etc.). This instruction set manual provides an easy and direct access to the instructions of the Siemens 16-bit microcontrollers by listing them according to different criteria, and also unloads the technical manuals for the different devices from redundant information. This manual also describes the different addressing mechanisms and the relation between the logical addresses used in a program and the resulting physical addresses. There is also information provided to calculate the execution time for specific instructions depending on the used address locations and also specific exceptions to the standard rules. Description Levels In the following sections the instructions are compiled according to different criteria in order to provide different levels of precision: • Cross Reference Tables summarize all instructions in condensed tables • The Instruction Set Summary groups the individual instructions into functional groups • The Opcode Table references the instructions by their hexadecimal opcode • The Instruction Description describes each instruction in full detail All instructions listed in this manual are executed by the following devices (new derivatives will be added to this list): C161V, C161K, C161O, C161RI, C161SI, C161CI, C163, C163F, C164CI, C165, C167, C167CR, C167SR, C167S, C167CS. A few instructions (ATOMIC and EXTended instructions) have been added for these devices and are not recognized by the following devices: SAB 80C166, SAB 80C166W, SAB 83C166, SAB 83C166W, SAB 88C166, SAB 88C166W. These differences are noted for each instruction, where applicable. Semiconductor Group 5 Version 1.2, 12.97 C166 Family Instruction Set Short Instruction Summary 30Mar98@15:00h 2 Short Instruction Summary The following compressed cross-reference tables quickly identify a specific instruction and provide basic information about it. Two ordering schemes are included: The first table (two pages) is a compressed cross-reference table that quickly identifies a specific hexadecimal opcode with the respective mnemonic. The second table lists the instructions by their mnemonic and identifies the addressing modes that may be used with a specific instruction and the instruction length depending on the selected addressing mode. This reference helps to optimize instruction sequences in terms of code size and/ or execution time. • 0x 1x 2x 3x 4x 5x 6x 7x x0 ADD ADDC SUB SUBC CMP XOR AND OR x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x2 ADD ADDC SUB SUBC CMP XOR AND OR x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x4 ADD ADDC SUB SUBC - XOR AND OR x5 ADDB ADDCB SUBB SUBCB - XORB ANDB ORB x6 ADD ADDC SUB SUBC CMP XOR AND OR x7 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x8 ADD ADDC SUB SUBC CMP XOR AND OR x9 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB xA BFLDL BFLDH BCMP BMOVN BMOV BOR BAND BXOR xB MUL MULU PRIOR - DIV DIVU DIVL DIVLU xC ROL ROL ROR ROR SHL SHL SHR SHR xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET Semiconductor Group 6 Version 1.2, 12.97 C166 Family Instruction Set Short Instruction Summary 30Mar98@15:00h Note: Both ordering schemes (hexadecimal opcode and mnemonic) are provided in more detailled lists in the following sections of this manual. Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. They are marked in the cross-reference table. 8x 9x Ax Bx Cx Dx Ex Fx x0 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV MOV x1 NEG CPL NEGB CPLB - AT/EXTR MOVB MOVB x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV x3 - - - - - - - MOVB x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB x5 - - DISWDT EINIT MOVBZ MOVBS - - x6 CMPI1 CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV x7 IDLE PWRDN SRVWDT SRST - EXTP/S/R MOVB MOVB x8 MOV MOV MOV MOV MOV MOV MOV - x9 MOVB MOVB MOVB MOVB MOVB MOVB MOVB - xA JB JNB JBC JNBS CALLA CALLS JMPA JMPS xB - TRAP CALLI CALLR RET RETS RETP RETI xC - JMPI ASHR ASHR NOP EXTP/S/R PUSH POP xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET Semiconductor Group 7 Version 1.2, 12.97 C166 Family Instruction Set Short Instruction Summary 30Mar98@15:00h Mnemonic ADD[B] ADDC[B] AND[B] OR[B] SUB[B] SUBC[B] XOR[B] Addressing ModesBytes Rwn Rwm Rwn [Rwi] Rwn [Rwi+] Rwn #data3 reg reg mem #data16 mem reg ASHR ROL / ROR SHL / SHR BAND BCMP BMOV BMOVN BOR / BXOR BCLR BSET BFLDH BFLDL MOV[B] Rwn Rwn Rwm #data4 2 2 Mnemonic CPL[B] NEG[B] DIV DIVL DIVLU DIVU MUL MULU CMPD1/2 CMPI1/2 bitaddrZ.z bitaddrQ.q 4 CMP[B] 2 CALLA JMPA CALLI JMPI CALLS JMPS CALLR JMPR JB JBC JNB JNBS PCALL POP PUSH RETP SCXT MOVBS MOVBZ EXTS EXTSR NOP RET RETI RETS 1) 1) 1) 1) 2 2 2 2 2) 4 4 4 bitaddrQ.q bitoffQ #mask8 #data8 4 Rwn Rwn Rwn Rwn [Rwm] [-Rwm] [Rwn] [Rwn+] [Rwn] Rwm #data4 [Rwm] [Rwm+] Rwn Rwn [Rwm] [Rwm] [Rwm+] 1) 1) 1) 1) 1) 1) 2 2 2 2 2 2 2 2 2 reg Rwn [Rwm+#d16] [Rwn] mem reg mem Rwn reg mem #data16 [Rwm+#d16] Rwn mem [Rwn] mem reg Rbm mem reg 2) 1) 1) 4 4 4 4 4 4 4 2 4 4 Rwm #seg - #irang2 #irang2 3) PRIOR TRAP ATOMIC EXTR EXTP EXTPR SRST/IDLE PWRDN SRVWDT DISWDT EINIT 2 4 2 Addressing ModesBytes Rwn 1) Rwn 2 2 Rwn Rwm 2 Rwn Rwn Rwn Rwn Rwn Rwn Rwn reg reg cc #data4 #data16 mem Rwm [Rwi] [Rwi+] #data3 #data16 mem caddr 2 4 4 2 2 2 2 4 4 4 cc [Rwn] 2 seg caddr 4 rel cc bitaddrQ.q rel rel 2 2 4 1) 1) 1) 1) 2) reg reg caddr 4 2 reg reg Rwn #data16 mem Rwm 4 4 2 #trap7 #irang2 Rwm #pag - 3) #irang2 #irang2 3) 2 2 2 4 4 1) Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rwn]!). Byte oriented instructions (suffix ‘B’) use #data8 instead of #data16. 3) The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. 2) Semiconductor Group 8 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h 3 Instruction Set Summary This chapter summarizes the instructions by listing them according to their functional class. This allows to identify the right instruction(s) for a specific required function. The following notes apply to this summary: Data Addressing Modes Rw: – Word GPR (R0, R1, … , R15) Rb: – Byte GPR (RL0, RH0, …, RL7, RH7) reg: – SFR or GPR (in case of a byte operation on an SFR, only the low byte can be accessed via ‘reg’) mem: – Direct word or byte memory location […]: – Indirect word or byte memory location (Any word GPR can be used as indirect address pointer, except for the arithmetic, logical and compare instructions, where only R0 to R3 are allowed) bitaddr: – Direct bit in the bit-addressable memory area bitoff: – Direct word in the bit-addressable memory area #data: – Immediate constant (The number of significant bits which can be specified by the user is represented by the respective appendix ’x’) #mask8: – Immediate 8-bit mask used for bit-field modifications Multiply and Divide Operations The MDL and MDH registers are implicit source and/or destination operands of the multiply and divide instructions. Branch Target Addressing Modes caddr: – Direct 16-bit jump target address (Updates the Instruction Pointer) seg: – Direct 2-bit segment address (Updates the Code Segment Pointer) rel: – Signed 8-bit jump target word offset address relative to the Instruction Pointer of the following instruction #trap7: – Immediate 7-bit trap or interrupt number. Semiconductor Group 9 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Extension Operations The EXT* instructions override the standard DPP addressing scheme: #pag10: – Immediate 10-bit page address. #seg8: – Immediate 8-bit segment address. Note: The EXTended instructions are not available in the SAB 8XC166(W) devices. Branch Condition Codes cc: Symbolically specifiable condition codes cc_UC cc_Z cc_NZ cc_V cc_NV cc_N cc_NN cc_C cc_NC cc_EQ cc_NE cc_ULT cc_ULE cc_UGE cc_UGT cc_SLE cc_SGE cc_SGT cc_NET Semiconductor Group – – – – – – – – – – – – – – – – – – – Unconditional Zero Not Zero Overflow No Overflow Negative Not Negative Carry No Carry Equal Not Equal Unsigned Less Than Unsigned Less Than or Equal Unsigned Greater Than or Equal Unsigned Greater Than Signed Less Than or Equal Signed Greater Than or Equal Signed Greater Than Not Equal and Not End-of-Table 10 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary Mnemonic Description Bytes Arithmetic Operations ADD Rw, Rw Add direct word GPR to direct GPR 2 ADD Rw, [Rw] Add indirect word memory to direct GPR 2 ADD Rw, [Rw +] Add indirect word memory to direct GPR and postincrement source pointer by 2 2 ADD Rw, #data3 Add immediate word data to direct GPR 2 ADD reg, #data16 Add immediate word data to direct register 4 ADD reg, mem Add direct word memory to direct register 4 ADD mem, reg Add direct word register to direct memory 4 ADDB Rb, Rb Add direct byte GPR to direct GPR 2 ADDB Rb, [Rw] Add indirect byte memory to direct GPR 2 ADDB Rb, [Rw +] Add indirect byte memory to direct GPR and post-increment source pointer by 1 2 ADDB Rb, #data3 Add immediate byte data to direct GPR 2 ADDB reg, #data8 Add immediate byte data to direct register 4 ADDB reg, mem Add direct byte memory to direct register 4 ADDB mem, reg Add direct byte register to direct memory 4 ADDC Rw, Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw, [Rw] Add indirect word memory to direct GPR with Carry 2 ADDC Rw, [Rw +] Add indirect word memory to direct GPR with Carry and post-increment source pointer by 2 2 ADDC Rw, #data3 Add immediate word data to direct GPR with Carry 2 ADDC reg, #data16 Add immediate word data to direct register with Carry 4 ADDC reg, mem Add direct word memory to direct register with Carry 4 ADDC mem, reg Add direct word register to direct memory with Carry 4 ADDCB Rb, Rb Add direct byte GPR to direct GPR with Carry 2 ADDCB Rb, [Rw] Add indirect byte memory to direct GPR with Carry 2 ADDCB Rb, [Rw +] Add indirect byte memory to direct GPR with Carry and post-increment source pointer by 1 2 ADDCB Rb, #data3 Add immediate byte data to direct GPR with Carry 2 ADDCB reg, #data8 Add immediate byte data to direct register with Carry 4 ADDCB reg, mem Add direct byte memory to direct register with Carry 4 Semiconductor Group 11 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Arithmetic Operations (cont’d) ADDCB mem, reg Add direct byte register to direct memory with Carry 4 SUB Rw, Rw Subtract direct word GPR from direct GPR 2 SUB Rw, [Rw] Subtract indirect word memory from direct GPR 2 SUB Rw, [Rw +] Subtract indirect word memory from direct GPR and post-increment source pointer by 2 2 SUB Rw, #data3 Subtract immediate word data from direct GPR 2 SUB reg, #data16 Subtract immediate word data from direct register 4 SUB reg, mem Subtract direct word memory from direct register 4 SUB mem, reg Subtract direct word register from direct memory 4 SUBB Rb, Rb Subtract direct byte GPR from direct GPR 2 SUBB Rb, [Rw] Subtract indirect byte memory from direct GPR 2 SUBB Rb, [Rw +] Subtract indirect byte memory from direct GPR and post-increment source pointer by 1 2 SUBB Rb, #data3 Subtract immediate byte data from direct GPR 2 SUBB reg, #data8 Subtract immediate byte data from direct register 4 SUBB reg, mem Subtract direct byte memory from direct register 4 SUBB mem, reg Subtract direct byte register from direct memory 4 SUBC Rw, Rw Subtract direct word GPR from direct GPR with Carry 2 SUBC Rw, [Rw] Subtract indirect word memory from direct GPR with Carry 2 SUBC Rw, [Rw +] Subtract indirect word memory from direct GPR with Carry and post-increment source pointer by 2 2 SUBC Rw, #data3 Subtract immediate word data from direct GPR with Carry 2 SUBC reg, #data16 Subtract immediate word data from direct register with Carry 4 SUBC reg, mem Subtract direct word memory from direct register with Carry 4 SUBC mem, reg Subtract direct word register from direct memory with Carry 4 SUBCB Rb, Rb Subtract direct byte GPR from direct GPR with Carry 2 SUBCB Rb, [Rw] Subtract indirect byte memory from direct GPR with Carry 2 SUBCB Rb, [Rw +] Subtract indirect byte memory from direct GPR with Carry and post-increment source pointer by 1 2 SUBCB Rb, #data3 Subtract immediate byte data from direct GPR with Carry 2 SUBCB reg, #data8 Subtract immediate byte data from direct register with Carry 4 Semiconductor Group 12 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Arithmetic Operations (cont’d) SUBCB reg, mem Subtract direct byte memory from direct register with Carry 4 SUBCB mem, reg Subtract direct byte register from direct memory with Carry 4 MUL Rw, Rw Signed multiply direct GPR by direct GPR (16-16-bit) 2 MULU Rw, Rw Unsigned multiply direct GPR by direct GPR (16-16-bit) 2 DIV Rw Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL Rw Signed long divide register MD by direct GPR (32-/16-bit) 2 DIVLU Rw Unsigned long divide register MD by direct GPR (32-/16-bit) 2 DIVU Rw Unsigned divide register MDL by direct GPR (16-/16-bit) 2 CPL Rw Complement direct word GPR 2 CPLB Rb Complement direct byte GPR 2 NEG Rw Negate direct word GPR 2 NEGB Rb Negate direct byte GPR 2 Logical Instructions AND Rw, Rw Bitwise AND direct word GPR with direct GPR 2 AND Rw, [Rw] Bitwise AND indirect word memory with direct GPR 2 AND Rw, [Rw +] Bitwise AND indirect word memory with direct GPR and post-increment source pointer by 2 2 AND Rw, #data3 Bitwise AND immediate word data with direct GPR 2 AND reg, #data16 Bitwise AND immediate word data with direct register 4 AND reg, mem Bitwise AND direct word memory with direct register 4 AND mem, reg Bitwise AND direct word register with direct memory 4 ANDB Rb, Rb Bitwise AND direct byte GPR with direct GPR 2 ANDB Rb, [Rw] Bitwise AND indirect byte memory with direct GPR 2 ANDB Rb, [Rw +] Bitwise AND indirect byte memory with direct GPR and post-increment source pointer by 1 2 ANDB Rb, #data3 Bitwise AND immediate byte data with direct GPR 2 ANDB reg, #data8 Bitwise AND immediate byte data with direct register 4 ANDB reg, mem Bitwise AND direct byte memory with direct register 4 ANDB mem, reg Bitwise AND direct byte register with direct memory 4 Semiconductor Group 13 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Logical Instructions (cont’d) OR Rw, Rw Bitwise OR direct word GPR with direct GPR 2 OR Rw, [Rw] Bitwise OR indirect word memory with direct GPR 2 OR Rw, [Rw +] Bitwise OR indirect word memory with direct GPR and post-increment source pointer by 2 2 OR Rw, #data3 Bitwise OR immediate word data with direct GPR 2 OR reg, #data16 Bitwise OR immediate word data with direct register 4 OR reg, mem Bitwise OR direct word memory with direct register 4 OR mem, reg Bitwise OR direct word register with direct memory 4 ORB Rb, Rb Bitwise OR direct byte GPR with direct GPR 2 ORB Rb, [Rw] Bitwise OR indirect byte memory with direct GPR 2 ORB Rb, [Rw +] Bitwise OR indirect byte memory with direct GPR and post-increment source pointer by 1 2 ORB Rb, #data3 Bitwise OR immediate byte data with direct GPR 2 ORB reg, #data8 Bitwise OR immediate byte data with direct register 4 ORB reg, mem Bitwise OR direct byte memory with direct register 4 ORB mem, reg Bitwise OR direct byte register with direct memory 4 XOR Rw, Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw, [Rw] Bitwise XOR indirect word memory with direct GPR 2 XOR Rw, [Rw +] Bitwise XOR indirect word memory with direct GPR and post-increment source pointer by 2 2 XOR Rw, #data3 Bitwise XOR immediate word data with direct GPR 2 XOR reg, #data16 Bitwise XOR immediate word data with direct register 4 XOR reg, mem Bitwise XOR direct word memory with direct register 4 XOR mem, reg Bitwise XOR direct word register with direct memory 4 XORB Rb, Rb Bitwise XOR direct byte GPR with direct GPR 2 XORB Rb, [Rw] Bitwise XOR indirect byte memory with direct GPR 2 XORB Rb, [Rw +] Bitwise XOR indirect byte memory with direct GPR and post-increment source pointer by 1 2 XORB Rb, #data3 Bitwise XOR immediate byte data with direct GPR 2 XORB reg, #data8 Bitwise XOR immediate byte data with direct register 4 XORB reg, mem Bitwise XOR direct byte memory with direct register 4 XORB mem, reg Bitwise XOR direct byte register with direct memory 4 Semiconductor Group 14 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR bitaddr Clear direct bit 2 BSET bitaddr Set direct bit 2 BMOV bitaddr, bitaddr Move direct bit to direct bit 4 BMOVN bitaddr, bitaddr Move negated direct bit to direct bit 4 BAND bitaddr, bitaddr AND direct bit with direct bit 4 BOR bitaddr, bitaddr OR direct bit with direct bit 4 BXOR bitaddr, bitaddr XOR direct bit with direct bit 4 BCMP bitaddr, bitaddr Compare direct bit to direct bit 4 BFLDH bitoff, #mask8, #data8 Bitwise modify masked high byte of bit-addressable direct word memory with immediate data 4 BFLDL bitoff, #mask8, #data8 Bitwise modify masked low byte of bit-addressable direct word memory with immediate data 4 CMP Rw, Rw Compare direct word GPR to direct GPR 2 CMP Rw, [Rw] Compare indirect word memory to direct GPR 2 CMP Rw, [Rw +] Compare indirect word memory to direct GPR and post-increment source pointer by 2 2 CMP Rw, #data3 Compare immediate word data to direct GPR 2 CMP reg, #data16 Compare immediate word data to direct register 4 CMP reg, mem Compare direct word memory to direct register 4 CMPB Rb, Rb Compare direct byte GPR to direct GPR 2 CMPB Rb, [Rw] Compare indirect byte memory to direct GPR 2 CMPB Rb, [Rw +] Compare indirect byte memory to direct GPR and post-increment source pointer by 1 2 CMPB Rb, #data3 Compare immediate byte data to direct GPR 2 CMPB reg, #data8 Compare immediate byte data to direct register 4 CMPB reg, mem Compare direct byte memory to direct register 4 Compare and Loop Control Instructions CMPD1 Rw, #data4 Compare immediate word data to direct GPR and decrement GPR by 1 2 CMPD1 Rw, #data16 Compare immediate word data to direct GPR and decrement GPR by 1 4 Semiconductor Group 15 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Compare and Loop Control Instructions (cont’d) CMPD1 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1 4 CMPD2 Rw, #data4 Compare immediate word data to direct GPR and decrement GPR by 2 2 CMPD2 Rw, #data16 Compare immediate word data to direct GPR and decrement GPR by 2 4 CMPD2 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 2 4 CMPI1 Rw, #data4 Compare immediate word data to direct GPR and increment GPR by 1 2 CMPI1 Rw, #data16 Compare immediate word data to direct GPR and increment GPR by 1 4 CMPI1 Rw, mem Compare direct word memory to direct GPR and increment GPR by 1 4 CMPI2 Rw, #data4 Compare immediate word data to direct GPR and increment GPR by 2 2 CMPI2 Rw, #data16 Compare immediate word data to direct GPR and increment GPR by 2 4 CMPI2 Rw, mem Compare direct word memory to direct GPR and increment GPR by 2 4 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 Prioritize Instruction PRIOR Rw, Rw Shift and Rotate Instructions SHL Rw, Rw Shift left direct word GPR; number of shift cycles specified by direct GPR 2 SHL Rw, #data4 Shift left direct word GPR; number of shift cycles specified by immediate data 2 SHR Rw, Rw Shift right direct word GPR; number of shift cycles specified by direct GPR 2 Semiconductor Group 16 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Shift and Rotate Instructions (cont’d) SHR Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data 2 ROL Rw, Rw Rotate left direct word GPR; number of shift cycles specified by direct GPR 2 ROL Rw, #data4 Rotate left direct word GPR; number of shift cycles specified by immediate data 2 ROR Rw, Rw Rotate right direct word GPR; number of shift cycles specified by direct GPR 2 ROR Rw, #data4 Rotate right direct word GPR; number of shift cycles specified by immediate data 2 ASHR Rw, Rw Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by direct GPR 2 ASHR Rw, #data4 Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by immediate data 2 Data Movement MOV Rw, Rw Move direct word GPR to direct GPR 2 MOV Rw, #data4 Move immediate word data to direct GPR 2 MOV reg, #data16 Move immediate word data to direct register 4 MOV Rw, [Rw] Move indirect word memory to direct GPR 2 MOV Rw, [Rw +] Move indirect word memory to direct GPR and post-increment source pointer by 2 2 MOV [Rw], Rw Move direct word GPR to indirect memory 2 MOV [-Rw], Rw Pre-decrement destination pointer by 2 and move direct word GPR to indirect memory 2 MOV [Rw], [Rw] Move indirect word memory to indirect memory 2 MOV [Rw +], [Rw] Move indirect word memory to indirect memory and post-increment destination pointer by 2 2 MOV [Rw], [Rw +] Move indirect word memory to indirect memory and post-increment source pointer by 2 2 MOV Rw, [Rw + #data16] Move indirect word memory by base plus constant to direct GPR 4 MOV [Rw + #data16], Rw Move direct word GPR to indirect memory by base plus constant 4 Semiconductor Group 17 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Data Movement (cont’d) MOV [Rw], mem Move direct word memory to indirect memory 4 MOV mem, [Rw] Move indirect word memory to direct memory 4 MOV reg, mem Move direct word memory to direct register 4 MOV mem, reg Move direct word register to direct memory 4 MOVB Rb, Rb Move direct byte GPR to direct GPR 2 MOVB Rb, #data4 Move immediate byte data to direct GPR 2 MOVB reg, #data8 Move immediate byte data to direct register 4 MOVB Rb, [Rw] Move indirect byte memory to direct GPR 2 MOVB Rb, [Rw +] Move indirect byte memory to direct GPR and post-increment source pointer by 1 2 MOVB [Rw], Rb Move direct byte GPR to indirect memory 2 MOVB [-Rw], Rb Pre-decrement destination pointer by 1 and move direct byte GPR to indirect memory 2 MOVB [Rw], [Rw] Move indirect byte memory to indirect memory 2 MOVB [Rw +], [Rw] Move indirect byte memory to indirect memory and post-increment destination pointer by 1 2 MOVB [Rw], [Rw +] Move indirect byte memory to indirect memory and post-increment source pointer by 1 2 MOVB Rb, [Rw + #data16] Move indirect byte memory by base plus constant to direct GPR 4 MOVB [Rw + #data16], Rb Move direct byte GPR to indirect memory by base plus constant 4 MOVB [Rw], mem Move direct byte memory to indirect memory 4 MOVB mem, [Rw] Move indirect byte memory to direct memory 4 MOVB reg, mem Move direct byte memory to direct register 4 MOVB mem, reg Move direct byte register to direct memory 4 MOVBS Rw, Rb Move direct byte GPR with sign extension to direct word GPR 2 MOVBS reg, mem Move direct byte memory with sign extension to direct word register 4 MOVBS mem, reg Move direct byte register with sign extension to direct word memory 4 Semiconductor Group 18 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes Data Movement (cont’d) MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct word GPR 2 MOVBZ reg, mem Move direct byte memory with zero extension to direct word register 4 MOVBZ mem, reg Move direct byte register with zero extension to direct word memory 4 Jump and Call Operations JMPA cc, caddr Jump absolute if condition is met 4 JMPI cc, [Rw] Jump indirect if condition is met 2 JMPR cc, rel Jump relative if condition is met 2 JMPS seg, caddr Jump absolute to a code segment 4 JB bitaddr, rel Jump relative if direct bit is set 4 JBC bitaddr, rel Jump relative and clear bit if direct bit is set 4 JNB bitaddr, rel Jump relative if direct bit is not set 4 JNBS bitaddr, rel Jump relative and set bit if direct bit is not set 4 CALLA cc, caddr Call absolute subroutine if condition is met 4 CALLI cc, [Rw] Call indirect subroutine if condition is met 2 CALLR rel Call relative subroutine 2 CALLS seg, caddr Call absolute subroutine in any code segment 4 PCALL reg, caddr Push direct word register onto system stack and call absolute subroutine 4 TRAP #trap7 Call interrupt service routine via immediate trap number 2 System Stack Operations POP reg Pop direct word register from system stack 2 PUSH reg Push direct word register onto system stack 2 SCXT reg, #data16 Push direct word register onto system stack und update register with immediate data 4 SCXT reg, mem Push direct word register onto system stack und update register with direct memory 4 Semiconductor Group 19 Version 1.2, 12.97 C166 Family Instruction Set Instruction Set Summary 30Mar98@15:00h Instruction Set Summary (cont’d)* Mnemonic Description Bytes RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 Return from intra-segment subroutine and pop direct word register from system stack 2 Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 Return Operations RETP reg RETI System Control ATOMIC #irang2 Begin ATOMIC sequence *) 2 EXTR #irang2 Begin EXTended Register sequence *) 2 2 EXTP Rw, #irang2 Begin EXTended Page sequence *) EXTP #pag10, #irang2 Begin EXTended Page sequence *) 4 EXTPR Rw, #irang2 Begin EXTended Page and Register sequence *) 2 Begin EXTended Page and Register sequence *) 4 2 EXTPR #pag10, #irang2 EXTS Rw, #irang2 Begin EXTended Segment sequence *) EXTS #seg8, #irang2 Begin EXTended Segment sequence *) 4 EXTSR Rw, #irang2 Begin EXTended Segment and Register sequence *) 2 Begin EXTended Segment and Register sequence *) 4 EXTSR #seg8, #irang2 Miscellaneous NOP *) Null operation 2 The EXTended instructions are not available in the SAB 8XC166(W) devices. Semiconductor Group 20 Version 1.2, 12.97 C166 Family Instruction Set Instruction Opcodes 30Mar98@15:00h 4 Instruction Opcodes The following pages list the instructions of the 16-bit microcontrollers ordered by their hexadecimal opcodes. This helps to identify specific instructions when reading executable code, ie. during the debugging phase. Notes for Opcode Lists 1) These instructions are encoded by means of additional bits in the operand field of the instruction x0H – x7H: x8H – xBH: xCH – xFH: Rw, #data3 Rw, [Rw] Rw, [Rw +] or or or Rb, #data3 Rb, [Rw] Rb, [Rw +] For these instructions only the lowest four GPRs, R0 to R3, can be used as indirect address pointers. 2) These instructions are encoded by means of additional bits in the operand field of the instruction 00xx.xxxxB: 01xx.xxxxB: 10xx.xxxxB: 11xx.xxxxB: EXTS EXTP EXTSR EXTPR or ATOMIC or EXTR The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. Notes on the JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the opcode. Two mnemonic representation alternatives exist for some of the condition codes. Notes on the BCLR and BSET Instructions The position of the bit to be set or to be cleared is specified by the opcode. The operand ‘bitoff.n’ (n = 0 to 15) refers to a particular bit within a bit-addressable word. Notes on the Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by ‘----’ is decoded by the CPU. Semiconductor Group 21 Version 1.2, 12.97 C166 Family Instruction Set Instruction Opcodes 30Mar98@15:00h Hexcode Mnemonic Operands 00 01 02 03 04 Number of Bytes 2 2 4 4 4 Hex- Numcode ber of Bytes 20 2 21 2 22 4 23 4 24 4 Mnemonic Operands ADD ADDB ADD ADDB ADD Rw, Rw Rb, Rb reg, mem reg, mem mem, reg SUB SUBB SUB SUBB SUB Rw, Rw Rb, Rb reg, mem reg, mem mem, reg 05 06 07 08 4 4 4 2 ADDB ADD ADDB ADD mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitoff, #mask8, #data8 Rw, Rw Rw, Rw cc_UC, rel 25 26 27 28 4 4 4 2 SUBB SUB SUBB SUB 29 2 SUBB 2A 4 BCMP mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr 09 2 ADDB 0A 4 BFLDL 0B 0C 0D 2 2 2 MUL ROL JMPR 2B 2C 2D 2 2 2 PRIOR ROR JMPR 0E 0F 10 11 12 13 14 15 16 17 18 2 2 2 2 4 4 4 4 4 4 2 BCLR BSET ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC 2E 2F 30 31 32 33 34 35 36 37 38 2 2 2 2 4 4 4 4 4 4 2 BCLR BSET SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC SUBCB SUBC 39 2 SUBCB 3A 4 BMOVN MULU ROL JMPR bitoff.0 bitoff.0 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitoff, #mask8, #data8 Rw, Rw Rw, #data4 cc_NET, rel 19 2 ADDCB 1A 4 BFLDH 1B 1C 1D 2 2 2 3B 3C 3D 2 2 ROR JMPR 1E 1F 2 2 BCLR BSET bitoff.1 bitoff.1 3E 3F 2 2 BCLR BSET Semiconductor Group 22 Rw, Rw Rw, Rw cc_EQ, rel or cc_Z, rel bitoff.2 bitoff.2 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw, #data4 cc_NE, rel or cc_NZ, rel bitoff.3 bitoff.3 Version 1.2, 12.97 C166 Family Instruction Set Instruction Opcodes 30Mar98@15:00h Hexcode Mnemonic Operands 40 41 42 43 44 Number of Bytes 2 2 4 4 - Hex- Numcode ber of Bytes 60 2 61 2 62 4 63 4 64 4 Mnemonic Operands CMP CMPB CMP CMPB - Rw, Rw Rb, Rb reg, mem reg, mem - AND ANDB AND ANDB AND Rw, Rw Rb, Rb reg, mem reg, mem mem, reg 45 46 47 48 4 4 2 CMP CMPB CMP 65 66 67 68 4 4 4 2 ANDB AND ANDB AND 69 2 ANDB BMOV reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr 6A 4 BAND mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr 49 2 CMPB 4A 4 4B 4C 4D 2 2 2 DIV SHL JMPR Rw Rw, Rw cc_V, rel 6B 6C 6D 2 2 2 DIVL SHR JMPR Rw Rw, Rw cc_N, rel 4E 4F 50 51 52 53 54 55 56 57 58 2 2 2 2 4 4 4 4 4 4 2 BCLR BSET XOR XORB XOR XORB XOR XORB XOR XORB XOR 6E 6F 70 71 72 73 74 75 76 77 78 2 2 2 2 4 4 4 4 4 4 2 BCLR BSET OR ORB OR ORB OR ORB OR ORB OR 59 2 XORB 79 2 ORB 5A 4 BOR bitoff.4 bitoff.4 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr 7A 4 BXOR bitoff.6 bitoff.6 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr 5B 5C 5D 2 2 2 DIVU SHL JMPR Rw Rw, #data4 cc_NV, rel 7B 7C 7D 2 2 2 DIVLU SHR JMPR Rw Rw, #data4 cc_NN, rel 5E 5F 2 2 BCLR BSET bitoff.5 bitoff.5 7E 7F 2 2 BCLR BSET bitoff.7 bitoff.7 Semiconductor Group 23 Version 1.2, 12.97 C166 Family Instruction Set Instruction Opcodes 30Mar98@15:00h Hexcode Mnemonic Operands 80 81 82 83 84 Number of Bytes 2 2 4 4 Hex- Numcode ber of Bytes A0 2 A1 2 A2 4 A3 A4 4 Mnemonic Operands CMPI1 NEG CMPI1 MOV Rw, #data4 Rw Rw, mem [Rw], mem CMPD1 NEGB CMPD1 MOVB Rw, #data4 Rb Rw, mem [Rw], mem 85 86 87 88 4 4 2 CMPI1 IDLE MOV Rw, #data16 [-Rw], Rw A5 A6 A7 A8 4 4 4 2 DISWDT CMPD1 SRVWDT MOV Rw, [Rw] 89 2 MOVB [-Rw], Rb A9 2 MOVB Rb, [Rw] 8A 4 JB bitaddr, rel AA 4 JBC bitaddr, rel 8B 8C 8D 2 JMPR AB AC AD 2 2 2 CALLI ASHR JMPR cc, [Rw] Rw, Rw cc_SGT, rel 8E 8F 90 91 2 2 2 2 BCLR BSET CMPI2 CPL cc_C, rel or cc_ULT, rel bitoff.8 bitoff.8 Rw, #data4 Rw AE AF B0 B1 2 2 2 2 BCLR BSET CMPD2 CPLB bitoff.10 bitoff.10 Rw, #data4 Rb 92 93 94 4 4 CMPI2 MOV Rw, mem mem, [Rw] B2 B3 B4 4 4 CMPD2 MOVB Rw, mem mem, [Rw] 95 96 97 4 4 CMPI2 PWRDN Rw, #data16 B5 B6 B7 4 4 4 EINIT CMPD2 SRST Rw, #data16 98 99 9A 2 2 4 MOV MOVB JNB Rw, [Rw+] Rb, [Rw+] bitaddr, rel B8 B9 BA 2 2 4 MOV MOVB JNBS [Rw], Rw [Rw], Rb bitaddr, rel 9B 9C 2 2 TRAP JMPI #trap7 cc, [Rw] BB BC 2 2 CALLR ASHR rel Rw, #data4 9D 2 JMPR BD 2 JMPR cc_SLE, rel 9E 9F 2 2 BCLR BSET cc_NC, rel or cc_UGE, rel bitoff.9 bitoff.9 BE BF 2 2 BCLR BSET bitoff.11 bitoff.11 Semiconductor Group 24 Rw, #data16 Version 1.2, 12.97 C166 Family Instruction Set Instruction Opcodes 30Mar98@15:00h Hexcode Mnemonic Operands C0 C1 C2 C3 C4 Number of Bytes 2 4 4 MOVBZ MOVBZ MOV C5 C6 C7 C8 4 4 2 MOVBZ SCXT MOV Rw, Rb reg, mem [Rw+#data16], Rw mem, reg reg, #data16 [Rw], [Rw] C9 2 MOVB CA 4 CALLA CB CC CD 2 2 2 RET NOP JMPR CE CF D0 D1 2 2 2 2 D2 D3 D4 4 4 BCLR BSET MOVBS ATOMIC or EXTR MOVBS MOV D5 D6 D7 4 4 4 MOVBS SCXT EXTP(R), EXTS(R) Hex- Numcode ber of Bytes E0 2 E1 2 E2 4 E3 E4 4 Mnemonic Operands MOV MOVB PCALL MOVB E5 E6 E7 E8 4 4 2 MOV MOVB MOV Rw, #data4 Rb, #data4 reg, caddr [Rw+#data16], Rb reg, #data16 reg, #data8 [Rw], [Rw+] [Rw], [Rw] E9 2 MOVB [Rw], [Rw+] cc, addr EA 4 JMPA cc, caddr cc_SLT, rel EB EC ED 2 2 2 RETP PUSH JMPR reg reg cc_UGT, rel bitoff.12 bitoff.12 Rw, Rb #irang2 2) EE EF F0 F1 2 2 2 2 BCLR BSET MOV MOVB bitoff.14 bitoff.14 Rw, Rw Rb, Rb reg, mem Rw, [Rw + #data16] mem, reg reg, mem #pag10,#irang2 #seg8, #irang2 F2 F3 F4 4 4 4 MOV MOVB MOVB F5 F6 F7 4 4 MOV MOVB reg, mem reg, mem Rb, [Rw + #data16] mem, reg mem, reg [Rw+], [Rw] [Rw+], [Rw] seg, caddr F8 F9 FA 4 JMPS seg, caddr Rw, #irang2 2) FB FC 2 2 RETI POP reg cc_SGE, rel FD 2 JMPR cc_ULE, rel bitoff.13 bitoff.13 FE FF 2 2 BCLR BSET bitoff.15 bitoff.15 2) D8 D9 DA 2 2 4 MOV MOVB CALLS DB DC 2 2 DD 2 RETS EXTP(R), EXTS(R) JMPR DE DF 2 2 BCLR BSET Semiconductor Group 25 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h 5 Instruction Description This chapter describes each instruction in detail. The instructions are ordered alphabetically, and the description contains the following elements: •Instruction Name• Specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference. The mnemonics have been chosen with regard to the particular operation which is performed by the specified instruction. •Syntax• Specifies the mnemonic opcode and the required formal operands of the instruction as used in the following subsection ’Operation’. There are instructions with either none, one, two or three operands, which must be separated from each other by commas: MNEMONIC {op1 {,op2 {,op3 } } } The syntax for the actual operands of an instruction depends on the selected addressing mode. All of the addressing modes available are summarized at the end of each single instruction description. In contrast to the syntax for the instructions described in the following, the assembler provides much more flexibility in writing C166 Family programs (e.g. by generic instructions and by automatically selecting appropriate addressing modes whenever possible), and thus it eases the use of the instruction set. For more information about this item please refer to the Assembler manual. •Operation• This part presents a logical description of the operation performed by an instruction by means of a symbolic formula or a high level language construct. The following symbols are used to represent data movement, arithmetic or logical operators. Diadic operations: (opX) operator (opY) ← (opY) is MOVED into (opX) + (opX) is ADDED to (opY) - (opY) is SUBTRACTED from (opX) * (opX) is MULTIPLIED by (opY) / (opX) is DIVIDED by (opY) ∧ (opX) is logically ANDed with (opY) ∨ (opX) is logically ORed with (opY) ⊕ (opX) is logically EXCLUSIVELY ORed with (opY) ⇔ (opX) is COMPARED against (opY) mod (opX) is divided MODULO (opY) is operator (opX) logically COMPLEMENTED Monadic operations: ¬ (opX) Semiconductor Group 26 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h Missing or existing parentheses signify whether the used operand specifies an immediate constant value, an address or a pointer to an address as follows: opX Specifies the immediate constant value of opX (opX) Specifies the contents of opX (opXn) Specifies the contents of bit n of opX ((opX)) Specifies the contents of the contents of opX (ie. opX is used as pointer to the actual operand) The following operands will also be used in the operational description: CP Context Pointer register CSP Code Segment Pointer register IP Instruction Pointer MD Multiply/Divide register (32 bits wide, consists of MDH and MDL) MDL, MDH Multiply/Divide Low and High registers (each 16 bit wide ) PSW Program Status Word register SP System Stack Pointer register SYSCON System Configuration register C Carry condition flag in the PSW register V Overflow condition flag in the PSW register SGTDIS Segmentation Disable bit in the SYSCON register count Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation tmp Temporary variable for an intermediate result 0, 1, 2,... Constant values due to the data format of the specified operation •Data Types• This part specifies the particular data type according to the instruction. Basically, the following data types are possible: BIT, BYTE, WORD, DOUBLEWORD Except for those instructions which extend byte data to word data, all instructions have only one particular data type. Note that the data types mentioned in this subsection do not consider accesses to indirect address pointers or to the system stack which are always performed with word data. Moreover, no data type is specified for System Control Instructions and for those of the branch instructions which do not access any explicitly addressed data. Semiconductor Group 27 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h •Description• This part provides a brief verbal description of the action that is executed by the respective instruction. •Condition Code• This notifies that the respective instruction contains a condition code, so it is executed, if the specified condition is true, and is skipped, if it is false. The table below summarizes the 16 possible condition codes that can be used within Call and Branch instructions. The table shows the mnemonic abbreviations, the test that is executed for a specific condition and the internal representation by a 4-bit number. Condition Code Mnemonic cc Test Description Condition Code Number c cc_UC 1=1 Unconditional 0H cc_Z Z=1 Zero 2H cc_NZ Z=0 Not zero 3H cc_V V=1 Overflow 4H cc_NV V=0 No overflow 5H cc_N N=1 Negative 6H cc_NN N=0 Not negative 7H cc_C C=1 Carry 8H cc_NC C=0 No carry 9H cc_EQ Z=1 Equal 2H cc_NE Z=0 Not equal 3H cc_ULT C=1 Unsigned less than 8H cc_ULE (Z∨C) = 1 Unsigned less than or equal FH cc_UGE C=0 Unsigned greater than or equal 9H cc_UGT (Z∨C) = 0 Unsigned greater than EH cc_SLT (N⊕V) = 1 Signed less than CH cc_SLE (Z∨(N⊕V)) = 1 Signed less than or equal BH cc_SGE (N⊕V) = 0 Signed greater than or equal DH cc_SGT (Z∨(N⊕V)) = 0 Signed greater than AH cc_NET (Z∨E) = 0 Not equal AND not end of table 1H Semiconductor Group 28 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h •Condition Flags• This part reflects the state of the N, C, V, Z and E flags in the PSW register which is the state after execution of the corresponding instruction, except if the PSW register itself was specified as the destination operand of that instruction (see Note). The resulting state of the flags is represented by symbols as follows: ’*’ The flag is set due to the following standard rules for the corresponding flag: N=1: MSB of the result is set N=0: MSB of the result is not set C=1: Carry occured during operation C=0: No Carry occured during operation V=1: Arithmetic Overflow occured during operation V=0: No Arithmetic Overflow occured during operation Z=1: Result equals zero Z=0: Result does not equal zero E=1: Source operand represents the lowest negative number (either 8000h for word data or 80h for byte data) E=0: Source operand does not represent the lowest negative number for the specified data type ’S’ The flag is set due to rules which deviate from the described standard. For more details see instruction pages (below) or the ALU status flags description. ’-’ The flag is not affected by the operation. ’0’ The flag is cleared by the operation. ’NOR’ The flag contains the logical NORing of the two specified bit operands. ’AND’ The flag contains the logical ANDing of the two specified bit operands. ’OR’ The flag contains the logical ORing of the two specified bit operands. ’XOR’ The flag contains the logical XORing of the two specified bit operands. ’B’ The flag contains the original value of the specified bit operand. ’B’ The flag contains the complemented value of the specified bit operand. Note: If the PSW register was specified as the destination operand of an instruction, the condition flags can not be interpreted as just described, because the PSW register is modified depending on the data format of the instruction as follows: For word operations, the PSW register is overwritten with the word result. For byte operations, the non-addressed byte is cleared and the addressed byte is overwritten. For bit or bit-field operations on the PSW register, only the specified bits are modified. Supposed that the condition flags were not selected as destination bits, they stay unchanged. This means that they keep the state after execution of the previous instruction. In any case, if the PSW was the destination operand of an instruction, the PSW flags do NOT represent the condition flags of this instruction as usual. Semiconductor Group 29 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h •Addressing Modes• This part specifies which combinations of different addressing modes are available for the required operands. Mostly, the selected addressing mode combination is specified by the opcode of the corresponding instruction. However, there are some arithmetic and logical instructions where the addressing mode combination is not specified by the (identical) opcodes but by particular bits within the operand field. The addressing mode entries are made up of three elements: Mnemonic Shows an example of what operands the respective instruction will accept. Format This part specifies the format of the instructions as it is represented in the assembler listing. The figure below shows the reference between the instruction format representation of the assembler and the corresponding internal organization of such an instruction format (N = nibble = 4 bits). The following symbols are used to describe the instruction formats: 00H through FFH : Instruction Opcodes 0, 1 : Constant Values :.... : Each of the 4 characters immediately following a colon represents a single bit :..ii : 2-bit short GPR address (Rwi) SS : Code segment number (seg). 8-bit for C165/7, 2-bit (:..ss) for SAB8xC166 :..## : 2-bit immediate constant (#irang2) :.### : 3-bit immediate constant (#data3) c : 4-bit condition code specification (cc) n : 4-bit short GPR address (Rwn or Rbn) m : 4-bit short GPR address (Rwm or Rbm) q : 4-bit position of the source bit within the word specified by QQ z : 4-bit position of the destination bit within the word specified by ZZ # : 4-bit immediate constant (#data4) t:ttt0 : 7-bit trap number (#trap7) QQ : 8-bit word address of the source bit (bitoff) rr : 8-bit relative target address word offset (rel) RR : 8-bit word address reg ZZ : 8-bit word address of the destination bit (bitoff) ## : 8-bit immediate constant (#data8) ## xx : 8-bit immediate constant (represented by #data16, byte xx is not significant) @@ : 8-bit immediate constant (#mask8) MM MM : 16-bit address (mem or caddr; low byte, high byte) ## ## : 16-bit immediate constant (#data16; low byte, high byte) Number of Bytes Specifies the size of an instruction in bytes. All C166 Family instructions consist of either 2 or 4 bytes. Regarding the instruction size, all instructions can be classified as either single word or double word instructions. Semiconductor Group 30 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h Representation in the Assembler Listing: N2N1 N4N3 N6N5 N8N7 High Byte 2nd word Low Byte 2nd word High Byte 1st word Low Byte 1st word Internal Organization: MSB N8 Bits in ascending order LSB N7 N6 N5 N4 N3 N2 N1 Figure 5-1: Instruction Format Representation Notes on the ATOMIC and EXTended Instructions These instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable standard and PEC interrupts and class A traps during a sequence of the following 1...4 instructions. The length of the sequence is determined by an operand (op1 or op2, depending on the instruction). The EXTended instruction additionally change the addressing mechanism during this sequence (see detailled instruction description). The ATOMIC and EXTended instructions become active immediately, so no additional NOPs are required. All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense. Any instruction type can be used with the ATOMIC and EXTended instructions. CAUTION: When a Class B trap interupts an ATOMIC or EXTended sequence, this sequence is terminated, the interrupt lock is removed and the standard condition is restored, before the trap routine is executed! The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions! CAUTION: Be careful, when using the ATOMIC and EXTended instructions with other system control or branch instructions. CAUTION: Be careful, when using nested ATOMIC and EXTended instructions. There is ONE counter to control the length of such a sequence, ie. issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with value of the new instruction. Note: The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices. The following pages of this section contain a detailled description of each instruction of the C166 Family in alphabetical order. Semiconductor Group 31 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ADD ADD Integer Addition Syntax ADD Operation (op1) ← (op1) + (op2) Data Types WORD Description Performs a 2’s complement binary addition of the source operand specified by op2 and the destination operand specified by op1. The sum is then stored in op1. Condition Flags op1, op2 E Z V C N * * * * * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ADD Rwn, Rwm 00 nm 2 ADD Rwn, [Rwi] 08 n:10ii 2 ADD Rwn, [Rwi+] 08 n:11ii 2 ADD Rwn, #data3 08 n:0### 2 ADD reg, #data16 06 RR ## ## 4 ADD reg, mem 02 RR MM MM 4 ADD mem, reg 04 RR MM MM 4 32 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ADDB ADDB Integer Addition Syntax ADDB Operation (op1) ← (op1) + (op2) Data Types BYTE Description Performs a 2’s complement binary addition of the source operand specified by op2 and the destination operand specified by op1. The sum is then stored in op1. Condition Flags op1, op2 E Z V C N * * * * * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ADDB Rbn, Rbm 01 nm 2 ADDB Rbn, [Rwi] 09 n:10ii 2 ADDB Rbn, [Rwi+] 09 n:11ii 2 ADDB Rbn, #data3 09 n:0### 2 ADDB reg, #data16 07 RR ## xx 4 ADDB reg, mem 03 RR MM MM 4 ADDB mem, reg 05 RR MM MM 4 33 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ADDC Integer Addition with Carry ADDC Syntax ADDC Operation (op1) ← (op1) + (op2) + (C) Data Types WORD Description Performs a 2’s complement binary addition of the source operand specified by op2, the destination operand specified by op1 and the previously generated carry bit. The sum is then stored in op1. This instruction can be used to perform multiple precision arithmetic. Condition Flags op1, op2 E Z V C N * S * * * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero and previous Z flag was set. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ADDC Rwn, Rwm 10 nm 2 ADDC Rwn, [Rwi] 18 n:10ii 2 ADDC Rwn, [Rwi+] 18 n:11ii 2 ADDC Rwn, #data3 18 n:0### 2 ADDC reg, #data16 16 RR ## ## 4 ADDC reg, mem 12 RR MM MM 4 ADDC mem, reg 14 RR MM MM 4 34 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ADDCB Integer Addition with Carry ADDCB Syntax ADDCB Operation (op1) ← (op1) + (op2) + (C) Data Types BYTE Description Performs a 2’s complement binary addition of the source operand specified by op2, the destination operand specified by op1 and the previously generated carry bit. The sum is then stored in op1. This instruction can be used to perform multiple precision arithmetic. Condition Flags op1, op2 E Z V C N * S * * * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero and previous Z flag was set.. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a carry is generated from the most significant bit of the specified data type. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ADDCB Rbn, Rbm 11 nm 2 ADDCB Rbn, [Rwi] 19 n:10ii 2 ADDCB Rbn, [Rwi+] 19 n:11ii 2 ADDCB Rbn, #data3 19 n:0### 2 ADDCB reg, #data16 17 RR ## xx 4 ADDCB reg, mem 13 RR MM MM 4 ADDCB mem, reg 15 RR MM MM 4 35 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h AND AND Logical AND Syntax AND Operation (op1) ← (op1) ∧ (op2) Data Types WORD Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * 0 0 * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes AND Rwn, Rwm 60 nm 2 AND Rwn, [Rwi] 68 n:10ii 2 AND Rwn, [Rwi+] 68 n:11ii 2 AND Rwn, #data3 68 n:0### 2 AND reg, #data16 66 RR ## ## 4 AND reg, mem 62 RR MM MM 4 AND mem, reg 64 RR MM MM 4 36 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ANDB ANDB Logical AND Syntax ANDB Operation (op1) ← (op1) ∧ (op2) Data Types BYTE Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * 0 0 * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ANDB Rbn, Rbm 61 nm 2 ANDB Rbn, [Rwi] 69 n:10ii 2 ANDB Rbn, [Rwi+] 69 n:11ii 2 ANDB Rbn, #data3 69 n:0### 2 ANDB reg, #data16 67 RR ## xx 4 ANDB reg, mem 63 RR MM MM 4 ANDB mem, reg 65 RR MM MM 4 37 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ASHR Arithmetic Shift Right ASHR Syntax ASHR Operation (count) ← (op2) (V) ← 0 (C) ← 0 DO WHILE (count) ≠ 0 (V) ← (C) ∨ (V) (C) ← (op10) (op1n) ← (op1n+1) [n=0...14] (count) ← (count) - 1 END WHILE Data Types WORD Description Arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2. To preserve the sign of the original operand op1, the most significant bits of the result are filled with zeros if the original MSB was a 0 or with ones if the original MSB was a 1. The Overflow flag is used as a Rounding flag. The LSB is shifted into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. Condition Flags op1, op2 E Z V C N 0 * S S * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag. Cleared for a shift count of zero. C The carry flag is set according to the last LSB shifted out of op1. Cleared for a shift count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ASHR Rwn, Rwm AC nm 2 ASHR Rwn, #data4 BC #n 2 38 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ATOMIC Begin ATOMIC Sequence ATOMIC Syntax ATOMIC Operation (count) ← (op1) [1 ≤ op1 ≤ 4] Disable interrupts and Class A traps DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ← (count) - 1 END WHILE (count) = 0 Enable interrupts and traps Description Causes standard and PEC interrupts and class A hardware traps to be disabled for a specified number of instructions. The ATOMIC instruction becomes immediately active such that no additional NOPs are required. Depending on the value of op1, the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction. All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense. Any instruction type can be used with the ATOMIC instruction. Note The ATOMIC instruction must be used carefully (see introductory note). The ATOMIC instruction is not available in the SAB 8XC166(W) devices. Condition Flags op1 E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic ATOMIC Semiconductor Group Format #irang2 D1 :00##-0 39 Bytes 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BAND BAND Bit Logical AND Syntax BAND Operation (op1) ← (op1) ∧ (op2) Data Types BIT Description Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N 0 NOR OR AND XOR E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BAND Semiconductor Group Format bitaddrZ.z, bitaddrQ.q 40 6A QQ ZZ qz Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BCLR BCLR Bit Clear Syntax BCLR Operation (op1) ← 0 Data Types BIT Description CLears the bit specified by op1. This instruction is primarily used for peripheral and system control. Condition Flags op1 E Z V C N 0 B 0 0 B E Always cleared. Z Contains the logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic BCLR Semiconductor Group bitaddrQ.q 41 Format Bytes qE QQ 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BCMP BCMP Bit to Bit Compare Syntax BCMP Operation (op1) ⇔ (op2) Data Types BIT Description Performs a single bit comparison of the source bit specified by operand op1 to the source bit specified by operand op2. No result is written by this instruction. Only the condition codes are updated. Note: The meaning of the condition flags for the BCMP instruction is different from the meaning of the flags for the other compare instructions. Condition Flags op1, op2 E Z V C N 0 NOR OR AND XOR E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BCMP Semiconductor Group Format bitaddrZ.z, bitaddrQ.q 42 2A QQ ZZ qz Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BFLDH BFLDH Bit Field High Byte Syntax BFLDH op1, op2, op3 Operation (tmp) ← (op1) (high byte (tmp)) ← ((high byte (tmp) ∧ ¬op2) ∨ op3) (op1) ← (tmp) Data Types WORD Description Replaces those bits in the high byte of the destination word operand op1 which are selected by a ’1’ in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3. Note: op1 bits which shall remain unchanged must have a ’0’ in the respective bit of both the AND mask op2 and the OR mask op3. Otherwise a ’1’ in op3 will set the corresponding op1 bit (see „Operation“). Condition Flags E Z V C N 0 * 0 0 * E Always cleared. Z Set if the word result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the word result is set. Cleared otherwise. Addressing Modes Mnemonic BFLDH Semiconductor Group Format bitoffQ, #mask8, #data8 1A QQ ## @@ 43 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BFLDL BFLDL Bit Field Low Byte Syntax BFLDL op1, op2, op3 Operation (tmp) ← (op1) (low byte (tmp)) ← ((low byte (tmp) ∧ ¬op2) ∨ op3) (op1) ← (tmp) Data Types WORD Description Replaces those bits in the low byte of the destination word operand op1 which are selected by a ’1’ in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3. Note: op1 bits which shall remain unchanged must have a ’0’ in the respective bit of both the AND mask op2 and the OR mask op3. Otherwise a ’1’ in op3 will set the corresponding op1 bit (see „Operation“). Condition Flags E Z V C N 0 * 0 0 * E Always cleared. Z Set if the word result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the word result is set. Cleared otherwise. Addressing Modes Mnemonic BFLDL Semiconductor Group Format bitoffQ, #mask8, #data8 0A QQ @@ ## 44 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BMOV BMOV Bit to Bit Move Syntax BMOV Operation (op1) ← (op2) Data Types BIT Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1. The source bit is examined and the flags are updated accordingly. Condition Flags op1, op2 E Z V C N 0 B 0 0 B E Always cleared. Z Contains the logical negation of the previous state of the source bit. V Always cleared. C Always cleared. N Contains the previous state of the source bit. Addressing Modes Mnemonic BMOV Semiconductor Group Format bitaddrZ.z, bitaddrQ.q 45 4A QQ ZZ qz Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BMOVN Bit to Bit Move and Negate BMOVN Syntax BMOVN Operation (op1) ← ¬(op2) Data Types BIT Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1. The source bit is examined and the flags are updated accordingly. Condition Flags op1, op2 E Z V C N 0 B 0 0 B E Always cleared. Z Contains the logical negation of the previous state of the source bit. V Always cleared. C Always cleared. N Contains the previous state of the source bit. Addressing Modes Mnemonic BMOVN Semiconductor Group Format bitaddrZ.z, bitaddrQ.q 46 3A QQ ZZ qz Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BOR BOR Bit Logical OR Syntax BOR Operation (op1) ← (op1) ∨ (op2) Data Types BIT Description Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The ORed result is then stored in op1. Condition Flags op1, op2 E Z V C N 0 NOR OR AND XOR E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BOR Semiconductor Group Format bitaddrZ.z, bitaddrQ.q 47 5A QQ ZZ qz Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BSET BSET Bit Set Syntax BSET Operation (op1) ← 1 Data Types BIT Description Sets the bit specified by op1. This instruction is primarily used for peripheral and system control. Condition Flags op1 E Z V C N 0 B 0 0 B E Always cleared. Z Contains the logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic BSET Semiconductor Group bitaddrQ.q 48 Format Bytes qF QQ 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h BXOR BXOR Bit Logical XOR Syntax BXOR Operation (op1) ← (op1) ⊕ (op2) Data Types BIT Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The XORed result is then stored in op1. Condition Flags op1, op2 E Z V C N 0 NOR OR AND XOR E Always cleared. Z Contains the logical NOR of the two specified bits. V Contains the logical OR of the two specified bits. C Contains the logical AND of the two specified bits. N Contains the logical XOR of the two specified bits. Addressing Modes Mnemonic BXOR Semiconductor Group Format bitaddrZ.z, bitaddrQ.q 49 7A QQ ZZ qz Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CALLA Call Subroutine Absolute Syntax CALLA Operation IF (op1) THEN CALLA op1, op2 (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← op2 ELSE next instruction END IF Description If the condition specified by op1 is met, a branch to the absolute memory location specified by the second operand op2 is taken. The value of the instruction pointer, IP, is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. If the condition is not met, no action is taken and the next instruction is executed normally. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLA Semiconductor Group Format cc, caddr CA c0 MM MM 50 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CALLI Call Subroutine Indirect Syntax CALLI Operation IF (op1) THEN CALLI op1, op2 (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← op2 ELSE next instruction END IF Description If the condition specified by op1 is met, a branch to the location specified indirectly by the second operand op2 is taken. The value of the instruction pointer, IP, is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. If the condition is not met, no action is taken and the next instruction is executed normally. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLI Semiconductor Group cc, [Rwn] 51 Format Bytes AB cn 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CALLR Call Subroutine Relative Syntax CALLR Operation (SP) ← (SP) - 2 CALLR op1 ((SP)) ← (IP) (IP) ← (IP) + sign_extend (op1) Description A branch is taken to the location specified by the instruction pointer, IP, plus the relative displacement, op1. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the instruction pointer (IP) is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. The value of the IP used in the target address calculation is the address of the instruction following the CALLR instruction. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLR Semiconductor Group Format rel BB rr 52 Bytes 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CALLS Call Inter-Segment Subroutine Syntax CALLS Operation (SP) ← (SP) - 2 CALLS op1, op2 ((SP)) ← (CSP) (SP) ← (SP) - 2 ((SP)) ← (IP) (CSP) ← op1 (IP) ← op1 Description A branch is taken to the absolute location specified by op2 within the segment specified by op1. The value of the instruction pointer (IP) is placed onto the system stack. Because the IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address to the calling routine. The previous value of the CSP is also placed on the system stack to insure correct return to the calling segment. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic CALLS Semiconductor Group Format seg, caddr DA SS MM MM 53 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CMP CMP Integer Compare Syntax CMP Operation (op1) ⇔ (op2) Data Types WORD Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1. The flags are set according to the rules of subtraction. The operands remain unchanged. Condition Flags op1, op2 E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes CMP Rwn, Rwm 40 nm 2 CMP Rwn, [Rwi] 48 n:10ii 2 CMP Rwn, [Rwi+] 48 n:11ii 2 CMP Rwn, #data3 48 n:0### 2 CMP reg, #data16 46 RR ## ## 4 CMP reg, mem 42 RR MM MM 4 54 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CMPB CMPB Integer Compare Syntax CMPB Operation (op1) ⇔ (op2) Data Types BYTE Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1. The flags are set according to the rules of subtraction. The operands remain unchanged. Condition Flags op1, op2 E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes CMPB Rbn, Rbm 41 nm 2 CMPB Rbn, [Rwi] 49 n:10ii 2 CMPB Rbn, [Rwi+] 49 n:11ii 2 CMPB Rbn, #data3 49 n:0### 2 CMPB reg, #data16 47 RR ## xx 4 CMPB reg, mem 43 RR MM MM 4 55 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CMPD1 Integer Compare and Decrement by 1 Syntax CMPD1 Operation (op1) ⇔ (op2) CMPD1 op1, op2 (op1) ← (op1) - 1 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is decremented by one. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. Condition Flags E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes CMPD1 Rwn, #data4 A0 #n 2 CMPD1 Rwn, #data16 A6 Fn ## ## 4 CMPD1 Rwn, mem A2 Fn MM MM 4 56 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CMPD2 Integer Compare and Decrement by 2 Syntax CMPD2 Operation (op1) ⇔ (op2) CMPD2 op1, op2 (op1) ← (op1) - 2 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is decremented by two. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. Condition Flags E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes CMPD2 Rwn, #data4 B0 #n 2 CMPD2 Rwn, #data16 B6 Fn ## ## 4 CMPD2 Rwn, mem B2 Fn MM MM 4 57 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CMPI1 Integer Compare and Increment by 1 Syntax CMPI1 Operation (op1) ⇔ (op2) CMPI1 op1, op2 (op1) ← (op1) + 1 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is incremented by one. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. Condition Flags E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes CMPI1 Rwn, #data4 80 #n 2 CMPI1 Rwn, #data16 86 Fn ## ## 4 CMPI1 Rwn, mem 82 Fn MM MM 4 58 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CMPI2 Integer Compare and Increment by 2 Syntax CMPI2 Operation (op1) ⇔ (op2) CMPI2 op1, op2 (op1) ← (op1) + 2 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY GPR registers. Once the subtraction has completed, the operand op1 is incremented by two. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range. Condition Flags E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes CMPI2 Rwn, #data4 90 #n 2 CMPI2 Rwn, #data16 96 Fn ## ## 4 CMPI2 Rwn, mem 92 Fn MM MM 4 59 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CPL Integer One’s Complement CPL Syntax CPL Operation (op1) ← ¬(op1) Data Types WORD Description Performs a 1’s complement of the source operand specified by op1. The result is stored back into op1. Condition Flags op1 E Z V C N * * 0 0 * E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CPL Semiconductor Group Format Rwn 91 n0 60 Bytes 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h CPLB Integer One’s Complement CPLB Syntax CPL Operation (op1) ← ¬(op1) Data Types BYTE Description Performs a 1’s complement of the source operand specified by op1. The result is stored back into op1. Condition Flags op1 E Z V C N * * 0 0 * E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic CPLB Semiconductor Group Rbn 61 Format Bytes B1 n0 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h DISWDT Disable Watchdog Timer DISWDT Syntax DISWDT Operation Disable the watchdog timer Description This instruction disables the watchdog timer. The watchdog timer is enabled by a reset. The DISWDT instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function. Following a reset, this instruction can be executed at any time until either a Service Watchdog Timer instruction (SRVWDT) or an End of Initialization instruction (EINIT) are executed. Once one of these instructions has been executed, the DISWDT instruction will have no effect. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format DISWDT A5 5A A5 A5 62 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h DIV 16-by-16 Signed Division Syntax DIV Operation (MDL) ← (MDL) / (op1) DIV op1 (MDH) ← (MDL) mod (op1) Data Types WORD Description Performs a signed 16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). Condition Flags E Z V C N 0 * S 0 * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIV Semiconductor Group Rwn 63 Format Bytes 4B nn 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h DIVL 32-by-16 Signed Division Syntax DIVL Operation (MDL) ← (MD) / (op1) DIVL op1 (MDH) ← (MD) mod (op1) Data Types WORD, DOUBLEWORD Description Performs an extended signed 32-bit by 16-bit division of the two words stored in the MD register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). Condition Flags E Z V C N 0 * S 0 * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIVL Semiconductor Group Rwn 64 Format Bytes 6B nn 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h DIVLU 32-by-16 Unsigned Division Syntax DIVLU Operation (MDL) ← (MD) / (op1) DIVLU op1 (MDH) ← (MD) mod (op1) Data Types WORD, DOUBLEWORD Description Performs an extended unsigned 32-bit by 16-bit division of the two words stored in the MD register by the source word operand op1. The unsigned quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). Condition Flags E Z V C N 0 * S 0 * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIVLU Semiconductor Group Rwn 65 Format Bytes 7B nn 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h DIVU 16-by-16 Unsigned Division Syntax DIVU Operation (MDL) ← (MDL) / (op1) DIVU op1 (MDH) ← (MDL) mod (op1) Data Types WORD Description Performs an unsigned 16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register (MDL) and the remainder is stored in the high order word of the MD register ( MDH). Condition Flags E Z V C N 0 * S 0 * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic overflow occurred, ie. the result cannot be represented in a word data type, or if the divisor (op1) was zero. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic DIVU Semiconductor Group Rwn 66 Format Bytes 5B nn 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h EINIT EINIT End of Initialization Syntax EINIT Operation End of Initialization Description This instruction is used to signal the end of the initialization portion of a program. After a reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT instruction has been executed at which time it goes high. This enables the program to signal the external circuitry that it has successfully initialized the microcontroller. After the EINIT instruction has been executed, execution of the Disable Watchdog Timer instruction (DISWDT) has no effect. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format EINIT B5 4A B5 B5 67 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h EXTR Begin EXTended Register Sequence Syntax EXTR Operation (count) ← (op1) [1 ≤ op1 ≤ 4] Disable interrupts and Class A traps SFR_range = Extended DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ← (count) - 1 END WHILE (count) = 0 SFR_range = Standard Enable interrupts and traps Description Causes all SFR or SFR bit accesses via the ’reg’, ’bitoff’ or ’bitaddr’ addressing modes being made to the Extended SFR space for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The value of op1 defines the length of the effected instruction sequence. Note The EXTR instruction must be used carefully (see introductory note). The EXTR instruction is not available in the SAB 8XC166(W) devices. Condition Flags EXTR op1 E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic EXTR Semiconductor Group Format #irang2 D1 :10##-0 68 Bytes 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h EXTP EXTP Begin EXTended Page Sequence Syntax EXTP Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Page = (op1) DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ← (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The EXTP instruction becomes immediately active such that no additional NOPs are required. For any long (’mem’) or indirect ([...]) address in the EXTP instruction sequence, the 10-bit page number (address bits A23-A14) is not determined by the contents of a DPP register but by the value of op1 itself. The 14-bit page offset (address bits A13-A0) is derived from the long or indirect address as usual. The value of op2 defines the length of the effected instruction sequence. Note The EXTP instruction must be used carefully (see introductory note). The EXTP instruction is not available in the SAB 8XC166(W) devices. Condition Flags op1, op2 E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes EXTP Rwm, #irang2 DC :01##-m 2 EXTP #pag, #irang2 D7 :01##-0 pp 0:00pp 4 69 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h EXTPR Begin EXTended Page and Register Sequence EXTPR Syntax EXTPR Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Page = (op1) AND SFR_range = Extended DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ← (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) AND SFR_range = Standard Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the ’reg’, ’bitoff’ or ’bitaddr’ addressing modes being made to the Extended SFR space for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. For any long (’mem’) or indirect ([...]) address in the EXTP instruction sequence, the 10-bit page number (address bits A23-A14) is not determined by the contents of a DPP register but by the value of op1 itself. The 14-bit page offset (address bits A13-A0) is derived from the long or indirect address as usual. The value of op2 defines the length of the effected instruction sequence. Note The EXTPR instruction must be used carefully (see introductory note). The EXTPR instruction is not available in the SAB 8XC166(W) devices. Condition Flags op1, op2 E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes EXTPR Rwm, #irang2 DC :11##-m 2 EXTPR #pag, #irang2 D7 :11##-0 pp 0:00pp 4 70 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h EXTS Begin EXTended Segment Sequence Syntax EXTS Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Segment = (op1) DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ← (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The EXTS instruction becomes immediately active such that no additional NOPs are required. For any long (’mem’) or indirect ([...]) address in an EXTS instruction sequence, the value of op1 determines the 8-bit segment (address bits A23-A16) valid for the corresponding data access. The long or indirect address itself represents the 16-bit segment offset (address bits A15-A0). The value of op2 defines the length of the effected instruction sequence. Note The EXTS instruction must be used carefully (see introductory note). The EXTS instruction is not available in the SAB 8XC166(W) devices. Condition Flags EXTS op1, op2 E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes EXTS Rwm, #irang2 DC :00##-m 2 EXTS #seg, #irang2 D7 :00##-0 ss 00 4 71 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h EXTSR Begin EXTended Segment and Register SequenceEXTSR Syntax EXTSR Operation (count) ← (op2) [1 ≤ op2 ≤ 4] Disable interrupts and Class A traps Data_Segment = (op1) AND SFR_range = Extended DO WHILE ((count) ≠ 0 AND Class_B_trap_condition ≠ TRUE) Next Instruction (count) ← (count) - 1 END WHILE (count) = 0 Data_Page = (DPPx) AND SFR_range = Standard Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the ’reg’, ’bitoff’ or ’bitaddr’ addressing modes being made to the Extended SFR space for a specified number of instructions. During their execution, both standard and PEC interrupts and class A hardware traps are locked. The EXTSR instruction becomes immediately active such that no additional NOPs are required. For any long (’mem’) or indirect ([...]) address in an EXTSR instruction sequence, the value of op1 determines the 8-bit segment (address bits A23-A16) valid for the corresponding data access. The long or indirect address itself represents the 16-bit segment offset (address bits A15-A0). The value of op2 defines the length of the effected instruction sequence. Note The EXTSR instruction must be used carefully (see introductory note). The EXTSR instruction is not available in the SAB 8XC166(W) devices. Condition Flags op1, op2 E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic EXTSR Rwm, #irang2 EXTSR #seg, #irang2 72 Format DC :10##-m D7 :10##-0 ss 00 Bytes 2 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h IDLE IDLE Enter Idle Mode Syntax IDLE Operation Enter Idle Mode Description This instruction causes the part to enter the idle mode. In this mode, the CPU is powered down while the peripherals remain running. It remains powered down until a peripheral interrupt or external interrupt occurs. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format IDLE 87 78 87 87 73 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JB Relative Jump if Bit Set Syntax JB Operation IF (op1) = 1 THEN JB op1, op2 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types BIT Description If the bit specified by op1 is set, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JB instruction. If the specified bit is clear, the instruction following the JB instruction is executed. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JB Semiconductor Group Format bitaddrQ.q, rel 74 8A QQ rr q0 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JBC Relative Jump if Bit Set and Clear Bit Syntax JBC Operation IF (op1) = 1 THEN JBC op1, op2 (op1) = 0 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types BIT Description If the bit specified by op1 is set, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The bit specified by op1 is cleared, allowing implementation of semaphore operations. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JBC instruction. If the specified bit was clear, the instruction following the JBC instruction is executed. Condition Flags E Z V C N 0 B 0 0 B E Always cleared. Z Contains logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic JBC Semiconductor Group Format bitaddrQ.q, rel 75 AA QQ rr q0 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JMPA Absolute Conditional Jump Syntax JMPA Operation IF (op1) = 1 THEN JMPA op1, op2 (IP) ← op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken. If the condition is not met, no action is taken, and the instruction following the JMPA instruction is executed normally. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPA Semiconductor Group Format cc, caddr EA c0 MM MM 76 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JMPI Indirect Conditional Jump Syntax JMPI Operation IF (op1) = 1 THEN JMPI op1, op2 (IP) ← op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met, a branch to the absolute address specified by op2 is taken. If the condition is not met, no action is taken, and the instruction following the JMPI instruction is executed normally. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPI Semiconductor Group cc, [Rwn] 77 Format Bytes 9C cn 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JMPR Relative Conditional Jump Syntax JMPR Operation IF (op1) = 1 THEN JMPR op1, op2 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Description If the condition specified by op1 is met, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction. If the specified condition is not met, program execution continues normally with the instruction following the JMPR instruction. Condition Codes See condition code table. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPR Semiconductor Group Format cc, rel cD rr 78 Bytes 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JMPS Absolute Inter-Segment Jump Syntax JMPS Operation (CSP) ← op1 JMPS op1, op2 (IP) ← op2 Description Condition Flags Branches unconditionally to the absolute address specified by op2 within the segment specified by op1. E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JMPS Semiconductor Group Format seg, caddr FA SS MM MM 79 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JNB Relative Jump if Bit Clear Syntax JNB Operation IF (op1) = 0 THEN JNB op1, op2 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types BIT Description If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JNB instruction. If the specified bit is set, the instruction following the JNB instruction is executed. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic JNB Semiconductor Group Format bitaddrQ.q, rel 80 9A QQ rr q0 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h JNBS Relative Jump if Bit Clear and Set Bit Syntax JNBS Operation IF (op1) = 0 THEN JNBS op1, op2 (op1) = 1 (IP) ← (IP) + sign_extend (op2) ELSE Next Instruction END IF Data Types BIT Description If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The bit specified by op1 is set, allowing implementation of semaphore operations. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the IP used in the target address calculation is the address of the instruction following the JNBS instruction. If the specified bit was set, the instruction following the JNBS instruction is executed. Condition Flags E Z V C N 0 B 0 0 B E Always cleared. Z Contains logical negation of the previous state of the specified bit. V Always cleared. C Always cleared. N Contains the previous state of the specified bit. Addressing Modes Mnemonic JNBS Semiconductor Group Format bitaddrQ.q, rel 81 BA QQ rr q0 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h MOV MOV Move Data Syntax MOV Operation (op1) ← (op2) Data Types WORD Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. Condition Flags op1, op2 E Z V C N * * - - * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the source operand op2 is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Rwn, Rwm Rwn, #data4 reg, #data16 Rwn, [Rwm] Rwn, [Rwm+] [Rwm], Rwn [-Rwm], Rwn [Rwn], [Rwm] [Rwn+], [Rwm] [Rwn], [Rwm+] Rwn, [Rwm+#data16] [Rwm+#data16], Rwn [Rwn], mem mem, [Rwn] reg, mem mem, reg 82 Format F0 nm E0 #n E6 RR ## ## A8 nm 98 nm B8 nm 88 nm C8 nm D8 nm E8 nm D4 nm ## ## C4 nm ## ## 84 0n MM MM 94 0n MM MM F2 RR MM MM F6 RR MM MM Bytes 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h MOVB MOVB Move Data Syntax MOVB Operation (op1) ← (op2) Data Types BYTE Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. Condition Flags op1, op2 E Z V C N * * - - * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the source operand op2 is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB Rbn, Rbm Rbn, #data4 reg, #data8 Rbn, [Rwm] Rbn, [Rwm+] [Rwm], Rbn [-Rwm], Rbn [Rwn], [Rwm] [Rwn+], [Rwm] [Rwn], [Rwm+] Rbn, [Rwm+#data16] [Rwm+#data16], Rbn [Rwn], mem mem, [Rwn] reg, mem mem, reg 83 Format F1 nm E1 #n E7 RR ## xx A9 nm 99 nm B9 nm 89 nm C9 nm D9 nm E9 nm F4 nm ## ## E4 nm ## ## A4 0n MM MM B4 0n MM MM F3 RR MM MM F7 RR MM MM Bytes 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h MOVBS Move Byte Sign Extend Syntax MOVBS Operation (low byte op1) ← (op2) MOVBS op1, op2 IF (op27) = 1 THEN (high byte op1) ← FFH ELSE (high byte op1) ← 00H END IF Data Types WORD, BYTE Description Moves and sign extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. Condition Flags E Z V C N 0 * - - * E Always cleared. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the source operand op2 is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes MOVBS Rwn, Rbm D0 mn 2 MOVBS reg, mem D2 RR MM MM 4 MOVBS mem, reg D5 RR MM MM 4 84 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h MOVBZ Move Byte Zero Extend Syntax MOVBZ Operation (low byte op1) ← (op2) MOVBZ op1, op2 (high byte op1) ← 00H Data Types WORD, BYTE Description Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. The contents of the moved data is examined, and the condition codes are updated accordingly. Condition Flags E Z V C N 0 * - - 0 E Always cleared. Z Set if the value of the source operand op2 equals zero. Cleared otherwise. V Not affected. C Not affected. N Always cleared. Addressing Modes Semiconductor Group Mnemonic Format Bytes MOVBZ Rwn, Rbm C0 mn 2 MOVBZ reg, mem C2 RR MM MM 4 MOVBZ mem, reg C5 RR MM MM 4 85 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h MUL Signed Multiplication MUL Syntax MUL Operation (MD) ← (op1) * (op2) Data Types WORD Description Performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively. The signed 32-bit result is placed in the MD register. Condition Flags op1, op2 E Z V C N 0 * S 0 * E Always cleared. Z Set if the result equals zero. Cleared otherwise. V This bit is set if the result cannot be represented in a word data type. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic MUL Semiconductor Group Rwn, Rwm 86 Format Bytes 0B nm 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h MULU Unsigned Multiplication MULU Syntax MULU Operation (MD) ← (op1) * (op2) Data Types WORD Description Performs a 16-bit by 16-bit unsigned multiplication using the two words specified by operands op1 and op2 respectively. The unsigned 32-bit result is placed in the MD register. Condition Flags op1, op2 E Z V C N 0 * S 0 * E Always cleared. Z Set if the result equals zero. Cleared otherwise. V This bit is set if the result cannot be represented in a word data type. Cleared otherwise. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic MULU Semiconductor Group Rwn, Rwm 87 Format Bytes 1B nm 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h NEG Integer Two’s Complement NEG Syntax NEG Operation (op1) ← 0 - (op1) Data Types WORD Description Performs a binary 2’s complement of the source operand specified by op1. The result is then stored in op1. Condition Flags op1 E Z V C N * * * S * E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic NEG Semiconductor Group Format Rwn 81 n0 88 Bytes 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h NEGB Integer Two’s Complement NEGB Syntax NEGB Operation (op1) ← 0 - (op1) Data Types BYTE Description Performs a binary 2’s complement of the source operand specified by op1. The result is then stored in op1. Condition Flags op1 E Z V C N * * * S * E Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Mnemonic NEGB Semiconductor Group Rbn 89 Format Bytes A1 n0 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h NOP NOP No Operation Syntax NOP Operation No Operation Description This instruction causes a null operation to be performed. A null operation causes no change in the status of the flags. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes NOP CC 00 2 90 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h OR OR Logical OR Syntax OR Operation (op1) ← (op1) ∨ (op2) Data Types WORD Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * 0 0 * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes OR Rwn, Rwm 70 nm 2 OR Rwn, [Rwi] 78 n:10ii 2 OR Rwn, [Rwi+] 78 n:11ii 2 OR Rwn, #data3 78 n:0### 2 OR reg, #data16 76 RR ## ## 4 OR reg, mem 72 RR MM MM 4 OR mem, reg 74 RR MM MM 4 91 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ORB ORB Logical OR Syntax ORB Operation (op1) ← (op1) ∨ (op2) Data Types BYTE Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * 0 0 * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ORB Rbn, Rbm 71 nm 2 ORB Rbn, [Rwi] 79 n:10ii 2 ORB Rbn, [Rwi+] 79 n:11ii 2 ORB Rbn, #data3 79 n:0### 2 ORB reg, #data16 77 RR ## xx 4 ORB reg, mem 73 RR MM MM 4 ORB mem, reg 75 RR MM MM 4 92 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h PCALL Push Word and Call Subroutine Absolute Syntax PCALL Operation (tmp) ← (op1) PCALL op1, op2 (SP) ← (SP) - 2 ((SP)) ← (tmp) (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← op2 Data Types WORD Description Pushes the word specified by operand op1 and the value of the instruction pointer, IP, onto the system stack, and branches to the absolute memory location specified by the second operand op2. Because IP always points to the instruction following the branch instruction, the value stored on the system stack represents the return address of the calling routine. Condition Flags E Z V C N * * - - * E Set if the value of the pushed operand op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the pushed operand op1 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the pushed operand op1 is set. Cleared otherwise. Addressing Modes Mnemonic PCALL Semiconductor Group Format reg, caddr E2 RR MM MM 93 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h POP Pop Word from System Stack Syntax POP Operation (tmp) ← ((SP)) POP op1 (SP) ← (SP) + 2 (op1) ← (tmp) Data Types WORD Description Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1. The Stack Pointer is then incremented by two. Condition Flags E Z V C N * * - - * E Set if the value of the popped word represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the popped word equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the popped word is set. Cleared otherwise. Addressing Modes Mnemonic POP Semiconductor Group reg 94 Format Bytes FC RR 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h PRIOR PRIOR Prioritize Register Syntax PRIOR op1, op2 Operation (tmp) ← (op2) (count) ← 0 DO WHILE (tmp15) ≠ 1 AND (count) ≠ 15 AND (op2) ≠ 0 (tmpn) ← (tmpn-1) (count) ← (count) + 1 END WHILE (op1) ← (count) Data Types WORD Description This instruction stores a count value in the word operand specified by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its MSB is equal to one. If the source operand op2 equals zero, a zero is written to operand op1 and the zero flag is set. Otherwise the zero flag is cleared. Condition Flags E Z V C N 0 * 0 0 0 E Always cleared. Z Set if the source operand op2 equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Always cleared. Addressing Modes Mnemonic PRIOR Semiconductor Group Rwn, Rwm 95 Format Bytes 2B nm 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h PUSH Push Word on System Stack Syntax PUSH Operation (tmp) ← (op1) PUSH op1 (SP) ← (SP) - 2 ((SP)) ← (tmp) Data Types WORD Description Moves the word specified by operand op1 to the location in the internal system stack specified by the Stack Pointer, after the Stack Pointer has been decremented by two. Condition Flags E Z V C N * * - - * E Set if the value of the pushed word represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the pushed word equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the pushed word is set. Cleared otherwise. Addressing Modes Mnemonic PUSH Semiconductor Group reg 96 Format Bytes EC RR 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h PWRDN Enter Power Down Mode PWRDN Syntax PWRDN Operation Enter Power Down Mode Description This instruction causes the part to enter the power down mode. In this mode, all peripherals and the CPU are powered down until the part is externally reset. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. To further control the action of this instruction, the PWRDN instruction is only enabled when the non-maskable interrupt pin (NMI) is in the low state. Otherwise, this instruction has no effect. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format PWRDN 97 68 97 97 97 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h RET Return from Subroutine Syntax RET Operation (IP) ← ((SP)) RET (SP) ← (SP) + 2 Description Condition Flags Returns from a subroutine. The IP is popped from the system stack. Execution resumes at the instruction following the CALL instruction in the calling routine. E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes RET CB 00 2 98 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h RETI Return from Interrupt Routine Syntax RETI Operation (IP) ← ((SP)) RETI (SP) ← (SP) + 2 IF (SYSCON.SGTDIS=0) THEN (CSP) ← ((SP)) (SP) ← (SP) + 2 END IF (PSW) ← ((SP)) (SP) ← (SP) + 2 Description Condition Flags Returns from an interrupt routine. The PSW, IP, and CSP are popped off the system stack. Execution resumes at the instruction which had been interrupted. The previous system state is restored after the PSW has been popped. The CSP is only popped if segmentation is enabled. This is indicated by the SGTDIS bit in the SYSCON register. E Z V C N S S S S S E Restored from the PSW popped from stack. Z Restored from the PSW popped from stack. V Restored from the PSW popped from stack. C Restored from the PSW popped from stack. N Restored from the PSW popped from stack. Addressing Modes Semiconductor Group Mnemonic Format Bytes RETI FB 88 2 99 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h RETP Return from Subroutine and Pop Word Syntax RETP Operation (IP) ← ((SP)) RETP op1 (SP) ← (SP) + 2 (tmp) ← ((SP)) (SP) ← (SP) + 2 (op1) ← (tmp) Data Types WORD Description Returns from a subroutine. The IP is first popped from the system stack and then the next word is popped from the system stack into the operand specified by op1. Execution resumes at the instruction following the CALL instruction in the calling routine. Condition Flags E Z V C N * * - - * E Set if the value of the word popped into operand op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if the value of the word popped into operand op1 equals zero. Cleared otherwise. V Not affected. C Not affected. N Set if the most significant bit of the word popped into operand op1 is set. Cleared otherwise. Addressing Modes Mnemonic RETP Semiconductor Group reg 100 Format Bytes EB RR 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h RETS Return from Inter-Segment Subroutine Syntax RETS Operation (IP) ← ((SP)) RETS (SP) ← (SP) + 2 (CSP) ← ((SP)) (SP) ← (SP) + 2 Description Condition Flags Returns from an inter-segment subroutine. The IP and CSP are popped from the system stack. Execution resumes at the instruction following the CALLS instruction in the calling routine. E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes RETS DB 00 2 101 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ROL ROL Rotate Left Syntax ROL Operation (count) ← (op2) (C) ← 0 DO WHILE (count) ≠ 0 (C) ← (op115) (op1n) ← (op1n-1) [n=1...15] (op10) ← (C) (count) ← (count) - 1 END WHILE Data Types WORD Description Rotates the destination word operand op1 left by as many times as specified by the source operand op2. Bit 15 is rotated into Bit 0 and into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. Condition Flags op1, op2 E Z V C N 0 * 0 S * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Always cleared. C The carry flag is set according to the last MSB shifted out of op1. Cleared for a rotate count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ROL Rwn, Rwm 0C nm 2 ROL Rwn, #data4 1C #n 2 102 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h ROR ROR Rotate Right Syntax ROR Operation (count) ← (op2) (C) ← 0 (V) ← 0 DO WHILE (count) ≠ 0 (V) ← (V) ∨ (C) (C) ← (op10) (op1n) ← (op1n+1) [n=0...14] (op115) ← (C) (count) ← (count) - 1 END WHILE Data Types WORD Description Rotates the destination word operand op1 right by as many times as specified by the source operand op2. Bit 0 is rotated into Bit 15 and into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. Condition Flags op1, op2 E Z V C N 0 * S S * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if in any cycle of the rotate operation a ‘1’ is shifted out of the carry flag. Cleared for a rotate count of zero. C The carry flag is set according to the last LSB shifted out of op1. Cleared for a rotate count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes ROR Rwn, Rwm 2C nm 2 ROR Rwn, #data4 3C #n 2 103 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SCXT SCXT Switch Context Syntax SCXT op1, op2 Operation (tmp1) ← (op1) (tmp2) ← (op2) (SP) ← (SP) - 2 ((SP)) ← (tmp1) (op1) ← (tmp2) Data Types WORD Description Used to switch contexts for any register. Switching context is a push and load operation. The contents of the register specified by the first operand, op1, are pushed onto the stack. That register is then loaded with the value specified by the second operand, op2. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format Bytes SCXT reg, #data16 C6 RR ## ## 4 SCXT reg, mem D6 RR MM MM 4 104 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SHL SHL Shift Left Syntax SHL Operation (count) ← (op2) (C) ← 0 DO WHILE (count) ≠ 0 (C) ← (op115) (op1n) ← (op1n-1) [n=1...15] (op10) ← 0 (count) ← (count) - 1 END WHILE Data Types WORD Description Shifts the destination word operand op1 left by as many times as specified by the source operand op2. The least significant bits of the result are filled with zeros accordingly. The MSB is shifted into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. Condition Flags op1, op2 E Z V C N 0 * 0 S * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Always cleared. C The carry flag is set according to the last MSB shifted out of op1. Cleared for a shift count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes SHL Rwn, Rwm 4C nm 2 SHL Rwn, #data4 5C #n 2 105 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SHR SHR Shift Right Syntax SHR Operation (count) ← (op2) (C) ← 0 (V) ← 0 DO WHILE (count) ≠ 0 (V) ← (C) ∨ (V) (C) ← (op10) (op1n) ← (op1n+1) [n=0...14] (op115) ← 0 (count) ← (count) - 1 END WHILE Data Types WORD Description Shifts the destination word operand op1 right by as many times as specified by the source operand op2. The most significant bits of the result are filled with zeros accordingly. Since the bits shifted out effectively represent the remainder, the Overflow flag is used instead as a Rounding flag. This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than, less than or equal to one half an LSB. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used. Condition Flags op1, op2 E Z V C N 0 * S S * E Always cleared. Z Set if result equals zero. Cleared otherwise. V Set if in any cycle of the shift operation a ‘1’ is shifted out of the carry flag. Cleared for a shift count of zero. C The carry flag is set according to the last LSB shifted out of op1. Cleared for a shift count of zero. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes SHR Rwn, Rwm 6C nm 2 SHR Rwn, #data4 7C #n 2 106 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SRST SRST Software Reset Syntax SRST Operation Software Reset Description This instruction is used to perform a software reset. A software reset has the same effect on the microcontroller as an externally applied hardware reset. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. Condition Flags E Z V C N 0 0 0 0 0 E Always cleared. Z Always cleared. V Always cleared. C Always cleared. N Always cleared. Addressing Modes Semiconductor Group Mnemonic Format SRST B7 48 B7 B7 107 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SRVWDT Service Watchdog Timer SRVWDT Syntax SRVWDT Operation Service Watchdog Timer Description This instruction services the Watchdog Timer. It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence. Once this instruction has been executed, the watchdog timer cannot be disabled. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. Condition Flags E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Semiconductor Group Mnemonic Format SRVWDT A7 58 A7 A7 108 Bytes 4 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SUB SUB Integer Subtraction Syntax SUB Operation (op1) ← (op1) - (op2) Data Types WORD Description Performs a 2’s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes SUB Rwn, Rwm 20 nm 2 SUB Rwn, [Rwi] 28 n:10ii 2 SUB Rwn, [Rwi+] 28 n:11ii 2 SUB Rwn, #data3 28 n:0### 2 SUB reg, #data16 26 RR ## ## 4 SUB reg, mem 22 RR MM MM 4 SUB mem, reg 24 RR MM MM 4 109 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SUBB SUBB Integer Subtraction Syntax SUBB Operation (op1) ← (op1) - (op2) Data Types BYTE Description Performs a 2’s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes SUBB Rbn, Rbm 21 nm 2 SUBB Rbn, [Rwi] 29 n:10ii 2 SUBB Rbn, [Rwi+] 29 n:11ii 2 SUBB Rbn, #data3 29 n:0### 2 SUBB reg, #data16 27 RR ## xx 4 SUBB reg, mem 23 RR MM MM 4 SUBB mem, reg 25 RR MM MM 4 110 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SUBC Integer Subtraction with Carry SUBC Syntax SUBC Operation (op1) ← (op1) - (op2) - (C) Data Types WORD Description Performs a 2’s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1. The result is then stored in op1. This instruction can be used to perform multiple precision arithmetic. Condition Flags op1, op2 E Z V C N * S * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero and the previous Z flag was set. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes SUBC Rwn, Rwm 30 nm 2 SUBC Rwn, [Rwi] 38 n:10ii 2 SUBC Rwn, [Rwi+] 38 n:11ii 2 SUBC Rwn, #data3 38 n:0### 2 SUBC reg, #data16 36 RR ## ## 4 SUBC reg, mem 32 RR MM MM 4 SUBC mem, reg 34 RR MM MM 4 111 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h SUBCB Integer Subtraction with Carry SUBCB Syntax SUBCB Operation (op1) ← (op1) - (op2) - (C) Data Types BYTE Description Performs a 2’s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1. The result is then stored in op1. This instruction can be used to perform multiple precision arithmetic. Condition Flags op1, op2 E Z V C N * * * S * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Set if an arithmetic underflow occurred, ie. the result cannot be represented in the specified data type. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes SUBCB Rbn, Rbm 31 nm 2 SUBCB Rbn, [Rwi] 39 n:10ii 2 SUBCB Rbn, [Rwi+] 39 n:11ii 2 SUBCB Rbn, #data3 39 n:0### 2 SUBCB reg, #data16 37 RR ## xx 4 SUBCB reg, mem 33 RR MM MM 4 SUBCB mem, reg 35 RR MM MM 4 112 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h TRAP TRAP Software Trap Syntax TRAP op1 Operation (SP) ← (SP) - 2 ((SP)) ← (PSW) IF (SYSCON.SGTDIS=0) THEN (SP) ← (SP) - 2 ((SP)) ← (CSP) (CSP) ← 0 END IF (SP) ← (SP) - 2 ((SP)) ← (IP) (IP) ← zero_extend (op1*4) Description Condition Flags Invokes a trap or interrupt routine based on the specified operand, op1. The invoked routine is determined by branching to the specified vector table entry point. This routine has no indication of whether it was called by software or hardware. System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected. The RETI, return from interrupt, instruction is used to resume execution after the trap or interrupt routine has completed. The CSP is pushed if segmentation is enabled. This is indicated by the SGTDIS bit in the SYSCON register. E Z V C N - - - - - E Not affected. Z Not affected. V Not affected. C Not affected. N Not affected. Addressing Modes Mnemonic TRAP Semiconductor Group #trap7 113 Format Bytes 9B t:ttt0 2 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h XOR Logical Exclusive OR XOR Syntax XOR Operation (op1) ← (op1) ⊕ (op2) Data Types WORD Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * 0 0 * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes XOR Rwn, Rwm 50 nm 2 XOR Rwn, [Rwi] 58 n:10ii 2 XOR Rwn, [Rwi+] 58 n:11ii 2 XOR Rwn, #data3 58 n:0### 2 XOR reg, #data16 56 RR ## ## 4 XOR reg, mem 52 RR MM MM 4 XOR mem, reg 54 RR MM MM 4 114 Version 1.2, 12.97 C166 Family Instruction Set Instruction Description 30Mar98@15:00h XORB Logical Exclusive OR XORB Syntax XORB Operation (op1) ← (op1) ⊕ (op2) Data Types BYTE Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1. The result is then stored in op1. Condition Flags op1, op2 E Z V C N * * 0 0 * E Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table. Z Set if result equals zero. Cleared otherwise. V Always cleared. C Always cleared. N Set if the most significant bit of the result is set. Cleared otherwise. Addressing Modes Semiconductor Group Mnemonic Format Bytes XORB Rbn, Rbm 51 nm 2 XORB Rbn, [Rwi] 59 n:10ii 2 XORB Rbn, [Rwi+] 59 n:11ii 2 XORB Rbn, #data3 59 n:0### 2 XORB reg, #data16 57 RR ## xx 4 XORB reg, mem 53 RR MM MM 4 XORB mem, reg 55 RR MM MM 4 115 Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h 6 Addressing Modes The Siemens 16-bit microcontrollers provide a lot of powerful addressing modes for access to word, byte and bit data (short, long, indirect), or to specify the target address of a branch instruction (absolute, relative, indirect). The different addressing modes use different formats and cover different scopes. Short Addressing Modes All of these addressing modes use an implicit base offset address to specify an 18-bit or 24-bit physical address (SAB 80C166 group or C167/5 group, respectively). Short addressing modes allow to access the GPR, SFR or bit-addressable memory space: Physical Address = Base Address + ∆ * Short Address Note: ∆ is 1 for byte GPRs, ∆ is 2 for word GPRs. Mnemonic Physical Address Short Address Range Scope of Access Rw (CP) + 2*Rw Rw = 0...15 GPRs (Word) Rb (CP) + 1*Rb Rb = 0...15 GPRs (Byte) reg 00’FE00H 00’F000H (CP) (CP) + 2*reg + 2*reg *) + 2*(reg∧0FH) + 1*(reg∧0FH) reg reg reg reg = 00H...EFH = 00H...EFH = F0H...FFH = F0H...FFH SFRs ESFRs GPRs GPRs (Word, Low byte) (Word, Low byte)*) (Word) (Bytes) bitoff 00’FD00H + 2*bitoff 00’FF00H + 2*(bitoff∧FFH) (CP) + 2*(bitoff∧0FH) bitoff bitoff bitoff = 00H...7FH = 80H...EFH = F0H...FFH RAM SFR GPR Bit word offset Bit word offset Bit word offset bitaddr Word offset as with bitoff. Immediate bit position. bitoff bitpos = 00H...FFH = 0...15 Any single bit *) The Extended Special Function Register (ESFR) area is not available in the SAB 8XC166(W) devices. Semiconductor Group 116 Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h Rw, Rb: Specifies direct access to any GPR in the currently active context (register bank). Both ’Rw’ and ’Rb’ require four bits in the instruction format. The base address of the current register bank is determined by the content of register CP. ’Rw’ specifies a 4-bit word GPR address relative to the base address (CP), while ’Rb’ specifies a 4 bit byte GPR address relative to the base address (CP). reg: Specifies direct access to any (E)SFR or GPR in the currently active context (register bank). ’reg’ requires eight bits in the instruction format. Short ’reg’ addresses from 00 H to EFH always specify (E)SFRs. In that case, the factor ’∆’ equates 2 and the base address is 00’FE00H for the standard SFR area or 00’F000H for the extended ESFR area. ‘reg’ accesses to the ESFR area require a preceding EXT*R instruction to switch the base address (not available in the SAB 8XC166(W) devices). Depending on the opcode of an instruction, either the total word (for word operations) or the low byte (for byte operations) of an SFR can be addressed via 'reg'. Note that the high byte of an SFR cannot be accessed via the 'reg' addressing mode. Short 'reg' addresses from F0 H to FFH always specify GPRs. In that case, only the lower four bits of 'reg' are significant for physical address generation, and thus it can be regarded as being identical to the address generation described for the 'Rb' and 'Rw' addressing modes. bitoff: Specifies direct access to any word in the bit-addressable memory space. 'bitoff' requires eight bits in the instruction format. Depending on the specified 'bitoff' range, different base addresses are used to generate physical addresses: Short 'bitoff' addresses from 00H to 7FH use 00’FD00H as a base address, and thus they specify the 128 highest internal RAM word locations (00’FD00Hh to 00’FDFEH). Short 'bitoff' addresses from 80H to EFH use 00’FF00H as a base address to specify the highest internal SFR word locations (00’FF00H to 00’FFDEH) or use 00’F100H as a base address to specify the highest internal ESFR word locations (00’F100H to 00’F1DEH). ‘bitoff’ accesses to the ESFR area require a preceding EXT*R instruction to switch the base address (not available in the SAB 8XC166(W) devices). For short 'bitoff' addresses from F0H to FFH, only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR. bitaddr: Any bit address is specified by a word address within the bit-addressable memory space (see 'bitoff'), and by a bit position ('bitpos') within that word. Thus, 'bitaddr' requires twelve bits in the instruction format. Semiconductor Group 117 Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h Long Addressing Mode This addressing mode uses one of the four DPP registers to specify a physical 18-bit or 24-bit address. Any word or byte data within the entire address space can be accessed with this mode. The C167/5 devices also support an override mechanism for the DPP adressing scheme. Note: Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. After reset, the DPP registers are initialized in a way that all long addresses are directly mapped onto the identical physical addresses. Any long 16-bit address consists of two portions, which are interpreted in different ways. Bits 13...0 specify a 14-bit data page offset, while bits 15...14 specify the Data Page Pointer (1 of 4), which is to be used to generate the physical 18-bit or 24-bit address (see figure below). 15 14 13 0 16-bit Long Address DPP0 DPP1 DPP2 DPP3 14-bit page offset 18/24-bit Physical Address Figure 6-1: Interpretation of a 16-bit Long Address The SAB 8XC166(W) devices support an address space of up to 256 KByte, while the C167/5 devices support an address space of up to 16 MByte, so only the lower two or ten bits (respectively) of the selected DPP register content are concatenated with the 14-bit data page offset to build the physical address. The long addressing mode is referred to by the mnemonic ‘mem’. Mnemonic Physical Address Long Address Range Scope of Access mem (DPP0) (DPP1) (DPP2) (DPP3) || || || || 0000H...3FFFH 4000H...7FFFH 8000H...BFFFH C000H...FFFFH mem pag || mem∧3FFFH 0000H...FFFFH (14-bit) Any Word or Byte mem seg || mem 0000H...FFFFH (16-bit) Any Word or Byte Semiconductor Group mem∧3FFFH mem∧3FFFH mem∧3FFFH mem∧3FFFH 118 Any Word or Byte Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h DPP Override Mechansim in the C167/5 Other than the older devices from the SAB 80C166 group the C167 and C165 devices provide an override mechanism that allows to bypass the DPP addressing scheme temporarily. The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction EXTP(R) replaces the content of the respective DPP register, while instruction EXTS(R) concatenates th complete 16-bit long address with the specified segment base address. The overriding page or segment may be specified directly as a constant (#pag, #seg) or via a word GPR (Rw). 15 EXTP(R): 14 13 0 16-bit Long Address #pag 14-bit page offset 24-bit Physical Address 15 EXTS(R): 0 16-bit Long Address #seg 16-bit segment offset 24-bit Physical Address Figure 6-2: Overriding the DPP Mechanism Indirect Addressing Modes These addressing modes can be regarded as a combination of short and long addressing modes. This means that long 16-bit addresses are specified indirectly by the contents of a word GPR, which is specified directly by a short 4-bit address (’Rw’=0 to 15). There are indirect addressing modes, which add a constant value to the GPR contents before the long 16-bit address is calculated. Other indirect addressing modes allow decrementing or incrementing the indirect address pointers (GPR content) by 2 or 1 (referring to words or bytes). In each case, one of the four DPP registers is used to specify physical 18-bit or 24-bit addresses. Any word or byte data within the entire memory space can be addressed indirectly. Note: The exceptions for instructions EXTP(R) and EXTS(R), ie. overriding the DPP mechanism, apply in the same way as described for the long addressing modes. Some instructions only use the lowest four word GPRs (R3...R0) as indirect address pointers, which are specified via short 2-bit addresses in that case. Semiconductor Group 119 Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h Note: Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap. After reset, the DPP registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses. Physical addresses are generated from indirect address pointers via the following algorithm: 1) Calculate the physical address of the word GPR, which is used as indirect address pointer, using the specified short address (’Rw’) and the current register bank base address (CP). GPR Address = (CP) + 2 * Short Address 2) Pre-decremented indirect address pointers (‘-Rw’) are decremented by a data-typedependent value (∆=1 for byte operations, ∆=2 for word operations), before the long 16-bit address is generated: (GPR Address) = (GPR Address) - ∆ ; [optional step!] 3) Calculate the long 16-bit address by adding a constant value (if selected) to the content of the indirect address pointer: Long Address = (GPR Pointer) + Constant 4) Calculate the physical 18-bit or 24-bit address using the resulting long address and the corresponding DPP register content (see long 'mem' addressing modes). Physical Address = (DPPi) + Page offset 5) Post-Incremented indirect address pointers (‘Rw+’) are incremented by a data-typedependent value (∆=1 for byte operations, ∆=2 for word operations): (GPR Pointer) = (GPR Pointer) + ∆ ; [optional step!] The following indirect addressing modes are provided: Mnemonic Particularities [Rw] Most instructions accept any GPR (R15...R0) as indirect address pointer. Some instructions, however, only accept the lower four GPRs (R3...R0). [Rw+] The specified indirect address pointer is automatically post-incremented by 2 or 1 (for word or byte data operations) after the access. [-Rw] The specified indirect address pointer is automatically pre-decremented by 2 or 1 (for word or byte data operations) before the access. [Rw+#data16] The specified 16-bit constant is added to the indirect address pointer, before the long address is calculated. Semiconductor Group 120 Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h Constants The C166 Family instruction set also supports the use of wordwide or bytewide immediate constants. For an optimum utilization of the available code storage, these constants are represented in the instruction formats by either 3, 4, 8 or 16 bits. Thus, short constants are always zero-extended while long constants are truncated if necessary to match the data format required for the particular operation (see table below): Mnemonic Word Operation Byte Operation #data3 0000H + data3 00H + data3 #data4 0000H + data4 00H + data4 #data8 0000H + data8 data8 #data16 data16 data16 ∧ FFH #mask 0000H + mask mask Note: Immediate constants are always signified by a leading number sign ’#’. Instruction Range (#irang2) The effect of the ATOMIC and EXTended instructions can be defined for the following 1...4 instructions. This instruction range (1...4) is coded in the 2-bit constant #irang2 and is represented by the values 0...3. Branch Target Addressing Modes Different addressing modes are provided to specify the target address and segment of jump or call instructions. Relative, absolute and indirect modes can be used to update the Instruction Pointer register (IP), while the Code Segment Pointer register (CSP) can only be updated with an absolute value. A special mode is provided to address the interrupt and trap jump vector table, which resides in the lowest portion of code segment 0. Mnemonic Target Address Target Segment Valid Address Range caddr (IP) = caddr - caddr = 0000H...FFFEH rel (IP) = (IP) + 2*rel (IP) = (IP) + 2*(rel+1) - rel rel = 00H...7FH = 80H...FFH [Rw] (IP) = ((CP) + 2*Rw) - Rw = 0...15 seg - (CSP) = seg seg = 0...255(3) #trap7 (IP) = 0000H + 4*trap7 (CSP) = 0000H trap7 = 00H...7FH Semiconductor Group 121 Version 1.2, 12.97 C166 Family Instruction Set Addressing Modes 30Mar98@15:00h caddr: Specifies an absolute 16-bit code address within the current segment. Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of ’caddr’ must always contain a ’0’, otherwise a hardware trap would occur. rel: This mnemonic represents an 8-bit signed word offset address relative to the current Instruction Pointer contents, which points to the instruction after the branch instruction. Depending on the offset address range, either forward (’rel’= 00H to 7FH) or backward (’rel’= 80H to FFH) branches are possible. The branch instruction itself is repeatedly executed, when ’rel’ = ’-1’ (FFH) for a word-sized branch instruction, or ’rel’ = ’-2’ (FEH) for a double-word-sized branch instruction. [Rw]: In this case, the 16-bit branch target instruction address is determined indirectly by the content of a word GPR. In contrast to indirect data addresses, indirectly specified code addresses are NOT calculated via additional pointer registers (eg. DPP registers). Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit of the address pointer GPR must always contain a ’0’, otherwise a hardware trap would occur. seg: Specifies an absolute code segment number. The devices of the SAB 80C166 group support 4 different code segments, while the devices of the C167/5 group support 256 different code segments, so only the two or eight lower bits (respectively) of the ’seg’ operand value are used for updating the CSP register. #trap7: Specifies a particular interrupt or trap number for branching to the corresponding interrupt or trap service routine via a jump vector table. Trap numbers from 00H to 7FH can be specified, which allow to access any double word code location within the address range 00’0000H...00’01FCH in code segment 0 (ie. the interrupt jump vector table). For the association of trap numbers with the corresponding interrupt or trap sources please refer to chapter “Interrupt and Trap Functions”. Semiconductor Group 122 Version 1.2, 12.97 C166 Family Instruction Set Instruction State Times 30Mar98@15:00h 7 Instruction State Times Basically, the time to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. The fastest processing mode is to execute a program fetched from the internal ROM. In that case most of the instructions can be processed within just one machine cycle, which is also the general minimum execution time. All external memory accesses are performed by the on-chip External Bus Controller (EBC), which works in parallel with the CPU. Mostly, instructions from external memory cannot be processed as fast as instructions from the internal ROM, because some data transfers, which internally can be performed in parallel, have to be performed sequentially via the external interface. In contrast to internal ROM program execution, the time required to process an external program additionally depends on the length of the instructions and operands, on the selected bus mode, and on the duration of an external memory cycle, which is partly selectable by the user. Processing a program from the internal RAM space is not as fast as execution from the internal ROM area, but it offers a lot of flexibility (ie. for loading temporary programs into the internal RAM via the chip’s serial interface, or end-of-line programming via the bootstrap loader). The following description allows evaluating the minimum and maximum program execution times. This will be sufficient for most requirements. For an exact determination of the instructions’ state times it is recommended to use the facilities provided by simulators or emulators. This section defines the subsequently used time units, summarizes the minimum (standard) state times of the 16-bit microcontroller instructions, and describes the exceptions from that standard timing. Time Unit Definitions The following time units are used to describe the instructions’ processing times: [fCPU]: CPU operating frequency (may vary from 1 MHz to 20 MHz). [State]: One state time is specified by one CPU clock period. Henceforth, one State is used as the basic time unit, because it represents the shortest period of time which has to be considered for instruction timing evaluations. 1 [State] = 1/fCPU = 50 [s] ; for fCPU = variable [ns] ; for fCPU = 20 MHz [ACT]: This ALE (Address Latch Enable) Cycle Time specifies the time required to perform one external memory access. One ALE Cycle Time consists of either two (for demultiplexed external bus modes) or three (for multiplexed external bus modes) state times plus a number of state times, which is determined by the number of waitstates programmed in the MCTC (Memory Cycle Time Control) and MTTC (Memory Tristate Time Control) bit fields of the SYSCON/BUSCONx registers. In case of demultiplexed external bus modes: = (2 + (15 – MCTC) + (1 – MTTC)) * States 1*ACT = 100 ns ... 900 ns ; for fCPU = 20 MHz In case of multiplexed external bus modes: = 3 + (15 – MCTC) + (1 – MTTC) * States 1*ACT = 150 ns ... 950 ns ; for fCPU = 20 MHz Semiconductor Group 123 Version 1.2, 12.97 C166 Family Instruction Set Instruction State Times 30Mar98@15:00h The total time (Ttot), which a particular part of a program takes to be processed, can be calculated by the sum of the single instruction processing times (TIn) of the considered instructions plus an offset value of 6 state times which considers the solitary filling of the pipeline, as follows: Ttot = TI1 + TI2 + ... + TIn + 6 * States The time TIn, which a single instruction takes to be processed, consists of a minimum number (TImin) plus an additional number (TIadd) of instruction state times and/or ALE Cycle Times, as follows: TIn = TImin + TIadd Minimum State Times The table below shows the minimum number of state times required to process an instruction fetched from the internal ROM (TImin (ROM)). The minimum number of state times for instructions fetched from the internal RAM (TImin (RAM)), or of ALE Cycle Times for instructions fetched from the external memory (TImin (ext)), can also be easily calculated by means of this table. Most of the 16-bit microcontroller instructions - except some of the branches, the multiplication, the division and a special move instruction - require a minimum of two state times. In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations. The injected target instruction of a cache jump instruction can be considered for timing evaluations as if being executed from the internal ROM, regardless of which memory area the rest of the current program is really fetched from. For some of the branch instructions the table below represents both the standard number of state times (ie. the corresponding branch is taken) and an additional TImin value in parentheses, which refers to the case that either the branch condition is not met or a cache jump is taken. Minimum Instruction State Times [Unit = ns] TImin (ROM) [States] TImin (ROM) (@ 20 MHz CPU clock) CALLI, CALLA 4 200 CALLS, CALLR, PCALL 4 JB, JBC, JNB, JNBS 4 JMPS 4 JMPA, JMPI, JMPR 4 Instruction (+2) 200 (+2) 200 (+2) 200 10 500 DIV, DIVL, DIVU, DIVLU 20 1000 MOV[B] Rn, [Rm+#data16] 4 200 RET, RETI, RETP, RETS 4 200 TRAP 4 200 All other instructions 2 100 124 (+100) 200 MUL, MULU Semiconductor Group (+100) (+100) Version 1.2, 12.97 C166 Family Instruction Set Instruction State Times 30Mar98@15:00h Instructions executed from the internal RAM require the same minimum time as if being fetched from the internal ROM plus an instruction-length dependent number of state times, as follows: For 2-byte instructions: TImin(RAM) = TImin(ROM) + 4 * States For 4-byte instructions: TImin(RAM) = TImin(ROM) + 6 * States In contrast to the internal ROM program execution, the minimum time TImin(ext) to process an external instruction additionally depends on the instruction length. TImin(ext) is either 1 ALE Cycle Time for most of the 2-byte instructions, or 2 ALE Cycle Times for most of the 4-byte instructions. The following formula represents the minimum execution time of instructions fetched from an external memory via a 16-bit wide data bus: For 2-byte instructions: For 4-byte instructions: TImin(ext) = 1*ACT + (TImin(ROM) - 2) * States TImin(ext) = 2*ACTs + (TImin(ROM) - 2) * States Note: For instructions fetched from an external memory via an 8-bit wide data bus, the minimum number of required ALE Cycle Times is twice the number for a 16-bit wide bus. Additional State Times Some operand accesses can extend the execution time of an instruction TIn. Since the additional time TIadd is mostly caused by internal instruction pipelining, it often will be possible to evade these timing effects in time-critical program modules by means of a suitable rearrangement of the corresponding instruction sequences. Simulators and emulators offer a lot of facilities, which support the user in optimizing his program whenever required. • Internal ROM operand reads: TIadd = 2 * States Both byte and word operand reads always require 2 additional state times. • Internal RAM operand reads via indirect addressing modes: TIadd = 0 or 1 * State Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause additional state times. However, reading an indirectly addressed internal RAM operand will extend the processing time by 1 state time, if the preceding instruction auto-increments or autodecrements a GPR as shown in the following example: In In+1 : MOV R1 , [R0+] : MOV [R3], [R2] ; auto-increment R0 ; if R2 points into the internal RAM space: ; TIadd = 1 * State In this case, the additional time can simply be avoided by putting another suitable instruction before the instruction In+1 indirectly reading the internal RAM. Semiconductor Group 125 Version 1.2, 12.97 C166 Family Instruction Set Instruction State Times 30Mar98@15:00h • Internal SFR operand reads: TIadd = 0, 1 * State or 2 * States Mostly, SFR read accesses do NOT require additional processing time. In some rare cases, however, either one or two additional state times will be caused by particular SFR operations, as follows: – Reading an SFR immediately after an instruction, which writes to the internal SFR space, as shown in the following example: In In+1 : MOV T0, #1000h : ADD R3, T1 ; write to Timer 0 ; read from Timer 1: TIadd = 1 * State – Reading the PSW register immediately after an instruction, which implicitly updates the condition flags, as shown in the following example: In In+1 : ADD R0, #1000h : BAND C, Z ; implicit modification of PSW flags ; read from PSW: TIadd = 2 * States – Implicitly incrementing or decrementing the SP register immediately after an instruction, which explicitly writes to the SP register, as shown in the following example: In In+1 : MOV SP, #0FB00h : SCXT R1, #1000h ; explicit update of the stack pointer ; implicit decrement of the stack pointer: : TIadd = 2 * States In these cases, the extra state times can be avoided by putting other suitable instructions before the instruction In+1 reading the SFR. • External operand reads: TIadd = 1 * ACT Any external operand reading via a 16-bit wide data bus requires one additional ALE Cycle Time. Reading word operands via an 8-bit wide data bus takes twice as much time (2 ALE Cycle Times) as the reading of byte operands. • External operand writes: TIadd = 0 * State ... 1 * ACT Writing an external operand via a 16-bit wide data bus takes one additional ALE Cycle Time. For timing calculations of external program parts, this extra time must always be considered. The value of TIadd which must be considered for timing evaluations of internal program parts, may fluctuate between 0 state times and 1 ALE Cycle Time. This is because external writes are normally performed in parallel to other CPU operations. Thus, TIadd could already have been considered in the standard processing time of another instruction. Writing a word operand via an 8-bit wide data bus requires twice as much time (2 ALE Cycle Times) as the writing of a byte operand. Semiconductor Group 126 Version 1.2, 12.97 C166 Family Instruction Set Instruction State Times 30Mar98@15:00h • Jumps into the internal ROM space: TIadd = 0 or 2 * States The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2 additional state times, if the branch target instruction is a double word instruction at a nonaligned double word location (xxx2H, xxx6H, xxxAH, xxxEH), as shown in the following example: label : .... .... In+1 : .... : JMPA cc_UC, label ; any non-aligned double word instruction : (eg. at location 0FFEH) ; if a standard branch is taken: : TIadd = 2 * States (TIn = 6 * States) A cache jump, which normally requires just 2 state times, will be extended by 2 additional state times, if both the cached jump target instruction and its successor instruction are non-aligned double word instructions, as shown in the following example: label : .... ; any non-aligned double word instruction : (eg. at location 12FAH) It+1 .... ; any non-aligned double word instruction : : (eg. at location 12FEH) ; provided that a cache jump is taken: In+1 :JMPR cc_UC, label : TIadd = 2 * States (TIn = 4 * States) If required, these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses (xxx0H, xxx4H, xxx8H, xxxCH). • Testing Branch Conditions: TIadd = 0 or 1 * States Mostly, NO extra time is required for conditional branch instructions to decide whether a branch condition is met or not. However, an additional state time is required, if the preceding instruction writes to the PSW register, as shown in the following example: In In+1 : BSET USR0 :JMPR cc_Z, label ; write to PSW ; test condition flag in PSW: TIadd = 1 * State In this case, the extra state time can simply be intercepted by putting another suitable instruction before the conditional branch instruction. Semiconductor Group 127 Version 1.2, 12.97