19-3982; Rev 0; 10/07 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator Features The MAX8655 synchronous-PWM buck regulator operates from a 4.5V to 25V input and generates an output voltage adjustable from 0.7V to 5.5V at loads up to 25A. Integrated power MOSFETs provide a small footprint, ease of layout, and reduced EMI. Removing the board trace inductances ensures the highest efficiency at high frequency. ♦ 25A Output Current The MAX8655 uses peak current-mode control architecture with an adjustable (200kHz to 1MHz), constantswitching frequency, which is externally synchronizable. The MAX8655’s adjustable current limit uses the inductor’s DC resistance to improve efficiency or an external sense resistor for higher accuracy. Foldback type current limit is available to reduce the power dissipation under severe-overload or short-circuit conditions. A reference input is provided for use with a high-accuracy external reference or for DDR and tracking applications. Monotonic startup provides safe starting into a prebiased output, where traditional step-down regulators discharge the output capacitor during soft-start, creating a negative voltage at the output and possibly damaging the load. A 180° out-of-phase synchronization output is available for synchronizing with another MAX8655. An enable input is provided for on/off control and to facilitate output sequencing. Output-voltage sensing for programmable overvoltage protection is provided and is independent of the feedback network to further enhance the output overvoltage protection. Overall, the MAX8655 provides enough flexibility for the experienced user, as well as simplicity and ease of use for non-power-supply engineers. ♦ Adjustable Switching Frequency and External Synchronization from 200kHz to 1MHz ♦ Integrated Power MOSFETs ♦ Operates from 4.5V to 25V Supply ♦ 1% FB Voltage Accuracy Over Temperature ♦ Adjustable Output Voltage Down to 0.7V ♦ Multiphase Operation with Accurate Current Sharing ♦ 180° Phase-Shifted Synchronization ♦ Adjustable Overcurrent Limit ♦ Adjustable Slope Compensation ♦ Selectable Current-Limit Mode: Latch-Off or Automatic Recovery ♦ Monotonic Output Voltage Rise at Startup into Prebias Output ♦ Output Sources and Sinks Current for DDR Applications ♦ Enable Input ♦ Power-OK (POK) Output ♦ Adjustable Soft-Start ♦ Independently Adjustable Overvoltage Protection Typical Operating Circuit POK FSYNC INPUT FSYNC SYNC OUTPUT SYNCO ILIM1 FB OVP SS COMP POWER-OK OUTPUT ILIM2 SCOMP Applications Point-of-Load Power Supplies Telecom Power Networking Nonisolated DC-DC Power Modules Servers and Workstations Notebook Computers IBA Power Supplies CS- CS+ PVIN OFF ENABLE INPUT Ordering Information VL IN MAX8655 VL ON EN VLGND BST LXB +Denotes a lead-free package. *EP = Exposed pad. 56 TQFN-EP* (8mm x 8mm) T5688M-4 INPUT 7V TO 28V OUTPUT 0.7V TO 12V UP TO 25A GND PVIN AVL -40°C to +85°C PKG CODE PGND MAX8655ETN+ PINPACKAGE MODE TEMP RANGE REFIN PART LX AVL Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8655 General Description MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator ABSOLUTE MAXIMUM RATINGS PVIN, IN, EN to GND ..............................................-0.3V to +30V BST to LXB ............................................................-0.3V to +7.5V LX, LXB to GND............ (-2.5V for < 50ns transient) -1V to +30V ILIM2, ILIM1, SYNCO, FSYNC, OVP, SCOMP to GND .....................................-0.3V to (VAVL + 0.3V) VL to PGND ...........................................................-0.3V to +7.5V AVL, FB, POK, COMP, SS, MODE, REFIN to GND ..-0.3V to +6V CS+, CS- to GND ....................................................-0.3V to +6V PGND to GND to VLGND ......................................-0.3V to +0.3V Operating Junction Temperature Range .......... -40°C to +125°C Junction Temperature ......................................................+150°C θJC (thermal resistance from junction to exposed pad) (Note 1) ...............................3.5°C/W θJT (thermal resistance from junction to the top) ............3.9°C/W ILX (RMS) .................................................................................27A Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 12V, VBST - VLX = 6.5V, TA = -40°C to +85°C, circuit of Figure 4, typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS PVIN Operating Voltage Range TYP 3 IN Operating Voltage Range VL = IN for VIN < 7V IN Quiescent Supply Current VFB = 0.75V, no switching Shutdown Supply Current MIN 4.5 2 MAX UNITS 25 V 25.0 V 3 mA EN = GND, VIN ≤ 28V 10 IIN + IVL + IAVL, EN = GND, VAVL = VVL = VIN = 5V 32 PVIN Shutdown Supply Current VPVIN = VLX = VBST AVL Undervoltage-Lockout Threshold VAVL rising, 3% typical hysteresis 3.90 Output-Voltage Adjust Range Minimum output voltage is limited by minimum duty cycle and external components 0.7 VL Regulation Voltage 7V < VIN < 28V AVL Regulation Voltage 5.5V < VVL < 7V, 1mA < ILOAD < 10mA AVL Output Current 1 4.15 µA µA 4.40 V 5.5 V V 6.0 6.5 7.0 4.900 4.975 5.050 10 V mA SOFT-START SS Shutdown Resistance From SS to GND, VEN = 0V SS Soft-Start Current VREF = 0.625V 20 100 Ω 23 28 µA VAVL 1.0V VAVL V -250 +250 nA 0 1.5 V 18 REFIN INPUT REFIN Dual Mode™ Threshold REFIN Input Bias Current VREFIN = 0.7V to 1.5V REFIN Input Voltage Range Dual Mode is a trademark of Maxim Integrated Products, Inc. 2 _______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator (VIN = 12V, VBST - VLX = 6.5V, TA = -40°C to +85°C, circuit of Figure 4, typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.693 0.7 0.707 VREFIN 0.00375 VREFIN VREFIN + 0.00375 V 70 110 160 µS 20 100 Ω 50 nA +1.5 V ERROR AMPLIFIER REFIN = AVL FB Regulation Voltage VREFIN = 0.7V to 1.5V Transconductance COMP Shutdown Resistance From COMP to GND, VEN = 0V FB Input Leakage Current VFB = 0.7V 5 FB Input Common-Mode Range -0.1 CURRENT-SENSE AMPLIFIER Voltage Gain VCS+ - VCS- = 30mV VOUT = 0 to 5.5V Part to part variation at TA = +85°C V/V 12 -4 +4 % CURRENT LIMIT Peak Current-Limit Threshold (VCS+ - VCS-) RILIM1 = 24kΩ 27.2 32 36.8 ILIM1 = AVL 60 80 92 Negative Current Limit % of valley current limit -90 -120 -150 % CS+, CS- Input Bias Current VCS+ = VCS- = 0 or 5.5V -25 +25 µA 0 5.5 V CS+, CS- Input Common-Mode Range mV SLOPE COMPENSATION Slope Compensation at Maximum Duty Cycle VSCOMP = 2.5V 231.25 250.00 268.75 VSCOMP = 1.25V 113.77 123.00 132.23 SCOMP = AVL SCOMP = GND 231.25 250.00 268.75 TA = 0°C to +85°C 113.77 123.00 132.23 TA = -40°C to +85°C 110.70 123.00 132.23 VAVL 0.5 SCOMP High Threshold SCOMP Low Threshold 0.5 SCOMP Adjustment Range 1.25 SCOMP Input Leakage Current VSCOMP = 1.25V to 2.5V mV V V 5 2.50 V 200 nA _______________________________________________________________________________________ 3 MAX8655 ELECTRICAL CHARACTERISTICS (continued) MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, VBST - VLX = 6.5V, TA = -40°C to +85°C, circuit of Figure 4, typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX RFSYNC = 21.0kΩ 800 1000 1200 RFSYNC = 143kΩ 160 200 240 UNITS OSCILLATOR Switching Frequency Minimum Off-Time Measured at LX 235 Minimum On-Time Measured at LX 75 kHz ns 100 ns 1200 kHz FSYNC Synchronization Range 160 FSYNC Input High Pulse Width 100 ns FSYNC Input Low Pulse Width 100 ns FSYNC Rise/Fall Time 100 SYNCO Phase Shift 180 SYNCO Output Low Level ISYNCO = 5mA SYNCO Output High Level ISYNCO = -5mA 0.4 VAVL - 1V V V FSYNC Input Low 0.4 FSYNC Input High ns Degrees 2.5 V V THERMAL PROTECTION Thermal Shutdown Rising temperature Thermal-Shutdown Hysteresis +160 °C 15 °C POK POK Threshold REFIN = AVL, VFB rising, typical hysteresis is 3% 629 650 671 mV VREFIN = 0.75V to 1.5V, VFB rising, typical hysteresis is 3% 88.7 91.7 94.7 % 25 200 mV 1 µA mV POK Output Voltage, Low VFB = 0.6V, IPOK = 2mA POK Leakage Current, High VPOK = 5.5V OVP OVP Threshold Voltage OVP, Leakage Current, High REFIN = AVL 770 800 840 VREFIN = 0.7V to 1.5V 110 115 120 % 500 nA 0.4 V VOVP = 0.8V MODE CONTROL MODE Logic-Level Low 4.5V ≤ VAVL ≤ 5.5V MODE Logic-Level High 4.5V ≤ VAVL ≤ 5.5V 1.8 MODE Input Current VMODE = 0 to VAVL -1 V +1 µA 0.45 V SHUTDOWN CONTROL EN Logic-Level Low 4.5V ≤ VAVL ≤ 5.5V EN Logic-Level High 4.5V ≤ VAVL ≤ 5.5V 2 VEN = 0V -1 EN Input Current VEN = 28V V +1 1.5 6.0 µA Note 2: Specifications are 100% production tested at TA = +85°C. Limits over the operating temperature range are guaranteed by design. 4 _______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator 12A LOAD 3.33 3.30 3.29 0.710 FB VOLTAGE (V) 3.31 7.5A LOAD 0.715 3.32 OUTPUT VOLTAGE (V) 3.32 3.31 3.30 3.29 0.705 0.700 0.695 3.28 3.28 0.690 3.27 3.27 0.685 3.26 3.26 0 5 10 15 LOAD CURRENT (A) 20 25 0.680 5 10 15 INPUT VOLTAGE (V) 20 RFSYNC = 76.8kΩ 390 380 TA = +25°C 370 0 40 80 EXPOSED PAD TEMPERATURE (°C) 120 MAX8655 toc05 MAX8655 toc04 400 -40 STEP-LOAD RESPONSE (CIRCUIT OF FIGURE 3) OSCILLATOR FREQUENCY vs. INPUT VOLTAGE (CIRCUIT OF FIGURE 4) OSCILLATOR FREQUENCY (kHz) OUTPUT VOLTAGE (V) 3.33 0.720 MAX8655 toc02 VIN = 12V FB VOLTAGE vs. EXPOSED PAD TEMPERATURE (CIRCUIT OF FIGURE 4) 3.34 MAX8655 toc01 3.34 LINE REGULATION (CIRCUIT OF FIGURE 4) MAX8655 toc03 LOAD REGULATION (CIRCUIT OF FIGURE 4) MAX8655 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) VOUT = 1.2V VOUT 50mV/div (AC-COUPLED) 0A TA = -40°C 360 350 340 TA = +85°C 330 IOUT 5A/div 320 310 300 8 13 18 23 INPUT VOLTAGE (V) 40μs/div 28 POWER-DOWN WAVEFORMS (CIRCUIT OF FIGURE 4) POWER-UP WAVEFORMS (CIRCUIT OF FIGURE 4) ENABLE WAVEFORMS (CIRCUIT OF FIGURE 4) MAX8655 toc07 MAX8655 toc06 MAX8655 toc08 VPOK 10V/div VPOK VIN 10V/div 5V/div 5V/div VEN 5V/div 1V/div VIN VPOK VOUT VOUT 5V/div 2V/div 5A/div ILX ILX 2ms/div 2V/div VOUT 10A/div ILX 200μs/div 10A/div 2ms/div _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) DUAL-PHASE SWITCHING (CIRCUIT OF FIGURE 5) FSYNC AND SYNCO (CIRCUIT OF FIGURE 4) MAX8655 toc10 MAX8655 toc09 VFSYNC VLX VSYNCO INTERNAL 350kHz SYNCHRONIZED TO OPERATION EXTERNAL 500kHz CLOCK 5V/div VLX (SLAVE) 5V/div 5V/div VLX (MASTER) 5V/div VSYNCO (MASTER) 5V/div 5V/div 1μs/div 1μs/div OVERVOLTAGE PROTECTION (CIRCUIT OF FIGURE 3) SHORT CIRCUIT AND RECOVERY MAX8655 toc11 VIN MAX8655 toc12 2V/div VOUT 500mV/div (AC-COUPLED) VOUT 1V/div VLX 5V/div IIN 1A/div 40μs/div 1ms/div CLOSED-LOOP BODE PLOT (CIRCUIT OF FIGURE 3) SAFE OPERATING AREA 40 180 144 20 72 10 36 0 0 GAIN -20 -30 25 OUTPUT CURRENT (A) 108 PHASE MARGIN (DEGREES) PHASE 30 -10 30 MAX8655 toc14 MAX8655toc13 50 GAIN (dB) MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator 20 15 10 5 -40 500 1k 2k 4k 10k 20k 40k 100k 200k400k FREQUENCY (Hz) 6 0 5 10 15 20 INPUT VOLTAGE (V) 25 30 _______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator (TA = +25°C, unless otherwise noted.) MAXIMUM OUTPUT CURRENT vs. EXPOSED PAD TEMPERATURE (CIRCUIT OF FIGURE 4) 80 80 70 60 50 40 VO = 3.3V 10A LOAD 10 0 5 8 EFFICIENCY vs. LOAD CURRENT 12V INPUT, 3.3V OUTPUT (CIRCUIT OF FIGURE 4) 1.0 20 200 90 80 180 160 40 60 50 40 30 30 20 20 10 10 0 0 1 10 LOAD CURRENT (A) 100 RVALLEY (kΩ) EFFICIENCY (%) 50 80 20 0 300 400 500 600 FREQUENCY (kHz) 700 800 80 60 40 20 0 5 10 15 20 VALLEY CURRENT LIMIT (A) 25 OUTPUT-CURRENT CAPABILITY vs. AMBIENT TEMPERATURE 30 300 LFM OUTPUT-CURRENT CAPABILITY (A) MAX8655 toc21 BOTTOM PCB TEMPERATURE (°C) 100 100 40 10A LOAD BOTTOM LAYER PCB TEMPERATURE vs. OUTPUT CURRENT VIN = 12V, VCC = 1.2V 120 60 200 120 3.5 140 70 60 2.0 2.5 3.0 OUTPUT VOLTAGE (V) RVALLEY vs. VALLEY CURRENT LIMIT 100 70 1.5 MAX8655 toc20 80 17 MAX8655 toc19 90 11 14 INPUT VOLTAGE (V) EFFICIENCY vs. FREQUENCY 12.0V INPUT 3.3V OUTPUT (CIRCUIT OF FIGURE 4) MAX8655 toc18 100 12V INPUT 10A LOAD 10 0 -40 -20 0 20 40 60 80 100 120 EXPOSED PAD TEMPERATURE (°C) 40 20 20 0 50 30 30 5 60 100 LFM 25 MAX8655 toc22 10 90 EFFICIENCY (%) EFFICIENCY (%) 15 MAX8655 toc17 90 70 20 100 MAX8655 toc16 25 OUTPUT CURRENT (A) 100 MAX8655 toc15 30 EFFICIENCY (%) EFFICIENCY vs. OUTPUT VOLTAGE (CIRCUIT OF FIGURE 4) EFFICIENCY vs. INPUT VOLTAGE (CIRCUIT OF FIGURE 4) 20 15 10 NO AIRFLOW 5 0 0 0 5 10 15 IOUT (A) 20 25 -40 -25 -10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX8655 Typical Operating Characteristics (continued) Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655 Pin Description PIN NAME FUNCTION Power-Input Supply. PVIN connects to the drain of the internal high-side MOSFET. Connect inputdecoupling capacitors as close as possible between PVIN and PGND. 1–5, 51–56 PVIN 6, 16–21 LX 7–15 PGND Power Ground Connection from Source of Internal Low-Side MOSFET. Connect input-decoupling capacitors as close as possible between PVIN and PGND. 22 VLGND Return for Low-Side MOSFET Gate-Driver Current 23, 28, 39, 48 GND Analog Ground. Connect all pins to the analog ground plane, and connect the analog and power ground planes together at the negative terminal of the output capacitor. Low-current signals return to GND. Pin 28 must be connected externally to GND-EP, the analog ground plane. 24 VL Internal 6.5V Linear-Regulator Output. Connect a 2.2µF to 10µF ceramic capacitor from VL to VLGND. For VIN < 7V, connect VL directly to IN. VL supplies power for the internal gate drivers. VL is the input to the AVL internal linear regulator. 25 IN Input Supply Voltage. IN is the input to the VL linear regulator. Connect VL to IN for VIN < 7V. Decouple to PGND with a 0.22µF ceramic capacitor. 26 EN Enable. Apply logic-high to EN to enable the output, or logic-low to place the regulator in low-power shutdown mode. Connect EN to IN for always-on operation. 27 AVL Internal 5V Linear-Regulator Output. AVL powers the MAX8655’s internal circuits. Connect a 1µF ceramic capacitor from AVL to GND. 29, 30, 42, 49 N.C. No Connection. Not internally connected. 31 CS+ Positive Differential Current-Sense Input 32 CS- Negative Differential Current-Sense Input ILIM1 Analog Programmable Current-Limit Input for Inductor Current. Connect a resistor from ILIM1 to GND to set the overcurrent threshold. ILIM1 sources 10µA through the resistor, and the voltage at ILIM1 is attenuated 7.5:1 to set the final current limit. For example, a 60kΩ resistor results in 600mV at ILIM1. This results in a current-limit threshold (VCS+ - VCS-) of 80mV. The ILIM1 resistor range is 24kΩ to 60kΩ. Connect ILIM1 to AVL to set the default threshold of 80mV. 34 OVP Output-Voltage Sensing for Overvoltage Protection. Connect OVP to the center of a resistor-divider connected between the output of the regulator and GND to set the FB independent output overvoltage trip point. Connect OVP to FB if this independence is not desired. The OVP threshold is 1.15 times the nominal feedback regulation voltage. 35 FB 36 COMP 37 SS Soft-Start. Connect a 0.01µF to 1µF ceramic capacitor from SS to GND. This capacitor sets the softstart period during startup. See the Startup and Soft-Start section for more details. SS is internally pulled to GND through 20Ω during shutdown. 38 REFIN External Reference Input. Connect REFIN to AVL to use the internal 0.7V reference for the feedback threshold. 33 8 External Inductor Connection. Connect to the external power inductor. Leave pin 6 unconnected for best routing. Feedback Input. Connect FB to the center of a resistor voltage-divider connected between the output and GND to set the output voltage. FB regulates to 0.7V or VREFIN. Loop Compensation. Connect COMP to an external RC network to compensate the loop. COMP is internally pulled to GND through 20Ω during shutdown. _______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator PIN NAME FUNCTION 40 ILIM2 41 SCOMP Programmable Slope-Compensation Input. Internal slope-compensation voltage rate is the voltage at SCOMP times 0.1 divided by the oscillator period (T). Connect SCOMP to AVL or GND to set to the default of 250mV/T or 125mV/T, respectively. 43 POK Open-Drain Power-OK Output. POK goes high impedance when the output voltage rises above 91% of the nominal regulation voltage. POK pulls low during shutdown or when the output drops below 88% of the nominal regulation voltage. 44 FSYNC Frequency Set and Synchronization Input. Connect a resistor from FSYNC to GND to set the switching frequency, or drive with a clock signal to synchronize between 160kHz and 1.2MHz. See the Switching Frequency and Synchronization section. 45 MODE Current-Limit Operating Mode Selection. Connect MODE to AVL for latch-off current limit or connect MODE to GND for automatic recovery current limit. 46 SYNCO Synchronization Output. Provides a clock output for synchronizing another MAX8655 with 180° out-of-phase operation. 47 BST Boost Capacitor Connection. Connect a 0.22µF ceramic capacitor from BST to LXB. 50 LXB LX Boost Capacitor Connection. Connect a 0.22µF ceramic capacitor between LXB and BST. — GND-EP Exposed Pad. Connect to GND externally. See the Pin Configuration. — PVIN-EP Exposed Pad. Internally connected to PVIN. See the Pin Configuration. — LX-EP Programmable Current-Limit Input. Connect a resistor from ILIM2 to GND to set the valley current limit. See the Setting the Current Limit section. Exposed Pad. Internally connected to LX. See the Pin Configuration. _______________________________________________________________________________________ 9 MAX8655 Pin Description (continued) MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator IN MAX8655 PVIN 6.5V LDO REGULATOR EN BST UVLO VL LEVEL SHIFT THERMAL SHDN LX SHOOT-THROUGH PROTECTION 5V AVL LDO AVL VL VOLTAGE REFERENCE REF SELECT LOGIC PWM CONTROL LOGIC VREF PGND VLGND SOFT-START CIRCUITRY REFIN SYNCO OVP SS 1.15V REF ERROR AMPLIFIER OSCILLATOR FSYNC SLOPE COMP SCOMP COMP CLAMP GM FB PWM COMPARATOR COMP OVP CURRENT-SENSE AMPLIFIER CS+ VSUM 12 CURRENT-LIMIT CONTROL LOGIC LEVEL SHIFT MODE CURRENT-LIMIT COMPARATOR X1 ILIM2 CS10μA VL POK ILIM1 GND ÷7.5 0.9V REF FB Figure 1. Functional Diagram 10 ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator DC-DC Converter Control Architecture The MAX8655 step-down regulator uses a PWM, peak current-mode control scheme. An internal transconductance amplifier establishes an integrated error voltage. The heart of the PWM controller is a PWM comparator that compares the integrated voltage-feedback signal against the amplified current-sense signal plus an adjustable slope-compensation ramp, which is summed with the current signal to ensure stability. At each rising edge of the internal clock, the internal highside MOSFET turns on until the PWM comparator trips or the maximum duty cycle is reached. During this ontime, current ramps up through the inductor, storing energy in the output inductor while sourcing current to the output. The current-mode feedback system regulates the peak inductor current as a function of the output-voltage error signal. The circuit acts as a switch-mode transconductance amplifier and pushes the output LC filter pole normally found in a voltagemode PWM to a higher frequency. Figure 1 is the functional diagram. During the second half of the cycle, the internal highside MOSFET turns off and the internal low-side MOSFET turns on. The output inductor releases the stored energy as the current ramps down, providing current to the load. The output capacitor stores charge when the inductor current exceeds the required load current and discharges when the inductor current is lower, smoothing the voltage across the load. Under soft-overload conditions, when the peak inductor current exceeds the selected current limit (see the Current-Limit Circuit section), the high-side MOSFET is turned off immediately and the low-side MOSFET is turned on and remains on to let the inductor current ramp down until the next clock cycle. Under severe-overload or short-circuit conditions, the valley foldback current limit is enabled to reduce power dissipation of external components. The MAX8655 operates in a forced-PWM mode. As a result, the regulator maintains a constant switching frequency, regardless of load, to allow for easier filtering of the switching noise. Internal Linear Regulators The MAX8655 contains two internal LDO regulators. The AVL regulator provides 5V for the IC’s internal circuitry, and the VL regulator provides 6.5V for the MOSFET gate drivers. Connect a 2.2µF ceramic capacitor from VL to VLGND, and connect a 1µF ceramic capacitor from AVL to GND. The AVL regulator input is internally connected to the VL regulator output. For 5V input applications, connect VL directly to IN and connect a 10Ω resistor from VL to AVL. Undervoltage Lockout When VAVL drops below 4.03V, the MAX8655 assumes that the supply voltage is too low to make valid decisions, so the undervoltage-lockout (UVLO) circuitry inhibits switching and turns off both internal power MOSFETs. When VAVL rises above 4.15V, the regulator enters the startup sequence and then resumes normal operation. Startup and Soft-Start The internal soft-start circuitry gradually ramps up the reference voltage to control the rate of rise of the output voltage and reduce input surge currents during startup. The soft-start period is determined by the value of the capacitor from SS to GND. The soft-start time is approximately (30.4ms/µF) x CSS. The MAX8655 also features monotonic output-voltage rise; therefore, both power MOSFETs are kept off if the voltage at FB is higher than the voltage at SS. This allows the MAX8655 to start up into a prebiased output without pulling the output voltage down. Before the MAX8655 begins the soft-start and powerup sequence, the following conditions must be met: • VAVL exceeds the 4.15V UVLO threshold. • EN is at logic-high. • The thermal limit is not exceeded. Enable The MAX8655 features a low-power shutdown mode. A logic-low at EN shuts down the regulator. During shutdown, the output is high impedance. Shutdown reduces the IN current to less than 10µA. A logic-high at EN enables the regulator. ______________________________________________________________________________________ 11 MAX8655 Detailed Description MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator VL BST MAX8655 LXB Figure 2. High-Side Gate Boost Circuit High-Side Gate-Drive Supply (BST) A flying capacitor boost circuit (Figure 2) generates the gate-drive voltage for the internal high-side n-channel MOSFET. The capacitor between BST and LXB is charged from VL to 6.5V minus the diode forward-voltage drop while the low-side MOSFET is on. When the low-side MOSFET is switched off, the stored voltage of the capacitor is stacked above LXB to provide the necessary turn-on voltage (VGS) for the high-side MOSFET. An internal switch between BST and the internal highside MOSFET’s gate closes to turn the MOSFET on. Current-Sense Amplifier The current-sense circuit amplifies the differential current-sense voltage (VCS+ - VCS-). This amplified current-sense signal and the internal-slope-compensation signal are summed (VSUM) together and fed into the PWM comparator’s inverting input. The PWM comparator shuts off the high-side MOSFET when V SUM exceeds the integrated feedback voltage (VCOMP). The differential current sense is also used to provide peak inductor current limiting. This current limit is more accurate than the valley current limit, which is measured across the internal low-side MOSFET. Current-Limit Circuit The MAX8655 uses both foldback and peak current limiting. The valley foldback current limit is used to reduce power dissipation of external components—mainly the inductor, internal power MOSFETs, and the upstream power source, when the output is severely overloaded or short circuited and when POK is low. Thus, the circuit can withstand short-circuit conditions continuously without causing overheating of any component. The peak constant current limit sets the current-limit point more accurately since it does not have to suffer the wide variation of the low-side power MOSFET’s on-resistance due to tolerance and temperature. 12 The valley current is sensed across the on-resistance of the low-side MOSFET. The valley current limit trips when the sensed current exceeds the valley current limit. Set the minimum valley current limit when the output voltage is at its nominal regulated value, higher than the maximum peak current-limit setting. With this method, the current-limit point accuracy is controlled by the peak current limit and is not interfered with by the wide variation of the MOSFET’s on-resistance. See the Setting the Current Limit section for how to set these limits. The MAX8655 can be configured for either an adjustable valley current-limit threshold with adjustable foldback ratio or a fixed valley current limit that latches the regulator off. To use foldback current limit with autorecovery, connect MODE to GND. When the latch-off mode is used, connect MODE to AVL and set the current-limit threshold with one resistor from ILIM2 to GND. Cycle EN or input power to reset the current-limit latch. The peak current limit is used to sense the inductor current, and is more accurate than the valley current limit because it does not depend upon the on-resistance of the low-side MOSFET. The peak current can be measured across the resistance of the inductor for the highest efficiency, or alternatively, a current-sense resistor can be used for more accurate current sensing. A resistor connected from ILIM1 to GND sets the peak current-limit threshold. For more information on the current limit, see the Setting the Current Limit section. Switching Frequency and Synchronization The MAX8655 has an adjustable internal oscillator that can be set to any frequency from 200kHz to 1MHz. To set the switching frequency, connect a resistor from FSYNC to GND. The MAX8655 can also be synchronized to an external clock by connecting the clock signal to FSYNC. A synchronization output (SYNCO) is provided to synchronize a second MAX8655 180° out-of-phase with the first by connecting SYNCO of the first MAX8655 to FSYNC of the second. When the first MAX8655 is synchronized to an external clock, the external clock is inverted to generate SYNCO. Therefore, to get 180° out-of-phase operation with an external clock, the clock input to the first MAX8655 should have a 50% duty cycle. Figure 3 is the single-phase, 600kHz switching, 10.8V to 13.2V input and 1.2V/20A output. Figure 4 shows single-phase, 350kHz switching, 6V to 20V input, and 3.3V/20A output. ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator MAX8655 R3 2.87kΩ R12 80.6kΩ C8 0.47μF C12 470pF R7 40.2kΩ CS- ILIM1 OVP FB SS COMP REFIN POK GND ILIM2 SCOMP R13 100kΩ POWER-OK OUTPUT N.C. C10 100pF AVL CS+ AVL R2 357Ω R9 56.2kΩ R5 4.02kΩ N.C. C13 R10 0.022μF 51.1kΩ GND FSYNC INPUT FOR INTERNAL OSCILLATOR OPERATION ONLY R8 41.2kΩ FSYNC AVL MODE EN SYNC OUTPUT SYNCO IN BST VL C14 1μF ENABLE INPUT OFF C16 0.22μF D1 GND GND MAX8655 N.C. C18 2.2μF C9 0.47μF R1 681Ω OUTPUT 1.2V UP TO 20A L1 0.56μH 1.8mΩ C6–C20 4 x 100μF CERAMIC PGND PGND PGND PVIN PGND LX PGND LX PVIN PGND LX PVIN PGND PVIN LX LX PVIN PVIN PVIN LX PVIN PVIN PVIN C1–C3 3 x 10μF CERAMIC LX PVIN INPUT 11.8V TO 13.2V VLGND LXB PGND C15 0.22μF PGND VL ON PVIN Figure 3. Single-Phase, 600kHz Switching, 10.8V to 13.2V Input, and 1.2V/20A Output REFIN Power-Good Signal (POK) The MAX8655 has a reference input (REFIN). When an external reference up to 1.5V is connected to REFIN, the feedback regulation voltage is equal to the voltage applied to REFIN. Connect REFIN to AVL to use the internal 0.7V reference. POK is an open-drain output on the MAX8655 that monitors the output voltage. When the output is above 92% of its nominal regulation voltage, POK is high impedance. When the output drops below 89% of its nominal regulation voltage, POK is internally pulled low. POK is also internally pulled low when the MAX8655 is shut down or in a fault condition. Overvoltage Protection The MAX8655 provides output overvoltage protection (OVP). The OVP threshold is set independent of the output regulation voltage with a resistor voltage-divider. When the voltage at OVP exceeds the OVP threshold, the regulator stops switching and latches on the lowside power MOSFET. Cycle EN or the power applied to AVL to clear the latch. Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the MAX8655. When the junction temperature exceeds +160°C, an internal thermal sensor shuts down the device, allowing the IC to cool. The thermal sensor turns the IC on again after the junction temperature cools by 15°C, resulting in a pulsed output during continuous thermal-overload conditions. ______________________________________________________________________________________ 13 MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator R3 11.5kΩ R4 11.5kΩ C8 0.22μF R2 3.57kΩ R9 71.5kΩ C10 100pF CS- ILIM1 OVP FB SS COMP POK REFIN POWER-OK OUTPUT GND SCOMP R13 100kΩ N.C. R6 3.09kΩ CS+ R5 3.09kΩ R7 243kΩ AVL N.C. R11 140kΩ R14 13kΩ ILIM2 AVL C12 560pF C13 0.022μF R12 10kΩ GND C14 1μF FSYNC INPUT R8 76.8kΩ FOR INTERNAL OSCILLATOR OPERATION ONLY AVL FSYNC AVL MODE EN SYNCO IN BST VL SYNC OUTPUT ENABLE INPUT OFF PVIN C16 0.22μF D1 VL C15 0.22μF GND GND MAX8655 N.C. C18 2.2μF VLGND LXB LX PVIN LX PVIN LX PVIN LX PVIN LX PVIN LX PVIN PGND R1 1.74kΩ L1 1μH 1.6mΩ C6–C19 3 x 220μF 15μΩ ESR PGND PGND PGND PGND PGND PGND PGND PGND LX PVIN PVIN PVIN PVIN PVIN C9 0.22μF OUTPUT 3.3V UP TO 20A INPUT 6V TO 20V C1–C5 5 x 10μF CERAMIC ON Figure 4. Single-Phase, 350kHz Switching, 6V to 20V Input, and 3.3V/20A Output Design Procedure Setting the Output Voltage To set the output voltage for the MAX8655, connect FB to the center of an external resistor-divider from the output to GND (R3 and R5 of Figure 5). Select R5 between 5kΩ and 24kΩ, and then calculate R3 with the following equation: LX R3 MAX8655 FB ⎛V ⎞ R3 = R5 × ⎜ OUT − 1⎟ ⎝ VFB ⎠ where VFB = 0.7V or VREFIN . R3 and R5 should be placed as close as possible to the IC. 14 R5 Figure 5. Setting the Output Voltage with a Resistor VoltageDivider ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator Setting the Switching Frequency To set the switching frequency, connect a resistor from FSYNC to GND. Calculate the resistor value in kΩ from the following equation: ⎛V ⎞ R4 = R6 × ⎜ OUT − 1⎟ ⎝ VOVP ⎠ 30600 − 9.914 fS where fS is the desired switching frequency in kHz. Setting the Slope Compensation where VOVP = 1.15 x VFB. Inductor Selection There are several parameters that must be examined when determining which inductor is to be used. Input voltage, output voltage, load current, switching frequency, and LIR. LIR is the ratio of the inductor current ripple to the maximum DC load current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple. A good compromise between size and efficiency is an LIR of 0.3. Once all the parameters are chosen, the inductor value is determined as follows: VOUT × (VIN − VOUT ) L= VIN × fS × ILOAD(MAX) × LIR where fS is the switching frequency. Choose a standard-value inductor close to the calculated value. The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. This is especially true if the inductance is increased without also increasing the physical size of the inductor. Find a low-loss inductor having the lowest possible DC resistance that fits the allotted dimensions. The chosen inductor’s saturation current rating must exceed the peak inductor current determined as: IPEAK = ILOAD(MAX) + RFSYNC = LIR × ILOAD(MAX) 2 For most applications where the duty cycle is less than 40%, connect SCOMP to GND to set the internal slope compensation to the default of 125mV/T, where T is the oscillator period (T = 1 / fS). For a slope compensation of 250mV/T, connect SCOMP to AVL. For applications with a duty cycle greater than 40%, set the SCOMP voltage with a resistor voltage-divider from AVL to GND (R11 and R12 in Figure 6). First, use the following equation to find the SCOMP voltage: VSCOMP = 120 × RL × (VO − 0.182 × VIN _ MIN ) fS × L where RL is the DC resistance of the inductor, VIN_MIN is the minimum operating input voltage, and fS is the switching frequency. Next, select a value for R11, typically 10kΩ, and solve for R12 as follows: R12 = (5V − VSCOMP ) × R11 VSCOMP This sets the internal slope-compensation voltage rate to VSCOMP / (10 x T). AVL MAX8655 R12 SCOMP R11 Figure 6. Resistor-Divider for Setting the Slope Compensation ______________________________________________________________________________________ 15 MAX8655 Setting the Output Overvoltage Protection To set the overvoltage threshold voltage for the MAX8655, connect OVP to the center of an external resistor-divider connected between the output and GND (R4 and R6 of Figure 3). Select R6 between 5kΩ and 24kΩ, then calculate R4 with the following equation: MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator Setting the Current Limit Valley Current Limit The MAX8655 has an adjustable valley current limit, configurable for foldback with automatic recovery, or constant-current limit with latch-up. To set the constantcurrent limit for the latch-up mode, connect a single resistor RILIM2 from ILIM2 to GND. For latch-up currentlimit mode, set RILIM2 equal to RVALLEY obtained from the RVALLEY vs. Valley Current Limit graph in the Typical Operating Characteristics section for the required valley current IVALLEY. IVALLEY is the value of the inductor valley current at maximum load (ILOAD(MAX) - 1/2 IP-P) To set the current limit for foldback mode, connect a resistor from ILIM2 to the output (RFOBK), and another resistor from ILIM2 to GND (RILIM2). See Figure 7. The values of RFOBK and RILIM2 are calculated as follows. First, select the percentage of foldback (PFB). This percentage corresponds to the current limit when VOUT equals zero divided by the current limit when V OUT equals its nominal voltage. A typical value of PFB is in the 15% to 40% range. A lower value of P FB yields lower short-circuit current. The following equations are used to calculate RFOBK and RILIM2: RFOBK = RILIM 2 = PFB × VOUT IILIM2 × (1− PFB ) IILIM 2 × RVALLEY × RFOBK VOUT + (IILIM 2 × (RFOBK − RVALLEY )) where IILIM2 is 5µA. If the resulting value of RILIM2 is negative, increase PFB. Peak Current Limit The peak current-limit threshold (VTH) is set by a resistor connected from ILIM1 to GND (RILIM1). VTH corresponds to the peak voltage across the sensing element (inductor or current-sense resistor). RILIM1 is calculated as follows: LX ILIM2 7.5 × VTH 10μA This allows a maximum DC output current of: V I ILIM = TH − P−P RL 2 where RL is the DC resistance of the inductor. To ensure maximum output current, use the minimum value of VTH from each setting, and the maximum RL values at the highest expected operating temperature. The DC resistance of the inductor’s copper wire has a +0.38%/°C temperature coefficient. An RC circuit is connected across the inductor (see Figure 8). The RC time constant is set to be 1.1 to 1.2 times the inductor (L/RL) time constant. Pick the value of C9 in the 0.1µF to 0.47µF range, and then calculate R1 from: R1 = 1.2L / (RL x C9) Add a resistor (R2 in Figure 8) to the CS- connection to minimize input offset error. Calculate the value of R2 as follows: • When VOUT ≥ 2.4V: RILIM1 × 10μA ⎞ ⎛ ⎜ 20μA + ⎟ × R1 ⎝ ⎠ 32kΩ R2 = 20μA • When VOUT < 2.4V: R2 = 15μA x R1 RILIM1 x 10μA ⎞ ⎛ ⎜15μA + ⎟ 32kΩ ⎝ ⎠ L1 OUT RFOBK MAX8655 RILIM1 = R1 C9 MAX8655 CS+ C10 RILIM2 Figure 7. ILIM2 Resistor Connections 16 VOUT LX R2 C11 CS- Figure 8. Current Sense Using the Inductor’s DC Resistance ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator Add a 100pF (C10) capacitor across the CS+ and CSinputs close to the IC. Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching. The input capacitors must meet the ripple-current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = ILOAD VOUT × (VIN − VOUT ) VIN I RMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2 x VOUT), so IRMS(MAX) = ILOAD / 2. Ceramic capacitors are recommended due to the low ESR and ESL at high frequency with relatively low cost. Choose a capacitor that exhibits less than 10°C temperature rise at the maximum operating RMS current for optimum long-term reliability. Ceramic capacitors with an X5R or better temperature characteristic are recommended. Output Capacitor The key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (ESR), the equivalent series inductance (ESL), and the voltage-rating requirements. These parameters affect the overall stability, output-voltage ripple, and transient response. The output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor’s ESR, and ESL caused by the current into and out of the capacitor. The maximum output-voltage ripple is estimated as follows: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL) The output-voltage ripple as a consequence of the ESR, ESL, and output capacitance is: VRIPPLE(ESR) = IP−P × ESR VRIPPLE(ESL) = VRIPPLE(C) = VIN × ESL L + ESL IP−P 8 × COUT × fS where IP-P is the peak-to-peak inductor current. V −V V IP−P = IN OUT × OUT fS × L VIN These equations are suitable for initial capacitor selection, but final values should be chosen based on a prototype or evaluation circuit. As a general rule, a smaller current ripple results in less output-voltage ripple. Since the inductor ripple current is a factor of the inductor value and input voltage, the output-voltage ripple decreases with larger inductance, and increases with higher input voltages. The MAX8655 is designed to work with polymer, tantalum, aluminum electrolytic, or ceramic output capacitors. The aluminum electrolytic capacitor is the least expensive; however, it has higher ESR. To compensate for this, use a ceramic capacitor in parallel to reduce the switching ripple and noise. Ceramic capacitors are recommended for high-frequency (500kHz to 1MHz) designs. For reliable and safe operation, ensure that the capacitor’s voltage and ripple-current ratings exceed the calculated values. The response to a load transient depends on the selected output capacitors. During a load transient, the output voltage instantly changes by ESR x ΔI LOAD. Before the regulator can respond, the output voltage deviates further, depending on the inductor and outputcapacitor values. After a short time (see the Typical Operating Characteristics section), the regulator responds by regulating the output voltage back to its nominal state. The regulator response time depends on its closed-loop bandwidth. With a higher bandwidth, the response time is faster, thus preventing the output voltage from further deviation from its regulating value. Compensation Design The MAX8655 uses an internal transconductance error amplifier whose output compensates the control loop. The external inductor, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost. Additionally, the compensation resistor and capacitors are selected to optimize control-loop stability. The component values, shown in Figures 3 and 4, yield stable operation over the given range of input-to-output voltages. The regulator uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. The voltage drop across the DC resistance of the inductor or the alternate series current-sense resistor is used to measure the inductor current. Current-mode control eliminates the double pole in the feedback loop caused by the ______________________________________________________________________________________ 17 MAX8655 Capacitor C11 is connected in parallel with R2 and is equal in value with C9. MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator inductor and output capacitor resulting in a smaller phase shift and requiring a less elaborate error-amplifier compensation than voltage-mode control. A simple series RC and CC is all that is needed to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering. For other types of capacitors, due to the higher capacitance and ESR, the frequency of the zero created by the capacitance and ESR is lower than the desired closed-loop crossover frequency. To stabilize a nonceramic output-capacitor loop, add another compensation capacitor from COMP to GND to cancel this ESR zero. See Figure 9. The basic regulator loop is modeled as a power modulator, an output feedback divider, and an error amplifier. The power modulator has DC gain GMOD(dc), set by gmc x RLOAD, with a pole and zero pair set by RLOAD, the output capacitor (COUT), and its equivalent series resistance (ESR). Below are equations that define the power modulator: RLOAD GMOD(dc) = gmc × ⎡ RLOAD × KS × (1 − D) − 0.5 ⎢1 + L × fS ⎣ where RLOAD = VOUT / IOUT(MAX), fS is the switching frequency, L is the output inductance, gmc = 1 / (AVCS x RL), where AVCS is the gain of the current-sense amplifier (12 typ), RL is the DC resistance of the inductor, the duty cycle D = VOUT / VIN. KS is a slope compensation factor calculated from the following equation: [( ) ] When COUT comprises “n” identical capacitors in parallel, the resulting COUT = n x COUT(EACH), and ESR = ESR(EACH) / n. Note that the capacitor zero for a parallel combination of like capacitors is the same as for an individual capacitor. Figure 10 is the simplified gain plot for the fzMOD > fC case. The feedback voltage-divider has a gain of GFB = VFB / VOUT, where VFB is equal to 0.7V. The transconductance error amplifier has a DC gain, GEA(DC) = gmEA x RO, where gmEA is the error-amplifier transconductance, which is equal to 110µS, and RO is the output resistance of the error amplifier, which is 30MΩ. A dominant pole (fpdEA) is set by the compensation capacitor (CC), the amplifier output resistance (RO), and the compensation resistor (RC); a zero (fzEA) is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole (fpEA) set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency (fC). Thus: fpdEA = VSCOMP × L × fS KS = 1 + 120 × (VIN − VO ) × RL When SCOMP is connected to GND, use VSCOMP = 1.25V; when SCOMP is connected to AVL, use VSCOMP = 2.5V. Find the pole and zero frequencies created by the power modulator as follows: 1 fpMOD = + 2π × RLOAD × COUT ⎡ ⎤ 1 × [KS × (1 − D) − 0.5]⎥ ⎢ ⎣ 2π × L × fS × COUT ⎦ 1 2π × COUT × ESR fzMOD = 1 2π × CC × (RO + RC ) fzEA = 1 2π × CC × RC fpEA = 1 2π × CF × RC CLOSED LOOP GAIN (dB) POWER MODULATOR ERROR AMPLIFIER COMP CF MAX8655 RC CC Figure 9. Compensation Components 18 fc 0dB FREQUENCY fpMOD FB DIVIDER fzMOD Figure 10. Simplified Gain Plot for the fzMOD > fC Case ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator f fpMOD << fC ≤ S 5 The error-amplifier gain at fC is: f GEA(fc) = gmEA × RC × zMOD fC Figure 11 is the simplified gain plot for the fzMOD < fC case. At the crossover frequency, the total loop gain must equal 1, and is expressed as: GEA(fc) × GMOD(fc) × VFB =1 VOUT For the case where fzMOD is greater than fC: CLOSED LOOP GAIN (dB) POWER MODULATOR ERROR AMPLIFIER GEA(fc) = gmEA × RC GMOD(fc) = GMOD(dc) × fpMOD fC 0dB FREQUENCY fpMOD FB DIVIDER fzMOD fc Then RC can be calculated as: VOUT RC = gmEA × VFB × GMOD(fc) where gmEA = 110µS. The error-amplifier compensation zero formed by RC and CC should be set at the modulator pole fPMOD. Calculate the value of CC as follows: CC = 1 2π × fp MOD × RC If fzMOD is less than 5 x fC, add a second capacitor CF from COMP to GND. The value of CF is: CF = 1 2π × RC × fzMOD As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. For the case where fzMOD is less than fC: The power modulator gain at fC is: GMOD(fc) = GMOD(dc) × fpMOD fzMOD Figure 11. Simplified Gain Plot for the fzMOD < fC Case RC is calculated as: V fC RC = OUT × VFB gmEA × GMOD(fc) × fzMOD where gmEA = 110µS. CC is calculated from: 1 CC = 2π × fp MOD × RC CF is calculated from: CF = 1 2π × RC × fzMOD The current-mode control model on which the above design procedure is based requires an additional highfrequency term, GS(s), to account for the effect of sampling the peak inductor current. The term G S (s) produces additional phase lag at crossover and should be modeled to estimate the phase margin obtainable by the selected compensation components. As a final step, it is useful to plot the dB gain and phase of the following loop-gain transfer function and check the ______________________________________________________________________________________ 19 MAX8655 The crossover frequency, fC, should be much higher than the power-modulator pole fPMOD. Also, fC should be less than or equal to 1/5 the switching frequency. Select a value for fC in the range: MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator obtained phase margin. A phase margin of at least 45° is recommended: GLOOP (s) = gmc × RLOAD ⎡ RLOAD ⎤ × (KS × (1 − D)) − 0.5 ⎥ ⎢1 + L × fS ⎣ ⎦ (1 + s / 2π × fzMOD ) × (1 + s / 2π × fpMOD ) [ ] × RLOAD = ⎡ RLOAD ⎤ ⎢1 + L × fs × KS × (1 − D) − 0.5 ⎥ ⎣ ⎦ 0.06 = 2.53 46.29 × 0.06 × [1.18(1 − 0.1) − 0.5] 1+ (0.56 x10 −6 )(600000) GMOD(dc) = gmc × fpMOD = gmEA × Ro × VFB GS (s) VO where the sampling effect quality factor: QC = 1 [π.(KS.(1 − D) − 0.5)] , Below is a numerical example to calculate RC and CC values of the typical operating circuit of Figure 3: AVCS = 12 L = 0.56µH ] 1 + 2π × RLOAD × COUT × 0.9 ⎡ ⎤ 1 ⎢ (1.18(1 − 0.1) − 0.5)⎥⎥ = 8.18kHz ⎢ 2π(0.56 x10 −6 )(600000)(400x10 −6 ) × 0.8 ⎣ ⎦ f fpMOD << fC ≤ S 5 1 ⎛ ⎞ s s2 ⎜1 + ⎟ + ⎜ π.Qc.fS ( π.f )2 ⎟ ⎝ S ⎠ ) ⎡ ⎤ 1 × [KS × (1 − D) − 0.5]⎥ = ⎢ ⎣ 2π × L × fS × COUT × 0.8 ⎦ 1 + 2π(400x10 −6 )(0.06) × 0.9 (1 + s / 2π × fzEA ) × (1 + s / 2π × fpEA ) × (1 + s / 2π × fpdEA ) GS (s) = [( 8.18kHz << fC ≤ 120kHz, select fC = 60kHz. fzMOD = 1 1 = = 884.2kHz 2π × 0.9 × COUT × ESR 2π × 0.9 × (400 × 10 −6 ) × 0.0005 Since fzMOD > fC: GMOD( fc) = GMOD(dc) × fpMOD fc = 2.53 × 8118 = 0.345 60000 V 1 RC = OUT × VFB gmEA × GMOD( fc) 1.2 1 = × − 0.7 (110 x10 6 )(0.307) RL = 1.8mΩ fS = 600kHz gmc = 1 / (AVCS x RL) = 1 / (12 x 0.0018) = 46.29S VOUT = 1.2V IOUT(MAX) = 20A RLOAD = VOUT / IOUT(MAX) = 1.2 / 20 = 0.06Ω RC = 44.7kΩ Select the nearest standard value: RC = 40.2kΩ: COUT = 4 x 100µF = 400µF ESR = 2mΩ/4 = 0.5mΩ D = VOUT / VIN = 1.2/12 = 0.1: Select the nearest standard value: CC = 470pF: KS = 1 + VSCOMP × L × fS 120 × (VIN − VO ) × RL 1.25(0.56 x10 −6 )(600000) = 1+ 120(12 − 1.2)(0.0018) = 1.18 20 CC = CF = 1 2π × fp MOD × RC = 1 2π × 8181 × (40.2 x103 ) = 483.9pF 1 1 = = 5pF 2π × RC × fzMOD 2π × (40.2 × 103 ) × (884.2 x103 ) R7 = RC = 40.2kΩ C12 = CC = 470pF C11 = CF = 5pF (not used) ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator PCB Layout Guidelines Careful PCB layout is critical to achieve low losses and clean, stable operation. Refer to the MAX8655 Evaluation Kit for an example layout. If it is necessary to deviate from this layout, follow the procedure below. Follow these guidelines for good PCB layout: 1) Place IC decoupling capacitors as close as possible to the IC pins. Separate the power and analog ground planes. Place the input ceramic decoupling capacitor directly across and as close as possible to PVIN and PGND. This is to help contain the high switching current within this small loop. 2) For output current greater than 10A, a four-layer PCB is recommended. Pour an analog ground plane in the second layer underneath the IC to minimize noise coupling. 3) Connect input, output, and VL capacitors to the power ground plane; connect all other capacitors to the signal ground plane. Connect analog and power ground planes at the output capacitor. 4) Place the inductor current-sense resistor and capacitor as close as possible to the inductor. Make a Kelvin connection to minimize the effect of PCB trace resistance. Place the input bias balance resistor (R2 in Figure 8) near CS-. Run two closely parallel traces from across capacitor C9 to CS+ and the input bias balance resistor R2. 5) Connect the exposed pad sections to the corresponding IC pins and allow sufficient copper area to help cooling the device. 6) Place the feedback and compensation components as close as possible to the IC pins. Connect the feedback resistor-divider from FB to VOUT as close as possible to the farthest output capacitor. Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 21 MAX8655 Applications Information Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator N.C. N.C. CS+ CS- ILIM1 OVP FB COMP SS REFIN GND ILIM2 N.C. TOP VIEW SCOMP MAX8655 Pin Configuration 42 41 40 39 38 37 36 35 34 33 32 31 30 29 POK 43 28 GND FSYNC 44 27 AVL MODE 45 26 EN GND-EP SYNCO 46 25 IN BST 47 24 VL GND 48 23 GND MAX8655ETN N.C. 49 22 VLGND LXB 50 21 LX PVIN 51 20 LX PVIN 52 PVIN-EP 19 LX LX-EP PVIN 53 18 LX PVIN 54 17 LX PVIN 55 16 LX + 10 11 12 13 14 PGND 9 PGND PVIN 8 PGND PVIN 7 PGND PVIN 6 PGND 5 PGND 4 PGND 3 PGND 2 LX 1 PVIN 15 PGND PVIN PVIN 56 THIN QFN (8mm x 8mm) 22 ______________________________________________________________________________________ Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator 56L THIN QFN.EPS ______________________________________________________________________________________ 23 MAX8655 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX8655 Highly Integrated, 25A, Wide-Input, Internal MOSFET, Step-Down Regulator Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.