19-4426; Rev 2; 7/10 KIT ATION EVALU E L B AVAILA High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package The MAX15040 high-efficiency switching regulator delivers up to 4A load current at output voltages from 0.6V to (0.9 x VIN). The device operates from 2.4V to 3.6V, making it ideal for on-board point-of-load and postregulation applications. Total output-voltage accuracy is within ±1% over load, line, and temperature. The MAX15040 features 1MHz fixed-frequency PWM mode operation. The high operating frequency allows for small-size external components. The low-resistance on-chip nMOS switches ensure high efficiency at heavy loads while minimizing critical parasitic inductances, making the layout a much simpler task with respect to discrete solutions. Following a simple layout and footprint ensures first-pass success in new designs. The MAX15040 incorporates a high-bandwidth (> 15MHz) voltage-error amplifier. The voltage-mode control architecture and the voltage-error amplifier permit a Type III compensation scheme to achieve maximum loop bandwidth, up to 200kHz. High loop bandwidth provides fast transient response, resulting in less required output capacitance and allowing for allceramic capacitor designs. The MAX15040 features an output overload hiccup protection and peak current limit on both high-side (sourcing current) and low-side (sinking and sourcing current) MOSFETs, for ultra-safe operations in case of high output prebias, short-circuit conditions, severe overloads, or in converters with bulk electrolytic capacitors. The MAX15040 features an adjustable output voltage. The output voltage is adjustable by using two external resistors at the feedback or by applying an external reference voltage to the REFIN/SS input. The MAX15040 offers programmable soft-start time using one capacitor to reduce input inrush current. A built-in thermal shutdown protection assures safe operation under all conditions. The MAX15040 is available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch WLP package. Features o Internal 15mΩ RDS(ON) MOSFETs o Continuous 4A Output Current o ±1% Output-Voltage Accuracy Over Load, Line, and Temperature o Operates from 2.4V to 3.6V Supply o Adjustable Output from 0.6V to (0.9 x VIN) o Adjustable Soft-Start Reduces Inrush Supply Current o Factory-Trimmed 1MHz Switching Frequency o Compatible with Ceramic, Polymer, and Electrolytic Output Capacitors o Safe Startup into Prebias Output o Enable Input/Power-Good Output o Fully Protected Against Overcurrent and Overtemperature o Overload Hiccup Protection o Sink/Source Current in DDR Applications o 2mm x 2mm, 16-Bump (4 x 4 Array), 0.5mm Pitch WLP Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX15040EWE+ -40°C to +85°C 16 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. Typical Operating Circuit INPUT 2.4V TO 3.6V IN EN BST MAX15040 OUTPUT LX VDD Applications GND Server Power Supplies Point-of-Load ASIC/CPU/DSP Core and I/O Voltages DDR Power Supplies Base-Station Power Supplies Telecom and Networking Power Supplies RAID Control Power Supplies FB REFIN/SS COMP VDD PWRGD GND Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX15040 General Description MAX15040 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package ABSOLUTE MAXIMUM RATINGS IN, VDD, PWRGD to GND ......................................-0.3V to +4.5V LX to GND....................-0.3V to the lower of 4.5V or (VIN + 0.3V) LX Transient ..............(VGND - 1.5V, <50ns), (VIN + 1.5V, <50ns) COMP, FB, REFIN/SS, EN to GND ..............-0.3V to the lower of 4.5V or (VDD + 0.3V) LX RMS Current (Note 1) .........................................................5A BST to LX..................................................................-0.3V to +4V BST to GND ..............................................................-0.3V to +8V Continuous Power Dissipation (TA = +70°C) 16-Bump (4 x 4 Array), 0.5mm Pitch WLP (derated 12.5mW/°C above +70°C)...........................1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Continuous Operating Temperature at Full Load Current (Note 2) ...........................................+105°C Storage Temperature Range .............................-65°C to +150°C Soldering Temperature (reflow) .......................................+260°C Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed the package power dissipation limit of the device. Note 2: Continuous operation at full current beyond +105°C may degrade product life. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = VDD = 3.3V, TA = -40°C to +85°C. Typical values are at TA = +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS 3.60 V IN/VDD IN and VDD Voltage Range 2.40 VIN = 2.5V 0.52 1 VIN = 3.3V 0.8 1.5 IN Supply Current No load, no switching VDD Supply Current No load, no switching Total Supply Current (IN + VDD) No load Total Shutdown Current from IN and VDD VIN = VDD = VBST - VLX = 3.6V, VEN = 0V VDD Undervoltage Lockout Threshold LX starts/stops switching VIN = 2.5V 3.7 5.5 VIN = 3.3V 4 6 VIN = VDD = 2.5V 12 VIN = VDD = 3.3V 23 VDD rising VDD falling VDD UVLO Deglitching 1.75 mA mA mA 0.1 2 2 2.2 1.9 2 µA V µs BST BST Leakage Current VBST = VDD = VIN = 3.6V, VLX = 3.6V or 0V, VEN = 0V TA = +25°C TA = +85°C 2 0.025 µA PWM COMPARATOR PWM Comparator Propagation Delay 10mV overdrive 10 ns COMP COMP Clamp Voltage High VDD = 2.4V to 3.6V 2.03 V COMP Clamp Voltage Low VDD = 2.4V to 3.6V 0.73 V 1.6 V/µs VDD = 2.4V to 3.6V 830 mV 1 V 8 Ω COMP Slew Rate PWM Ramp Valley PWM Ramp Amplitude COMP Shutdown Resistance 2 From COMP to GND, VEN = 0V _______________________________________________________________________________________ High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package (VIN = VDD = 3.3V, TA = -40°C to +85°C. Typical values are at TA = +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.594 0.600 0.606 V ERROR AMPLIFIER FB Regulation Accuracy Using internal reference Open-Loop Voltage Gain 1kΩ from COMP to GND (Note 4) 115 dB Error-Amplifier Unity-Gain Bandwidth Series 5kΩ, 100nF from COMP to GND (Note 4) 26 MHz Error-Amplifier Common-Mode Input Range VDD = 2.4V to 2.6V 0 VDD - 1.80 VDD = 2.6V to 3.6V 0 VDD - 1.85 Error-Amplifier Minimum Output Current VCOMP = 1.2V, sinking 500 VCOMP = 1.0V, sourcing 1000 FB Input Bias Current VFB = 0.7V, using internal reference, TA = +25°C -200 V µA -100 nA REFIN/SS REFIN/SS Charging Current VREFIN/SS = 0.45V 7 REFIN/SS Discharge Resistance REFIN/SS Common-Mode Range REFIN/SS Offset Voltage 8 9 VDD = 2.4V to 2.6V 0 VDD - 1.80 VDD = 2.6V to 3.6V 0 VDD - 1.85 Error amplifier offset TA = +25°C 30 -4.5 µA Ω 520 V µV +4.5 mV LX (ALL BUMPS COMBINED) LX On-Resistance, High Side ILX = -0.4A LX On-Resistance, Low Side ILX = 0.4A LX Peak Current-Limit Threshold VIN = 2.5V LX Leakage Current VIN = 3.6V, VEN = 0V VIN = VBST - VLX = 2.5V 21 VIN = VBST - VLX = 3.3V 19 VIN = 2.5V 16 VIN = 3.3V 15 High-side sourcing 5.5 7 Low-side sinking 5.5 7 TA = +25°C VLX = 0V mΩ mΩ A -2 VLX = 3.6V TA = +85°C +2 µA 1.03 MHz 0.2 LX Switching Frequency VIN = 2.5V to 3.3V, TA = +25°C 0.92 1 LX Maximum Duty Cycle VIN = 2.5V to 3.3V, TA = +25°C 92 96 % 80 ns LX Minimum On-Time RMS LX Output Current 4 A ENABLE EN Input Logic-Low Threshold 0.7 EN Input Logic-High Threshold EN Input Current 1.7 VEN = 0 or 3.6V, VIN = VDD = 3.6V V TA = +25°C TA = +85°C V 1 0.3 µA _______________________________________________________________________________________ 3 MAX15040 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VIN = VDD = 3.3V, TA = -40°C to +85°C. Typical values are at TA = +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS THERMAL SHUTDOWN Thermal-Shutdown Threshold Rising Thermal-Shutdown Hysteresis +165 °C 20 °C POWER-GOOD (PWRGD) VFB falling, VREFIN/SS = 0.6V Power-Good Threshold Voltage 87 90 VFB rising, VREFIN/SS = 0.6V 93 % of VREFIN/SS 92.5 Clock cycles Power-Good Edge Deglitch VFB falling or rising PWRGD Output-Voltage Low IPWRGD = 4mA (sinking) 0.03 PWRGD Leakage Current VDD = VPWRGD = 3.6V, VFB = 0.9V 0.01 µA 48 Current-Limit Startup Blanking 112 Clock cycles Restart Time 896 Clock cycles 0.15 V OVERCURRENT LIMIT (HICCUP MODE) FB Hiccup Threshold VFB falling 70 % of VREFIN/SS Hiccup Threshold Blanking Time VFB falling 36 µs Note 3: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and characterization. Note 4: Guaranteed by design. Typical Operating Characteristics (VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.) EFFICIENCY vs. OUTPUT CURRENT EFFICIENCY vs. OUTPUT CURRENT 90 VOUT = 1.5V VOUT = 1.2V 70 VOUT = 2.5V 60 90 EFFICIENCY (%) VOUT = 1.8V 80 80 VOUT = 1.8V VOUT = 1.5V 70 VOUT = 1.2V 60 50 50 VIN = VDD = 2.5V VDD = VIN = 3.3V 40 40 0.1 1 OUTPUT CURRENT (A) 4 MAX15040 toc02 100 MAX15040 toc01 100 EFFICIENCY (%) MAX15040 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package 10 0.1 1 OUTPUT CURRENT (A) _______________________________________________________________________________________ 10 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package 1.15 80 FREQUENCY (MHz) EFFICIENCY (%) 1.10 VOUT = 1.8V 70 VOUT = 1.5V VOUT = 1.2V 60 1.05 1.00 0.95 TA = +85°C 0.90 50 VDD = 3.3V VIN = 2.5V 0.4 TA = -40°C 0.85 40 10 1 VOUT = 1.2V 0.3 0.2 0.1 0 -0.1 VOUT = 1.8V -0.2 -0.3 -0.4 -0.5 0.80 0.1 2.4 2.6 2.8 3.0 3.2 3.4 2.4 3.6 2.6 2.8 3.0 3.2 INPUT VOLTAGE (V) LOAD REGULATION LOAD-TRANSIENT RESPONSE MAX15040 toc06 3.6 SWITCHING WAVEFORMS MAX15040 toc08 MAX15040 toc07 0 3.4 INPUT VOLTAGE (V) OUTPUT CURRENT (A) 0.10 OUTPUT VOLTAGE ERROR (%) TA = +25°C 0.5 OUTPUT VOLTAGE ERROR (%) MAX15040 toc04 90 LINE REGULATION 1.20 MAX15040 toc03 100 FREQUENCY vs. INPUT VOLTAGE MAX15040 toc05 EFFICIENCY vs. OUTPUT CURRENT AC-COUPLED 50mV/div VOUT AC-COUPLED 100mV/div VOUT -0.10 ILX 2A/div VOUT = 2.5V -0.20 VOUT = 1.8V IOUT -0.30 0 1A/div VOUT = 1.5V 2V/div VLX -0.40 VOUT = 1.2V 0 0 INTERNAL REFERENCE -0.50 0 1 2 3 4 400ns/div 40µs/div LOAD CURRENT (A) SHUTDOWN WAVEFORM SOFT-START WAVEFORM MAX15040 toc09 VEN MAX15040 toc10 2V/div 2V/div VEN 0 0 VOUT 1V/div 1V/div VOUT 0 0 IOUT = 1.8A 10µs/div MAX15040 Typical Operating Characteristics (continued) (VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.) 400µs/div _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.) INPUT SHUTDOWN CURRENT vs. INPUT VOLTAGE RMS INPUT CURRENT DURING SHORT CIRCUIT vs. INPUT VOLTAGE HICCUP CURRENT LIMIT MAX15040 toc12 VOUT 1V/div 0 12 10A/div IOUT 8 0 4 5A/div IIN MAX15040 toc13 16 0.5 RMS INPUT CURRENT (A) MAX15040 toc11 20 INPUT SHUTDOWN CURRENT (nA) 0.4 0.3 0.2 0.1 0 VEN = 0 VOUT = 0 0 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 1ms/div 2.6 INPUT VOLTAGE (V) 2.8 3.0 3.2 SOFT-START WITH REFIN/SS MAX15040 toc15 MAX15040 toc14 0.610 NO LOAD 0.608 0.606 2A/div 0 IIN 0.604 0.602 500mV/div VREFIN/SS 0.600 0 0.598 1V/div VOUT 0.596 0 0.594 2V/div VPWRGD 0.592 0 0.590 -40 -15 10 35 60 85 200µs/div TEMPERATURE (°C) STARTING INTO PREBIAS OUTPUT WITH NO LOAD STARTING INTO PREBIAS OUTPUT WITH 2A LOAD MAX15040 toc17 MAX15040 toc16 VEN 2V/div 2V/div VEN 0 0 VOUT 1V/div 0 1V/div VOUT 0 2A/div IOUT 0 VPWRGD VPWRGD 2V/div 0 2V/div 0 400µs/div 6 3.4 INPUT VOLTAGE (V) FEEDBACK VOLTAGE vs. TEMPERATURE FEEDBACK VOLTAGE (V) MAX15040 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package 400µs/div _______________________________________________________________________________________ 3.6 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package CASE TEMPERATURE vs. AMBIENT TEMPERATURE STARTING INTO PREBIAS OUTPUT ABOVE NOMINAL SETPOINT WITH NO LOAD MAX15040 toc18 VOUT 1V/div 0 2V/div 0 VPWRGD CASE TEMPERATURE (°C) VEN CASE = TOP SIDE OF DEVICE MEASURED ON A MAX15040EVKIT 100 2V/div MAX15040 toc19 120 80 60 40 20 0 -20 IOUT = 4A -40 -40 1ms/div -15 10 35 60 85 AMBIENT TEMPERATURE (°C) Pin Description BUMP NAME FUNCTION A1, A2 GND A3, A4 IN Power-Supply Input. Input supply range is from 2.4V to 3.6V. Bypass IN to GND with a 22µF ceramic capacitor in parallel to a 0.1µ F ceramic capacitor as close as possible to the device. B1, B2, B3 LX Inductor Connection. All LX bumps are internally connected together. Connect all LX bumps to the switched side of the inductor. LX is high impedance when the device is in shutdown mode. B4 VDD Supply Input. VDD powers the internal analog core. Connect VDD to IN with a 10Ω resistor. Connect a 1µF ceramic capacitor from VDD to GND. C1 BST High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor. C2, C3 I.C. Internally Connected. Leave unconnected or connect to ground. C4 EN Enable Input. Connect EN to GND to disable the device. Connect EN to VDD to enable the device. Analog/Power Ground. Connect GND to the PCB ground plane at one point near the input bypass capacitor return terminal as close as possible to the device. D1 PWRGD Power-Good Output. PWRGD is an open-drain output that goes high impedance when VFB exceeds 92.5% of VREFIN/SS and VREFIN/SS is above 0.54V. PWRGD is internally pulled low when VFB falls below 90% of VREFIN/SS or VREFIN/SS is below 0.54V. PWRGD is internally pulled low when the device is in shutdown mode, VDD is below the internal UVLO threshold, or the device is in thermal shutdown. D2 FB Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set the output voltage from 0.6V to 90% of VIN. D3 COMP D4 Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to FB and the converter output (see the Compensation Design section). COMP is internally pulled to GND when the device is in shutdown mode. External Reference Input/Soft-Start Timing Capacitor Connection. Connect REFIN/SS to a system voltage to force FB to regulate to REFIN/SS voltage. REFIN/SS is internally pulled to GND when the device is in REFIN/SS shutdown and thermal shutdown mode. If no external reference is applied, the internal 0.6V reference is automatically selected. REFIN/SS is also used to perform soft-start. Connect a minimum of 1nF capacitor from REFIN/SS to GND to set the startup time (see the Soft-Start and Reference Input (REFIN/SS) section). _______________________________________________________________________________________ 7 MAX15040 Typical Operating Characteristics (continued) (VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.) High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package MAX15040 Block Diagram VDD MAX15040 EN UVLO CIRCUITRY SHUTDOWN CONTROL CURRENT-LIMIT COMPARATOR BIAS GENERATOR LX ILIM THRESHOLD BST IN VOLTAGE REFERENCE BST SWITCH SHDN SOFT-START CONTROL LOGIC LX IN THERMAL SHUTDOWN REFIN/SS GND ERROR AMPLIFIER CURRENT-LIMIT COMPARATOR PWM COMPARATOR ILIM THRESHOLD FB 1VP-P OSCILLATOR COMP SHDN COMP CLAMPS FB 0.9 x VREFIN/SS 8 PWRGD _______________________________________________________________________________________ GND High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package INPUT 2.4V TO 3.6V IN R1 10Ω C1 22µF BST C3 0.1µF U1 C9 0.1µF OPTIONAL R10 2.2Ω C15 1000pF IN LX MAX15040 LX VDD L1 0.47µH OUTPUT 1.8V/4A LX C5 1µF R6 430Ω ON C2 22µF EN OFF C10 470pF C4 0.01µF R3 8.06kΩ 1% GND FB C11 820pF REFIN/SS C8 0.033µF R4 5.1kΩ R7 4.02kΩ 1% COMP VDD C12 33pF PWRGD GND R5 20kΩ Figure 1. All-Ceramic Capacitor Design with VOUT = 1.8V Detailed Description The MAX15040 high-efficiency, voltage-mode switching regulator is capable of delivering up to 4A of output current. The MAX15040 provides output voltages from 0.6V to (0.9 x VIN) from 2.4V to 3.6V input supplies, making it ideal for on-board point-of-load applications. The output-voltage accuracy is better than ±1% over load, line, and temperature. The MAX15040 features a 1MHz fixed switching frequency, allowing the user to achieve all-ceramic capacitor designs and fast transient responses. The high operating frequency minimizes the size of external components. The MAX15040 is available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch WLP package. The REFIN/SS function makes the MAX15040 an ideal solution for DDR and tracking power supplies. Using internal low-RDSON (15mΩ) n-channel MOSFETs for both high- and low-side switches maintains high efficiency at both heavy-load and high-switching frequencies. The MAX15040 employs voltage-mode control architecture with a high-bandwidth (> 15MHz) error amplifier. The op-amp voltage-error amplifier works with Type III compensation to fully utilize the bandwidth of the highfrequency switching to obtain fast transient response. Adjustable soft-start time provides flexibilities to minimize input startup inrush current. An open-drain, power-good (PWRGD) output goes high impedance when VFB exceeds 92.5% of VREFIN/SS and VREFIN/SS is above 0.54V. PWRGD goes low when VFB falls below 90% of VREFIN/SS or VREFIN/SS is below 0.54V. Controller Function The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator and generates the driver signals for both high-side and lowside MOSFETs. The control logic block controls the break-before-make logic and the timing for charging the bootstrap capacitors. The error signal from the voltageerror amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator to produce the required PWM signal. The high-side switch turns on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the VCOMP signal or the current-limit threshold is exceeded. The low-side switch then turns on for the remainder of the oscillator cycle. _______________________________________________________________________________________ 9 MAX15040 Typical Application Circuit MAX15040 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package Current Limit Undervoltage Lockout (UVLO) The internal, high-side MOSFET has a typical 7A peak current-limit threshold. When current flowing out of LX exceeds this limit, the high-side MOSFET turns off and the low-side MOSFET turns on. The low-side MOSFET remains on until the inductor current falls below the lowside current limit. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. The MAX15040 uses a hiccup mode to prevent overheating during short-circuit output conditions. During current limit, if V FB drops below 70% of VREFIN/SS and stays below this level for typically 36µs (12µs min) or more, the device enters hiccup mode. The high-side MOSFET and the low-side MOSFET turn off and both COMP and REFIN/SS are internally pulled low. The device remains in this state for 896 clock cycles and then attempts to restart for 112 clock cycles. If the fault-causing current limit has cleared, the device resumes normal operation. Otherwise, the device reenters hiccup mode. The UVLO circuitry inhibits switching when V DD is below 1.9V (typ). Once VDD rises above 2V (typ), UVLO clears and the soft-start function activates. A 100mV hysteresis is built in for glitch immunity. Soft-Start and Reference Input (REFIN/SS) The MAX15040 utilizes an adjustable soft-start function to limit inrush current during startup. An 8µA (typ) current source charges an external capacitor connected to REFIN/SS. The soft-start time is adjusted by the value of the external capacitor from REFIN/SS to GND. The required capacitance value is determined as: C= 8µA × t SS 0.6V where tSS is the required soft-start time in seconds. Connect a minimum 1nF capacitor between REFIN/SS and GND. REFIN/SS is also an external reference input (REFIN/SS). The device regulates FB to the voltage applied to REFIN/SS. The internal soft-start is not available when using an external reference. Figure 2 shows a method of soft-start when using an external reference. If an external reference is not applied, the device uses the internal 0.6V reference. BST The gate-drive voltage for the high-side, n-channel switch is generated by a flying-capacitor boost circuit. The capacitor between BST and LX is charged from the VIN supply while the low-side MOSFET is on. When the low-side MOSFET is switched off, the voltage of the capacitor is stacked above LX to provide the necessary turn-on voltage for the high-side internal MOSFET. Power-Good Output (PWRGD) PWRGD is an open-drain output that goes high impedance when VFB is above 92.5% x VREFIN/SS and VREFIN/SS is above 0.54V. PWRGD pulls low when VFB is below 90% of VREFIN/SS for at least 48 clock cycles or V REFIN/SS is below 0.54V. PWRGD is low during shutdown. Setting the Output Voltage The MAX15040 output voltage is adjustable from 0.6V to 90% of VIN by connecting FB to the center tap of a resistor-divider between the output and GND (Figure 3). To determine the values of the resistor-divider, first select the value of R3 between 2kΩ and 10kΩ. Then use the following equation to calculate R4: R4 = (VFB x R3)/(VOUT - VFB) where V FB is equal to the reference voltage at REFIN/SS and VOUT is the output voltage. For VOUT = 0.6V, remove R4. If no external reference is applied at REFIN/SS, the internal reference is automatically selected and VFB becomes 0.6V. LX R3 MAX15040 R1 REFIN/SS R2 C R4 MAX15040 Figure 2. Typical Soft-Start Implementation with External Reference 10 FB Figure 3. Setting the Output Voltage with a Resistor VoltageDivider ______________________________________________________________________________________ High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package Thermal Protection Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds TJ = +165°C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 20°C, causing a pulsed output during continuous overload conditions. The soft-start sequence begins after recovery from a thermal-shutdown condition. Applications Information IN and VDD Decoupling To decrease the noise effects due to the high switching frequency and maximize the output accuracy of the MAX15040, decouple VIN with a 22µF capacitor in parallel with a 0.1µF capacitor from VIN to GND. Also decouple VDD with a 1µF capacitor from VDD to GND. Place these capacitors as close as possible to the device. Inductor Selection Choose an inductor with the following equation: L= VOUT × (VIN − VOUT ) fS × VIN × LIR × IOUT(MAX) where LIR is the ratio of the inductor ripple current to full load current at the minimum duty cycle and fS is the switching frequency (1MHz). Choose LIR between 20% to 40% for best performance and stability. Use an inductor with the lowest possible DC resistance that fits in the allotted dimensions. Powdered iron or ferrite core types are often the best choice for performance. With any core material, the core must be large enough not to saturate at the current limit of the MAX15040. Output-Capacitor Selection The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s ESL. Estimate the output voltage ripple due to the output capacitance, ESR, and ESL as follows: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: IP − P VRIPPLE(C) = 8 x COUT x fS VRIPPLE(ESR) = IP − P x ESR I VRIPPLE(ESL) = P − P x ESL or tON I VRIPPLE(ESL) = P − P x ESL tOFF or whichever is higher. The peak-to-peak inductor current (IP-P) is: V − VOUT V IP−P = IN x OUT fS × L VIN Use these equations for initial output capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ∆ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for more details. ______________________________________________________________________________________ 11 MAX15040 Shutdown Mode Drive EN to GND to shut down the device and reduce quiescent current to less than 0.1µA. During shutdown, LX is high impedance. Drive EN high to enable the MAX15040. MAX15040 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package Input-Capacitor Selection The input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the device. The total input capacitance must be equal to or greater than the value given by the following equation to keep the input ripple voltage within the specification and minimize the high-frequency ripple current being fed back to the input source: CIN _ MIN = D x TS x IOUT VIN − RIPPLE where VIN-RIPPLE is the maximum allowed input ripple voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage, D is the duty cycle (VOUT/VIN), and TS is the switching period (1/fS) = 1µs. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. The input capacitor must meet the ripple current requirement imposed by the switching currents. The RMS input ripple current is given by: VOUT × (VIN − VOUT ) IRIPPLE = ILOAD × VIN where IRIPPLE is the input RMS ripple current. total equivalent series resistance of the output capacitor. If there is more than one output capacitor of the same type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single output capacitor divided by the total number of output capacitors. The MAX15040 high switching frequency allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher than the unitygain crossover frequency, fC, and the zero cannot be used to compensate for the double pole created by the output inductor and capacitor. The double pole produces a gain drop of 40dB/decade and a phase shift of 180°. The compensation network must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. Therefore, use type III compensation as shown in Figure 4 and Figure 5. Type III compensation possesses three poles and two zeros with the first pole, fP1_EA, located at zero frequency (DC). Locations of other poles and zeros of the type III compensation are given by: 1 fZ1_ EA = 2π x R1 x C1 fZ2 _ EA = 1 2π x R3 x C3 fP3 _ EA = 1 2π x R1 x C2 fP2 _ EA = 1 2π x R2 x C3 Compensation Design The power transfer function consists of one double pole and one zero. The double pole is introduced by the inductor, L, and the output capacitor, CO. The ESR of the output capacitor determines the zero. The double pole and zero frequencies are given as follows: fP1_ LC = fP2 _ LC = 1 ⎛ R + ESR ⎞ 2π x L x C O x ⎜ O ⎟ ⎝ RO + RL ⎠ fZ _ ESR = 1 2π x ESR x CO where RL is equal to the sum of the output inductor’s DC resistance (DCR) and the internal switch resistance, RDSON. A typical value for RDSON is 15mΩ. RO is the output load resistance, which is equal to the rated output voltage divided by the rated output current. ESR is the 12 The above equations are based on the assumptions that C1 >> C2, and R3 >> R2, which are true in most applications. Placements of these poles and zeros are determined by the frequencies of the double pole and ESR zero of the power transfer function. It is also a function of the desired closed-loop bandwidth. The following section outlines the step-by-step design procedure to calculate the required compensation components for the MAX15040. The output voltage is determined by: R4 = 0.6 × R3 V ( OUT − 0.6) For VOUT = 0.6V, R4 is not needed. ______________________________________________________________________________________ High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package COMPENSATION TRANSFER FUNCTION VOUT COUT MAX15040 R2 C3 OPEN-LOOP GAIN THIRD POLE DOUBLE POLE R3 MAX15040 L LX GAIN (dB) FB R1 C1 COMP R4 C2 POWER-STAGE TRANSFER FUNCTION SECOND POLE FIRST AND SECOND ZEROS FREQUENCY (Hz) Figure 4. Type III Compensation Network Figure 5. Type III Compensation Illustration The zero-cross frequency of the closed-loop, fC, should be between 10% and 20% of the switching frequency, fS (1MHz). A higher zero-cross frequency results in faster transient response. Once fC is chosen, C1 is calculated from the following equation: ⎛ V ⎞ 2.5 ⎜ IN ⎟ ⎝ VP − P ⎠ C1 = R 2 x π x R3 x (1 + L ) × fC RO The above equations provide accurate compensation when the zero-cross frequency is significantly higher than the double-pole frequency. When the zero-cross frequency is near the double-pole frequency, the actual zerocross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces the zerocross frequency. Also, set the third pole of the type III compensation close to the switching frequency (1MHz) if the zero-cross frequency is above 200kHz to boost the phase margin. The recommended range for R3 is 2kΩ to 10kΩ. Note that the loop compensation remains unchanged if only R4’s resistance is altered to set different outputs. where VP-P = 1VP-P (typ). Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type III compensation less than the LC double-pole frequency to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency. Hence: R1 = C3 = 1 x 0.8 x C1 1 x 0.8 x R 3 L x CO x (RO + ESR) RL + RO L x CO x (RO + ESR) RL + RO Setting the second compensation pole, f P2_EA , at fZ_ESR yields: R2 = CO x ESR C3 Set the third compensation pole at 1/2 of the switching frequency (500kHz) to gain phase margin. Calculate C2 as follows: 1 C2 = π x R1 x fS Soft-Starting into a Prebiased Output The MAX15040 soft-starts into a prebiased output without discharging the output capacitor. In safe prebiased startup, both low-side and high-side switches remain off to avoid discharging the prebiased output. PWM operation starts when the voltage on REFIN/SS crosses the voltage on FB. The PWM activity starts with the low-side switch turning on first to build the bootstrap capacitor charge. Power-good (PWRGD) asserts 48 clock cycles after FB crosses 92.5% of the final regulation set point. After 4096 clock cycles, the device switches from prebiased safe startup mode to forced PWM mode. The MAX15040 is capable of starting into a prebias voltage higher than the nominal set point without abruptly discharging the output. This is achieved by using the sink current control of the low-side MOSFET, which has four internally set sinking current-limit thresholds. An internal 4-bit DAC steps through these thresholds, starting from the lowest current limit to the highest, in 128 clock cycles on every power-up. ______________________________________________________________________________________ 13 MAX15040 High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package Pin Configuration PCB Layout Considerations and Thermal Performance Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX15040 evaluation kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout: 1) Connect input and output capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 2) Place capacitors on VDD, IN, and REFIN/SS as close as possible to the device and the corresponding bump using direct traces. Keep power ground plane and signal ground plane separate. (BUMPS ON BOTTOM) TOP VIEW 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. GND GND IN IN A1 A2 A3 A4 LX LX LX VDD B1 B2 B3 B4 BST I.C. I.C. EN C1 C2 C3 C4 PWRGD FB COMP REFIN/SS D1 D2 D3 D4 4) Connect IN, LX, and GND separately to a large copper area to help cool the device to further improve efficiency and long-term reliability. WLP 5) Ensure all feedback connections are short. Place the feedback resistors and compensation components as close to the device as possible. 6) Route high-speed switching nodes, such as LX and BST, away from sensitive analog areas (FB, COMP). Chip Information PROCESS: BiCMOS 14 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 WLP W162B2+1 21-0200 — ______________________________________________________________________________________ High-Efficiency, 4A, Step-Down Regulator with Integrated Switches in 2mm x 2mm Package REVISION NUMBER REVISION DATE 0 1/09 Initial release 1 5/10 Revised the Absolute Maximum Ratings and Electrical Characteristics. 2 7/10 Revised the Absolute Maximum Ratings. DESCRIPTION PAGES CHANGED — 1–4 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX15040 Revision History