APW8700 Dual-Phase Synchronous-Rectifier Buck Controller Features General Description • Voltage-Mode Operation with Current Sharing • Operate with 4.5V~13.2V Supply Voltage The APW8700, two-phase PWM control IC, provides a precision voltage regulation system for advanced graphic • Support Single and Two-Phase Operations • +2% Reference Voltage Accuracy Over card and motherboard applications. The integration of power MOSFET drivers into the controller IC and reduces the number of external parts for a cost and space saving power management solution. Temperature • Loss-Less Inductor DCR Current Sensing • Adjustable Over Current Protection use DCR The APW8700 uses a voltage-mode PWM architecture, operating with adjust frequency from 100kHz to 800kHz. Current Sensing • The device uses the voltage across the DCRs of the inductors for current sensing achieves high efficiency. The Programmable PWM Switching Frequency from device integrates adjustable load line voltage positioning (droop) and adopts low side RDS_ON for channel-cur- 100kHz to 800kHz • Dynamic Output Voltage Adjustment • Adjustable Soft-start • QFN4x4-24 Package • Halogen and Lead Free Available (RoHS Compliant) rent balance. The automatic phase reduction and over-current protection are accomplished through continuous inductor DCRs current sensing. The APW8700 also implement a one-bit VID control operation in which the feedback voltage is regulated and Simplified Application Circuit tracks external input reference voltage. This controller protection features include over- VIN temperature(OTP), over-voltage(OVP), under-voltage (UVP) and over-current protections (OCP). SS ON OFF UGATE1 RT/EN VOUT The device also provides a power-on-reset function and a programmable soft-start to prevent wrong operation and PSI LGATE1 limit the input surge current during power-on or start-up. The APW8700 is available in QFN4x4-24 packages. VREF REFIN UGATE2 COMP Applications FB LGATE2 • • VGA Mother Board ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 1 www.anpec.com.tw APW8700 Ordering and Marking Information Package Code QA : QFN4x4-24 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW8700 Assembly Material Handling Code Temperature Range Package Code APW8700 QA : APW8700 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration APW8700 LGATE2 BOOT2 PHASE2 VID UGATE2 RSET 24 23 22 21 20 19 REFIN 1 18 VCC VREF 2 17 PVCC RT/EN 3 IOFS 4 16 LGATE1 15 PHASE1 (Exposed Pad) GND COMP 5 FB 6 UGATE1 13 BOOT1 AGND EAP SS 10 11 12 PSI 9 CSP 8 CSN 7 14 QFN4x4-24 Top View Absolute Maximum Ratings (Note 1) Symbol Parameter VVCC Input Supply Voltage (VVCC to GND) VPVCC Gate Driver Supply Voltage (VPVCC to GND) BOOT1/2 to PHASE1/2 Voltage BOOT1/2 to GND Voltage UGATE1/2 to PHASE1/2 Voltage VLGATE1/2 LGATE1/2 to GND Voltage VPHASE1/2 PHASE1/2 to GND Voltage PD Rating Unit -0.3 ~ 16 V -0.3 ~ VVCC+1 V -0.3 ~ 16 V -0.3 ~ 30 V > 200ns -0.3 ~ VBOOT1/2+0.3 V < 200ns -5 ~ VBOOT1/2+5 V > 200ns -0.3 ~ VVCC+0.3 V < 200ns -5 ~ VVCC+5 V > 200ns -0.3 ~ 16 V < 200ns -10 ~ 30 V REFIN, VREF, RT/EN, IOFS, COMP, FB, EAP, SS, CSP, CSN, PSI, VID, RSET to AGND Voltage -0.3 ~ 7 V AGND to GND -0.3 +0.3 V 2.5 W Power Dissipation Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 2 www.anpec.com.tw APW8700 Absolute Maximum Ratings (Cont.) (Note 1) Symbol TJ Parameter Rating Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature (10 Seconds) Unit 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol Parameter Typical Value Unit θJA Junction-to-Ambient Resistance in free air (Note 2) QFN4x4-24 41 o θJC Junction-to-Case Resistance QFN4x4-24 9 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit VVCC VCC Supply Voltage (VVCC to GND) 4.5 ~ 13.2 V VOUT VOUT to GND 0.6 ~ 5.5 V Converter Input Voltage 2 ~ 13.2 V 100 ~ 800 kHz VIN FOSC Oscillator Frequency IOUT Converter Output Current TA TJ 0 ~ 60 Ambient Temperature Junction Temperature A -40 ~ 85 o -40 ~ 125 o C C Note 3: Refer to the application circuit for further information. Electrical Characteristics Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over VVCC = 12V, TA= 25oC, unless otherwise noted. Symbol Parameter APW8700 Test Conditions Unit Min. Typ. Max. 4.5 - 13.2 V - 4 5 mA SUPPLY CURRENT VCC IDD_SD Supply Voltage Range Input DC Bias Current IDD VPVCC No switching, RT/EN=GND - 5 7 mA 8 9 10 V POR Threshold of VCC 3.8 4.1 4.4 V POR Hysteresis 0.3 0.5 0.6 V POR Threshold of PVCC 3.8 4.1 4.4 V POR Hysteresis 0.3 0.5 0.6 V UGATE1/2, LGATE1/2 open, switching Regulated Supply Voltage Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 RT/EN=GND, IPVCC=0mA 3 www.anpec.com.tw APW8700 Electrical Characteristics (Cont.) Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over VVCC = 12V, TA= 25oC, unless otherwise noted. Symbol Parameter APW8700 Test Conditions Min. Typ. Unit Max. CHIP ENABLE/FREQUENCY SETTING IRT/EN RT/EN Source Current RT/EN=GND RT/EN Shutdown Threshold VRT/EN Enable Debounce time RT/EN high debounce RT/EN Voltage RRT/ENB=33kΩ Switching Frequency Setting Range - - 120 µA 0.45 0.5 0.55 V - 200 - µs - 1 - V 100 - 800 kHz FOSC Free Run Switching Frequency RRT/EN=33kΩ 255 300 345 kHz ΔFOSC Switching Frequency Accuracy FOSC=200kHz~500kHz -15 - 15 % SOFT-START ISS Soft-start Current During Soft-start - 20 - µA SS Source/Sink Current Capability After Soft-start - 200 - µA - 85 - % OSCILLATOR Maximum Duty Cycle Minmum Duty Cycle ΔVOSC Ramp Amplitude - 0 - % VVCC=12V - 1.5 - V V POWER SAVING MODE VPSI Threshold Voltage to Enter Dual Phase VPSI Rising 0.55 0.6 0.65 ΔVPSI Hysteresis to Enter Single Phase VPSI Falling - 0.2 - V 2 Phase to single phase debounce Continuously - 0.2 - ms REFERENCE VOLTAGE VREF ΔVREF VFB Reference Voltage Accuracy IREF=100µA, TJ= -20oC ~ 70oC 1.98 2.00 2.02 V VREF Maximum Output Current VREF=GND 20 - - mA Reference Voltage Load Regulation IREF=0~2mA -5 - 5 mV Output Voltage Accuracy VREFIN-VFB, VREFIN=0.8V~2V, RDRP=0Ω -5 - 5 mV 0.2 - VREF V RL = 10kΩ, CL =10pF - 80 - V/V VFB operating range ERROR AMPLIFIER Open-Loop DC Gain (Note 4) Open-Loop Bandwidth VCOMP ICOMP (Note 4) RL = 10kΩ, CL =10pF - 20 - MHz Slew Rate (Note 4) RL = 10kΩ, CL =10pF - 8 - V/µs FB Input Leakage Current VFB=1V - 0.1 0.5 µA COMP High Voltage RL = 10kΩ, CL =10pF - 4.8 - V/µs COMP Low Voltage RL = 10kΩ, CL =10pF - 0.2 - µA Maximum COMP Source Current VCOMP=2V - 2 - mA Maximum COMP Sink Current VCOMP=2V - 2 - mA Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 4 www.anpec.com.tw APW8700 Electrical Characteristics (Cont.) Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over VVCC = 12V, TA= 25oC, unless otherwise noted. Symbol Parameter APW8700 Test Conditions Min. Typ. Unit Max. TOTAL CURRENT SENSE ICSN_MAX ICSN_OCP 100 - - µA GM Amplifier Offset -5 - 5 mV Over-Current Protection Threshold Level 55 60 65 µA Maximum Sourcing Current Droop Accuracy IDRP/ICSN 90 100 110 % PSI Accuracy IPSI/ICSN 90 100 110 % PHASE CURRENT SENSE gm VIOFS Trans-conductance IOFS Voltage - 1.0 - mA/V 100kΩ from IOFS to VREF 1.425 1.5 1.575 V 100kΩ from IOFS to GND 0.475 0.5 0.525 V VID CONTROL INPUT VIH Logic High Threshold Level 1.2 - - V VIL Logic Low Threshold Level - - 0.4 V RRSET On Resistance of RSET MOSFET VID=High - 20 - Ω IRSET Leakage Current of RSET Pin VRSET=2V, VID=GND - - 0.1 µA RUG_SRC Upper Side Gate Sourcing IUGATE=100mA Sourcing - 2 4 Ω RUG_SNK Upper Side Gate Sinking IUGATE=100mA Sinking - 1.5 3 Ω RLG_SRC Low Side Gate Sourcing ILGATE=100mA Sourcing - 2 4 Ω RLG_SNK Low Side Gate Sinking ILGATE=100mA Sinking Gate Driver TDT Dead-time - 1 2 Ω - 30 - ns 125 130 135 % - 20 - % 50 55 % µA PROTECTION Over Voltage Protection (OVP) VFB/VEAP Over Voltage Hysteresis Under Voltage Protection (UVP) VFB/VEAP 45 Over Current Protection (OCP) ICSN 55 60 65 Over Temperature Protection (OTP) - 150 - ο Over Temperature Hysteresis - 20 - ο C C Note 4: Guarantee by design, not production test Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 5 www.anpec.com.tw APW8700 Pin Description PIN NAME FUNCTION 1 REFIN External Reference Input. This is input pin of external reference voltage. Connect a voltage divider from VREF to REFIN to AGND to set the reference voltage. 2 VREF Reference Voltage Output. This is the output pin of high precision 2V reference voltage. Bypass this pin with a 1µF ceramic capacitor to AGND. 3 RT/EN Operation Frequency Setting. Connecting a resistor between this pin and AGND to set the operation frequency. Pull this pin to ground to shut down the APW8700. 4 IOFS 5 COMP 6 FB 7 AGND 8 EAP Current Balance Adjustment. Connect a resistor from this pin to VREF or GND to adjust the current sharing. Error Amplifier Output. Use this pin in combination with the FB pin to compensate the voltage-control feedback loop of the converter. Feedback Voltage. This pin is the inverting input to the error amplifier. Use this pin in combination with the COMP pin to compensate the voltage control feedback loop of the converter. Analog Ground. Connect this pin to the GND pin where the output voltage is to be regulated. Non-Inverting Input of Error Amplifier. Connect a resistor to SS pin to set the droop slope. 9 SS 10 CSN Soft Start Output. Connect a capacitor to GND to set the soft start interval. Inverting Input of Current Sensing Amplifier. 11 CSP Non-Inverting Input of Current Sensing Amplifier. 12 PSI Power Saving Indicator. Connect a resistor from PSI to AGND to set the power saving mode threshold current level. Connect this pin to VREF for always two phases operation. Short this pin to ground for always single-phase operation. Don’t left this pin floating. 13 BOOT1 Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF.Ensure that CBOOT is placed near the IC. 14 UGATE1 Upper Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 15 PHASE1 Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE1 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 16 LGATE1 Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. 17 PVCC Supply Voltage for Gate Driver. This pin is the output of internal 9V LDO. It provides current for gate drives. Bypass this pin with a minimum 1µF ceramic capacitor. If VCC below 7V, connect this pin to VCC is recommended. 18 VCC Supply Voltage. This pin provides current for internal control circuit and 9V LDO. Bypass this pin with a minimum 1µF ceramic capacitor next to the IC. 19 LGATE2 Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. 20 PHASE2 Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. 21 UGATE2 Upper Gate Driver Output for channel 2. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 6 www.anpec.com.tw APW8700 Pin Description(Cont.) PIN NAME FUNCTION 22 BOOT2 Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF.Ensure that CBOOT is placed near the IC. 23 VID VID Input. This pin is used to adjust reference voltage. Logic high turns on the internal MOSFET connected to RSET pin. 24 RSET Reference Voltage Setting. This pin is an open drain output that is pulled low when VID = high. Connect a resistor from this pin to REFIN pin to set the reference voltage. Exposed Pad GND Power Ground. Tie this pad to the ground island/plane through the lowest impedance connection available. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 7 www.anpec.com.tw APW8700 Typical Operating Characteristics Refer to the “Typical Application Circuits”, VIN=12V, VOUT=1.05V, TA=25oC unless otherwise specified Reference Voltage vs. Junction Reference Voltage vs. Supply Voltage 2.05 2.04 2.015 Reference Voltage, VREF(V) Reference Voltage, VREF(V) Temperature 2.020 2.03 2.02 2.01 2 1.99 1.98 1.97 2.010 2.005 2.000 1.995 1.990 1.985 1.96 1.980 -40 -20 0 1.95 4 5 6 7 8 9 10 11 12 13 14 Supply Voltage, VVCC (V) 5.0 5.0 4.5 4.5 LGATE Driver On Resistance (Ω) UGATE Driver On Resistance (Ω) UGATE Driver On Resistance vs. PVCC Voltage 4.0 UGATE Source 3.5 3.0 2.5 2.0 1.5 1.0 20 40 60 80 100 120 140 160 Junction Temperature, TJ(oC) UGATE Sink 0.5 LGATE Driver On Resistance vs. Supply Voltage 4.0 3.5 3.0 LGATE Source 2.5 2.0 1.5 1.0 LGATE Sink 0.5 0.0 0.0 4 5 6 7 8 4 9 5 6 7 8 9 10 11 12 Supply Voltage, VVCC (V) PVCC Voltage, VPVCC (V) PVCC Voltage vs. Supply Voltage 10 PVCC Voltage, VPVCC(V) 9 8 7 6 5 4 3 2 IPVCC = 10mA 1 0 4 5 6 7 8 9 10 11 12 13 14 Supply Voltage, VVCC (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 8 www.anpec.com.tw APW8700 Operating Waveforms Enable 1 Shutdown VRT , 1 V/Div, DC VRT , 1V/Div, DC 1 VPHASE 1, 10V/Div, DC 2 2 VPHASE 1, 10V/Div, DC VSS, 0 .5V /Div, DC VSS , 0.5V/Div, DC 3 3 VOUT , 0 .5V /Div, DC VOUT , 0.5V/Div, DC 4 4 Time: 500µs/Div Time: 500µs/Div Power ON 1 Power OFF VRT , 1 V/Div, DC 1 VRT, 1V/Div, DC VPHASE1, 5V/Div, DC 2 2 V PHASE1 , 5V/Div, DC VSS , 0.5V/Div, DC VSS, 0.5V/Div, DC 3 3 VOUT, 0.5V/Div, DC VOUT , 0.5V/Div, DC 4 4 Time: 500µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 Time: 50µs/Div 9 www.anpec.com.tw APW8700 Operating Waveforms PSI 1 OVP VPSI, 1V/Div, DC VFB, 1V/Div, DC VPHASE1, 10V/Div, DC 1 VPHASE2, 10V/Div, DC 2 2 3 VUGATE1, 10V/Div, DC 3 Time: 50µs/Div VLGATE1, 10V/Div, DC Time: 10µs/Div OCP V SS, 1V/Div, DC 1 VOUT , 1 V/Div, DC 2 I L1 +I L2 , 20A/Div, DC 3+4 I L1, 10A/Div, DC 3 I L2, 10A/Div, DC 4 Time: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 10 www.anpec.com.tw APW8700 Block Diagram VCC Internal Regulator 1 VREF Power On Reset Internal Regulator 2 PVCC IOFS RSET VID Current Balance Current Limit Buffer AGND REFIN Gm Amplifier CSP CSN SS Error Amplifier EAP FB Over Current Protection GND COMP Power Saving Setting IDRP PSI PVCC PVCC BOOT1 BOOT2 Logic Control UGATE1 Logic Control VOSC1 UGATE2 VOSC2 PHASE1 PHASE2 Oscillator VCC VCC Enable LGATE1 LGATE2 1V 0.5V RT/EN Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 11 www.anpec.com.tw APW8700 Typical Application Circuit VREF (option) VREF 1µF 1k PHASE2 (option) CSP REFIN 1k (option) IOFS 8.1k CSN 0.1µF 3k NC PHASE1 10k VOUT RSET VID PVCC 1µF AGND VCC SS 47nF 0 1µF GND BOOT1 EAP OFF ON 33k RT/EN 40k PSI 2N7002 0.1µF COMP 0.27k 220nF 100nF 12R Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 FB 10µFx2 UGATE1 PHASE1 BOOT2 270µFx2 VOUT APM3109 0.8µH LGATE1 10nF 680 VIN =12V APM3106 820µFx3 10µFx2 0.1µF 10µFx2 UGATE2 PHASE2 LGATE2 12 APM3109 0.8µH APM3106 www.anpec.com.tw APW8700 Function Description VCC Power-On-Reset (POR) The Power-On-Reset (POR) circuit compares the input voltage at VCC with the POR threshold (4.1V rising, typical) to ensure the input voltage is high enough for reliable operation. The 0.5V (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage ex- dV SS I SS 20 µ A = = dt C SS C SS During soft-start dV SS ISS 200 µ A = = dt C SS C SS After soft-start Figure 2 shows the simplified voltage control loop of APW8700. VREF is a reference voltage output with 1% ceeds the POR rising threshold, startup begins. When the input voltage falls below the POR falling threshold, the controller turns off the converter. accuracy and up to 20mA sourcing capability. RSET is an open drain output that is controlled by VID pin. RSET is VREF pulled to FBRTN when VID = 1 and is set high impedance when VID = 0. This is the output pin of high precision 2V reference voltage. Bypass this pin with a 1µF ceramic capacitor to V SS = V REF × AGND. The VREF have capability to drive 20mA output current. VSS = VREF × VCC POR UVLO R2 R1 + R 2 VID=0 R2 // R3 R1+ (R2 // R3) VID=1 PVCC VREF R1 REF R2 RT/EN SS=EAP R3 REFIN RSET VID VID AGND Figure 1. Power on/off sequence CSS SS Current Limit Buffer Soft-start RDRP After the VCC voltage exceeds the POR voltage threshold VOUT and the RT/EN voltage exceeds 0.5V, the device initials a start-up process and then ramps up the output voltage to Error Amplifier EAP FB the setting of output voltage. A 20µA current source starts to charge the capacitor (CSS ) connected with SS and IDRP AGND pins. Connect error amplifier non-inverting input, EAP, to SS. The VFB starts to rise with the same rate as COMP the soft-start voltage. Once the SS voltage reaches 80% of VREFIN, the soft-start process is completed after 3ms. After the soft-start process is completed, the SS could source/sink 200µA. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 Figure 2. Simplified voltage control loop 13 www.anpec.com.tw APW8700 Function Description (Cont.) Shutdown Control and Frequency Setting RT/EN is a multi function pin. Pull RT/EN below 0.5V to The differential current of the current balance control circuit (ISEN1-ISEN2) is used to fine-tune the COMP1/2 voltage. shuts down the device. Connecting a resistor between this pin and GND to set the operation frequency. The op- The VCOMP1 and VCOMP2 will increase or decrease because of these two currents. For example, when ISEN1>ISEN2, the eration frequency range could be set from 100kHz to 800kHz. In shutdown mode, the UGATEx and LGATEx are VCOMP1 will decrease and the VCOMP2 will increase. Therefore, the duty of PWM1 will decrease and the duty of PWM2 will pulled to PHASEx and GND respectively. When the pulldown device is released, the APW8700 initiate a soft- increase. Then, the device will reduce IL1 current and increase IL2 current for current sharing, vice verse. start process. Rx The switching frequency, FOSC, could be calculated as: F OSC = PHASE1 10000 ( kHz ) R RT ( k Ω ) COMP VOFFSET ISEN1 ISEN2 Sample & Hold ISEN1- ISEN2 Current Balance IOFS Rx 1000 COMP1 COMP2 IOFS PHASE2 IOFS Switching Frequency(kHz) VOFFSET Figure 4. Current balance scheme Current Sense Below shows the circuit of sensing inductor current. Connecting a series resistor (RS) and a capacitor (CS) network in parallel with the inductor and measuring the voltage (VC) across the capacitor can sense the inductor current. 100 10 100 RRT(kΩ) L1 Figure 3. Switching Frequency vs. RT resistance DCR1 VOUT PHASE1 Current Balancer The APW8700 adopts parasitic on-resistance of the lower RS EAP switches current balance as show in figure 4. When the lower switches turn on, the GM amplifier senses the volt- CS + VC - CSP RCSN age drop across the lower switches and converts it into current signal each time it turns on. The sampled and CSN IDRP ICSN held current is expressed as: ISENx IPSI IL X ⋅ RDS ( ON ) V OFFSET = + RX RX Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 PSI Figure 5. DCR current sense scheme 14 www.anpec.com.tw APW8700 Function Description (Cont.) The equations of the sensing network are: Automatic Phase Reduction The APW8700 implements automatic phase reduction that turns off phase 2 at light load condition and reduces VL1(s) = IL1(s) × (sL1 + DCR1) VC(s) = VL1(s) × both switching and conduction losses. The automatic phase reduction maintains high power conversion effi- 1 IL1(s) × ( sL1 + DCR1) = 1 + sRSCS 1 + sRSCS ciency over the output current range. The output current is sensed and mirrored to PSI pin as: Take RSCS = L1 DCR1 IPSI = ICSN = If the above is true, the voltage across the capacitor CS equal to voltage drop across the inductor DCR1, and the The IPSI creates a voltage VPSI as: voltage VC is proportional to the inductor current IL1. VC = DCR1× IL1 ICSN = IOUT × DCR1 2 × RCSN VPSI = RPSI × IPSI = VC IL1 × DCR1 = RCSN RCSN IOUT × DCR1× RPSI 2 × RCSN The APW8700 operates at dual phase if VPSI exceeds 0.6V and at single phase at VPSI below 0.4V. There is a 200mV hystersis at the phase change threshold. There is a 0.2ms delay when entering single phase operation where IL1 is the inductor current of phase 1 and no time delay when entering dual phase operation. DCR1 is the inductor resistance of phase 1 When operating single phase, both UGATE2 and LGATE2 are turned off. Due to the APW8700 implement current balance circuit. At two phase operation, the IL1 equal half of output current, IOUT. Droop Setting ICSN = IOUT × DCR1 2 × RCSN In some high current applications, a requirement on precisely controlled output impedance is imposed. This dependence of output voltage on load current is often termed Over Current Protection (OCP) The APW8700 feature an over current protection adopt droop regulation. As shown in figure 4, the droop control block generates a voltage through external resistor RDRP current sensing. When I CSN exceed 60µA at operation, the over current occurs. In over-current protection, the IC shuts and then set the droop voltage. The droop voltage, VDRP, is proportional to the total current in two channels. As off the converter. The ICSN can be describe as: shown in the following equation: V FB = V SS − IDRP × R DRP VC IOUT × DCR1 ICSN = = RCSN 2 × RCSN where IDRP is the droop current that mirrored from ICSN. The output voltage also can be describe as: The APW8700 initial a soft-start process until recycle POR or EN/RT. V FB = V SS − IDRP × RDRP = V SS − Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 15 IOUT × DCR 1× R DRP 2 × RCSN www.anpec.com.tw APW8700 Function Description (Cont.) Offset Current Adjust UVP The APW8700 integrated IOFS allows the offset current The under-voltage protection circuit monitors the voltage on FB (VFB) by Under-Voltage (UV) comparator to protect to adjust phase current. The IOFS pin voltage is nominal 0.5V when connecting a resistor to GND and 1.5V when the PWM converter against short-circuit conditions. When the VFB falls below the falling UVP threshold (50% VEAP), a connecting a resistor to VREF. Connecting a resistor from IOFS pin to GND generate a current source as: fault signal is generated and the device turns off highside and low-side MOSFETs. The converter shuts down IOFS= 0.5V/RIOFS This current is add to phase 1 current signal ISEN1 for cur- and the output is latched to be floating. The APW8700 will initials a soft-start process until re-cycle RT/EN or VCC rent balance. Consequently, phase 2 will share more percentage of output current. Connecting a resistor from IOFS pin to VREF generates a current source as: IOFS= (2V-1.5V) /RIOFS This current is add to phase 2 current signal ISEN2 for current balance. Consequently, phase 1 will share more percentage of output current. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW8700. When the junction temperature exo ceeds 150 C, a thermal sensor pulls UGTAEx and LGATEx low, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and regulates the output voltage again after the junction temo o perature cools by 20 C. The OTP is designed with a 20 C hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions increasing the lifetime of the device. OVP The over-voltage protection (OVP) circuit monitors the FB (VFB) voltage to prevent the output from over-voltage. When the V FB rises to 130% of the EAP voltage (V EAP ), the APW 8700 turns off high-side and turn on low-side MOSFETs to sink output voltage (VOUT). As soon as the VFB falls below 110% of V EAP , the OVP comparator is disengaged. The chip will restore its normal operation. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 16 www.anpec.com.tw APW8700 Application Information PWM Compensation The output LC filter of a step down converter introduces a The PWM modulator is shown in figure 8. The input is the output of the error amplifier and the output is the PHASE double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A node. The transfer function of the PWM modulator is given by : compensation network among COMP, FB, and V OUT should be added. The compensation network is shown GAINPWM = in Figure 9. The output LC filters consists of the output inductors and output capacitors. For two-phase convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the transfer function of the LC filter is given by: OSC 1 + s × ESR × COUT 1 s2 × L × COUT + s × ESR × COUT + 1 2 The poles and zero of this transfer functions are: 1 FLC = 1 2× π× L × COUT 2 1 FESR = 2 × π × ESR × COUT PHASE Output of Error Amplifier Driver Figure 8. The PWM Modulator The compensation network is shown in figure 9. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by : the ESR of the output capacitors. V OUT GAINAMP L2=L COUT V PHASE2 PWM Comparator ∆VOSC The FLC is the double-pole frequency of the two-phase LC filters, and FESR is the frequency of the zero introduced by L1=L VIN Driver GAINLC = V PHASE1 VIN ∆VOSC 1 1 // R2 + VCOMP sC1 sC2 = = 1 VOUT R1// R3 + sC3 1 1 s + ×s + R2 × C2 R1 + R3) × C3 ( R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 C1 C2 × × × R3 C3 ESR Figure 6. The Output LC Filter The pole and zero frequencies of the transfer function FLC are: -40dB/dec FZ1 = 1 2 × π × R2 × C2 1 2 × π × (R1+ R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 1 FP2 = 2 × π × R3 × C3 GAIN (dB) FZ2 = FESR -20dB/dec Frequency(Hz) Figure 7. Frequency Resopnse of the LC filters Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 17 www.anpec.com.tw APW8700 Application Information (Cont.) PWM Compensation (Cont.) 5. Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the C1 R3 C3 R2 C2 compensation gain at FP2 with the capabilities of the error amplifier. VOUT R1 FB FP2 = 0.5 X FSW VCOMP FZ2 = FLC VREF Combine the two equations will get the following component calculations: Figure 9. Compensation Network The closed loop gain of the converter can be written as: R3 = R1 FSW −1 2 × FLC C3 = 1 π × R3 × FSW GAINLC X GAINPWM X GAINAMP Figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. FZ1 FZ2 FP1 FP2 GAIN (dB) 1. Choose a value for R1, usually between 1K and 5K. 2. Select the desired zero crossover frequency FO= (1/5 ~ 1/10) X FSW Use the following equation to calculate R2: R2 = ∆VOSC FO × × R1 VIN FLC 20log (VIN/ΔVOSC) FLC 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. FESR Converter Gain PWM & Filter Gain FZ1 = 0.75 X FLC Calculate the C2 by the equation: C2 = Compensation Gain 20log (R2/R1) Frequency(Hz) Figure 10. Converter Gain and Frequency 1 2 × π × R2 × FLC × 0.75 Output Inductor Selection 4. Set the pole at the ESR zero frequency FESR: The duty cycle (D) of a buck converter is the function of FP1 = FESR Calculate the C1 by the following equation: the input voltage and output voltage. Once an output voltage is fixed, it can be written as: C1 = C2 2 × π × R2 × C2 × FESR − 1 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 18 www.anpec.com.tw APW8700 Application Information (Cont.) Output Inductor Selection (Cont.) caused by the AC peak-to-peak sum of the inductor’s current. The ripple voltage of output capacitors can be V D = OUT VIN represented by: For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple currents, ∆IP-P, and af- ∆VESR fects the load transient reponse. Higher inductor value These two components constitute a large portion of the total output voltage ripple. In some applications, multiple reduces the output capacitors’ripple current and induces lower output ripple voltage. The ripple current can be capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support approxminated by: ∆IP - P = VIN - 2VOUT VOUT × FSW × L VIN Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Output Capacitor Selection another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. For getting same load transient response, the output capacitance of two-phase converter only needs around half of output capacitance of single-phase converter. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from overheating. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of low-side MOSFET. Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting output capacitors. Higher The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and larg- performance low ESR capacitors is recommended for switching regulator applications. In addition to high fre- est RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the quency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For two-phase converter, the voltage drop ∆VCOUT and ESR voltage drop ∆V ESR Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 ∆IP − P 8 × COUT × FSW = ∆IP − P × RESR ∆VCOUT = 19 www.anpec.com.tw APW8700 Application Information (Cont.) 2 Input Capacitor Selection (Cont.) Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW RMS current of the bulk input capacitor is roughly calcu- Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) lated as the following equation : where 2 IRMS = I is the load current OUT TC is the temperature dependency of RDS(ON) IOUT × 2D ⋅ (1 - 2D) 2 FSW is the switching frequency tSW is the switching interval For a through hole design, several electrolytic capacitors may be needed. For surface mount design, solid tan- D is the duty cycle Note that both MOSFETs have conduction losses while talum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. MOSFET Selection the high-side MOSFET includes an additional transition loss. The switching interval, t SW , is the function of The APW8700 requires two N-Channel power MOSFETs on each phase. These should be selected based upon the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and RDS(ON), gate supply requirements, and thermal management requirements. can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. In high-current applications, the MOSFET power dissipation, package selection, and heatsink are the domi- Layout Consideration nant design factors. The power dissipation includes two loss components, conduction loss, and switching loss. The conduction losses are the largest component of power dissipation for both the high-side and the lowside MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses since the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltagecurrent transitions and do not adequately model power loss due the reverse-recovery of the low-side MOSFET body diode. The gate-charge losses are dissipated by the APW8700 and don’t heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. For the high-side and low-side MOSFETs, the losses are approximately given by the following equations: Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 20 In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Figure 11. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: www.anpec.com.tw APW8700 Application Information (Cont.) Layout Consideration (Cont.) • Keep the switching nodes (UGATEx, LGATEx, BOOTx, and PHASEx) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, APW8700 V IN1=VIN keep traces to these nodes as short as possible and there should be no other weak signal traces in paralBOOT1 lel with theses traces on any layer. • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers UGATE1 to the MOSFETs (UGATEx and LGATEx) should be short and wide. PHASE1 • Place the source of the high-side MOSFET and the LGATE1 L1 RS1 drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of CSP the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASEx nodes) CSN can get better heat sinking. • For experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. To avoid the noise LGATE2 interference, the current sensing trace should be away from the noisy switching nodes. PHASE2 CS RCSN L O A D RS2 L2 UGATE2 • Decoupling capacitors, the resistor-divider, and boot V OUT capacitor should be close to their pins. (For example, BOOT2 place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible). • The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground should be close to the grounds of the VIN2 =VIN output capacitors and low-side MOSFET. • Locate the resistor-divider close to the FB pin to mini- Figure 11. Layout Guidelines mize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATEx, LGATEx, BOOTx, and PHASEx). Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 21 www.anpec.com.tw APW8700 Package Information QFN4x4-24 D b E A A1 D2 A3 L E2 Pin 1 Corner e QFN4x4-24 S Y M B O L MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 0.30 0.008 2.80 0.098 2.80 0.098 0.45 0.014 MILLIMETERS A3 b 0.20 REF 0.18 D D2 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 0.110 0.157 BSC 0.50 BSC 0.35 0.012 0.157 BSC 4.00 BSC 2.50 e L 0.008 REF 4.00 BSC 2.50 E E2 INCHES 0.110 0.020 BSC 22 0.018 www.anpec.com.tw APW8700 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN4x4-24 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type Unit Quantity QFN4x4-24 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 23 www.anpec.com.tw APW8700 Taping Direction Information QFN4x4-24 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 24 www.anpec.com.tw APW8700 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 25 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8700 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 26 www.anpec.com.tw