PAGE 1 ELAN MICROELECTRONICS CORP. 240 Channel Segment Driver for Dot matrix STN Liquid Crystal Display with Low Voltage Drive EM65H134 Contents 1. General description 2 2. Feature 2 3. Applications 2 4. Pin configurations (package) 3 5. Functional block diagram 4 6. Pin descriptions 5 7. Function description 7 8. Absolute maximum rating 16 9. DC electrical characteristics 18 10. AC electrical characteristics 20 11. Timing diagrams 21 12. Application circuit 22 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 2 ELAN MICROELECTRONICS CORP. GeneralDescription The EM65H134 is a 240-channel segment LCD driver LSI, Which drives a dot matrix STN liquid crystal display at low power. The EM65H134 operates with a low 5V LCD drive voltage and a low 3V logic voltage. The EM65H134 includes shadowing correction circuit in order to improve image quality. The EM65H134 is packaged in a fine pitch slim TCP( slim type carrier package) technology, it is deal for substantially decreasing the size of LCD module frame. Feature - Duty cycle: Up to 1/300 LCD drive voltage: 3.5 to 5.5 V 240 LCD drive circuits Operating voltage: 2.7 to 5.5 V Eight data bits Shift clock speed —25 MHz max/3 V —40 MHz max/5 V - Shadowing correction circuit - Display-off function - Slim-TCP —Output lead pitch: 70μm —User area: 5.5mm - Automatic generation of the chip enable signal - Standby function Applications - PDA - Dictionary - Message display product 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 3 ELAN MICROELECTRONICS CORP. S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . S 239 S 240 S1 PinConfiguration 1----------------------------------------------------------------------------------------------------------------------240 EM65H134 Top View V ML V 0L V 1L V DD DIR EIO1 /DS P OF D I0 D I1 D I2 D I3 D I4 D I5 D I6 D I7 X CK LP FR E IO 2 C C1 C C2 C C3 C C4 VSS V 1R V 0R V MR 267--------------------------------------------------------------------------------------------241 Note: The pin configuration is LSI chip, not TCP. Figure1. Pin configuration 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 4 ELAN MICROELECTRONICS CORP. Functional Block Diagram V0R , V M R , V 1R V 0L , V S1 , S 2 ,......... .................... ........, S239 , S240 ML , V 1L 3 V DD V SS 3 240 bits 3-level driver (Liquid crystal display driver circuit) 240 CC1~CC4 240 Correction circuit /DSPOF 240 LP Line latch circuit 8 FR DI0~DI7 Data shift and arithmetic circuit 8 DIR XCK EIO1 8 8 data latch 8 8 8 8 8 .... Shift register EIO2 Figure 2. Block diagram 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 5 ELAN MICROELECTRONICS CORP. Pin Descriptions Table1 pin description Symbol Pin No. VDD 264 VSS V0R , V0L VMR , VML V1R , V1L DI0 – DI7 XCK 244 266,242 267,241 256,243 260 t0 253 252 LP 251 FR 250 DIR 263 /DSPOF 261 EIO1，EIO 2 262,249 I/O Connected to Functions I Power Supply Power supply for internal logic connects to +2.7 to +5.5V I GND Connect to Ground I Power Supply Power supply for LCD driver level Ensure that the voltage are set such that V1<V M<V 0 , VM=0.5(V 0-V1) I Controller Input for display data input data into 8 pins DI0 – DI7 I Controller Clock signal for taking display data Data is read on the falling of the clock pulse I Controller Latch signal for display data Data is latched on the falling edge of the clock pulse I Controller AC signal for LCD driver Input a frame inversion signal I Controller Directional selection for reading display data DIR Data read direction H S240 to S1 L S1 to S240 I Controller When the signal is low，the output (S 1 – S240) of LCD drive be set to level VM I/O Controller Input/output for chip selection In output state，the output pin must connect to input pin of next EM65H134 In input state，the input pin of the fist EM65H134 must connect to Vss，the other input pin must connect to the output pin of previous EM65H134. DIR EIO 1 EIO 2 H output input L input output 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 6 ELAN MICROELECTRONICS CORP. Table1 pin description (continous) CC1 248 I CC2 247 I CC3 246 I CC4 245 I S1-S240 1 to 240 O Rising crosstalk correction signal.The V1 level output is reset to VM level when CC1 is high. Falling crosstalk correction signal.The V0 level output is reset to VM level when CC2 is high. Waveform distortion non-selected (black) data correction signal.The present output pin (non-selected)and the next output pin (non-selected) are reset to the VM level when CC3 is high. Waveform distortion selected (white) data correction signal.The present output pin (selected)and the next output pin (selected) are reset to the VM level when CC4 is high. LCD driver output. One of two levels is output according to the combination of the FR signal and display data, when /DSPOF is in VDD 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 7 ELAN MICROELECTRONICS CORP. FUNCTIONDESCRIPTIONS - Shift Register The 30-bit shift register generate latch signal for data latch circuit at the falling edge of XCK signal. The shift direction is selected by DIR signal. - Data Latch It latches the data on the 8 bits data bus(DI0 to DI7) and output the data to line latch. It is controlled by shift register. - Line Latch All 240 bits, which have been read into the data latch are simultaneously latched at the falling edge of the LP signal then output to the correction circuit and 3-level driver. - 3-level Driver Drive LCD panel from driver output pins, selecting one of three levels (V0, VM, V1) based on the line latch data, correction circuit(CC1 to CC4) and /DSPOF. -Correction Circuit This circuit corrects the shadowing volume. 1.The circuit compares the crosstalk correction signals (CC1 and CC2) from the external circuits and present output, and determines whether the effective value is increased due to crosstalk. If the effective value is increased, the output level is reset to the VM level. 2.The circuit compares the output data to the next output data. If there are no data changes due to the waveform distortion correction signal (CC3 and CC4), the output level is reset to VM level. The reset period can be adjusted by using CC1 to CC4. The correction needed depends on each output pin. -Data Shift and Arithmetic Circuit The data shifter shifts the destinations of data output when necessary. The arithmetic circuit performs operations for the data and FR signal. LP FR Segment Common Figure 3. FR、LP、output timing 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 8 ELAN MICROELECTRONICS CORP. Relation between FR、latch data、/DSPOF and output level Table 2 LCD driver output voltage level FR Latch data /DSPOF H H H H L H L H H L L H Ｘ Ｘ L VSS≦ V1< V M< V 0 H:VDD Driver output voltage level V0 V1 V1 V0 VM L:V SS Ｘ :Do n ’ t c a r e Relationship between the display data and driver output and data output destination Table 3 Relationship between the display data and driver output DIR EIO1 EIO2 Data Figure of clock Input 1st 2nd 3rd … 28th L Input Output DI0 S8 S16 S24 … S224 DI1 S7 S15 S23 … S223 DI2 S6 S14 S22 … S222 DI3 S5 S13 S21 … S221 DI4 S4 S12 S20 … S220 DI5 S3 S11 S19 … S229 DI6 S2 S10 S18 … S228 DI7 S1 S9 S17 … S227 H Output Input DI0 S233 S225 S217 … S17 DI1 S234 S226 S218 … S18 DI2 S235 S227 S219 … S19 DI3 S236 S228 S220 … S20 DI4 S237 S229 S221 … S21 DI5 S238 S230 S222 … S22 DI6 S239 S231 S223 … S23 DI7 S240 S232 S224 … S24 29th S232 S231 S230 S229 S228 S227 S226 S225 S9 S10 S11 S12 S13 S14 S15 S16 30th S240 S239 S238 S237 S236 S235 S234 S233 S1 S2 S3 S4 S5 S6 S7 S8 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 9 ELAN MICROELECTRONICS CORP. Data output destination The direction of data latch and the chip enable input/output pin can be select by DIR signal. DIR=VSS ,Enable input: EIO1 ,Enable output: EIO2 S1 S2 S3 S4 S5 S6 S7 S8 D7 D6 D5 D4 D3 D2 D1 D0 S233 S234 S235 S236 S237 S238 S239 S240 D7 D6 D5 First data D4 D3 D2 D1 D0 Last data DIR=VDD ,Enable input: EIO2 ,Enable output: EIO1 S1 S2 S3 S4 S5 S6 S7 S8 D0 D1 D2 D3 D4 D5 D6 D7 S233 S234 S235 S236 S237 S238 S239 S240 D0 D1 D2 Last data D3 D4 D5 D6 D7 First data Figure 4. Data output destination Operating timing Figure 4 shows the 8-bit data -latch timing when DIR=GND; that is, when the EIO1 pin is a chip-enable input and the EIO2 pin is a chip-enable output. When SHL=V cc, the EIO1 pin is a chip-enable output and the EIO2 pin is a chip-enable input. When a low chip-enable signal is input via the EIO1 pin, the EM65H134 is first released from the data-standby state, then, at the falling edge of the following XCK pulse, it is released entirely from the standby state and starts latching data. It simultaneously latches eight bits of data at the falling edge of each XCK pulse. When it has latched 232 bits of data, it sets the EIO2 signal to low. When it has latched 240 bits of data, it automatically stops and enters the standby state, initiating the next EM65H134, provided its EIO2 pin is connected to the EIO1 pin of the next EM65H134. The EM65H134 output one line of data from the S1 to S240 pins at the falling edge of each LP pulse. Data d1 is output from S1, and d240 from S240 when SHL=GND, and d1 is output from S240, and d240 from S1 when DIR= Vcc. 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 10 ELAN MICROELECTRONICS CORP. DIR=VSS Line LP XCK 1 DI0 2 3 29 30 31 d8 d16 d240 d1 d9 d233 299 300 301 DI7 EI (NO.1) EO (NO.1) EO (NO.2) EO (NO.3) NO.1 latch data NO.2 latch data NO.3 latch data EO (NO.10) NO.10 latch data S1~S240 Figure 5. Data latch timing 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 11 ELAN MICROELECTRONICS CORP. Correction circuit The EM65H134 include shadowing correction circuits. There are two types of shadowing: one caused by crosstalk, and the other by waveform distortion. In both types, image quality can be improved by correction circuits CC1, CC2, CC3, and CC4. (1) CC1 and CC2(Shadowing caused by crosstalk) (a) (b) Corresponding sections FR waveform at (a) (Normally black panel) white white waveform at (b) showing section whiteblackblack white white black black white SEG COM SEG COM Figure 6. Shadowing caused by crosstalk When a ruled line is displayed, noise occurs in the common VM level in the LCD panel due to the segment change of a solid background in FR reverse. This is because many segments display the solid background and are simultaneously changed, affecting the common VM level (creating crosstalk). The effective voltage for section (a) in the solid background becomes low. On the other hand, the effective voltage for section (b) becomes high. Shadowing occurs in the corresponding sections due to the different voltages. The EM65H134s compare the crosstalk correction signals CC1 and CC2 and the present output, and determine whether the effective value is increased by the crosstalk. If increased, the output level is reset to the VM, which corrects the effective voltages in (a) and (b) and suppresses the shadowing. Figure 8 shows an example of the crosstalk-correction-signal external circuit. The basic potentials of a comparator (VM+△V and VM－△V’) are corrected according to the shadowing level for output correction while CC1 and CC2 are high. CC1 corrects the rising crosstalk, and CC2 corrects the falling crosstalk. 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 12 ELAN MICROELECTRONICS CORP. Waveform in section(b) Waveform in section(a) Before correction After correction Effective voltage decreased VM VM SEG waveform SEG waveform SEG waveform SEG waveform VM+ V VM VM VM- V' Effective voltage correction CC1 Effective voltage increased CC2 Figure 7. Effective voltage correction Comparator VM+ V CC1 VM power supply Power supply circuit VM- V' CC2 Figure8. CC1 and CC2 external circuit 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 13 ELAN MICROELECTRONICS CORP. (2) CC3 and CC4(shadowing caused by waveform distortion) (a) Corresponding sections (b) (Normally black panel) black waveform at (a) white black FR reversed white black white waveform at (b) white COM SEG SEG COM black Figure 9. Shadowing caused by waveform distortion When the background is displayed in grayscale (for example, in a checker pattern), many segment levels are changed in section (a) but not in section (b). The effective voltage for section (a) becomes low because distortion occurs in the segment output waveform due to driver or panel impedance. On the other hand, the effective voltage for section (b) becomes high because the waveform is changed only slightly. Shadowing occurs in the corresponding sections due to the different voltages. The EM65H134 compare the present output data and the next output data. If the data is not changed, the output level is reset to the VM, which corrects the effective voltages in (a) and (b). The high width is corrected according to the shadowing level for output correction while CC3 and CC4 are high. CC3 corrects the non-selected output pin (black background), and CC4 corrects the selected output pin (white background). 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 14 ELAN MICROELECTRONICS CORP. Waveform in section(b) Waveform in section(a) Before correction After correction Effective voltage decreased VM VM SEG waveform SEG waveform SEG waveform SEG waveform VM VM Effective voltage correction CC3 VM SEG waveform CC4 Figure 10. Effective voltage correction by waveform distortion 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 15 ELAN MICROELECTRONICS CORP. FR M n-1 M n+1 M n LP XCK DI0~DI7 m-1 m n-4 n-3 n-2 n-1 n * * * last data * : invalid CC1 CC2 CC3 CC4 Data Latch (m) Line Latch ( M n - 1) current output data (m) ( M n - 1) current output data Compared result for correctioncircuit (( m ) ( M n - 1)) (n) ( M n ) next output data (n) ( M n ) next output data ((n) ( M n )) c a l c u l a t e r e s u l t Segment output: (a)V1 reset (V1->VM) (m) ( M n - 1) current output data (b)V0 reset (V0->VM) (m) ( M n - 1) current output data (c)V0 reset (V0->VM) (m) ( M n - 1) current output data (d)V1 reset (V1->VM) (m) ( M n - 1) current output data VM VM VM VM (n) ( M n ) next output data (n) ( M n ) next output data (n) ( M n ) next output data (n) ( M n ) next output data VM reset (correction) Figure 11. Compared result for correction circuit The correction circuit compares the present output data (line latch) and the next output data (data latch). Depending on the compared result, the circuit resets the high width of CC3 to the VM for the output without a data change if the data is the non-selected output ((c) in figure 12). The circuit resets the high width of CC4 to the VM if the data is the selected output ((d) in figure 12). CC3 and CC4 are input after the last valid data is transferred. CC1 forcibly resets the V1 output to for the high width ((a) in the figure 12). CC2 forcibly resets the V0 output to VM for the high width ((b) in figure 12). Therefore, shadowing caused by waveform distortion is corrected with CC3 or CC4 (non-selected or selected), and shadowing caused by crosstalk is corrected with CC1 or CC2 (in the V0 or V1 direction). Note: The high period from CC1 to CC4 should be matched with the shadowing level. 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 16 ELAN MICROELECTRONICS CORP. Absolute Maximum ratings Table 4 absolute maximum ratings Parameter Symbol Condit ions Applicable pins Ratings Unit Supply voltage (1) VDD Referenced VDD *1,*2 -0.3 to +7.0 V to Supply voltage (2) V0 V0L, V0R *1,*2 -0.3 to +7.0 V V (0V) Input voltage(1) VI1 XCK, LP,DIR,FR, EIO 1 , -0.3 to VDD+0.3 V SS EIO2 , DI0-7,/DSPOF, CC1 to CC4 *1 Input voltage(2) VI2 VML,VMR,V1L,V1R *1,*2 -0.3 to V0 +0.3 V Operating temperature Topr -30to +75 ℃ Storage temperature Tstg -55 to +110 ℃ Note：1. if the LSI is used beyond the above maximum ratings, it may be permanently damaged. It should always be used within it’s specified operating range for normal operation to prevent malfunctions or degraded reliabilility. 2. As show in figure11, user should conform to the following turn on/off sequence for the power and signal. Otherwise, the LSI will malfunction or will be permanently damaged. In addition, the LSI reliability will be affected. VDD 2.7 V 2.7 V /DSPOF V0 0 ms 0 ms 0 ms 0 ms VM VM V1 V1 0 ms 0 ms input-signal colck data signal-undefined initialization period period (at least one frame) ( 0 ms : minimun specification ) Figure 12. Turn on/off timing 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 17 ELAN MICROELECTRONICS CORP. 3. Turn on the power: (1) Turn on the power in the order of GND-VDD, GND-V0, and VM/V1. THEN ground the /DSPOF pin. (2) The LCD forcibly outputs the VM level by the DISPLAYOFF function. (3) Even an input signal disturbed immediately after VDD is applied, the DISPLAYOFF function has priority. (4) Input the specific signal to initialize the registers in the driver. The initialization period must be at lease one frame. (5) The preparation for the normal display is completed. Apply the VDD level to the /DSPOF pin to cancel the DISPLAYOFF function. At this time, the level of pin V0, VM and V1 must rise to the specific potential. 4. Turn off the power: The procedure is basically the reverse of that used to turn on the power. (1) Ground the /DSPOF pin. (2) Turn off the LCD power in the order of VM/V1 and GND-V0. (3) Ground VDD and an input signal. At this time, the level of pin V0, VM and V1 must fall to 0V. Since the DISPLAYOFF function stops when VDD fall to 0V, the LCD may output a level other than VM. Therefore, a display failure may occur when the power is turn off or on. 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 18 ELAN MICROELECTRONICS CORP. DC CHARACTERISTICS Table 5 DC characteristics 1 (VSS = GND=0V, VDD = +2.7 to +4.5V, V0 -Vss= 3.5 to 5.5V, Ta = -30~+75°C) Parameter Input voltage Output voltage Input leakage current (1) Symbol VIH VIL Conditions VOH IOH=-0.4mA VOL IIL1 IOL=+0.4mA VI =VDD - VSS IIL2 VI =V0 - VSS Input leakage current (2) Output resistance R ON *1 Stand-by current Consumed current Consumed current ISTB *2 *3 IDD *2 *3 I0 *2 Applicable pins Min DI0 -DI7, XCK, 0.7VDD LP,DIR,FR,EIO 1, 0 EIO 2, /DSPOF, CC1 to CC4 EIO 1, EIO 2 VDD-0. 4 Type V0R,VOL Y1- Y240 VMR,VML V1R,V1L VI = V DD VDD=3V VDD fXCK=25MHZ VI = Vss fLP=100KHZ VDD fFR =4kHZ V0L, V 0R Unit V V V +0.4 +5 V uA +100 uA 0.5 1.0 0.5 0.4 1.0 2.0 1.0 1.0 kΩ 1.0 6.0 mA 0.4 1.0 mA DI0 -DI7, XCK, LP, -5 DIR, FR, MD, EIO1, EIO 2, /DSPOF VML,VMR ,V1L,V1R -100 ION = 150uA Max VDD 0.3VDD mA Table 6 DC characteristics 2 (VSS =GND= 0V, VDD = 4.5V to 5.5V, V0 -Vss= 3.5 to 5.5V, Ta = -30~+75°C) Parameter Symbol Input voltage VIH VIL Output voltage Input leakage current (1) Input leakage current (2) Output resistance Stand-by current Consumed current Consumed current Conditions VOH IOH=-0.4mA VOL IIL1 IOL=+0.4mA VI=VDD - VSS IIL2 VI=V0 - VSS RON *1 ION = 150uA ISTB *2 *3 IDD *2 *3 I0 *2 Applicable pins Min DI0 -DI7, XCK, 0.7VDD LP,DIR,FR,EIO 1, 0 EIO 2, /DSPOF, CC1 to CC4 EIO 1, EIO 2 VDD-0. 4 Type Unit V V V +0.4 +5 V uA +100 uA 0.5 1.0 0.5 1.0 1.0 2.0 1.0 2.0 kΩ 3.0 15 mA 0.4 2.0 mA DI0 -DI7, XCK, LP, -5 DIR, FR, MD, EIO1, EIO 2, /DSPOF VML,VMR ,V1L,V1R -100 V0R,VOL Y1- Y240 VMR,VML V1R,V1L VI = V DD VDD=5V VDD fXCK=40MHZ VI = Vss fLP=160KHZ VDD fFR =6kHZ V0L, V 0R Max VDD 0.3VDD mA 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 19 ELAN MICROELECTRONICS CORP. Note : 1. Indicate the resistance between one of thwe pins Y1~Y240 and one of the voltage supply pins,when load current is applied to the Y pins. Defined under the following conditions: V0-Vss = 5.5V; VM = (V0=V1)/2; V1 = Vss+1 V1 should be near the ground level, VM should be near the middle voltage between V1 and V0. V1should be within the range of △V = 2.5V0, which is the range within which RON, the LCD driver circuit’s output impedance, is stable. See figure 13 2. Input and output are excluded. When a CMOS input is left floating, excess the current flows from the power supply through the input circuit. To avoid this, VIH and VIL must be used at VDD and Vss, respectively. 3. VI = enable input,. When DIR = Vss, VI = EIO1. When DIR = VDD , VI = EIO2 4. The voltage of each signal is show in figure 14 V0 VM V = 0.25 V0 V1 GND Figure 13.Relationship between driver output waveform and each level voltage Segment voltage Segment waveform Common voltage Common waveform VH(38.0V) V 0(5.0V) V DD ( 3 . 3 V ) VM(3.0V) V DD ( 3 . 3 V ) VM(3.0V) V1(1.0V) GND(0.0V) GND(0.0V) VL(-32.0V) Normal display period displayoff period Normal display period displayoff period Figure 14. Signal voltage 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 20 ELAN MICROELECTRONICS CORP. AC Electrical characteristic Table 7 AC electrical characteristics 1 (VSS = GND=0V, VDD = 2.7 to 4.5V, V0 -Vss= 3.5 to 5.5V, Ta = 30~75°C) Parameter Symbol Condition Min Typ Max Unit Shift clock period Shift clock “H” pulse width Shift clock “L” pulse width Data setup time Data hold time Latch pulse “H” pulse width Shift and latch clock set up time Shift and latch clock hold time Shift and latch clock rise time Shift and latch clock fall time FR set up time FR hold time Output delay time CC setup time CC hold time TWCK TWCKH TWCKL TDS TDH TWLPH TS 40 15 15 10 10 30 20 TH TR TF TFS TFH TD TCCS TCCH 50 ns ns ns ns ns ns ns 30 30 20 20 CL=100pF 500 20 20 ns ns ns ns ns ns ns ns Table 8 AC electrical characteristics 2 (VSS =GND= 0V, VDD = 4.5 to 5.5V, V0 -Vss= 3.5 to 5.5V, Ta = 30~75°C) Parameter Symbol Condition Min Typ Max Unit Shift clock period Shift clock “H” pulse width Shift clock “L” pulse width Data setup time Data hold time Latch pulse “H” pulse width Shift and latch clock set up time Shift and latch clock hold time Shift and latch clock rise time Shift and latch clock fall time FR set up time FR hold time Output delay time CC setup time CC hold time TWCK TWCKH TWCKL TDS TDH TWLPH TS 25 10 10 6 6 25 20 TH TR TF TFS TFH TD TCCS TCCH 50 ns ns ns ns ns ns ns 20 20 20 20 CL=100pF 500 20 20 ns ns ns ns ns ns ns ns NOTES: 1. The load must be less than 10 pF between the EIO1 and EIO2 connections of the EM65H134s. 2. connect the load circuit as shown in figure 15. Test point 100 pF Figure 15. Load circuit for output delay time 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 21 ELAN MICROELECTRONICS CORP. Timing diagram TR TF T W CKH T WCKL T W CK 0.7 V DD XCK 0.3 V DD T DS T DH 0.7 V DD DI0~DI7 0.3 V DD 0.7 V DD FR 0.3 V DD T FS T FH T WLPH 0.7 V DD LP 0.3 V DD TS TH XCK 0.7 V DD LP 0.3 V DD TD 0.8 V 0 S (n) 0.2 V 1 0.7 V DD LP 0.3 V DD LAST FIRST XCK T CCH CC3 CC4 T CCS 0.3 V DD 0.3 V DD Correct the waveform by CC3 and CC4 after XCK fetches the last data. Complete correction before data from the next line is output at the falling edge of LP. Figure 16. AC characteristics 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 PAGE 22 ELAN MICROELECTRONICS CORP. Applicationcircuit D IR EIO1 VLC DL ,R GN D VEEL, R VEO VD D 320 * 3 *240 S240 ~ S1 DIR EM65H134 EIO2 EM65H134 DIR EIO1 (N0. 4) correction circuit Figure 17. Application circuit 本資料所有權屬義隆電子股份有限公司, 非經書面准許不可翻印複印或轉變其他任何形式° ALL RIGHTS STRICTLY RESERVED, ANY PORTION IN THIS PAPER SHALL NOT BE REPRODUCED, COPIED WITHOUT PERMISSION. 文件格式管制版次：1.2 試行版/發行日：2001/ 7/16 Seg 958 Seg 959 Seg 960 EIO1 C C1~ CC4 /DSPOF D 0~ D7 FR XC K LP ~ EM65H134 EIO2 V1L ,R VML ,R V0L ,R VDD GND C C1~ CC4 /DSPOF D 0~ D7 FR XC K LP (N0. 2) V1L ,R VML ,R V0L ,R VDD GND V1L ,R VML ,R V0L ,R VDD GND Power supply circuit VDD DIR EIO1 C C1~ CC4 /DSPOF D 0~ D7 FR XC K LP (N0. 1) ----------------------------- S240 ~ S1 VDD EIO2 Seg 721 Seg 722 Seg 723 ~~~~~~~~~~~~~~~~~ S240 ~ S1 VDD LCD controller ----------------------------- Seg 478 Seg 479 Seg 480 Seg 241 Seg 242 Seg 243 ----------------------------- Seg 238 Seg 239 Seg 240 1/240 Duty Seg 1 Seg 2 Seg 3 C2 C1 LCD Panel C1 ~ C240 EIO2 LP CLP /RST /DSPOF AMP M/S /DOC FR FRS0~FRS4 VHL,R VML,R VLL,R