ETC HD66339

HD66339 (TFT Driver)
64-level Grayscale Driver with 480 Outputs for the TFT
Liquid Crystal Display for SXGA and UXGA Systems
ADE-207-332(Z)
Rev.1.0
Nov. 2001
Description
The HD66339 is a TFT driver LSI suitable for UXGA systems (ten HD66339s used). It receives 6-bit-perpixel digital display data, and generates and outputs voltages for 64 grayscales. The output circuit includes
an operational amplifier and is capable of alternating outputs of positive-polarity and negative-polarity
voltages on individual output pins. This results in a high-quality display with minimal crosstalk.
The effective output voltage deviation is limited to about ±2 mV by incorporating the original chopper-type
amplifier circuit.
Features
• High-speed operation
 Operating clock: 55 MHz (Vcc = 2.7 to 3.6 V) and 45 MHz (Vcc = 2.3 to 2.7 V)
• Operational power-supply voltage range
 VCC = 2.3 to 3.6 V
 VLCD = 6.5 to 10.0 V
• LCD drive voltage
 Low-voltage side: GND + 0.1 to VLCD/2 (V)
 High-voltage side: VLCD/2 to VLCD - 0.1 (V)
• 480 LCD drive circuits
• Output voltage deviation
 ±2 mV (effective value)
HD66339
• Multicolor display
 The HD66339 receives 6-bit-per-pixel digital display data, and selects and outputs a display voltage
from 64 grayscale voltages, enabling a maximum of 260,000 display colors when using R/G/B color
filters.
• 36 data bits (6 grayscale code bits × 3 RGB dots × 2 pixels)
• Dot inversion drive
 The voltage can be alternated between positive polarity and negative polarity on individual output
pins, allowing a dot-by-dot inversion drive even with a single-sided layout configuration. This
provides a high-quality display with minimal crosstalk. Also, since both positive-polarity and
negative-polarity voltages are generated by an externally provided reference power supply, either an
asymmetric or a symmetric drive can be used according to the characteristics of the liquid crystal.
• N-raster-row inversion drive
 The polarity can be inverted by each N-raster-rows. The charge or discharge current under the TFT
load can be lowered and flicker on the specific display can be reduced.
• Chopper-type operational amplifier
 The output circuit includes an operational amplifier, which enables the external reference power
supply circuit to be configured using only resistance ladders. In addition, use of the chopper-type
amplifier eliminates output voltage deviations between frames and ensures high-quality displays.
• Bidirectional shift
• Chip-enable signal generation circuit
• Package
 TCP (customized package dimensions)
• Supported systems
 SXGA (1280 × 1024 dot) , UXGA (1600 × 1200 dot) notebook PCs, monitors, and other OA
equipment
2
HD66339
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y480
Y479
Y478
Y477
Y476
Y475
Y474
Y473
Y472
Pin Arrangement
The TCP package dimensions are
not standardized.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Top View
1
2
3
4
5
6
7
8
9
10
EIO2
D55
D54
D53
D52
D51
D50
D45
D44
D43
11
12
13
14
15
16
17
18
19
20
D42
D41
D40
D35
D34
D33
D32
D31
D30
VCC
21
22
23
24
25
26
27
28
29
30
SHL
TESTIN
TESTOUT
V9
V8
V7
V6
V5
VLCD
GND2
31
32
33
34
35
36
37
38
39
40
V4
V3
V2
V1
V0
GND1
TESTCLK
CL2
CL1
M
41
42
43
44
45
46
47
48
49
50
POL1
POL2
D25
D24
D23
D22
D21
D20
D15
D14
51
52
53
54
55
56
57
58
59
60
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
61 EIO1
Note: The TESTIN, TESTOUT, and TESTCLK pins need not be available outside the TCP.
Figure 1 Pin Arrangement
3
HD66339
Internal Block Diagram
CL2
EIO1
Clock control
EIO2
M
SHL
CL1
D55 to D50, D45 to D40, Data
D35 to D30, D25 to D20, inversion
D15 to D10, D05 to D00 circuit
Latch address selector
6 planes
480 latch circuits (1)
POL1
POL2
VLCD
VCC
GND
V5 to V9
480 latch circuits (2)
Grayscale voltage
generation
V0 to V4
6 planes
64 positive-polarity
grayscales
480 decoders
64 negative-polarity
grayscales
480 output amplifier circuits
Y1Y2Y3Y4
Y480
Figure 2 Block Diagram
1. Clock control unit
Generates the chip-enable signals (EIO1, EIO2) and controls internal timing signals.
2. Data inversion circuit
Uses the POL1 and POL2 signals to perform polarity inversion (at high levels) or non-inversion (at low
levels) processing of input display data.
3. Latch address selector
Generates latch signals for sequentially latching the input display data.
4. Latch circuits (1)
480 × 6-bit latch circuits that sequentially latch 6-output × 6-bit input display data.
5. Latch circuits (2)
Performs latching, in synchronization with CL1, of the 480 × 6-bit data latched by latch circuits (1).
4
HD66339
6. Decoders
Decodes the 6-bit data and selects the liquid-crystal application voltages.
7. Grayscale voltage generation unit
Performs resistance-division of the external input voltage, and generates 64 positive-polarity grayscales
and 64 negative-polarity grayscales.
8. Output amplifier circuits
Outputs the grayscale voltage that has been selected for each output and buffered in the operational
amplifier.
5
HD66339
Pin Functions
Table 1 Pin Functions
Signal
Name
Quantity
Input/Output
Function
VLCD
1
Power supply
VLCD – GND: Driver-circuit power supply
VCC – GND: Logic-circuit power supply
VCC
1
Power supply
Attach the path capacitor to each IC as showed below to
stabilize a power supply voltage.
GND
2
Power supply
VLCD
1 µF
0.1 µF
VCC
GND
V9 to V5
5
Power supply
Reference power supply for generating the liquid-crystal
application voltage. Supply a voltage in the range VLCD/2
to VLCD - 0.1 to pins V0–V4, and a voltage in the range
GND + 0.1 to VLCD/2 to pins V5–V9.
V4 to V0
5
CL1
1
Input
Data of one raster-row is transferred to the latch when the
high level of this clock is latched at the CL2 rising edge, and
the liquid-crystal application voltage is output at the CL1
falling edge. The output during the high level is in the highimpedance state. One pulse must be input for each
horizontal period.
CL2
1
Input
Display data is latched at the rising edge of this clock.
After the start pulse input, the start pulse output goes high
at the rising edge of the 80th clock, and this becomes the
start pulse of the next-stage driver. The 81st clock of the
first-stage driver is the start-pulse latch clock of the nextstage driver.
After the start pulse input, display data latching is halted
automatically after 82 clock pulses are input.
At least two CL2 clocks must be input during the high-level
period of CL1.
POL1
2
Input
Data-polarity inversion signal to reduce power consumption
of data bus lines in the interface.
When POL1/POL2 is high, display data is inverted in the
driver.
When POL1/POL2 is low, display data is input without
being inverted in the driver.
POL1: D0j to D2j control, POL2: D3j to D5j control
36
Input
Inputs 6-bit (grayscale data) × 6-pixel display data.
POL2
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
6
Di0 is the LSB, and Di5 the MSB.
HD66339
Table 1 Pin Functions (cont)
Signal
Name
Quantity
Input/Output
Function
EIO1
2
Input/output
Chip-enable signals. Input/output switching is controlled by
the SHL signal. When these signals are used as inputs,
display data latching is performed when the input goes high.
When these signals are used as outputs, a low-to-high
transition is made at the rising edge of the 80th pulse of the
CL2 signal, and the next-stage driver is activated.
EIO2
SHL
VCC
GND
M
1
Input
EIO1
Input
Output
EIO2
Output
Input
Current-alternating signal, controlling liquid-crystal alternate
current drive. The M signal is input after provision of a setup
time with respect to the rise of the CL1 signal. Positivepolarity (V0–V4) and negative-polarity (V5–V9) output
voltages are generated as shown below according to the
polarity of the latched M signal.
M Odd output pins (Y1,Y3,...,Y479)
Even output pins (Y2,Y4,...,Y480)
0
Positive-polarity liquid-crystal
application voltage is output
Negative-polarity liquid-crystal
application voltage is output
1
Negative-polarity liquid-crystal
application voltage is output
Positive-polarity liquid-crystal
application voltage is output
Y1 to Y480
480
Output
Signal lines for output of liquid-crystal application voltages.
SHL
1
Input
Controls display-data shift direction.
LAST
VCC
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
1ST
1ST
GND
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
LAST
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
D55 to D50
D45 to D40
D35 to D30
D25 to D20
D15 to D10
D05 to D00
Y480
Y479
Y478
Y477
Y476
Y475
Y6
Y5
Y4
Y3
Y2
Y1
Y480
Y479
Y478
Y477
Y476
Y475
Y6
Y5
Y4
Y3
Y2
Y1
7
HD66339
Table 1 Pin Functions (cont)
Signal Name
Quantity
Input/Output
Function
TESTCLK
1
Input
Input pin for test signal. The TESTCLK pin is
connected to GND in normal operation. It is possible to
connect the TESTCLK pin to a neighboring GND on the
TCP. The TESTCLK pin cannot be left open because it
is not pulled down.
TESTIN
1
Input
Input pin for test signal. The TESTIN pin should be left
open because it is pulled down to GND. The TESTIN
pin is not normally extended to a pin of the TCP
package.
TESTOUT
1
Output
Output pin for test signal. Leave this pin open.
The TESTOUT pin is not normally extended to a pin of
the TCP package.
8
HD66339
System Overview
Figure 3 is a block diagram of the configuration of an UXGA (1600 × 1200) compatible TFT color panel
with the HD66339s. The HD66339 latches 6-bit data for each dot, selects a level from the 64 positivepolarity or negative-polarity liquid-crystal application voltages generated internally, and outputs that
voltage.
Display data (6 bits X 6 pixels)
Liquid-crystal drive power
HD66339 control signals
supply (V9 to V0)
Scan driver control
signals (FRM, CL3)
1200
(CL1, CL2, M, EIO)
Scan driver
Controller
By configuring pixels using R/G/B color filters, a full-color display of approximately 260,000 colors can be
achieved. In addition, use of the pin-by-pin output inversion function allows row-by-row inversion drive
and dot-by-dot inversion drive even with a single-sided HD66339 arrangement, enabling a high-quality
display.
HD66339
NO.1
HD66339
NO.2
HD66339
NO.8
384
384
384
RGB
TFT color panel
260,000 colors, 1600 X 1200 dots
Scan driver voltages (VGON, VGOFF)
Counter-electrode
voltage (VCOM)
Liquid-crystal
driver power
supply circuit
Figure 3 System Block Diagram
9
HD66339
CL1
CL2
1 2 3
801
1 2 3
EIO
6-bit X 6-dot
digital data
1
2 3
801
One frame period
FRM
1 One horizontal
1200
period
CL1
HV64
(V0 to V4)
LV64
(V5 to V9)
HV64
Y1
HV64
Odd pins
LV64
LV64
LV64
LV64
HV64
HV64
HV64
HV64
Y480 Even pins
LV64
LV64
Note: HV64 indicates 64 high-voltage grayscales.
LV64 indicates 64 low-voltage grayscales.
Figure 4 Timing Chart (Example of a Dot-inversion Drive System)
10
HD66339
Operation Timing
When SHL = Vcc
1 line
1
2
3
80
81
82
83
799
800
801
CL2
2 tcyc (min.)
EIO1
CL1
1 tcyc (max.)
POL1, 2
Dij
1 tcyc
INVALID
799
Final data
800
INVALID
Blanking
period
INVALID
1
2
79
80
81
82
1
2
798
799
800
Final data
First next-line data
2 tcyc (min.)
INVALID
1
2
3
Blanking
period
First next-line data
2 tcyc (min.)
IC (NO. 1) data latch
IC (NO. 2)
IC (NO. 10)
EIO2
(NO. 1)
EIO2
(NO. 10)
Y1 to Y 480
Figure 5 Operation Timing
The high level of the enable-input signal (when SHL = V CC: EIO1) is latched at the rising edge of the datalatch clock signal CL2, and data latching begins after one CL2 signal cycle. Data of 6 bits × RGB × 2
pixels, i.e. 6 outputs are simultaneously latched at the rising edge of the CL2 signal. At the rising edge of
the 80th clock pulse of the CL2 signal, the enable-output signal (when SHL = VCC: EIO2) is driven high,
and the operation is automatically halted (the standby state is entered) when latching of data for 480 outputs
is completed. By connecting the EIO2 pin to the next-stage EIO1 pin, the next-stage IC is activated in the
same way.
The data-latch clock signal CL2 does not require a clock-halted period. Two-clock period (min.) after
final-data input in one horizontal period is a blanking period, and data input is invalid in this period. At
least two clocks of the CL2 signal must be input during the high-level period of the CL1 signal.
11
HD66339
M Signal and Data Input
This example shows the relationship between the data input, M signal, and output level, with dot-by-dot
inversion and frame inversion. The HD66339 driver must hold the M signal during the high-level period of
CL1. The grayscale-voltage selection circuits for high and low voltages are operated according to the M
signal level at the rise of CL1, and the grayscale voltages are output at the following falling edges of CL1.
To provide stable output operation of the buffer amplifier, the output is placed in the high-impedance state
in the high-level period of CL1.
Frame 1
Frame 2
Line
1
2
3
LAST-2 LAST-1 LAST
1
2
3
CL1
M
EIO
(Start pulse)
Display
data
Line 1 data Line 2 data Line 3 data
Last-1 line
data
Last line
data
Line 1 data Line 2 data
Line 3 data
High / low
voltage
selection
signal
(internal
operation)
Odd
output pins
Even
output pins
HV
HV
HV
LV
HV
LV
HV
LV
LV
LV
HV
LV
Note: HV indicates 64 high-voltage grayscales.
LV indicates 64 low-voltage grayscales.
Figure 6 Relationship between the M Signal and Data Input
12
HD66339
Pin-by-Pin Inversion Drive
The HD66339 can generate 64-level positive-polarity and negative-polarity grayscale voltages with respect
to the inverted reference voltage for individual adjacent odd and even output pins. In addition, the liquidcrystal alternate current drive can be controlled by switching the polarity of the M signal. (See the Pin
Functions section.)
In this way, when HD66339s are arranged on either the upper or lower side of a TFT LCD panel, a dot
inversion drive can be performed in which grayscale voltages of different polarity are applied to individual
adjacent dots by switching the M signal on each CL1 clock, reducing the crosstalk which adversely affects
image quality, and so achieving a high-quality display.
Odd frames
Even frames
HD66339
HD66339
Gate driver
HD66339
Gate driver
HD66339
Figure 7 Dot Inversion Drive
When the M signal switches on each CL1n clock, the following n-raster-row inversion drive can be used on
each horizontal dot and vertical n-raster-row.
Odd frames
HD66339
HD66339
HD66339
Gate driver
Gate driver
HD66339
Even frames
Figure 8 N-raster-row Inversion Drive
13
HD66339
When the M signal switches on each FLM signal, the following frame inversion drive can be used on each
horizontal dot and vertical frame.
Odd frames
HD66339
HD66339
Gate driver
Gate driver
HD66339
Even frames
Figure 9 Frame Inversion Drive
14
HD66339
HD66339
Display Data and Output Voltage
With input of a 10-level liquid-crystal power supply and 6-bit digital data, the HD66339 outputs 64
grayscale voltage levels on the high-voltage side and 64 grayscale voltage levels on the low-voltage side.
The relationship between the input voltages of the liquid-crystal power supply, digital codes, and output
voltages is shown below.
Y1
V0
Power supply
circuit
64 positivepolarity levels
HD66339
Dynamic range:
max. 9.8 V
V9
Y480
64 negativepolarity levels
Display data
(6-bit digital data)
Figure 10 Selection of the LCD Drive Output Level
15
HD66339
Table 2 64 High-Voltage Grayscales
Display Data
Di5
Di4
Di3
Di2
Di1
Di0
64 High-voltage
Grayscale Levels
1
1
1
1
1
1
V4
1
1
1
1
1
0
V4+(V3–V4)X340/4260
1
1
1
1
0
1
V4+(V3–V4)X680/4260
1
1
1
1
0
0
V4+(V3-V4)X1020/4260
1
1
1
0
1
1
V4+(V3-V4)X1360/4260
1
1
1
0
1
0
V4+(V3-V4)X1680/4260
1
1
1
0
0
1
V4+(V3-V4)X1990/4260
1
1
1
0
0
0
V4+(V3-V4)X2290/4260
1
1
0
1
1
1
V4+(V3-V4)X2580/4260
1
1
0
1
1
0
V4+(V3-V4)X2850/4260
1
1
0
1
0
1
V4+(V3-V4)X3110/4260
1
1
0
1
0
0
V4+(V3-V4)X3360/4260
1
1
0
0
1
1
V4+(V3-V4)X3600/4260
1
1
0
0
1
0
V4+(V3-V4)X3830/4260
1
1
0
0
0
1
V4+(V3-V4)X4050/4260
1
1
0
0
0
0
V3
1
0
1
1
1
1
V3+(V2-V3)X200/2765
1
0
1
1
1
0
V3+(V2-V3)X380/2765
1
0
1
1
0
1
V3+(V2-V3)X555/2765
1
0
1
1
0
0
V3+(V2-V3)X730/2765
1
0
1
0
1
1
V3+(V2-V3)X905/2765
1
0
1
0
1
0
V3+(V2-V3)X1075/2765
1
0
1
0
0
1
V3+(V2-V3)X1245/2765
1
0
1
0
0
0
V3+(V2-V3)X1415/2765
1
0
0
1
1
1
V3+(V2-V3)X1580/2765
1
0
0
1
1
0
V3+(V2-V3)X1745/2765
1
0
0
1
0
1
V3+(V2-V3)X1910/2765
1
0
0
1
0
0
V3+(V2-V3)X2075/2765
1
0
0
0
1
1
V3+(V2-V3)X2245/2765
1
0
0
0
1
0
V3+(V2-V3)X2415/2765
1
0
0
0
0
1
V3+(V2-V3)X2590/2765
1
0
0
0
0
0
V2
16
HD66339
Table 2 64 High-Voltage Grayscales (cont)
Display Data
Di5
Di4
Di3
Di2
Di1
Di0
64 High-voltage
Grayscale Levels
0
1
1
1
1
1
V2+(V1-V2)X180/4140
0
1
1
1
1
0
V2+(V1-V2)X370/4140
0
1
1
1
0
1
V2+(V1-V2)X570/4140
0
1
1
1
0
0
V2+(V1-V2)X780/4140
0
1
1
0
1
1
V2+(V1-V2)X1000/4140
0
1
1
0
1
0
V2+(V1-V2)X1230/4140
0
1
1
0
0
1
V2+(V1-V2)X1470/4140
0
1
1
0
0
0
V2+(V1-V2)X1720/4140
0
1
0
1
1
1
V2+(V1-V2)X1980/4140
0
1
0
1
1
0
V2+(V1-V2)X2250/4140
0
1
0
1
0
1
V2+(V1-V2)X2530/4140
0
1
0
1
0
0
V2+(V1-V2)X2830/4140
0
1
0
0
1
1
V2+(V1-V2)X3150/4140
0
1
0
0
1
0
V2+(V1-V2)X3480/4140
0
1
0
0
0
1
V2+(V1-V2)X3810/4140
0
1
0
0
0
0
V1
0
0
1
1
1
1
V1+(V0-V1)X370/7670
0
0
1
1
1
0
V1+(V0-V1)X770/7670
0
0
1
1
0
1
V1+(V0-V1)X1220/7670
0
0
1
1
0
0
V1+(V0-V1)X1670/7670
0
0
1
0
1
1
V1+(V0-V1)X2170/7670
0
0
1
0
1
0
V1+(V0-V1)X2670/7670
0
0
1
0
0
1
V1+(V0-V1)X3170/7670
0
0
1
0
0
0
V1+(V0-V1)X3670/7670
0
0
0
1
1
1
V1+(V0-V1)X4170/7670
0
0
0
1
1
0
V1+(V0-V1)X4670/7670
0
0
0
1
0
1
V1+(V0-V1)X5170/7670
0
0
0
1
0
0
V1+(V0-V1)X5670/7670
0
0
0
0
1
1
V1+(V0-V1)X6170/7670
0
0
0
0
1
0
V1+(V0-V1)X6670/7670
0
0
0
0
0
1
V1+(V0-V1)X7170/7670
0
0
0
0
0
0
V0
17
HD66339
Table 3 64 Low-Voltage Grayscales
Display Data
Di5
Di4
Di3
Di2
Di1
Di0
64 Low-voltage
Grayscale Levels
1
1
1
1
1
1
V5
1
1
1
1
1
0
V6+(V5-V6)X3920/4260
1
1
1
1
0
1
V6+(V5-V6)X3580/4260
1
1
1
1
0
0
V6+(V5-V6)X3240/4260
1
1
1
0
1
1
V6+(V5-V6)X2900/4260
1
1
1
0
1
0
V6+(V5-V6)X2580/4260
1
1
1
0
0
1
V6+(V5-V6)X2270/4260
1
1
1
0
0
0
V6+(V5-V6)X1970/4260
1
1
0
1
1
1
V6+(V5-V6)X1680/4260
1
1
0
1
1
0
V6+(V5-V6)X1410/4260
1
1
0
1
0
1
V6+(V5-V6)X1150/4260
1
1
0
1
0
0
V6+(V5-V6)X900/4260
1
1
0
0
1
1
V6+(V5-V6)X660/4260
1
1
0
0
1
0
V6+(V5-V6)X430/4260
1
1
0
0
0
1
V6+(V5-V6)X210/4260
1
1
0
0
0
0
V6
1
0
1
1
1
1
V7+(V6-V7)X2565/2765
1
0
1
1
1
0
V7+(V6-V7)X2385/2765
1
0
1
1
0
1
V7+(V6-V7)X2210/2765
1
0
1
1
0
0
V7+(V6-V7)X2035/2765
1
0
1
0
1
1
V7+(V6-V7)X1860/2765
1
0
1
0
1
0
V7+(V6-V7)X1690/2765
1
0
1
0
0
1
V7+(V6-V7)X1520/2765
1
0
1
0
0
0
V7+(V6-V7)X1350/2765
1
0
0
1
1
1
V7+(V6-V7)X1185/2765
1
0
0
1
1
0
V7+(V6-V7)X1020/2765
1
0
0
1
0
1
V7+(V6-V7)X855/2765
1
0
0
1
0
0
V7+(V6-V7)X690/2765
1
0
0
0
1
1
V7+(V6-V7)X520/2765
1
0
0
0
1
0
V7+(V6-V7)X350/2765
1
0
0
0
0
1
V7+(V6-V7)X175/2765
1
0
0
0
0
0
V7
18
HD66339
Table 3 64 Low-Voltage Grayscales (cont)
Display Data
Di5
Di4
Di3
Di2
Di1
Di0
64 Low-voltage
Grayscale Levels
0
1
1
1
1
1
V8+(V7-V8)X3960/4140
0
1
1
1
1
0
V8+(V7-V8)X3770/4140
0
1
1
1
0
1
V8+(V7-V8)X3570/4140
0
1
1
1
0
0
V8+(V7-V8)X3360/4140
0
1
1
0
1
1
V8+(V7-V8)X3140/4140
0
1
1
0
1
0
V8+(V7-V8)X2910/4140
0
1
1
0
0
1
V8+(V7-V8)X2670/4140
0
1
1
0
0
0
V8+(V7-V8)X2420/4140
0
1
0
1
1
1
V8+(V7-V8)X2160/4140
0
1
0
1
1
0
V8+(V7-V8)X1890/4140
0
1
0
1
0
1
V8+(V7-V8)X1610/4140
0
1
0
1
0
0
V8+(V7-V8)X1310/4140
0
1
0
0
1
1
V8+(V7-V8)X990/4140
0
1
0
0
1
0
V8+(V7-V8)X660/4140
0
1
0
0
0
1
V8+(V7-V8)X330/4140
0
1
0
0
0
0
V8
0
0
1
1
1
1
V9+(V8-V9)X7300/7670
0
0
1
1
1
0
V9+(V8-V9)X6900/7670
0
0
1
1
0
1
V9+(V8-V9)X6450/7670
0
0
1
1
0
0
V9+(V8-V9)X6000/7670
0
0
1
0
1
1
V9+(V8-V9)X5500/7670
0
0
1
0
1
0
V9+(V8-V9)X5000/7670
0
0
1
0
0
1
V9+(V8-V9)X4500/7670
0
0
1
0
0
0
V9+(V8-V9)X4000/7670
0
0
0
1
1
1
V9+(V8-V9)X3500/7670
0
0
0
1
1
0
V9+(V8-V9)X3000/7670
0
0
0
1
0
1
V9+(V8-V9)X2500/7670
0
0
0
1
0
0
V9+(V8-V9)X2000/7670
0
0
0
0
1
1
V9+(V8-V9)X1500/7670
0
0
0
0
1
0
V9+(V8-V9)X1000/7670
0
0
0
0
0
1
V9+(V8-V9)X500/7670
0
0
0
0
0
0
V9
19
HD66339
Ladder Resistance Values
Resistance
Name
V0,V9
V1,V8
Resistance
Value (Ω)
Resistance
Name
Resistance
Value (Ω)
Resistance
Name
R0
500
R21
280
R42
170
R1
500
R22
270
R43
175
R2
500
R23
260
R44
175
R3
500
R24
250
R45
175
R4
500
R25
240
R46
180
R5
500
R26
230
R47
200
R48
210
V3,V6
R6
500
R27
220
R7
500
R28
210
R49
220
R8
500
R29
200
R50
230
R9
500
R30
190
R51
240
R10
500
R31
180
R52
250
R32
175
R53
260
V2,V7
R11
500
R12
450
R33
175
R54
270
R13
450
R34
170
R55
290
R14
400
R35
170
R56
300
R15
370
R36
165
R57
310
R16
330
R37
165
R58
320
R17
330
R38
165
R59
340
R18
330
R39
165
R60
340
R19
320
R40
170
R61
340
R20
300
R41
170
R62
340
Total
18835
V4,V5
20
Resistance
Value (Ω)
HD66339
Input Data and Output Voltages
The HD66339 outputs grayscale voltages of different polarity at the odd and even output pins with respect
to the LCD counter-electrode voltage. As an example, figure 11 shows the relationship between the input
data and output voltages when VLCD - 0.1 ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VLCD/2, and VLCD/2 ≥ V5 ≥
V6 ≥ V7 ≥ V8 ≥ V9 ≥ GND + 0.1.
High-voltage output
V0
V1
V2
V3
V4
VCOM
V6
V7
V8
111111
110000
MSB
100000
LSB
010000
V9
000000
Low–voltage output
V5
Input data
Figure 11 Relationship between Input Data and Output Voltages
21
HD66339
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Notes
Logic circuit
(low voltage)
VCC
–0.3 to + 4.6
V
1
LCD drive circuit
(high voltage)
VLCD
–0.3 to + 11.0
V
1
Input voltage (high voltage)
Vt1
–0.3 to VLCD + 0.3
V
1, 3
Input voltage (low voltage)
Vt2
–0.3 to VCC + 0.3
V
1, 2
Storage temperature
Tstg
–55 to +110
°C
Power supply
voltage
If the LSI is used beyond the above maximum ratings, it may be permanently damaged. It should
always be used within its specified operating range for normal operation to prevent malfunction or
degraded reliability.
Notes: 1. Value when GND = 0 V.
2. Applies to the CL1, CL2, SHL, Dij, M, POL1, and POL2 input pins, and the EIO1 and EIO2
input/output pins when used as input.
3. Specifies the voltage to be input to the LCD drive power supply pins.
The following relationships must be observed: VLCD - 0.1 ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VLCD/2,
and VLCD/2 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ GND + 0.1.
Recommended Operating Ranges
Item
Symbol
Ratings
Unit
Notes
Logic circuit
(low voltage)
VCC
+2.3 to + 3.6
V
1
LCD drive circuit
(high voltage)
VLCD
+6.5 to + 10.0
V
1
γ compensation power supply voltage
(high voltage)
Vt1U
VLCD/2 to VLCD – 0.1
V
1
γ compensation power supply voltage
(low voltage)
Vt1L
GND + 0.1 to VLCD /2
V
1
Driver output voltage
Vout
GND + 0.1 to
VLCD – 0.1
V
1
Max. clock frequency
Fmax
55
MHz
2
Operating temperature
Topr
–30 to +75
°C
Power supply
voltage
Note:
22
1. Value when GND = 0 V.
2. Value when Vcc = 2.7 to 3.6 V.
HD66339
Electrical Characteristics
DC Characteristics (Conditions (unless otherwise specified): VCC – GND = 2.3 V to 3.6 V, VLCD –
GND = 6.5 V to 10.0 V, Ta = –30°C to +75°C)
Applicable
Pin
Item
Symbol
Input high-level
voltage
VIH
Input low-level
voltage
VIL
Output highlevel voltage
VOH
Output low-level
voltage
VOL
Input leakage
current (1)
IL1
CL1, CL2, SHL,
Dij, M, POL1,
and POL2
Input leakage
current (2)
IL2
EIO1(I) and
EIO2(I)
γ compensation
power supply
voltage current
Iref
V0, V5
Output voltage
deviation
∆V0
CL1, CL2, SHL,
Dij, M, POL1,
POL2, EIO1(I),
and EIO2(I)
EIO1(O) and
EIO2(O)
Min.
Typ.
Max.
Uni t
0.7 ×
VCC
VCC
V
0
0.3 ×
VCC
V
VCC –
0.4
Conditions
V
I OH = –0. 4 mA
0.4
V
I OL = 0. 4 mA
–2
+2
µA
–5
+5
µA
800
µA
600
V0–V4 = 4.0 V
V5–V9 = 4.0 V
V4, V9
–800
–600
µA
Y1 to Y480
—
±10
±20
mV
Input data
00 to 07, and
38 to 3F
±5
±14
mV
Input data
08 to 37
Output voltage
deviation in
offset cancel
operation
∆V0fc
Y1 to Y480
—
±2
±7
mV
Input data
00 to 3F
Average output
voltage
dispersion
∆V ∆
Y1 to Y480
—
±20
—
mV
Input data
00 to 07, and
38 to 3F
±10
—
mV
Input data
08 to 37
-0.5
mA
VLCD = 8.0 V
VX = 7.5 V
VOUT = 6.5 V
mA
VLCD = 8.0 V
VX = 1.0 V
VOUT = 2.0 V
Output current
of drivers
IOH
Y1 to Y480
IOL
Y1 to Y480
0.5
Note
1
23
HD66339
DC Characteristics (Conditions (unless otherwise specified): VCC – GND = 2.3 V to 3.6 V, VLCD –
GND = 6.5 V to 10.0 V, Ta = –30°C to +75°C) (cont)
Item
Symbol
Applicable
Pin
Min.
Typ.
Max.
Uni t
Conditions
Note
Logic unit
consumptive
current
I CC
VCC
—
3.0
5.0
mA
VCC = 3.3 V
VLCD = 8.0 V
f CL1 = 83 kHz
2
Driver unit
consumptive
current
I LCD
VLCD
—
5.0
8.0
mA
(1 horizontal
period = 12
µs)
f C L2 = 55 MHz
Input
capacitance 1
C1
Input pins
except EIO1
and EIO2
—
5
10
pF
Ta = 25°C
Input
capacitance 2
C2
EIO1 and
EIO2
—
5
10
pF
Ta = 25°C
Notes: 1. The average output voltage dispersion is the difference in average output voltage between chips;
the average output voltage is the average voltage within the chip for the same display data. The
average output voltage dispersion is a reference value.
2. With outputs unloaded, and excluding the current flowing in V0 to V9. The specification applies
to the display pattern (among solid black, solid white, and dot check patterns) with the largest
current.
24
HD66339
AC Characteristics 1 (Conditions (unless otherwise specified): VCC – GND = 2.7 V to 3.6 V, VLCD –
GND = 6.5 V to 10.0 V, Ta = –30°C to +75°C, Tr = Tf = 6 ns)
Item
Symbol
Applicable
Pins
Min.
Clock cycle time
Trate
CL2
18
ns
Clock low-level width
Tcwl
CL2
4
ns
Clock high-level
width
Tcwh
CL2
4
ns
Data setup time
Tds
Dij and CL2
3
ns
Data hold time
Tdh
Dij and CL2
0
ns
Start pulse setup
time
Tss
EIO1, EIO2,
and CL2
3
ns
Start pulse hold time
Tsh
EIO1, EIO2,
and CL2
0
ns
POL1, 2 setup time
Tps
POL1, POL2,
and CL2
3
ns
POL1, 2 hold time
Tph
POL1, POL2,
and CL2
0
ns
Start pulse low
period
Tspl
EIO1, EIO2,
and CL1
6
ns
CL1 high-level width
Tcl1wh
CL1
2
CLK
Last data timing
Tldt
CL1 and CL2
2
CLK
Time between CL1
start pulses
Tcl1-eio
CL1, EIO1,
and EIO2
2
CLK
M setup time
Tms
M and CL1
5
ns
M hold time
Tmh
M and CL1
5
ns
Start pulse delay
time
Tsd
EIO1, EIO2,
and CL2
Driver output delay
time 1
(load condition 1)
Tdd1
CL1 and
Y1 to Y480
Tdd2
CL1 and
Y1 to Y480
Typ.
Max.
Unit
Conditions
Notes
14
ns
CL = 15 pF
2
3
µs
VLCD = 8.5 V
95% error
1
7
10.5
µs
VLCD = 8.5 V
95% error
2
25
HD66339
Note 1: The specification applies to the following conditions.
Load condition 1
0.9 kΩ
0.9 kΩ
Test point
Y1 to Y480
6 pF
6 pF
10 stages
Note 2: The specification applies to the following conditions.
Load condition 2
5 kΩ
5 kΩ
Test point
Y1 to Y480
8 pF
8 pF
10 stages
26
HD66339
AC Characteristics 2 (Conditions (unless otherwise specified): VCC – GND = 2.3 V to 2.7 V, VLCD –
GND = 6.5 V to 10.0 V, Ta = –30°C to +75°C, Tr = Tf = 6 ns)
Item
Symbol
Applicable
Pins
Min.
Clock cycle time
Trate
CL2
22
ns
Clock low-level
width
Tcwl
CL2
6
ns
Clock high-level
width
Tcwh
CL2
6
ns
Data setup time
Tds
Dij and CL2
6
ns
Data hold time
Tdh
Dij and CL2
0
ns
Start pulse setup
time
Tss
EIO1, EIO2,
and CL2
6
ns
Start pulse hold
time
Tsh
EIO1, EIO2,
and CL2
0
ns
POL1, 2 setup
time
Tps
POL1,
POL2, and
CL2
6
ns
POL1, 2 hold
time
Tph
POL1,
POL2, and
CL2
0
ns
Start pulse low
period
Tspl
EIO1, EIO2,
and CL1
6
ns
CL1 high-level
width
Tcl1wh
CL1
2
CLK
Last data timing
Tldt
CL1 and
CL2
2
CLK
Time between
CL1 start pulses
Tcl1-eio
CL1, EIO1,
and EIO2
2
CLK
M setup time
Tms
M and CL1
6
ns
M hold time
Tmh
M and CL1
6
ns
Start pulse delay
time
Tsd
EIO1, EIO2,
and CL2
Driver output
delay time 1
(load condition 1)
Tdd1
CL1 and
Y1 to Y480
Tdd2
CL1 and
Y1 to Y480
Typ.
Max.
Unit
Conditions
Notes
16
ns
CL = 15 pF
2
3
µs
VLCD = 8.5 V
95% error
1
7
10.5
µs
VLCD = 8.5 V
95% error
2
27
HD66339
Note 1: The specification applies to the following conditions.
Load condition 1
0.9 kΩ
0.9 kΩ
Test point
Y1 to Y480
6 pF
6 pF
10 stages
Note 2: The specification applies to the following conditions.
Load condition 2
5 kΩ
5 kΩ
Test point
Y1 to Y480
8 pF
8 pF
10 stages
28
HD66339
Switching Characteristic Waveforms
Note : When not specified, the measurement
points are as follows:
0.7 x Vcc
0.3 x Vcc
Tr
Tf
Trate
0.9Vcc
Tcwh
Tcwl
0.1Vcc
CL2
1
INVALID
0.1Vcc
2
Tds
Tps
Dij,
POL1,2
0.9Vcc
Tdh
Tph
INVALID
1
Tss
Tsh
EIO input of the
first-stage IC
(start pulse)
80
CL2
81
1
82
2
Tsd
EIO output of
the first-stage
IC
Dij
VALID
(Last Data)
INVALID
VALID
VALID
Tldt
CL2
2
1
3
Tcl1wh
CL1
Tms
Tmh
M
Tcl1-eio
EIO input of the
first-stage IC
(start pulse)
Tspl
Hi-Z
Tdd1 Tdd2
Y1 to Y480
Last output voltage x 5 %
Last output voltage x 95 %
Y1 to Y480
29
HD66339
Power-supply Application and Shutdown Sequence
Use the HD66339 based on the following sequence.
(1)
(1)
GND
(1) = 0 s to 1 s
30
(1)
VLCD
VLCD
V0 to V9
V0 to V9
Vcc
Vcc
Input signal
Input signal
(1)
HD66339
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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31