19-1134; Rev 0; 10/96 KIT ATION EVALU LE B A IL A AV 12-Bit, 30Msps, TTL-Output ADC _____________________________Features ♦ Monolithic, 12-Bit, 30Msps Converter ♦ On-Chip Track/Hold ♦ ±2.0V Analog Input Range ♦ High Input Impedance ♦ 66dB SNR at 1MHz Input ♦ Low Power: 1.1W ♦ 5pF Input Capacitance ♦ TTL-Compatible Outputs ________________Ordering Information _________________________Applications PART TEMP. RANGE MAX1172CDJ 0°C to +70°C 32 Ceramic SB PIN-PACKAGE MAX1172CBH 0°C to +70°C 44 CERQUAD Radar Receivers Professional Video Instrumentation ___________________Pin Configurations Imaging TRACK/ HOLD AMPLIFIERS ASYNCHRONOUS 8-BIT SAR 8 34 35 36 37 38 39 40 41 30 29 5 6 28 MAX1172 N.C. VFB VSB VRT1 VRT2 VIN VRT3 VST VFT N.C. VCC 22 23 21 24 11 20 25 10 19 26 9 18 27 8 17 7 16 ERROR CORRECTION, DECODING 12 AND OUTPUT TLL DRIVERS 31 4 15 DIGITAL OUTPUT 3 14 4 42 44 ANALOG GAIN COMPRESSION PROCESSOR 4-BIT FLASH CONVERTER 32 13 INPUT BUFFER 33 2 12 VIN 1 N.C. D12 DGND DVCC N.C. CLK N.C. VEE N.C. AGND N.C. ________________Functional Diagram D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 N.C. 43 TOP VIEW Digital Spectrum Analyzers D1 D0 N.C. DGND DVCC VEE N.C. AGND N.C. VCC N.C. Digital Communications CERQUAD Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 1 MAX1172 _________________General Description The MAX1172 analog-to-digital converter (ADC) is a 12-bit monolithic ADC capable of sample rates greater than 30Msps. An on-board input buffer and track/hold function ensure excellent dynamic performance without the need for external components. A 5pF input capacitance minimizes development problems. Logic inputs and outputs are TTL compatible. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is a very low 1.1W with power-supply voltages of +5.0V and -5.2V. The MAX1172 also provides a wide input voltage range of ±2.0V. The MAX1172 is available in a 32-lead ceramic sidebrazed package and a 44-lead surface-mount CERQUAD package. MAX1172 12-Bit, 30Msps, TTL-Output ADC ABSOLUTE MAXIMUM RATINGS VCC .......................................................................................+6V VEE .........................................................................................-6V Analog Input ........................................................VFB ≤ VIN ≤ VFT VFB, VFT ................................................................. -3.0V, +3.0V Reference Ladder Current ..................................................12mA CLK IN ...................................................................................VCC Digital Outputs.......................................................0mA to -30mA Operating Temperature Range...............................0°C to +70°C Junction Temperature (Tj)................................................+175°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 30MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS TEST LEVEL Resolution MIN TYP MAX 12 UNITS Bits DC ACCURACY (TA = +25°C) Integral Nonlinearity ± full scale IV ±2.0 LSB Differential Nonlinearity 250kHz sample rate IV ±0.8 LSB I Guaranteed VI ±2.0 I 30 No Missing Codes ANALOG INPUT Input Voltage Range Input Bias Current TA = +25°C Input Resistance VIN = 0V, TA = +25°C I 100 V 60 300 µA kΩ V 5 pF V 120 MHz Positive Full-Scale Error V ±5.0 LSB Negative Full-Scale Error V ±5.0 LSB Input Capacitance Input Bandwidth 3dB small signal REFERENCE INPUT Reference Ladder Resistance VI Reference Ladder Tempco V 500 800 Ω 0.8 Ω/°C 40 MHz TIMING CHARACTERISTICS Maximum Conversion Rate VI Overvoltage Recovery Time V Pipeline Delay (Latency) 30 20 VI ns 1 Clock Cycle 18 ns Output Delay TA = +25°C V 14 Aperture Delay Time TA = +25°C V 1 ns Aperture Jitter Time TA = +25°C V 5 ps-RMS 2 _______________________________________________________________________________________ 12-Bit, 30Msps, TTL-Output ADC (VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 30MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONDITIONS TEST LEVEL MIN TYP MAX UNITS DYNAMIC PERFORMANCE Effective Number of Bits fIN = 500kHz 10.0 fIN = 1MHz 9.8 fIN = 3.58MHz 9.5 fIN = 500kHz Signal-to-Noise Ratio (without Harmonics) fIN = 1MHz fIN = 3.58MHz fIN = 500kHz Harmonic Distortion fIN = 1MHz fIN = 3.58MHz fIN = 500kHz Signal-to-Noise and Distortion fIN = 1MHz fIN = 3.58MHz TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX I 63 66 IV 58 61 I 63 65 IV 58 60 I 62 64 IV 58 60 I 63 65 IV 59 61 I 62 64 IV 58 60 I 59 61 IV 57 59 I 60 62 IV 55 57 I 59 61 IV 55 57 I 57 59 IV 54 Bits dB dB dB 56 Spurious-Free Dynamic Range fIN = 1MHz, TA = +25°C V 74 dBc Differential Phase fIN = 3.58MHz and 4.35MHz, TA = +25°C V 0.2 Degrees Differential Gain fIN = 3.58MHz and 4.35MHz, TA = +25°C V 0.7 % DIGITAL INPUTS Logic "1" Voltage V Logic "0" Voltage V Maximum Input Current Low TA = +25°C Maximum Input Current High TA = +25°C I 2.4 4.0 V 0.8 V 0 5 20 µA 5 20 µA I 0 Pulse Width Low (CLK) IV 15 Pulse Width High (CLK) IV 15 2.4 ns 300 ns DIGITAL OUTPUTS Logic "1" Voltage TA = +25°C I Logic "0" Voltage TA = +25°C I V 0.6 V _______________________________________________________________________________________ 3 MAX1172 ELECTRICAL CHARACTERISTICS (continued) MAX1172 12-Bit, 30Msps, TTL-Output ADC ELECTRICAL CHARACTERISTICS (continued) (VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 30MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) TEST LEVEL MIN TYP MAX VCC IV 4.75 5.0 5.25 DVCC IV 4.75 5.0 5.25 -VEE IV -4.95 -5.2 -5.45 PARAMETER CONDITIONS UNITS POWER-SUPPLY REQUIREMENTS Voltages ICC, TA = +25°C Currents DICC, TA = TMIN to TMAX -IEE, TA = +25°C Power Dissipation Power-Supply Rejection 5V ±0.25V, -5.2V ±0.25V I 135 150 IV 40 55 I 45 70 VI 1.1 1.3 V 1.0 V mA W LSB Note 1: Typical thermal impedances (unsoldered, in free air): 32 Ceramic SB: θjA = 50°C/W 44 CERQUAD: θjA = 78°C/W, θjA at 1m/s airflow = 58°C/W, θjC = 3.3°C/W Use forced-air cooling or heatsinking to maintain Tj ≤ 150°C. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA. 4 TEST LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25°C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25°C. Parameter is guaranteed over specified temperature range. _______________________________________________________________________________________ 12-Bit, 30Msps, TTL-Output ADC TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY 60 50 50 40 40 30 30 20 10 INPUT FREQUENCY (MHz) 100 10 INPUT FREQUENCY (MHz) 40 1 SPECTRAL RESPONSE 50 40 100 MAX1170 TOC-05 75 70 SNR, THD, SINAD (dB) AMPLITUDE (dB) 60 10 SAMPLE RATE (Msps) SNR, THD, SINAD vs. TEMPERATURE -30 SINAD (dB) SINAD 50 100 0 MAX1170 TOC-04 70 60 20 1 SIGNAL-TO-NOISE AND DISTORTION vs. INPUT FREQUENCY 80 SNR, THD 30 20 1 70 -60 -90 MAX1170 TOC-06 THD (dB) SNR (dB) SNR, THD, SINAD (dB) 70 60 80 MAX1170 TOC-02 MAX1170 TOC-01 70 SNR, THD, SINAD vs. SAMPLE RATE 80 MAX1170 TOC-03 SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY 80 SNR 65 THD 60 SINAD 55 30 -120 20 1 10 0INPUT FREQUENCY (MHz) 100 50 0 1 2 3 FREQUENCY (MHz) 4 5 -25 0 50 25 TEMPERATURE (°C) 75 _______________________________________________________________________________________ 5 MAX1172 __________________________________________Typical Operating Characteristics (fS = 30Msps, fIN = 1MHz, TA = +25°C, unless otherwise noted.) MAX1172 12-Bit, 30Msps, TTL-Output ADC _________________________________________________________________________Pin Description PIN NAME 6 Ceramic SB CERQUAD 1, 15 14, 41 DGND 2–13 43, 44, 1–10 D0–D11 14 13 D12 16, 32 15, 40 DVCC FUNCTION Digital Ground TTL Outputs (D0 = LSB) TTL Output Overrange Bit Digital +5.0V Supply (TTL Outputs) 17 17 CLK TLL Clock Input 18, 31 19, 39 VEE -5.2V Supply 19, 30 21, 37 AGND 20, 29 23, 35 VCC +5.0V Supply 21 25 VFT Force for Top of Reference Ladder 22 26 VST Sense for Top of Reference Ladder 23 27 VRT3 24 28 VIN 25 29 VRT2 Voltage Reference Tap 2 26 30 VRT1 Voltage Reference Tap 1 27 31 VSB Sense for Bottom of Reference Ladder 28 32 VFB Force for Bottom of Reference Ladder — 11, 12, 16, 18, 20, 22, 24, 33, 34, 36, 38, 42 N.C. No Connection Analog Ground Voltage Reference Tap 3 Analog Input, ±2.0V typical _______________________________________________________________________________________ 12-Bit, 30Msps, TTL-Output ADC MAX1172 N+1 N N+2 tPWH tPWL CLK tD OUTPUT DATA N-2 DATA VALID N N-1 DATA VALID N+1 Figure 1a. Timing Diagram CLK tD OUTPUT DATA DATA VALID Figure 1b. Single-Event Clock Table 1. Timing Parameters PARAMETER MIN DESCRIPTION tD CLK to Data Valid Prop Delay tPWH CLK High Pulse Width 15 tPWL CLK Low Pulse Width 15 _______________Detailed Description The MAX1172 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the MAX1172 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria for achieving the optimal device performance. TYP MAX UNITS 14 18 ns 300 ns ns Power Supplies and Grounding The MAX1172 requires -5.2V and +5V analog supply voltages. The +5V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line reduces the transient noise injected into the analog VCC. These beads should be connected as close to the device as possible. The connection between the beads and the MAX1172 should not be shared with any other device. Bypass each power-supply pin as close to the device as possible. Use 0.1µF for VEE and VCC, and 0.01µF for DVCC (chip capacitors are preferred). _______________________________________________________________________________________ 7 R1 100Ω 17 CLK + VIN +2.5V VOUT 6 GND TRIM 4 D11 13 21 VFT + IC1 (REF-03) 4 D12 14 (OVERRANGE) COARSE ADC 1µF 5 D10 12 D9 11 22 VST 10k C2 0.01µF 30k D8 10 ANALOG PRESCALER 2R 23 VRT3 C3 0.01µF 2R 25 VRT2 C4 0.01µF DGND C7 0.01µF R 28 VFB D4 6 18 31 19 AGND 30 20 29 D0 2 16 DGND C16 1µF SUCCESSIVE INTERPOLATION STAGE N DVCC -2.5V D5 7 D1 3 C6 0.01µF 6 D6 8 D2 4 2R DVCC C18 0.01µF D7 9 D3 5 27 VSB 30k VCC C17 0.01µF 7 +5V 4 VCC 8 C5 0.01µF -5.2V AGND 10k 2R AGND IC2 OP-07 SUCCESSIVE INTERPOLATION STAGE 1 26 VRT1 VEE 1 2 VEE 3 32 1 C8 C10 0.1µF 0.1µF C12 0.01µF C9 C11 0.1µF 0.1µF C13 0.01µF 15 NOTES: 1) D1 = SCHOTTKY OR HOT CARRIER DIODE D1 FB FB C15 C14 10µF 10µF FB 2) FB = FERRITE BEAD, FAIR RIGHT P/N 2743001111, TO BE MOUNTED AS CLOSELY AS POSSIBLE. THE FERRITE BEAD TO ADC CONNECTION SHOULD NOT BE SHARED WITH ANY OTHER DEVICE. 3) C1–C3 = CHIP CAPACITOR (RECOMMENDED) MOUNTED AS CLOSELY TO THE DEVICE’S PIN AS POSSIBLE 4) USE OF A SEPARATE SUPPLY FOR VCC AND DVCC IS NOT RECOMMENDED 5) R1 PROVIDES CURRENT LIMITING TO 45mA -5.2V (ANALOG) +5V (ANALOG) Figure 2. Typical Interface Circuit 8 (MSB) R C1 0.01µF DECODING NETWORK 2 +5V C19 1µF MAX1172 24 VIN VIN (±2V) DIGITAL OUTPUTS CLK (TTL) DGND MAX1172 12-Bit, 30Msps, TTL-Output ADC _______________________________________________________________________________________ (LSB) 12-Bit, 30Msps, TTL-Output ADC Voltage Reference The MAX1172 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5V typical), VFB (-2.5V typical) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800Ω. The +2.5V voltage source for reference VFT must be current limited to 20mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in Figures 2 and 3. In addition, there are five reference ladder taps (VST, VRT1, VRT2, VRT3, and VSB). VST is the sense for the top of the reference ladder (+2.0V), VRT2 is the midpoint of the ladder (0.0V typical), and VSB is the sense for the bottom of the reference ladder (-2.0V). VRT1 and VRT3 are quarter-point ladder taps (+1.0V and -1.0V typical, respectively). The voltages seen at V ST and VSB are the true full-scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5V and -2.5V typical, respectively). VST and VSB can be used to monitor the actual full-scale input voltage of the device. VRT1, VRT2, and VRT3 should not be driven to the expected ideal values, as is commonly done with standard flash converters. A decoupling capacitor of 0.01µF connected to AGND from each tap is recommended to minimize high-frequency noise injection. The analog input range will scale proportionally with respect to the reference voltage if a different input MAX1172 VCC ANALOG PRESCALER AGND and DGND are the two grounds available on the MAX1172. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power-supply sequencing latchup conditions. Use of the recommended interface circuit shown in Figure 2 will provide optimum device performance for the MAX1172. VIN VFT VEE Figure 3. Analog Equivalent Input Circuit range is required. The maximum scaling factor for device operation is ±20% of the recommended reference voltages of VFT and VFB. However, because the MAX1172 is laser trimmed to optimize performance with ±2.5V references, its accuracy will degrade if operated beyond a ±2% range. An example of a recommended reference driver circuit is shown in Figure 2. IC1 is REF-03, the +2.5V reference with a tolerance of 0.6% or ±0.015V. The 10kΩ potentiometer supports an adjustable range of 150mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. Adjust R1 and R4 such that VST and VSB are exactly +2.0V and -2.0V, respectively. The following errors are defined: +FS error = top of ladder offset voltage = ∆(+FS - VST) -FS error = bottom of ladder offset voltage = ∆(-FS - VSB) Where the +FS (full scale) input voltage is defined as the output 1LSB above the transition of 1–10 and 1–11, and the -FS input voltage is defined as the output 1LSB below the transition of 0–00 and 0–01. _______________________________________________________________________________________ 9 Analog Input SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE 67 MAX1170 FIG-04 VIN is the analog input. The full-scale input range will be 80% of the reference voltage or ±2V with VFB = -2.5V and VFT = +2.5V. The drive requirements for the analog inputs are minimal compared to those of conventional flash converters, due to the MAX1172’s extremely low 5pF input capacitance and high 300kΩ input impedance. For example, for an input signal of ±2Vp-p with an input frequency of 10MHz, the peak output current required for the driving circuit is only 628µA. 65 63 SNR (dB) 61 59 DUTY CYCLE = tPWH tPWL The MAX1172 is driven from a single-ended TTL input (CLK). The clock pulse width (t PWH ) must be kept between 15ns and 300ns to ensure proper operation of the internal track/hold amplifier (Figure 1a). When operating the MAX1172 at sampling rates above 3Msps, it is recommended that the clock input duty cycle be kept at 50% to optimize performance (Figure 4). The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (VIH ≤ 4.5V, tRISE < 6ns). In the event the clock is driven from a high current source, use a 100Ω (R1, Figure 2) resistor in series to current limit to approximately 45mA. Digital Outputs The format of the output data (D0-D11) is straight binary (Table 2). The outputs are latched on the rising edge of CLK with a typical propagation delay of 14ns. There is a one clock cycle latency between CLK and the valid output data (Figure 1a). The digital outputs’ rise times and fall times are not symmetrical. The rise time’s typical propagation delay is 14ns, and the typical fall time is 6ns (Figure 5). The nonsymmetrical rise and fall times create approximately 8ns of invalid data. Table 2. Output Data Information ANALOG INPUT OVERRANGE D10 OUTPUT CODE D9–D0 > +2.0V + 1/2LSB 1 1 1 1 111 1111 +2.0V - 1LSB 0.0V -2.0V + 1LSB < -2.0V 0 0 0 0 11 ØØ 00 00 1 111 ØØØØ 0000 0000 55 tPWH 57 Clock Input tPWL MAX1172 12-Bit, 30Msps, TTL-Output ADC 53 51 25 35 45 55 65 75 DUTY CYCLE OF POSITIVE CLOCK PULSE (%) Figure 4. Signal-to-Noise Ratio vs. Clock Duty Cycle Overrange Output The overrange output (D12) is an indication that the analog input signal has exceeded the full-scale input voltage by 1LSB. When this condition occurs, the outputs will switch to logic 1s. All other data outputs are unaffected by this operation. This feature makes it possible to include the MAX1172 in higher resolution systems. Evaluation Board The MAX1170 evaluation kit (EV kit) is available to aid designers in demonstrating the full performance of the MAX1172 (or of the MAX1170/MAX1171). This board includes a reference circuit, clock driver circuit, output data latches, and on-board reconstruction of the digital data. A separate EV kit manual describing the operation of this board is available. Contact the factory for price and availability. 111Ø ØØØØ 000Ø 0000 (Ø indicates the flickering bit between logic 0 and 1). 10 ______________________________________________________________________________________ 12-Bit, 30Msps, TTL-Output ADC CLK IN MAX1172 N N+1 2.4V tRISE 6ns 6ns typ 3.5V DATA OUT (ACTUAL) INVALID DATA 2.4V (N - 2) INVALID DATA (N - 1) (N) 0.8V 0.5V tPD1 14ns typ DATA OUT (EQUIVALENT) (N - 2) INVALID DATA INVALID DATA (N - 1) (N - 1) Figure 5. Digital Output Characteristics ____Pin Configurations (continued) TOP VIEW DGND 1 32 DVCC D0 2 31 VEE D1 3 D2 4 30 AGND MAX1172 D3 5 29 VCC 28 VFB D4 6 27 VSB D5 7 26 VRT1 D6 8 25 VRT2 D7 9 24 VIN D8 10 23 VRT3 D9 11 22 VST D10 12 21 VFT D11 13 20 VCC D12 14 19 AGND DGND 15 18 VEE DVCC 16 17 CLK Ceramic SB ______________________________________________________________________________________ 11 MAX1172 12-Bit, 30Msps, TTL-Output ADC ________________________________________________________Package Information DIM A B C D E F G H I J 32 1 G INCHES MAX MIN 0.099 0.081 0.020 0.016 0.105 0.095 0.050 typ – – 0.040 0.225 0.175 1.620 1.580 0.605 0.585 0.012 0.009 0.620 0.600 MILLIMETERS MIN MAX 2.06 2.51 0.41 0.51 2.41 2.67 – 1.27 1.02 – 4.45 5.72 40.13 41.15 14.86 15.37 0.23 0.30 15.24 15.75 H 32-PIN SIDEBRAZED PACKAGE A E F I J C B D DIM C A D B A B C D E F G H INCHES MAX MIN 0.000 0.546 typ 0.694 0.679 0.040 0.038 0.000 0.016 typ 0.000 0.008 typ 0.051 0.027 0.000 0.006 typ 0.140 0.115 MILLIMETERS MIN MAX 14.00 typ – 17.40 17.80 0.98 1.02 0.40 typ – 0.20 typ – 0.70 1.30 0.15 typ – 2.96 3.58 A B 44-PIN CERQUAD H 0-5° G E F Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.