HI1826 NS ESIG Semiconductor D NEW NOT OR ED F 86 D N E I30 OMM See H REC 6-Bit, 140 MSPS, Flash A/D Converter October 1998 Features Description • Ultra-High Speed Operation with Maximum Conversion Rate. . . . . . . . . . . . . . . . . . . . . . . 140 MSPS HI1826 is a 6-bit, 140 MSPS, flash A/D converter IC capable of digitizing analog signals at the maximum rate of 140 MSPS. The digital input/output level is compatible with the ECL 100K/10KH/10K. [ /Title (HI1826) • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF /Subject (6-Bit, 140 MSPS, Flash A/D Converter) •/Author Wide Analog () Input Bandwidth (Min) . . . . . . . . 200MHz Semiconductor, FlatOrdering Information •/Keywords Low Power(Harris Consumption . . . . . . . . . . .RGB, . . . . . .Video, .225mW Panel, LCD) PART TEMP. • Low Error Rate NUMBER RANGE (oC) /Creator () /DOCINFO pdfmark Applications HI1826JCQ -20 to 75 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S • RGB Graphics Processing [ /PageMode /UseOutlines • Digital Data Storage Read Channels /DOCVIEW pdfmark • Digital Communications Pinout AGND CLKN AVEE CLKP DVEE D0 (LSB) D1 D2 HI1826 (MQFP) TOP VIEW DGND1 1 32 31 30 29 28 27 26 25 24 DGND2 2 23 VRT NC 3 22 AGND NC 4 21 NC NC 5 20 VIN NC 6 19 AGND DGND2 7 18 VRB 8 17 VRBS DGND1 AGND AVEE NC INV DVEE D5 (MSB) D4 D3 9 10 11 12 13 14 15 16 VRTS CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 4-1 File Number 4107.2 HI1826 Block Diagram VRB VRBS VRTS VRT 18 17 24 23 REFERENCE RESISTANCE 20 VIN COMPARATOR ARRAY 8 DGND1 7 DGND2 19 AGND ENCODER LOGIC 12 DVEE 6 15 AVEE INV 13 EXOR ARRAY 6 CLKP 28 OUTPUT BUFFER CLK DRIVER CLKN 27 31 32 9 10 11 D0 D1 (LSB) 30 D2 D3 D4 D5 (MSB) 4-2 HI1826 Pin Descriptions PIN NO. SYMBOL I/O TYPICAL VOLTAGE LEVEL 16, 19, 22, 25 AGND - 0V Analog GND. Used as GND for input buffers and latches of comparators. Separated from DGND1 and DGND2. 15, 26 AVEE - -5.2V Analog VEE . Typical voltage is -5.2V. Connected internally with DVEE . (Resistance is 4 to 6Ω.) Connect to AGND through a ceramic chip capacitor of 0.1µF or more just near the pin. 28 CLKP I ECL 27 CLKN EQUIVALENT CIRCUIT DESCRIPTION CLK Input. DGND1 R CLK Complementary Input. When left open, voltage goes to ECL threshold potential (-1.3V). Although only CLKP input can be used for operation with CLKN input open, complementary input is recommended in order to attain high speed and stable operation. R R CLKP R CLKN R R DVEE 1, 8 DGND1 - 0V Digital GND for Internal Circuits. 2, 7 DGND2 - 0V Digital GND for Output Transistors. 12, 29 DVEE - -5.2V 30 D0 O ECL 31 D1 32 D2 9 D3 10 D4 11 D5 Digital VEE. Connected internally with AVEE. (Resistance is 4 to 6Ω.) Connect to DGND through a ceramic chip capacitor of 0.1µF or more just near the pin. DGND2 LSB of Data Output. External pull-down resistor is required. Data Output. External pull-down resistors are required. Di MSB of Data Output. External pull-down resistor is required. DVEE 4-3 HI1826 Pin Descriptions (Continued) PIN NO. SYMBOL I/O TYPICAL VOLTAGE LEVEL 13 INV I ECL EQUIVALENT CIRCUIT DESCRIPTION Output polarity inversion input for D0 (LSB) to D5 (MSB). (Refer to the output code table.) When left open, Low levels maintained. DGND1 R R 20 VIN I INV R DVEE R -1.3V VRT to VRB Analog Input. AGND VIN AVEE 18 VRB I -2V VRT R1 R VRTS 17 23 COMPARATOR 1 R VRBS VRT Reference Voltage (Bottom) Sense. COMPARATOR 2 I 0V R COMPARATOR 30 R COMPARATOR 31 24 Reference Voltage (Bottom) Force; typical voltage is -2V. Connect to AGND through a ceramic chip capacitor of 0.1µF or more and a tantalum capacitor of 10µF or more just near the pin. R VRTS Reference Voltage (Top) Force; typical voltage is 0V. When applying a voltage other than AGND to this pin, connect to AGND through a ceramic chip capacitor of 0.1µF for more and a tantalum capacitor of 10µF or more just near the pin. Reference Voltage (Top) Sense. COMPARATOR 32 R COMPARATOR 33 R COMPARATOR 63 VRBS VRB 3, 4 5, 6 14, 21 NC - R3 R - Not Connected. Although not connected in the IC, it is recommended that these pins should be connected to AGND or DGND on printed circuit board. 4-4 HI1826 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVEE) . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 0.5V Reference Voltage (VRT , VRB) . . . . . . . . . . . . . . . . . . . -1.5V to 0.5V | VRT - VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . -2.7V to 0.5V Digital Input Voltage (CLKP, CLKN, INV) . . . . . . . . . . . . -4V to 0.5V | CLKP - CLKN | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V Digital Output Current (ID0 to ID5) . . . . . . . . . . . . . . . -30mA to 0mA Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ns tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ns CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = +5V, VRB = 1.0V, VRT = 2.0V, TA = 25oC PARAMETER Resolution SYMBOL TEST CONDITIONS n MIN TYP MAX UNITS 6 6 6 bits DC CHARACTERISTICS Integral Linearity Error EIL fC = 140MHz -0.25 - +0.25 LSB Differential Linearity Error EDL fC = 140MHz -0.25 - +0.25 LSB Analog Input Capacitance CIN VIN = -1V + 0.07VRMS - 7 18 pF Analog Input Resistance RIN 300 - - kΩ Input Bias Current IIN - - 400 µA RREF - 200 - Ω VRT EOT - - 20 mV VRB EOB - - 20 mV Logic High Level VIH -1.13 - -0.65 V Logic Low Level VIL -2.1 - -1.5 V Logic High Current IIH Apply -0.8V to Input 0 - 50 µA Logic Low Current IIL Apply -1.6V to Input -50 - 50 µA - 7 140 - - MSPS - 10 - ps ANALOG INPUT VIN = -1V REFERENCE INPUT Reference Resistance Offset Voltage DIGITAL INPUT Input Capacitance pF SWITCHING CHARACTERISTICS Maximum Conversion Frequency fC Aperture Jitter tAJ Error rate 1E-9 TPS (Note 1) 4-5 HI1826 Electrical Specifications PARAMETER VDD = +5V, VRB = 1.0V, VRT = 2.0V, TA = 25oC (Continued) MIN TYP MAX UNITS tDS - 1.5 - ns High Pulse Width of Clock tPW1 3.0 - - ns Low Pulse Width of Clock tPW0 3.0 - - ns Sampling Delay SYMBOL TEST CONDITIONS DIGITAL OUTPUT Logic High Level VOH RL = 100Ω to -2V -1.10 - -0.65 V Logic Low Level VOL RL = 100Ω to -2V -2.1 - -1.6 V Output Delay tDO RL = 100Ω to -2V 3.0 3.6 4.2 ns Output Rise Time tr RL = 100Ω to -2V, 20% to 80% - 0.8 - ns Output Fall Time tf RL = 100Ω to -2V, 20% to 80% - 1.0 - ns DYNAMIC CHARACTERISTICS Analog Input Bandwidth fCLK = 140MHz, fIN = 69.999MHz 200 - - MHz Error Rate Error Amplitude ≥ 4 LSB -3dB fS - - 1E-09 TPS (Note 1) fCLK = 140MHz, fIN = 1MHz - 36 - dB S/N Ratio SNR fCLK = 140MHz, fIN = 35MHz 34 dB POWER SUPPLY Supply Current IEE Power Consumption PD AVEE = DVEE = -5.2V -60 -40 -25 mA - 225 - mW Note 1. TPS: Times Per Sample Output Code Table INV: 1 VIN (NOTE) STEP 0V 0 000000 111111 1 000001 111110 • • • • • • 31 011111 100000 32 100000 011111 • • • • • • 62 111110 000001 63 111111 000000 -1.0V -2.0V NOTE: VRT = 0V, VRB = -2V 4-6 D5 D0 INV:0 D5 D0 HI1826 Timing Diagram tDS ANALOG IN N+1 N N+2 tPW0 tPW1 CLKN CLKP DIGITAL OUT 80% N-1 20% N N+1 80% 20% tr tDO tf Test Circuits SIGNAL SOURCE fCLK VIN - 1kHz 4 6 CLKP A ECL LATCH HI1826 B CLKN + COMPARATOR A>B PULSE COUNTER ECL LATCH 2VP-P SINE WAVE DATA 4 1/ SIGNAL SOURCE 4 fCLK FIGURE 1. MAXIMUM CONVERSION RATE MEASUREMENT CIRCUIT +V S2 - S1 + S1: ON FOR A<B S2: ON FOR A>B 70MHz AMP VOSC1 φ:VARIABLE A<B A>B COMPARATOR VIN DUT HI1826 6 A6 A1 A0 B6 VIN BUFFER CLK 6 CLK (140MHz) CONTROLLER LOGIC ANALYZER 1024 SAMPLES “1” 000000 TO 111110 6 HI1826 fr B1 B0 “0” DVM 6 OSC2 ECL BUFFER 70MHZ FIGURE 2. INTEGRAL LINEARITY ERROR MEASUREMENT CIRCUIT, DIFFERENTIAL LINEARITY ERROR MEASUREMENT CIRCUIT FIGURE 3. SAMPLING DELAY MEASUREMENT CIRCUIT APERTURE JITTER MEASUREMENT CIRCUIT 4-7 HI1826 IIN -2V 20 19 18 17 VRBS AGND 25 AGND 21 VRB 22 AGND 23 VIN 24 VRT A VRTS -1V AGND 16 26 AVEE AVEE 15 27 CLKN 14 28 CLKP INV 13 IEE -5.2V A HI1826 29 DVEE DVEE 12 30 D0 (LSB) D5 (MSB) 11 D4 10 2 3 4 5 6 DGND1 1 DGND2 DGND2 32 D2 DGND1 31 D1 7 8 D3 9 FIGURE 4. SUPPLY CURRENT MEASUREMENT CIRCUIT ANALOG INPUT BIAS CURRENT MEASUREMENT CIRCUIT 4-8