HI1276 8-Bit, 500 MSPS, Flash A/D Converter August 1997 Features Description • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB The HI1276 is an 8-bit, ultra-high-speed, flash Analog-toDigital converter IC capable of digitizing analog signals at a maximum rate of 500 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 100K/10KH/10K. • Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.7 LSB • Built-In Integral Linearity Compensation Circuit • Ultra High Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . 500 MSPS The HI1276 is available in the Industrial temperature range and is supplied in a 68 lead ceramic LCC package. • Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 20pF Ordering Information • Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 300MHz PART NUMBER • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . -5.2V TEMP. RANGE (oC) PACKAGE PKG. NO. • Low Power Consumption (Typ) . . . . . . . . . . . . . . . 2.8W • Low Error Rate • Capable of Driving 50Ω Loads HI1276AIL -20 to 100 HI1276-EV 25 68 Ld CLCC J68.B Evaluation Board • Direct Replacement for Sony CXA1276K Applications • Radar Systems • Communication Systems • Digital Oscilloscopes • Direct RF Down-Conversion Pinout AVEE LINV 3 2 1 68 67 66 65 64 63 62 61 DVEE AVEE 4 D1 NC 5 D1 VRTS 6 D0 VRT 7 D0 AVEE 8 OR AVEE 9 OR AGND DGND1 HI1276 (CLCC) HEAT SINK UP, RECESSED CAVITY DOWN NC 10 60 DGND2 NC 11 59 D2 AVEE 12 58 D2 57 DVEE 56 D3 NC 13 AGND 14 VIN1 15 55 D3 VIN1 16 54 DGND2 AGND 17 53 DGND2 VRM 18 52 DGND1 AGND 19 51 DGND1 VIN2 20 50 D4 VIN2 21 49 D4 48 DVEE AGND 22 NC 23 47 D5 NC 24 46 D5 NC 25 45 NC 44 DGND2 NC 26 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-1 DGND1 DVEE D6 D6 D7 D7 MINV CLK CLK AVEE AVEE NC VRBS VRB AVEE AVEE AGND 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 File Number 3578.4 HI1276 Functional Block Diagram MINV 37 R1 VRT 6 VRTS 5 COMPARATOR R/2 R2 0 68 OR R 67 OR 1 R 39 D7 (MSB) 2 38 D7 R 41 D6 40 D6 63 VIN1 47 D5 R 15 46 D5 64 16 R 50 D4 65 OUTPUT 49 D4 56 D3 R 55 D3 126 59 D2 R 58 D2 127 R3 VRM 18 ENCODE LOGIC R 64 D1 128 63 D1 R 66 D0 (LSB) 129 65 D0 R 191 R 192 VIN2 20 R 21 193 R 254 R VRBS 31 R4 255 R/2 VRB 30 R5 CLK 35 CLK 36 CLOCK DRIVER 1 LINV 4-2 HI1276 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . -2.7 to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . AVEE to +0.5V |VRT - VRB |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V CLK, CLK, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DVEE to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7, IOR, ID0 to ID7, IOR) . . . . . . . . . . . . . -30mA to 0mA Thermal Resistance (Typical) θJAoC/W θJCoC/W CLCC Package . . . . . . . . . . . . . . . . . . 18 4 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions (Note 1) Supply Voltage MIN TYP AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V -5.2V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . .-0.05V 0V AGND - DGND . . . . . . . . . . . . . . . . . . . . .-0.05V 0V Temperature Range (Note 5) TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20oC - Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input Voltage, VIN . . . . . . . . . . . . . . MAX -4.95V 0.05V 0.05V MIN -0.1V -2.2V VRB TYP -2 -2 - MAX 0.1V -1.8V VRT 100oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER TA = 25oC, AVEE = DVEE = -5.2V, VRT , VRTS = 0V, VRB , VRBS = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution - 8 - Bits Integral Linearity Error, INL fC = 500 MSPS - ±0.3 ±0.7 LSB Differential Linearity Error, DNL fC = 500 MSPS - ±0.3 ±0.5 LSB Signal to Noise and Distortion Ratio, SINAD Input = 1kHz, Full Scale fC = 500 MSPS RMS Signal = -----------------------------------------------------------------Input = 100MHz, Full Scale RMS Noise + Distor tion fC = 500 MSPS - 46 - dB - 37 - dB Error Rate Input = 100MHz, Full Scale Error > 16 LSB, fC = 400 MSPS - 10-11 10-9 TPS (Note 3) Input = 125MHz, Full Scale Error > 16 LSB, fC = 500 MSPS - 10-8 10-6 TPS (Note 3) NTSC 40 IRE Mod. Ramp, fC = 500 MSPS - 1.0 - % - 0.5 - Degree - 1.0 - ns DYNAMIC CHARACTERISTICS Differential Gain Error, DG Differential Phase Error, DP Overrange Recovery Time Maximum Conversion Rate, fC 500 - - MSPS Aperture Jitter, tAJ Input = 150MHz - 11 - ps Sampling Delay, tDS Input = 150MHz 0.2 0.8 1.5 ns - 20 - pF 30 70 - kΩ - - 850 µA 300 - - MSPS 70 110 160 Ω ANALOG INPUT Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS Analog Input Resistance, RIN Input Bias Current, IIN VIN = -1V Full Scale Input Bandwidth VIN = 2VP-P REFERENCE INPUTS Reference Resistance, RREF 4-3 HI1276 TA = 25oC, AVEE = DVEE = -5.2V, VRT , VRTS = 0V, VRB , VRBS = -2V (Note 1) (Continued) Electrical Specifications PARAMETER Residual Resistance TEST CONDITIONS MIN TYP MAX UNITS 0.1 0.5 2.0 Ω R2 0.5 5.2 10 Ω R3 0.5 1.6 5.0 Ω R4 0.5 8.7 20 Ω R5 0.1 0.5 2.0 Ω -1.10 - - V R1 Note 2 DIGITAL INPUTS Logic H Level, VIH - - -1.55 V Logic H Current, IIH Input Connected to -0.8V 0 - 70 µA Logic L Current, IIL Input Connected to -1.6V -50 - 60 µA - 6 - pF Logic L Level, VIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH RL = 50Ω -1.03 - - V Logic L Level, VOL RL = 50Ω - - -1.58 V 45 50 55 % TIMING CHARACTERISTICS Clock Duty Cycle Output Rise Time, tr RL = 50Ω, 20% to 80% 0.5 0.7 1.0 ns Output Fall Time, tf RL = 50Ω, 80% to 20% 0.5 0.7 1.0 ns 1.5 1.9 2.3 ns -680 -520 - mA - 2.8 3.6 W Output Delay, tOD POWER SUPPLY CHARACTERISTICS Supply Current, IEE Note 4 Power Consumption, PD NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. 2 ( V RT – V RB ) 4. P D = I EEA • AV EE + I EED • DV EE + ------------------------------------- . R REF 5. TA is specified in still air and without heatsink. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2). Timing Diagram tDS ANALOG IN N+2 N+1 tPW1 tPW0 CLK CLK DIGITAL OUT N-1 20% 80% tr tOD FIGURE 1. 4-4 N 80% N+1 20% tf HI1276 Typical Performance Curves -0.45 -0.47 SUPPLY CURRENT (A) THERMAL RESISTANCE θJA (oC/W) 20 10 -0.51 -0.53 -0.55 -50 0 0 1 2 AIR FLOW (m/s) 3 REGISTER STRING CURRENT (mA) -09.0 -0.95 -1.00 -1.05 150 0 50 100 -16 -18 -20 -22 -24 -50 150 0 CASE TEMPERATURE (oC) 50 100 150 CASE TEMPERATURE (oC) FIGURE 4. DO PIN HIGH LEVEL VOLTAGE vs TEMPERATURE CHARACTERISTICS FIGURE 5. REGISTER STRING CURRENT vs TEMPERATURE CHARACTERISTICS -1.30 -1.55 CLK PIN OPEN VOLTAGE (V) -1.60 LOW LEVEL VOLTAGE (V) 100 -14 -0.85 -1.65 -1.70 -1.75 -1.80 -1.85 -50 50 FIGURE 3. SUPPLY CURRENT vs TEMPERATURE CHARACTERISTICS -0.80 -1.10 -50 0 CASE TEMPERATURE (oC) FIGURE 2. THERMAL RESISTANCE MOUNTED ON-BOARD HIGH LEVEL VOLTAGE (V) -0.49 -1.32 -1.34 -1.36 -1.38 -1.40 0 50 100 CASE TEMPERATURE (oC) 150 -50 0 50 100 CASE TEMPERATURE (oC) FIGURE 6. D0 PIN LEVEL VOLTAGE vs TEMPERATURE CHARACTERISTICS FIGURE 7. CLK PIN OPEN VOLTAGE vs TEMPERATURE CHARACTERISTICS 4-5 150 HI1276 Typical Performance Curves (Continued) -20 45 -30 HARMONICS (dB) 50 SINAD (dB) 40 35 30 -40 THIRD HARMONIC -50 SECOND HARMONIC -60 -70 25 -80 20 1 10 100 1 500 10 100 500 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) FIGURE 8. SINAD vs INPUT FREQUENCY CHARACTERISTICS FIGURE 9. HARMONIC DISTORTION vs INPUT FREQUENCY CHARACTERISTICS 10-6 10-6 INPUT FREQUENCY = CLOCK FREQUENCY/4 + 1kHz 16 LSB OR MORE ERROR 10-7 ERROR RATE (TPS) ERROR RATE (TPS) 10-7 10-8 10-9 10-8 10-9 CLOCK FREQUENCY: 500 MSPS INPUT FREQUENCY: 125.001MHz FULL SCALE 16 LSB OR MORE ERROR 10-10 450 10-10 500 550 0 600 50 CLK DUTY CYCLE (%) CLK FREQUENCY (MHz) FIGURE 10. ERROR RATE vs CONVERSION FREQUENCY CHARACTERISTICS 10-3 ERROR RATE (TPS) 10-4 10-5 FIGURE 11. ERROR RATE vs CLOCK DUTY CYCLE CHARACTERISTICS INPUT FREQUENCY = CLOCK FREQUENCY/ 4 + 1kHz FULL SCALE INPUT CLOCK FREQUENCY 500 MSPS 550 MSPS 450 MSPS 10-6 10-7 10-8 10-9 10-10 012345678 12 16 24 THRESHOLD LEVEL (LSB) 32 FIGURE 12. ERROR RATE vs THRESHOLD LEVEL CHARACTERISTICS 4-6 100 HI1276 Pin Descriptions PIN NUMBER SYMBOL 1 37 LINV I/O STANDARD VOLTAGE LEVEL I ECL EQUIVALENT CIRCUIT DESCRIPTION DGND1 43 51 52 61 Polarity Selection for LSBs (refer to the A/D Output Code Table.) Pulled low when left open. MINV Polarity Selection for MSB (refer to the A/D Output Code Table). Pulled low when left open. R R LINV 1 OR MINV 37 R -1.3V R 6 VRT I 0V 42 48 57 62 DVEE VRT Analog Reference Voltage (Top) (0V Typ). 6 5 VRTS O 0V VRTS R2 R1 Reference Voltage Sense (Top). R/2 Reference Voltage Mid Point. Can be used for linearity compensation. R Reference Voltage Sense (Bottom). 5 18 VRM I VRB/2 31 VRBS O -2V 30 VRB I -2V Analog Reference Voltage (Bottom). VRM R3 18 R TO COMPARATORS R VRBS R4 R/2 31 R5 VRB 30 15, 16 20, 21 VIN1 VIN2 I VRTS to VRBS VIN1 AGND 9, 14, 17, 19, 22, 27 15 TO COMP. 0 TO 127 16 20 128 TO 255 21 VIN2 4-7 Analog Input. All of the pins must be wired externally. HI1276 Pin Descriptions PIN NUMBER SYMBOL 35 CLK 36 CLK (Continued) I/O STANDARD VOLTAGE LEVEL I ECL EQUIVALENT CIRCUIT DESCRIPTION DGND1 43 CLK Input. Complementary CLK Input. Pulled down to -1.3V when left open. 51 52 R 61 R CLK R R 35 CLK 36 42 48 R 57 R 62 DVEE 38, 39 D7, D7 O ECL 44 53 DGND2 54 40, 41 D6, D6 46, 47 D5, D5 49, 50 D4, D4 55, 56 D3, D3 58, 59 D2, D2 63, 64 D1, D1 65, 66 D0, D0 67, 68 OR, OR 2, 3, 7, 8, 12, 28, 29, 33, 34 AVEE 9, 14, 17, 19, 22, 27 AGND 42, 48, 57, 62 DVEE 43, 51, 52, 61 DGND1 0V 44, 53, 54, 60 DGND2 (Note 6) 0V 60 MSB and Complementary Msb Data Output. D1 to D6: Data output D1 to D6: Complementary data output DI DI DVEE - AGND -5.2V DGND1 9 17 22 43 52 14 19 27 51 61 42 48 57 62 Overrange and Complementary Overrange Output. DGND2 44 53 54 0V -5.2V LSB Data Complementary Output LSB Data Output. 60 Analog Supply. Internally connected to DVEE (resistance: 4Ω to 6Ω). Analog Ground. INTERNAL ANALOG CIRCUIT INTERNAL DIGITAL CIRCUIT Digital Supply. Internally connected to AVEE (resistance: 4Ω to 6Ω). 4Ω TO 6Ω 2 8 29 42 57 3 12 33 48 62 7 28 34 DVEE D1 D1 Digital Ground. Digital Ground for Output Drive. AVEE 4, 10, 11, 13, 23, 24, 25, 26, 32 NC No-Connect pins. It is recommended to wire these pins to AGND. 45 NC No-Connect pin. It is recommended to wire these pins to DGND. NOTE: 6. VRT = VRTS = 0V, VRM = -1V or open, VRB = VRBS = -2V 4-8 HI1276 A/D OUTPUT CODE TABLE MINV 1, LINV 1 (NOTE 1) VIN STEP D7 D0 OR 1, 0 D7 D0 OR D7 0, 0 D0 OR D0 D7 1 000 • • • • • 00 1 100 • • • • • 00 1 011 • • • • • 11 1 111 • • • • • 11 0 1 0 0 0 0 254 255 0 0 0 011 • • • • • 11 011 • • • • • 10 • • • 000 • • • • • 00 111 • • • • • 11 • • • 100 • • • • • 01 100 • • • • • 00 100 • • • • • 00 0 0 0 0 100 • • • • • 00 100 • • • • • 01 • • • 111 • • • • • 11 000 • • • • • 00 • • • 011 • • • • • 10 011 • • • • • 11 011 • • • • • 11 0 0 127 128 000 • • • • • 00 000 • • • • • 01 • • • 011 • • • • • 11 100 • • • • • 00 • • • 111 • • • • • 10 111 • • • • • 11 111 • • • • • 11 111 • • • • • 11 111 • • • • • 10 • • • 100 • • • • • 00 011 • • • • • 11 • • • 000 • • • • • 01 000 • • • • • 00 000 • • • • • 00 0V -1V OR 0, 1 -2V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test Circuits FUNCTION GENERATOR 100 VIN 1 2 AMP 2Ω 8 DUT HI1276 8 ECL LATCH 110 NTSC SIGNAL SOURCE HI20201 100 AMP fms 10 BIT D/A 0V 110 -2V CLK CLK 2 1 -4.5V DIVIDER SG (CW) VECTOR SCOPE OSCILLOSCOPE DG/DP MAXIMUM CONVERSION RATE SWITCH POSITION 1. MAXIMUM CONVERSION RATE 2. DG/DP 50 DUTY FIGURE 13. MAXIMUM CONVERSION RATE AND DIFFERENTIAL GAIN/PHASE ERROR TEST CIRCUIT +V S2 - S1 : A < B : ON S2 : A > B : ON S1 + -V A<B A>B COMPARATOR VIN DUT HI1276 8 DVM “0” CLK (250 MSPS) A8 TO A1 A0 B8 TO B1 B0 CONTROLLER 8 BUFFER “1” 8 000 • • • 00 TO 111 • • • 10 FIGURE 14. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT 4-9 HI1276 Test Circuits (Continued) -5.2V A IEED 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 HI1276 -2V 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A IEEA A IIN -5.2V -1V FIGURE 15. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT 0V -1V VIN -2V 100MHz AMP CLK OSC1 φ: VARIABLE VIN fR HI1276 CLK OSC2 100MHz 8 ∆υ ∆t LOGIC ANALYZER t VIN 1024 SAMPLES ECL BUFFER CLK 129 128 127 126 125 σ (LSB) APERTURE JITTER Aperture jitter is defined as follows: ∆υ 256 t AJ = σ ⁄ ------- = σ ⁄ ---------- × 2πf , 2 ∆t Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 16A. FIGURE 16B. APERTURE JITTER TEST METHOD FIGURE 16. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT 4-10 HI1276 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-11 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029