HI1106 ® January 1998 Features NS ESIG D EW t RN O F ter a n D e E C 1 END /tsc port I1 1 7 OMM See H cal Sup rsil.com C E i R c hn . i nt e N OT r Te r w w w u High o o t ntac ERSIL o c T or 8-IN 1-88 8-Bit, 35 MSPS, Speed D/A Converter (TTL Input) Description • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit • High Speed Operation . . . . . . . . . . . . . . . . . . . . . 35MHz (Maximum Conversion Speed) • Non-Linearity . . . . . . . . . . . . . . . . . Less Than ±1/2 LSB The HI1106 is an 8-bit, 35MHz, high-speed D/A converter IC. Summing type current for the upper 2 bits and ladder type resistance for the lower 6 bits, ensures a low power consumption of 200mW (single power supply). • Low Glitch This IC is suitable for digital TVs, graphic displays and otherapplications. • TTL Compatible Input Ordering Information • Power Supply - Single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V - Dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V • Low Power Consumption - +5V Single Power Supply (Typ) . . . . . . . . . . 200mW - ±5V Dual Power Supply (Typ) . . . . . . . . . . . . 400mW PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. HI1106JCB -20 to 75 24 Ld SOIC M24.2-S HI1106JCP -20 to 75 24 Ld PDIP E24.4-S • Direct Replacement for the Sony CXA1106 Pinout HI1106 (PDIP, SOIC) TOP VIEW VREF 1 24 VSET AGND1 2 23 VEE AGND2 3 22 NC AOUT 4 21 NC DGND2 5 20 D0 (LSB) VCC 6 19 D1 DGND1 7 18 D2 NC 8 17 D3 CLK 9 16 D4 D7 (MSB) 10 15 D5 NC 11 14 NC D6 12 13 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 10-1 File Number 4113.3 HI1106 Functional Block Diagram DGND2 5 INPUT BUFFER D5 15 D4 16 DIGITAL DATA INPUT D3 17 D2 18 3 6 D1 19 4 3 6 CURRENT SWITCH 2 CLOCK SYNCHRONIZED CIRCUIT D6 12 DECODER 23 VEE D7 10 (MSB) D0 20 (LSB) VCC R R R 2R R 2R R 2R R 2R R 2R CLOCK BUFFER 6 3 -+ 7 VSET AGND1 INTERNAL REFERENCE VOLTAGE 24 CLK DGND1 AGND2 R 2 9 AOUT ANALOG OUTPUT 1 VREF Pin Descriptions PIN NO. SYMBOL 1 VREF EQUIVALENT CIRCUIT AGND1 2 AGND2 1 DESCRIPTION Internal Reference Voltage Output pin 1.2V (Typ). An external pull down resistance is necessary. For reference see Notes on Application 1. VEE 23 2 AGND1 Set to Analog VCC for signal power supply and to Analog GND for dual power supply. Connect to AGND2 and use. 3 AGND2 Connect to AGND1. 4 AOUT Analog Output pin. AGND2 3 RO 4 VEE 23 Set to Digital VCC for signal power supply and to Digital GND for dual power supply. 5 DGND2 6 VCC Digital VCC . 7 DGND1 Digital GND. 10-2 HI1106 Pin Descriptions PIN NO. SYMBOL 8 NC 9 CLK (Continued) EQUIVALENT CIRCUIT DESCRIPTION No Connect. Clock Input pin. VCC 6 9 7 DGND1 10, 12, 15 - 20 D7, D6, D5 - D0 Digital Input pin. D1 to MSB, D8 to LSB VCC 6 10, 12 15 TO 20 DGND1 7 11, 13, 14 NC No Connect 21, 22 NC Connect to AGND or VEE . 23 VEE Set to Analog GND for single power supply and to VEE for dual power supply. 24 VSET AGND1 Bias Input pin. Normally set VSET - VEE to 0.84V. For reference see Notes on Application 1. 2 24 VEE 23 NOTE: See the Application Circuit for reference. 10-3 HI1106 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage VCC - DGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 6V VEE - AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0V DGND2 - DGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 6V Digital Input Voltage VI . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1 - 0.3V to VCC + 0.3V VCLK . . . . . . . . . . . . . . . . . . . . . . . . DGND1 - 0.3V to VCC + 0.3V Input Voltage (V SET Pin), VSET . . . . . . . . VEE - 0.3V to VEE + 2.7V Output Current (V REF Pin), lREF . . . . . . . . . . . . . . . . . -5mA to 0mA Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . 1.27W Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Recommended Operating Conditions SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage VCC, DGND2, AGND1, AGND2 . . . . . . . . 4.75V 5V 5.25V DGND2 - AGND1, DGND2 - AGND2 . . . . -0.2V 0V 0.2V AGND1 - AGND2 . . . . . . . . . . . . . . . . . . . -0.1V 0V 0.1V Digital Input Voltage H Level, VIH, VCLKH . . . . . . . . . . . . . . . . . 2.0V VCC L Level, VIL, VCLKL . . . . . . . . . . . . . . . . . .DGND1 1V VSET Input Voltage, VSET . . . . . . . . . . . . . . 0.70V 0.84V 1V VREF Pin Current, IREF . . . . . . . . . . . . . . . .-3.0mA -0.4mA Clock Pulse Width (Note 1) tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns Temperature Range, TOPR . . . . . . . . . . . . . . . . . . . . -20oC to 75oC DUAL POWER SUPPLY Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND2 - AGND1, DGND2 - AGND2 . . . AGND1 - AGND2. . . . . . . . . . . . . . . . . . . Digital Input Voltage H Level, VIH , VCLKH . . . . . . . . . . . . . . . . L Level, VIL , VCLKL . . . . . . . . . . . . . . . . . VSET Input Voltage, VSET. . . . . . . . . . . . . . VREF Pin Current, IREF. . . . . . . . . . . . . . . . Clock Pulse Width tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIN TYP MAX 4.75V -5.5V -0.2V -0.1V 5V 5V 0V 0V 5.25V -4.75V -0.2V 0.1V 2.0V VCC DGND1 1V -4.30V -4.16V -4.00V -3mA -0.4mA 10ns 10ns - - CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. See Figure 6 in the Timing Diagram. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VCC = DGND2 = AGND1 = AGND2 = 5V, DGND1 = VEE = 0V, VSET = 0.84V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SINGLE POWER SUPPLY Resolution, n Maximum Conversion Speed, fMAX RL > 10kΩ, CL < 20pF Linearity Error, EL RL > 10kΩ Differential Linearity Error, ED Full Scale Output Voltage, VFS RL > 10kΩ Offset Voltage (Note 2), VOS RL > 10kΩ Output Resistance, RO Power Supply Current, ICC RL > 10kΩ, IREF = -400µA - 8 - Bit 35 - - MHz -0.5 - 0.5 LSB -0.5 - 0.5 LSB 0.9 1.0 1.1 V 0 4 10 mV 290 350 410 Ω 32 40 48 mA Digital Input Current H Level, IIH 0 - 5 µA L Level, IIL -400 - 0 µA -3 - 0 µA VSET Input Current, ISET Internal Reference Output Voltage, VREF IREF = -400µA 1.17 1.25 1.33 V Accuracy Output Voltage Range, VOC RL > 10kΩ 0.5 1.0 1.50 V 10 - - ns 2 - - ns Set-Up Time, tS Hold Time, tH Propagation Delay Time, tPD RL > 10kΩ - 11 - ns Glitch Energy, GE RL > 10kΩ, fCLK = 1MHz, Digital Lamp Output - 30 - pV/s NOTE: 3. V OS = AGND2 - V255 (V255 is the output voltage when full input is at high level). 10-4 HI1106 Electrical Specifications TA = 25oC, VCC = 5V, DGND1 = DGND2 = AGND1 = AGND2 = 0V, VEE = -5V, VSET - VEE = 0.84V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT - 8 - Bit 35 - - MHz -0.5 - 0.5 LSB -0.5 - 0.5 LSB DUAL POWER SUPPLY Resolution, n Maximum Conversion Speed, fMAX RL > 10kΩ, CL < 20pF Linearity Error, EL RL > 10kΩ Differential Linearity Error, DNL Full Scale Output Voltage, VFS RL > 10kΩ 0.9 1.0 1.1 V Offset Voltage, VOS RL > 10kΩ 0 4 10 mV 290 350 410 Ω 24 30 36 mA 40 50 60 mA H Level, IIH 0 - 5 µA L Level, IIL -400 - 0 µA -3 - 0 µA -3.83 -3.75 -3.67 V 0.5 1.0 1.50 V 10 - - ns 2 - - ns Output Resistance, RO Power Supply Current RL > 10kΩ, IREF = -400µA ICC IEE Digital Input Current VSET Input Current, ISET Internal Reference Output Voltage, VREF IREF = -400µA Accuracy Output Voltage Range, VOC RL > 10kΩ Set-Up Time, tS Hold Time, tH Propagation Delay Time, tPD RL > 10kΩ - 11 - ns Glitch Energy, GE RL > 10kΩ, fCLK = 1MHz Digital Lamp Output - 30 - pV/s INPUT/OUTPUT CODE TABLE (When Output Full Scale Voltage at 1.00V) INPUT CODE MSB LSB OUTPUT VOLTAGE (SINGLE SUPPLY) OUTPUT VOLTAGE (DUAL SUPPLY) 1 1 1 1 1 1 1 1 VCC -0V 1 0 0 0 0 0 0 0 V CC -0.5V -0.5V 0 0 0 0 0 0 0 0 VCC -1V -1V 10-5 HI1106 Test Circuits (MSB) D7 D6 D5 1 10 24 12 23 15 VREF VSET 3K 0.47µ VEE V HI1106 2 (LSB) D0 VCC DGND1 CLK TTL LEVEL SINGLE POWER SUPPLY CLK 20 3 AGND1 AGND2 6 V 7 4 9 5 AOUT DGND2 DUAL POWER SUPPLY DVCC AVCC DGND AGND VEE FIGURE 1. DC CHARACTERISTICS (MSB) D7 D6 D5 8-BIT COUNTER (TTL LATCH OUTPUT) 1 10 24 12 23 15 HI1106 (LSB) D0 VCC DGND1 CLK 2 3 20 VREF VSET 0.47µ VEE AGND1 AGND2 6 7 4 9 5 3K V AOUT DIGITAL LAMP WAVEFORM OCCURRENCE OSCILLOSCOPE RIN = 1MΩ CIN = 10pF BW = 20MHz DGND2 CLK 35MHz TTL LEVEL SQUARE WAVEFORM CLK SINGLE POWER SUPPLY DUAL POWER SUPPLY 2ns TO 14ns DATA DVCC AVCC DGND AGND VEE TIMING BETWEEN CLK AND DATA FIGURE 2. MAXIMUM CONVERSION SPEED 10-6 HI1106 Test Circuits (Continued) (MSB) D7 D6 D5 8-BIT COUNTER (TTL LATCH OUTPUT) 1 10 24 12 23 15 HI1106 (LSB) D0 VCC PULSE GENERATOR 1MHz TTL DGND1 CLK 2 3 20 VREF VSET 4 9 5 V AGND1 AGND2 6 7 3K 0.47µ VEE AOUT DIGITAL LAMP WAVEFORM OCCURRENCE OSCILLOSCOPE RIN = 1MΩ CIN = 20pF BW = 5MHz DGND2 DELAY CONTROLLING PULSE GENERATOR 1MHz TTL FET PROBE FET PROBE SINGLE POWER SUPPLY DUAL POWER SUPPLY OSCILLOSCOPE RIN = 50Ω CIN = 10pF BW = 200MHz DVCC AVCC DGND AGND VEE FIGURE 3. SET-UP TIME AND HOLD TIME 10-7 HI1106 Test Circuits (Continued) (MSB) D7 D6 D5 8-BIT COUNTER (TTL LATCH OUTPUT) 1 10 24 12 23 15 HI1106 (LSB) D0 VCC DGND1 CLK 2 3 20 VREF VSET 0.47µ VEE AGND1 AGND2 6 7 4 9 5 3K V AOUT DGND2 CLK 1MHz TTL LEVEL SQUARE WAVEFORM DIGITAL LAMP WAVEFORM OCCURRENCE OSCILLOSCOPE RIN = 1MΩ CIN = 10pF BW =5MHz CLK SINGLE POWER SUPPLY DUAL POWER SUPPLY 2ns TO 90ns DATA DVCC AVCC DGND AGND VEE TIMING BETWEEN CLK AND DATA FIGURE 4. GLITCH AREA 10-8 HI1106 Test Circuits (Continued) D7 D6 D5 1/ DIVIDER 2 1 10 24 12 23 15 HI1106 D0 VCC DGND1 CLK 20 2 3 VREF VSET 0.47µ VEE AGND1 AGND2 6 7 5 9 4 DGND2 AOUT FET PROBE CLK 10MHz TTL LEVEL SQUARE WAVEFORM SINGLE POWER SUPPLY 3K V FET PROBE OSCILLOSCOPE RIN = 50Ω CIN = 10pF BW = 200MHz CLK DUAL POWER SUPPLY 2ns TO 90ns DATA DVCC AVCC DGND AGND VEE TIMING BETWEEN CLK AND DATA FIGURE 5. PROPAGATION DELAY TIME 10-9 HI1106 Timing Diagram tPW1 tPW0 VTH = 1.5V CLK tS tS tS tH tH tH DATA VTH = 1.5V tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 6. Typical Performance Curves TA = 25oC VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0 2.0 VFS (V) VFS (V) 2.0 RL = 330Ω 1.0 0 TA = 25 oC VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0 VEE = -5V RL > 10kΩ 1.0 VSET (V) 2.0 RL = 330Ω 1.0 0 FIGURE 7. FULL-SCALE OUTPUT VOLTAGE (VFS) vs VSET (SINGLE POWER SUPPLY) RL > 10kΩ 1.0 VSET - VEE (V) FIGURE 8. FULL-SCALE OUTPUT VOLTAGE (VFS) vs VSET - VEE (DUAL POWER SUPPLY) 10-10 2.0 HI1106 Typical Performance Curves (Continued) 1.02 TA - VFS / VFS (25oC) TA - VFS / VFS (25oC) 1.02 1.00 0.98 VSET = 0.84V IREF = -400µA VCC = DGND2 = AGND1 0.96 = AGND2 = 5V DGND1 = VEE = 0 RL ≥ 10kΩ -20 0 1.00 0.98 0.96 20 40 60 80 -20 TA , AMBIENT TEMPERATURE (oC) 2.5 2.5 2.0 2.0 VOS (mV) VOS (mV) 3.0 -20 VSET = 0.84V IREF = -400µA VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0V RL ≥ 10kΩ 0 20 40 60 1.5 1.0 80 -20 TA , AMBIENT TEMPERATURE (oC) FIGURE 11. OUTPUT OFFSET VOLTAGE (VOS) vs TEMPERATURE (SINGLE POWER SUPPLY) 20 40 60 80 FIGURE 10. FULL-SCALE OUTPUT VOLTAGE (VFS) vs TEMPERATURE (DUAL POWER SUPPLY) 3.0 1.0 0 TA , AMBIENT TEMPERATURE (oC) FIGURE 9. FULL-SCALE OUTPUT VOLTAGE (VFS) vs TEMPERATURE (SINGLE POWER SUPPLY) 1.5 VSET - VEE = 0.84V IREF = -400µA VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V RL ≥ 10kΩ VSET - VEE = 0.84V IREF = -400µA VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V RL ≥ 10kΩ 0 20 40 60 TA , AMBIENT TEMPERATURE (oC) FIGURE 12. OUTPUT OFFSET VOLTAGE (VOS) vs TEMPERATURE (DUAL POWER SUPPLY) 10-11 80 HI1106 Typical Performance Curves IREF = -400µA VCC = 5V IREF = -400µA VCC = DGND2 = AGND1 AGND2 = 5V DGND1 = VEE = 0V 1.260 1.250 VREF (V) VREF (V) 1.260 (Continued) 1.240 1.230 DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V 1.250 1.240 1.230 -20 0 20 40 60 80 -20 0 TA , AMBIENT TEMPERATURE (oC) 40 60 80 TA , AMBIENT TEMPERATURE (oC) FIGURE 13. INTERNAL REFERENCE VOLTAGE (V REF) vs TEMPERATURE (SINGLE POWER SUPPLY) FIGURE 14. INTERNAL REFERENCE VOLTAGE (V REF) vs TEMPERATURE (DUAL POWER SUPPLY) VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0V VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V 2.0 VTH (V) VTH (V) 2.0 20 1.0 1.5 -20 0 20 40 60 80 -20 0 20 40 60 80 TA , AMBIENT TEMPERATURE (oC) TA , AMBIENT TEMPERATURE (oC) FIGURE 15. THRESHOLD VOLTAGE (VTH) OF DIGITAL INPUT vs TEMPERATURE (SINGLE POWER SUPPLY) FIGURE 16. THRESHOLD VOLTAGE (VTH) OF DIGITAL INPUT vs TEMPERATURE (DUAL POWER SUPPLY) 1.050 1.000 VFS (V) VOS (V) 3 TA = 25 oC VSET = 0.84V VCC = DGND2 = AGND1 2 = AGND2 DGND1 = VEE = 0V RL ≥ 10kΩ 1 4.5 5.0 VCC (V) 0.950 0.900 0.850 4.5 5.5 FIGURE 17. OUTPUT OFFSET VOLTAGE (VOS) vs SUPPLY VOLTAGE (SINGLE POWER SUPPLY) TA = 25oC VSET = 0.84V VCC = DGND2 = AGND1 = AGND2 DGND1 = VEE = 0V RL ≥ 10kΩ 5.0 VCC (V) 5.5 FIGURE 18. OUTPUT FULL-SCALE VOLTAGE (V FS) vs SUPPLY VOLTAGE (DUAL POWER SUPPLY) 10-12 Typical Performance Curves VFS (V) 1.260 (Continued) TA = 25 oC I REF = -400µA VCC = DGND2 = AGND1 = AGND2 DGND1 = VEE = 0V 1.250 1.240 1.230 4.5 5.0 5.5 VCC (V) FIGURE 19. INTERNAL REFERENCE VOLTAGE (VREF) vs SUPPLY VOLTAGE (SINGLE POWER SUPPLY) Application Circuits 13 8-BIT DIGITAL INPUT (TTL) D5 D4 D3 D2 D1 D0 NC NC VEE VSET 12 D6 16 D7 11 (MSB) 10 CLK 9 17 8 18 7 19 6 20 5 21 4 22 3 23 2 24 1 14 15 CLK (TTL) DGND1 VCC DGND2 - AOUT AGND2 AGND1 VREF 3K FIGURE 20. SINGLE POWER SUPPLY 10-13 + R† † LPF D/AOUT MATCHING RESISTANCE FOR LPF Application Circuits 13 8-BIT DIGITAL INPUT (TTL) D3 D2 D1 NC NC VEE VSET 16 17 8 18 7 19 6 20 5 21 4 22 3 15 D4 D6 D7 11 (MSB) 10 CLK 9 14 D5 D0 (LSB) 12 23 2 24 1 CLK (TTL) DGND1 VCC DGND2 - AOUT AGND2 AGND1 R † LPF + † D/A OUT MATCHING RESISTANCE FOR LPF VREF 3K DVCC AVCC DGND AGND VEE FIGURE 21. DUAL POWER SUPPLY Notes On Application 1. Setting of VREF Pin (Pin 24) The full-scale voltage of the D/A output is determined by VSET input voltage. As about (1.2V - VEE) DC voltage is generated at VREF pin (Pin 1) by connecting an external resistor from VREF pin to VEE pin (Pin 23), divide this voltage using resistors and apply it to VSET pin as Figure 22. Example of usage: 1 24 23 VREF IREF VSET VEE R VSET 3. D/A Output Pin Load Receive the D/A output stage at high impedance, so as to obtain: RL > 10kΩ, CL < 20pF. SINGLE POWER SUPPLY AGND DUAL POWER SUPPLY 2. Phase Relation Between Data and Clock To make the best use of the inherent characteristics of this D/A converter the phase relation between the data and clock applied from the exterior, should be properly set. Set up time (tS) and Hold time (tH ) should be as indicated in the Electrical Specifications. For tS and tH refer to Figure 6 in the Timing Waveform. Also, set the clock pulse width according to the Recommended Operating Conditions. 4. Noise Reduction Refer to the following notes in order to minimize noise contamination that occurs from outside the IC and penatrates D/A output. VEE FIGURE 22. The full-scale voltage of the D/A output can be determined from the following equation: VFS = 1.2 (VSET - VEE) (RL > 10kΩ, 0.4V ≤ VSET ≤ 1.2V Select an external resistor R (connected to VREF pin) so that IREF (current of an external resistor) is within the value indicated as the Recommended Operating Conditions of (-3mA < IREF < -0.4mA). 10-14 • The power supply line and ground line should be made as wide as possible when fixed to the printed circuit board. Analog and Digital circuits should be separated. • Connected a bypass capacitor between each of DVCC (Pin 6) and DGND1 (Pin 7); AGND1, 2 (Pins 2, 3) and VEE (Pin 23); VSET (Pin 24) and V EE (Pin 23), respectively.