HD74ALVC16836 20-bit Universal Bus Driver with 3-state Outputs ADE-205-209 (Z) Preliminary 1st. Edition January 1998 Description This 20-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE) input. The device operates in the transparent mode when the latch enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@V CC = 3.0 V) HD74ALVC16836 Function Table Inputs Output Y OE LE CLK A H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H H L H H X Y0 *1 L H L X Y0 *2 H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established, provided that CLK is high before LE goes low. 2. Output level before the indicated steady state input conditions were established. 2 HD74ALVC16836 Pin Arrangement OE 1 56 CLK Y1 2 55 A1 Y2 3 54 A2 53 GND GND 4 Y3 5 52 A3 Y4 6 VCC 7 51 A4 Y5 8 49 A5 Y6 9 48 A6 Y7 10 47 A7 50 VCC GND 11 46 GND Y8 12 45 A8 Y9 13 44 A9 Y10 14 43 A10 Y11 15 42 A11 Y12 16 41 A12 Y13 17 40 A13 GND 18 39 GND Y14 19 38 A14 Y15 20 37 A15 Y16 21 36 A16 VCC 22 35 VCC Y17 23 34 A17 Y18 24 33 A18 GND 25 32 GND Y19 26 31 A19 Y20 27 30 A20 NC 28 29 LE (Top view) 3 HD74ALVC16836 Absolute Maximum Ratings Item Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VCC +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin I CC or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 1 W Storage temperature Tstg –65 to 150 °C Supply voltage Input voltage *1 Output voltage Notes: *1, 2 Conditions TSSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current I OH — –12 mA — –12 VCC = 2.7 V — –24 VCC = 3.0 V — 12 — 12 VCC = 2.7 V — 24 VCC = 3.0 V Low level output current I OL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. 4 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVC16836 Logic Diagram OE CLK LE A1 1 56 29 55 1D C1 CLK 2 Y1 To nineteen other channels 5 HD74ALVC16836 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Max Unit Test Conditions Input voltage VIH 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 2.3 to 3.6 VCC–0.2 — 2.3 2.0 — I OH = –6 mA, VIH = 1.7 V 2.3 1.7 — I OH = –12 mA, VIH = 1.7 V 2.7 2.2 — I OH = –12 mA, VIH = 2.0 V 3.0 2.4 — I OH = –12 mA, VIH = 2.0 V 3.0 2.0 — I OH = –24 mA, VIH = 2.0 V 2.3 to 3.6 — 0.2 I OL = 100 µA 2.3 — 0.4 I OL = 6 mA, VIL = 0.7 V 2.3 — 0.7 I OL = 12 mA, VIL = 0.7 V 2.7 — 0.4 I OL = 12 mA, VIL = 0.8 V 3.0 — 0.55 I OL = 24 mA, VIL = 0.8 V VIL Output voltage VOH VOL V I OH = –100 µA Input current I IN 3.6 — ±5 µA VIN = VCC or GND Off state output current I OZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current I CC 3.6 — 40 µA VIN = VCC or GND 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at V CC or GND ∆I CC 6 HD74ALVC16836 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Maximum clock frequency f max Propagation delay time Output enable time Output disable time Input capacitance Output capacitance Typ Max Unit 2.5±0.2 150 — — MHz 2.7 150 — — 3.3±0.3 150 — — t PLH 2.5±0.2 1.0 — 4.2 t PHL 2.7 — 4.2 3.3±0.3 1.0 — 3.6 2.5±0.2 1.3 — 5.0 2.7 — 4.9 3.3±0.3 1.3 — 4.2 2.5±0.2 1.4 — 5.5 2.7 — 5.2 3.3±0.3 1.4 — 4.5 t ZH 2.5±0.2 1.4 — 5.5 t ZL 2.7 — 5.6 3.3±0.3 1.1 — 4.6 t HZ 2.5±0.2 1.0 — 4.5 t LZ 2.7 — 4.3 3.3±0.3 1.3 — 3.9 3.3 — 3.5 — 3.3 — 6.0 — 3.3 — 7.0 — CIN CO Min — — — — — FROM (Input) TO (Output) A Y LE Y CLK Y ns OE Y ns OE Y pF Control inputs ns Data inputs pF Outputs 7 HD74ALVC16836 Switching Characteristics (Ta = –40 to 85°C) (cont) Item Symbol VCC (V) Min Typ Max Unit FROM (Input) Setup time t su 2.5±0.2 1.4 — — ns Data before CLK↑ 2.7 1.7 — — 3.3±0.3 1.5 — — 2.5±0.2 1.2 — — Data before LE↑ 2.7 1.6 — — CLK “H” 3.3±0.3 1.3 — — 2.5±0.2 1.4 — — Data before LE↑ 2.7 1.5 — — CLK “L” 3.3±0.3 1.2 — — 2.5±0.2 0.9 — — 2.7 0.9 — — 3.3±0.3 0.9 — — 2.5±0.2 1.1 — — Data after LE↑ 2.7 1.1 — — CLK “H” or “L” 3.3±0.3 1.1 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — Hold time Pulse width 8 th tw ns ns Data after CLK↑ LE “L” CLK “H” or “L” HD74ALVC16836 Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ Note: 1. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 2 × VCC 6.0 V CL includes probe and jig capacitance. 9 HD74ALVC16836 Waveforms – 1 tr tf 90 % Input VIH 90 % Vref Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND 10 HD74ALVC16836 Waveforms – 3 tf tr Output Control VIH 90 % 90 % Vref Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B Vref1 VOL t HZ VOH Vref2 Vref ≈VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1 Notes: 1. 2. 3. 4. Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V VCC 2.7 V 1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH–0.15 V VOH–0.3 V VCC 3.0 V GND GND All input pulses are supplied by generators having the following characteristics : PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V) PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V) Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. The output are measured one at a time with one transition per measurement. 11 HD74ALVC16836 Package Dimensions Unit : mm +0.3 14.00 –0.1 29 6.10 +0.3 –0.1 56 0.20 +0.1 –0.05 0.50 28 0.08 M 0.15 ± 0.05 1 1.20 max 0.10 0.05 Min 0.40 Max 8.10 ± 0.3 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code 12 TTP-56D — — HD74ALVC16836 When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 13