ETC HD74ACT298RP

HD74ALVCH16832
1-to-4 Address Register / Driver with 3-state Outputs
ADE-205-214B (Z)
3rd. Edition
January 2001
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation.
The device is ideal for use in applications in which a single address bus is driving four separate memory
locations. The HD74ALVCH16832 can be used as a buffer or a register, depending on the logic level of
the select (SEL) input.
When SEL is a logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) inputs. Each OE controls two groups of seven outputs.
When SEL is a logic low, the device is in the register mode. The register is an edge triggered D-type flip
flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal
registers. OE controls operate the same as in the buffer mode.
When OE is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a
logic high, the outputs are in the high impedance state.
Neither SEL nor OE affect the internal operation of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down, OE should be tied to V CC through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
•
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@V CC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16832
Function Table
Inputs
Output Y
OE
SEL
CLK
A
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
2
HD74ALVCH16832
Pin Arrangement
4Y1 1
64 1Y2
3Y1 2
63 2Y2
GND 3
62 GND
2Y1 4
61 3Y2
1Y1 5
60 4Y2
6
59 VCC
A1 7
58 1Y3
GND 8
57 2Y3
VCC
56 GND
A2 9
GND 10
55 3Y3
A3 11
54 4Y3
VCC 12
53 GND
NC 13
GND 14
52 VCC
CLK 15
50 1Y4
OE1 16
49 2Y4
OE2 17
48 3Y4
SEL 18
47 4Y4
GND 19
46 GND
51 GND
A4 20
45 1Y5
A5 21
44 2Y5
VCC 22
43 VCC
GND 23
42 3Y5
A6 24
41 4Y5
GND 25
40 GND
A7 26
39 GND
VCC 27
38 VCC
4Y7 28
37 1Y6
3Y7 29
36 2Y6
GND 30
35 GND
2Y7 31
34 3Y6
1Y7 32
33 4Y6
(Top view)
3
HD74ALVCH16832
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
VO
–0.5 to VCC +0.5
V
Input clamp current
I IK
–50
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
I CC or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Supply voltage
Input voltage
*1
Output voltage
Notes:
*1, 2
Conditions
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
I OH
—
–12
mA
—
–12
VCC = 2.7 V
—
–24
VCC = 3.0 V
—
12
—
12
VCC = 2.7 V
—
24
VCC = 3.0 V
Low level output current
I OL
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
4
Conditions
VCC = 2.3 V
VCC = 2.3 V
HD74ALVCH16832
Logic Diagram
OE1
16
OE2
17
CLK
5
15
4
CLK
2
A1
7
D
2Y1
3Y1
Q
1
SEL
1Y1
4Y1
18
To six other channels
5
HD74ALVCH16832
Electrical Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Input voltage
VIH
Min
Max
Unit
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
2.3 to 3.6
VCC–0.2
—
2.3
2.0
—
I OH = –6 mA, VIH = 1.7 V
2.3
1.7
—
I OH = –12 mA, VIH = 1.7 V
2.7
2.2
—
I OH = –12 mA, VIH = 2.0 V
3.0
2.4
—
I OH = –12 mA, VIH = 2.0 V
3.0
2.0
—
I OH = –24 mA, VIH = 2.0 V
2.3 to 3.6
—
0.2
I OL = 100 µA
2.3
—
0.4
I OL = 6 mA, VIL = 0.7 V
2.3
—
0.7
I OL = 12 mA, VIL = 0.7 V
2.7
—
0.4
I OL = 12 mA, VIL = 0.8 V
3.0
—
0.55
I OL = 24 mA, VIL = 0.8 V
I IN
3.6
—
±5
I IN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V *2
I OZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current I CC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6) V,
other inputs at V CC or GND
VIL
Output voltage
VOH
VOL
Input current
Off state output current
∆I CC
V
µA
Test Conditions
I OH = –100 µA
VIN = VCC or GND
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2. This is the bus hold maximum dynamic current required to switch the input from one state to
another.
6
HD74ALVCH16832
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
2.5±0.2
150
—
—
MHz
2.7
150
—
—
3.3±0.3
150
—
—
t PLH
2.5±0.2
1.2
—
4.0
t PHL
2.7
—
—
4.1
3.3±0.3
1.6
—
3.6
2.5±0.2
1.1
—
4.5
2.7
—
—
4.4
3.3±0.3
1.5
—
3.9
2.5±0.2
1.3
—
5.2
2.7
—
—
5.2
3.3±0.3
1.7
—
4.4
t ZH
2.5±0.2
1.1
—
5.1
t ZL
2.7
—
—
5.0
3.3±0.3
1.2
—
4.3
t HZ
2.5±0.2
1.4
—
5.5
t LZ
2.7
—
—
4.7
3.3±0.3
1.6
—
4.5
2.5±0.2
2.0
—
—
2.7
2.0
—
—
3.3±0.3
1.6
—
—
2.5±0.2
0.7
—
—
2.7
0.5
—
—
3.3±0.3
1.1
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
3.3
—
4.5
—
3.3
—
5.0
—
3.3
—
7.5
—
Maximum clock frequency f max
Propagation delay time
Output enable time
Output disable time
Setup time
Hold time
Pulse width
Input capacitance
Output capacitance
t su
th
tw
CIN
CO
FROM
(Input)
TO
(Output)
A
Y
CLK
Y
SEL
Y
ns
OE
Y
ns
OE
Y
ns
ns
ns
ns
pF
Control inputs
Data inputs
pF
Outputs
7
HD74ALVCH16832
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
CL
500 Ω
Load Circuit for Outputs
Symbol
t PLH / t PHL
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
CL
Note:
8
1.
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
OPEN
OPEN
GND
GND
2 × VCC
30 pF
6.0 V
50 pF
CL includes probe and jig capacitance.
HD74ALVCH16832
Waveforms – 1
tr
tf
90 %
Input
VIH
90 %
Vref
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
Waveforms – 2
tr
VIH
90 %
Vref
Timing Input
10 %
tsu
GND
th
VIH
Data Input
Vref
Vref
GND
tw
VIH
Input
Vref
Vref
GND
9
HD74ALVCH16832
Waveforms – 3
tf
tr
Output
Control
VIH
90 %
90 %
Vref
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
Vref1
VOL
t HZ
VOH
Vref2
Vref
≈VOL1
TEST
VIH
Vref
Vref1
Vref2
VOH1
VOL1
Notes:
1.
2.
3.
4.
10
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
VCC
2.7 V
1/2 VCC
1.5 V
VOL +0.15 V VOL +0.3 V
VOH–0.15 V VOH–0.3 V
VCC
3.0 V
GND
GND
All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, t r ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)
Waveform – A is for an output with internal conditions such that the output is low except
when disabled by the output control.
Waveform – B is for an output with internal conditions such that the output is high except
when disabled by the output control.
The output are measured one at a time with one transition per measurement.
HD74ALVCH16832
Package Dimensions
Unit : mm
17.0
17.2 Max
33
6.10
64
1
32
0.50
*0.20 ± 0.05
0.08 M
1.0
8.10 ± 0.20
0.90 Max
*Pd plating
0.05 ± 0.05
0.08
*0.15 ± 0.05
1.20 Max
0° – 8°
0.5 ± 0.1
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-64D
—
Conforms
0.47 g
11
HD74ALVCH16832
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright  Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 2.0
12