CY7C192 64K x 4 Static RAM with Separate IO Features Functional Description ■ High speed ❐ 15 ns ■ CMOS for optimum speed/power ■ Low active power ❐ 860 mW The CY7C192 is a high performance CMOS static RAM organized as 65,536 x 4 bits with separate IO. Easy memory expansion is provided by active LOW Chip Enable (CE) and tri-state drivers. It has an automatic power down feature that reduces power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and write enable (WE) inputs are both LOW. ■ Low standby power ❐ 55 mW ■ TTL-compatible inputs and outputs ■ Automatic power down when deselected ■ Available in Pb-free and non Pb-free 28-Pin Molded SOJ package Data on the four input pins (I0 through I3) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Enable (CE) LOW while the Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins appears on the four data output pins. The output pins stay in high impedance state when Write Enable (WE) is LOW or Chip Enable (CE) is HIGH. A die coat ensures alpha immunity. Logic Block Diagram I0 I1 I2 I3 INPUT BUFFER SENSE AMPS O0 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 64K x 4 ARRAY O1 O2 O3 POWER DOWN CE A15 A10 A11 A12 A13 A14 COLUMN DECODER WE Cypress Semiconductor Corporation Document #: 38-05047 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 15, 2008 [+] Feedback CY7C192 Pin Configuration Figure 1. 28-Pin Molded SOJ Package Top View A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 I0 I1 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A5 A4 A3 A2 A1 A0 I3 I2 O3 O2 O1 O0 WE Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Document #: 38-05047 Rev. *D -15 15 145 10 Unit ns mA mA Page 2 of 9 [+] Feedback CY7C192 DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested Static Discharge Voltage............................................. >900V (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ........................................ −0.5V to VCC + 0.5V Range Commercial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Voltage[1] -15 Min Max Unit 2.4 V 0.4 V 2.2 VCC + 0.3V V −0.5 0.8 V VIL Input LOW IIX Input Leakage Current GND < VI < VCC −5 +5 μA IOZ Output Leakage Current GND < VO < VCC, Output Disabled −5 +5 μA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 145 mA ISB1 Automatic CE Power Down Current—TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE Power Down Current—CMOS Inputs Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f = 0 10 mA Capacitance Parameter CIN [3] COUT [3] Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max Unit 8 pF 10 pF Notes 1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05047 Rev. *D Page 3 of 9 [+] Feedback CY7C192 Figure 2. AC Test Loads and Waveforms R1 481Ω 5V R1 481Ω 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE 3.0V R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) (b) GND 10% 90% 10% 90% < 3 ns < 3 ns Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[4] -15 Parameter Description Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid tLZCE CE LOW to Low 15 Z[5] CE HIGH to High tPU CE LOW to Power Up tPD CE HIGH to Power Down Write 15 3 ns ns 15 3 Z[5,6] tHZCE ns ns ns 7 0 ns ns 15 ns Cycle[7] tWC Write Cycle Time 15 ns tSCE CE LOW to Write End 10 ns tAW Address Setup to Write End 10 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 9 ns tSD Data Setup to Write End 9 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE [5] WE HIGH to Low Z WE LOW to High Z [5, 6] 7 ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZW\E is less than tLZWE for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. Document #: 38-05047 Rev. *D Page 4 of 9 [+] Feedback CY7C192 Switching Waveforms Figure 3. Read Cycle No. 1[8, 9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2[8, 10] tRC CE tACE DATA OUT tHZCE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Figure 5. Write Cycle No. 1 (WE Controlled)[7] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED Notes 8.WE is HIGH for read cycle. 9.Device is continuously selected, CE = VIL. 10.Address valid prior to or coincident with CE transition LOW. Document #: 38-05047 Rev. *D Page 5 of 9 [+] Feedback CY7C192 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (CE Controlled)[7, 11] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tHD tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE Note 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. Document #: 38-05047 Rev. *D Page 6 of 9 [+] Feedback CY7C192 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB ICC 0.8 0.6 VIN =5.0V TA =25°C 0.4 0.2 1.0 0.8 0.6 VCC =5.0V VIN =5.0V 0.4 0.2 ISB 0.0 4.0 1.2 4.5 5.0 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.6 1.3 1.4 NORMALIZED tAA NORMALIZED tAA 125 1.2 1.1 TA =25°C 1.0 1.2 1.0 VCC =5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 0.6 -55 6.0 120 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 25 TYPICAL POWER ON CURRENT vs. SUPPLY VOLTAGE 2.5 25.0 DELTA t AA (ns) 30.0 2.0 1.5 1.0 2.0 3.0 4.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 VCC =5.0V TA =25°C 40 20 0 0.0 125 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 3.0 1.0 OUTPUT VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED I CC vs. CYCLE TIME 1.25 20.0 15.0 VCC =4.5V TA =25°C 10.0 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 5.0 0.5 0.0 0.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE (V) NORMALIZED IPO 25 OUTPUT SINK CURRENT (mA) 1.0 NORMALIZED ICC NORMALIZED ICC 1.2 ICC NORMALIZED ICC SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) Document #: 38-05047 Rev. *D 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Page 7 of 9 [+] Feedback CY7C192 Ordering Information Speed (ns) 15 Ordering Code Package Diagram CY7C192-15VC 51-85031 Package Type Operating Range 28-Pin Molded SOJ CY7C192-15VXC Commercial 28-Pin Molded SOJ (Pb-free) Package Diagram Figure 7. 28-Pin (300-Mil) Molded SOJ (51-85031) NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 A Document #: 38-05047 Rev. *D 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*C Page 8 of 9 [+] Feedback CY7C192 Document History Page Document Title: CY7C192 64K x 4 Static RAM with Separate IO Document Number: 38-05047 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107149 09/10/01 SZV Change Spec number from: 38-00076 to 38-05047 *A 359716 See ECN AJU Changed Static Discharge Voltage limit in the Maximum Ratings section (page 2) from 2001V to 900V Removed references to CY7C191 *B 419549 See ECN AJU Added Pb-free parts to the Ordering Information table and replaced the Package Name column with Package Diagram *C 492500 See ECN NXR Removed 20 ns and 25 ns speed bins Changed the Low active power from 220 mW to 55 mW Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Removed 28-Lead (300-Mil) PDIP package from product offering Updated Ordering Information table *D 2104606 See ECN VKN/AESA Removed 12 ns speed bin © Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. 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Document #: 38-05047 Rev. *D Revised February 15, 2008 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback