CY7C106BN 256K x 4 Static RAM Features Functional Description The CY7C106BN is a high performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tristate drivers. These devices have an automatic power down feature that reduces power consumption by more than 65% when the devices are deselected. ■ High speed ❐ tAA = 15 ns ■ CMOS for optimum speed/power ■ Low active power ❐ 495 mW ■ Low standby power ❐ 275 mW ■ 2.0V data retention (optional) ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). Reading from the devices is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106BN is available in a standard 400-mil-wide SOJ. Logic Block Diagram SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 512 x 512 x 4 ARRAY POWER DOWN Cypress Semiconductor Corporation Document #: 001-06429 Rev. *A • 198 Champion Court I/O2 I/O1 I/O0 CE WE 17 16 15 13 14 12 11 10 A0 COLUMN DECODER I/O3 OE • San Jose, CA 95134-1709 • 408-943-2600 Revised March 15, 2010 [+] Feedback CY7C106BN Pin Configuration Figure 1. 28-pin SOJ (Top View) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE Selection Guide Description 7C106BN-15 Maximum Access Time (ns) 15 Maximum Operating Current (mA) 80 Maximum Standby Current (mA) 30 Document #: 001-06429 Rev. *A Page 2 of 9 [+] Feedback CY7C106BN Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65×C to +150×C Ambient Temperature with Power Applied ........................................... –55×C to +125×C Supply Voltage on VCC Relative to GND[1] .....–0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Ambient Temperature[2] 0°C to +70°C Range Commercial VCC 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C106BN-15 Min Max Unit 0.4 V VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA 2.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage[1] –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 mA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 mA IOS Output Short Circuit Current[3] VCC = Max, VOUT = GND –300 mA ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC 80 mA ISB1 Automatic CE Power Down Current Max VCC, CE > VIH, VIN > VIH or VIN < —TTL Inputs VIL, f = fMAX 30 mA ISB2 Automatic CE Power Down Current Max VCC, —CMOS Inputs CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 10 mA Commercial Capacitance[4] Parameter CIN: Addresses Description Input Capacitance CIN: Controls COUT Test Conditions TA = 25×C, f = 1 MHz, VCC = 5.0V Output Capacitance Max Unit 7 pF 10 pF 10 pF Notes 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06429 Rev. *A Page 3 of 9 [+] Feedback CY7C106BN Figure 2. AC Test Loads and Waveforms R1 480Ω 5V R1 480Ω 5V OUTPUT ALL INPUT PULSES 3.0V 90% OUTPUT R2 255Ω 30 pF R2 GND 255Ω 5 pF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE (a) Equivalent to: 90% 10% 10% Rise Time < 1V/ns Fall Time < 1V/ns (b) THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V Switching Characteristics Over the Operating Range[5] Parameter Description 7C106B-15 Min Max Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 15 tOHA Data Hold from Address Change tACE CE LOW to Data Valid 15 ns tDOE OE LOW to Data Valid 7 ns tLZOE OE LOW to Low Z OE HIGH to High tLZCE CE LOW to Low Z[7] CE HIGH to High tPU CE LOW to Power Up WRITE CYCLE ns 7 3 ns ns 7 0 CE HIGH to Power Down ns ns 0 Z[6, 7] tHZCE tPD 3 Z[6, 7] tHZOE ns 15 ns ns 15 ns [8, 9] tWC Write Cycle Time 15 ns tSCE CE LOW to Write End 12 ns tAW Address Setup to Write End 12 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 12 ns tSD Data Setup to Write End 8 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low Z[7] 3 ns tHZWE WE LOW to High Z[6, 7] 7 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06429 Rev. *A Page 4 of 9 [+] Feedback CY7C106BN Data Retention Characteristics Over the Operating Range Parameter Conditions[10] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[4] Chip Deselect to Data Retention Time tR [4] Min Max Unit 250 μA 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time V 0 ns 200 ms Figure 3. Data Retention Waveform DATA RETENTION MODE 4.5V VCC 4.5V VDR > 2V tR tCDR CE Switching Waveforms Figure 4. Read Cycle No.1[11, 12] 1 tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 10. No input may exceed VCC +0.5V. 11. Device is continuously selected, OE and CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06429 Rev. *A Page 5 of 9 [+] Feedback CY7C106BN Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATA VALID tHZOE Notes 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 15. Data I/O is high impedance if OE = VIH. Document #: 001-06429 Rev. *A Page 6 of 9 [+] Feedback CY7C106BN Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE Input/Output Mode Power H X X High Z Power Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 15 Ordering Code CY7C106BN-15VC Package Diagram 51-85032 Package Type 28-Pin (400-Mil) Molded SOJ Operating Range Commercial Contact your local sales representative regarding availability of these parts. Document #: 001-06429 Rev. *A Page 7 of 9 [+] Feedback CY7C106BN Package Diagram Figure 9. 28-Pin (400 Mil) Molded SOJ PIN 1 I.D 14 1 .435 .445 .395 .405 15 DIMENSIONS IN INCHES MIN. MAX. 28 .720 .730 SEATING PLANE NO CHAMFER .128 .148 .026 .032 .050 TYP. .015 .020 0.004 .025 MIN. .007 .013 .360 .380 51-85032-*B NOTES : 1. PACKAGE WEIGHT : 1.24g 2. JEDEC REFERENCE : MS-027 Document #: 001-06429 Rev. *A 51-85032.*D Page 8 of 9 [+] Feedback CY7C106BN Document History Page Document Title: CY7C106BN 256K x 4 Static RAM Document Number: 001-06429 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 423847 See ECN NXR New Data sheet *A 2891262 03/12/2010 VKN Removed CY7C1006BN part from the data sheet Removed Industrial grade Removed 20ns speed bin Removed 28-pin (300-Mil) Molded SOJ package Updated POD for 28-pin (400-Mil) Molded SOJ package Updated Ordering information table Updated URLs in Sales, Solutions, and Legal Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06429 Rev. *A Revised March 15, 2010 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback