CYPRESS CY7C197N_11

CY7C197N
256 K × 1 Static RAM
256 K × 1 Static RAM
Features
Functional Description
■
High speed
❐ 25 ns
■
CMOS for optimum speed/power
■
Low active power
❐ 880 mW
The CY7C197N is a high-performance CMOS static RAM
organized as 256 K words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C197N has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable (CE)
and Write Enable (WE) inputs are both LOW. Data on the input
pin (DIN) is written into the memory location specified on the
address pins (A0 through A17).
■
Low standby power
❐ 220 mW
■
Transistor-transistor logic (TTL)-compatible inputs and outputs
■
Automatic power-down when deselected
Reading the device is accomplished by taking chip enable (CE)
LOW while Write Enable (WE) remains HIGH. Under these
conditions the contents of the memory location specified on the
address pins will appear on the data output (DOUT) pin.
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C197N uses a die coat to insure alpha immunity.
Logic Block Diagram
DI
1024 x 256
ARRAY
COLUMN
DECODER
SENSE AMPS
ROW DECODER
INPUT BUFFER
A13
A14
A15
A16
A17
A0
A1
A2
A3
A4
DO
POWER
DOWN
CE
A5 A6 A7 A8 A9 A10 A11 A12
Cypress Semiconductor Corporation
Document #: 001-06495 Rev. *D
•
198 Champion Court
WE
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 1, 2011
CY7C197N
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 4
Switching Characteristics ................................................ 5
Switching Waveforms ...................................................... 6
Typical DC and AC Characteristics ................................ 8
CY7C197N Truth Table ..................................................... 9
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Document #: 001-06495 Rev. *D
Package Diagram ............................................................ 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
CY7C197N
Pin Configurations
Selection Guide
Figure 1. 24-pin DIP (Top View)
A0
A1
A2
A3
A4
A5
A6
A7
A8
DOUT
WE
GND
1
24
2
23
22
3
4
21
5
20
6 7C197 19
18
7
8
17
9
16
10
15
14
11
12
13
Document #: 001-06495 Rev. *D
Description
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
DIN
CE
-25
Maximum access time (ns)
25
Maximum operating current (mA)
95
Maximum standby current (mA)
30
Page 3 of 13
CY7C197N
DC input voltage[1] ............................... –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground potential
(Pin 24 to Pin 12)..........................................–0.5 V to +7.0 V
DC voltage applied to outputs
in High Z state[1] .................................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch up current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
Commercial
0 °C to +70 °C
5 V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW voltage
VCC = Min, IOL =12.0 mA
VIH
Input HIGH voltage
voltage[1]
-25
Unit
Min
Max
2.4
–
V
–
0.4
V
2.2
VCC + 0.3 V
V
–0.5
0.8
V
+5
A
VIL
Input LOW
IIX
Input load current
GND < VI < VCC
–5
IOZ
Output leakage current
GND < VO < VCC, Output Disabled
–5
+5
A
IOS
Output short circuit current[2]
VCC = Max, VOUT = GND
–
–300
mA
ICC
VCC operating supply current
VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC
–
95
mA
ISB1
Automatic CE power-down
current—TTL inputs[3]
Max VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
–
30
mA
ISB2
Automatic CE power-down
current—CMOS inputs[3]
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
–
15
mA
Capacitance[4]
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
Max
Unit
8
pF
10
pF
Notes
1. V(min.) = -2.0 V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06495 Rev. *D
Page 4 of 13
CY7C197N
Figure 2. AC Test Loads and Waveforms[5]
R1 329 
R1 329
5V
5V
OUTPUT
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
3.0 V
R2
5 pF
202 
(255 MIL) INCLUDING
JIG AND
SCOPE
R2
255 
(255 MIL)
10%
90%
10%
90%
GND
< tr
< tr
(b)
Equivalent to:
THÉVENIN EQUIVALENT
125 
OUTPUT
1.90 V
Commercial
Switching Characteristics
Over the Operating Range[6]
Parameter
Description
-25
Min
Max
Unit
READ CYCLE
tRC
Read cycle time
25
–
ns
tAA
Address to data valid
–
25
ns
tOHA
Output hold from address change
3
–
ns
tACE
CE LOW to data valid
–
25
ns
3
–
ns
tLZCE
CE LOW to low
Z[7]
Z[7, 8]
tHZCE
CE HIGH to high
0
11
ns
tPU
CE LOW to power-up
0
–
ns
CE HIGH to power-down
–
20
ns
tWC
Write cycle time
25
–
ns
tSCE
CE LOW to write end
20
–
ns
tAW
Address setup to write end
20
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
20
–
ns
tSD
Data setup to write end
15
–
ns
tHD
Data hold from write end
0
–
ns
3
–
ns
0
11
ns
tPD
[9]
WRITE CYCLE
Z[7]
tLZWE
WE HIGH to low
tHZWE
WE LOW to high Z[7, 8]
Notes
5. tr = < 5 ns for the -25 and slower speeds.
6. Test conditions assume signal transition time of 5 ns or less for -25 and slower speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output
loading of the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 001-06495 Rev. *D
Page 5 of 13
CY7C197N
Switching Waveforms
Figure 3. Read Cycle No. 1[10, 11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
Figure 4. Read Cycle No. 2[10]
tRC
CE
tACE
tHZCE
tLZCE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
ICC
50%
50%
ISB
Figure 5. Write Cycle No. 1 (WE Controlled)[12]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
tHD
DATA UNDEFINED
tLZWE
HIGH IMPEDANCE
C197-8
Notes
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 001-06495 Rev. *D
Page 6 of 13
CY7C197N
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE Controlled)[13, 14]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tHD
tSD
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
Notes
13. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 001-06495 Rev. *D
Page 7 of 13
CY7C197N
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ICC
1.0
0.8
VIN = 5.0 V
TA = 25°C
0.6
0.4
0.2
ISB
0.0
4.0
4.5
5.0
5.5
1.2
1.0
0.8
0.6
VIN = 5.0 V
VCC = 5.0 V
0.4
0.2
ISB
0.0
–55
6.0
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.1
TA = 25°C
1.0
0.9
1.0
VCC = 5.0 V
0.8
0.6
55
3.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
20.0
2.0
1.5
1.0
0.5
0.0
0.0
15.0
VCC = 4.5 V
TA = 25°C
10.0
5.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 001-06495 Rev. *D
5.0
0.0
0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
200
400
600
800 1000
CAPACITANCE (pF)
VCC = 5.0 V
TA = 25°C
60
40
20
0
0.0
140
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE(V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
VCC = 5.0 V
TA = 25°C
40
20
0
0.0
25
125
AMBIENT TEMPERATURE(°C)
(ns)
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE(V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED IPO
1.2
DELTA tAA
0.8
4.0
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
1.2
ICC
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE(V)
NORMALIZED ICC vs. CYCLE TIME
1.25
NORMALIZED ICC
NORMALIZED ICC, ISB
NORMALIZED ICC, ISB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
1.00
VCC = 5.0 V
TA = 25°C
VIN = 5.0 V
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 8 of 13
CY7C197N
CY7C197N Truth Table
CE
WE
Input/Output
Mode
H
X
High Z
Deselect/Power-Down
L
H
Data Out
Read
L
L
Data In
Write
Ordering Information
Speed
(ns)
25
Ordering Code
CY7C197N-25PXC
Package
Diagram
51-85013
Package Type
24-pin (300-Mil) Molded DIP (Pb-free)
Operating
Range
Commercial
Contact your local sales representative regarding availability of these parts.
Ordering Code Definitions
CY 7C 197N - 25 PX C
C = Temperature range (Commercial)
PX = 24-pin molded DIP (Pb-free)
25 = Speed grade
197N = 256 K × 1 architecture
Family: 7C = Fast asynchronous SRAM
Company ID: CY = Cypress
Document #: 001-06495 Rev. *D
Page 9 of 13
CY7C197N
Package Diagram
Figure 7. 24-pin (300-Mil) PDIP (51-85013)
51-85013 *C
Document #: 001-06495 Rev. *D
Page 10 of 13
CY7C197N
Acronyms
Document Conventions
Acronym
Description
CE
chip enable
CMOS
complementary metal oxide semiconductor
DIP
dual inline package
I/O
input/output
PDIP
plastic dual inline package
SRAM
static random access memory
TTL
transistor-transistor logic
WE
write enable
Document #: 001-06495 Rev. *D
Units of Measure
Symbol
Unit of Measure
%
percent
°C
degree Celsius
mA
milliamperes
MHz
megahertz
mV
millivolts
mW
milliwatts
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
µA
microamperes
Page 11 of 13
CY7C197N
Document History Page
Document Title: CY7C197N, 256 K × 1 Static RAM
Document Number: 001-06495
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
424111
See ECN
NXR
New Data Sheet
*A
2958594
06/22/10
AJU
The EOL Prune part number CY7C197N-45PXC removed & Updated
package diagram.
*B
3095450
11/25/2010
AJU
Updated template.
Added Acronyms, Document Conventions, and Ordering Code Definitions
Removed –45 information.
Changed posting to external web.
*C
3246053
05/02/2011
PRAS
*D
3270287
07/01/2011
AJU
Document #: 001-06495 Rev. *D
Updated in new template.
Fixed units in Electrical Characteristics table.
Page 12 of 13
CY7C197N
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
Clocks & Buffers
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06495 Rev. *D
Revised July 1, 2011
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 13 of 13