CY2SSTV857-27 Differential Clock Buffer/Driver DDR333/PC2700-Compliant Features Description • Operating frequency: 60 MHz to 200 MHz The CY2SSTV857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-27 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-27 features differential feedback clock outputs and inputs. This allows the CY2SSTV857-27 to be used as a zero-delay buffer. • Supports 266, 333-MHz DDR SDRAM • 10 differential outputs from 1 differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps When used as a zero-delay buffer in nested clock trees, the CY2SSTV857-27 locks onto the input reference and translates with near-zero delay to low-skew outputs. • Power management control input • High-impedance outputs when input clock < 10 MHz • 2.5V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP package • Industrial temp. of –40° to +85°C • Conforms to JEDEC DDR specification Block Diagram Pin Configuration 3 2 PD # AVDD 5 T est and P ow erdo w n L o gic 37 16 6 46 4 45 VDDQ Y1 5 44 Y6 43 Y6# 42 VSS 6 7 22 VSS 8 Y4 Y4# Y2# 9 Y2 10 Y5 Y5# VDDQ 11 VDDQ 12 41 VSS 40 Y7# 39 Y7 38 VDDQ 37 PD# 36 F B IN C LK 13 C LK # 14 35 F B IN # Y7 Y7# VDDQ 15 34 VDDQ AVDD 16 33 FBOUT# AVSS 17 32 FBOUT 30 Y8 Y8# VSS 18 31 VSS 27 26 Y9 Y9# Y3# 19 30 Y8# Y8 40 29 32 33 • 3 Y1# 39 Cypress Semiconductor Corporation Document #: 38-07464 Rev. *G Y5 Y0 VDDQ CY2SSTV857-27 36 35 Y5# VSS 43 F B IN F B IN # VSS 47 Y3 Y3# 44 PLL 48 2 20 19 47 14 1 Y0# Y2 Y2# 46 13 VSS 10 9 23 C LK C LK# Y0 Y0# Y1 Y1# Y6 Y6# FBO UT FBO U T # 3901 North First Street • Y3 20 29 VDDQ 21 28 VDDQ Y4 22 27 Y9 Y4# 23 26 Y9# VSS 24 25 VSS San Jose, CA 95134 • 408-943-2600 Revised January 25, 2005 CY2SSTV857-27 Pin Description Electrical Characteristics Pin Name I/O[1] CLK, CLK# I Differential Clock Input. 35 FBIN# I Feedback Clock Input. Connect to FBOUT# for accessing the Differential Input PLL. 36 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. Pin Number 13, 14 Pin Description 3, 5, 10, 20, 22 Y(0:4) O Clock Outputs 2, 6, 9, 19, 23 Y#(0:4) O Clock Outputs LV Differential Input Differential Outputs 27, 29, 39, 44, 46 Y(9:5) O Clock Outputs 26, 30, 40, 43, 47 Y#(9:5) O Clock Outputs Differential Outputs 32 FBOUT O Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 33 FBOUT# O Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 37 PD# I Power Down# Input. When PD# is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled Hi-Z and the PLL is powered down. Differential Outputs 4, 11,12,15, 21, 28, 34, 38, 45 VDDQ 2.5V Power Supply for Output Clock Buffers. 2.5V Nominal 16 AVDD 2.5V Power Supply for PLL. When VDDA is at GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. 2.5V Nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 VSS Common Ground 0.0V Ground 17 AVSS Analog Ground 0.0V Analog Ground Zero-delay Buffer When used as a zero-delay buffer the CY2SSTV857-27 will likely be in a nested clock tree application. For these applications the CY2SSTV857-27 offers a differential clock input pair as a PLL reference. The CY2SSTV857-27 then can lock onto the reference and translate with near-zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes. Power Management Output enable/disable control of the CY2SSTV857-27 allows the user to implement power management schemes into the design. Outputs are three-stated/disabled when PD# is asserted low (see Table 1). Note: 1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07464 Rev. *G Page 2 of 9 CY2SSTV857-27 Table 1. Function Table Inputs AVDD PD# GND GND X X 2.5V 2.5V 2.5V Outputs CLK CLK# Y Y# FBOUT FBOUT# PLL H L H H H L L H H L H BYPASSED/OFF L H L BYPASSED/OFF L L L H H L Z Z Z Z Off Z Z Z Z OFF H L H H H L H L H On L H L H L On H < 10 MHz < 10 MHz Hi-Z Hi-Z Hi-Z HI-Z Off CLKIN FBIN t(phase error) FBOUT Yx tsk(o) Yx Yx tsk(o) Figure 1. Phase Error and Skew Waveforms CLKIN Yx or FBIN tpd Figure 2. Propagation Delay Time tPLH, tPHL Document #: 38-07464 Rev. *G Page 3 of 9 CY2SSTV857-27 Yx tC(n) tC(n+1) Figure 3. Cycle-to-cycle Jitter = 2.5" = 0.6" (Split to Terminator) DDR _SDRAM represents a capacitive load CLK 120 Ohm PLL DDR SDRAM CLK# VTR 120 Ohm VCP FBIN 120 Ohm DDR SDRAM FBIN# FBOUT FBOUT# 0.3" Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF Figure 4. Clock Structure # 1 = 2.5" = 0.6" (Split to Terminator) DDR-SDRAM represents a capacitive load CLK DDR-SDRAM DDR-SDRAM Stack PLL 120 Ohm DDR-SDRAM CLK# VTR 120 Ohm VCP FBIN 120 Ohm DDR-SDRAM FBIN# DDR-SDRAM Stack FBOUT FBOUT# DDR-SDRAM 0.3" Output load capacitancce for 4 DDR-SDRAM Loads: 10 pF < CL < 16 pF Figure 5. Clock Structure # 1 Document #: 38-07464 Rev. *G Page 4 of 9 CY2SSTV857-27 VDDQ VDDQ V D D Q /2 14 pF VTR 60 O hm OUT RT = 120 O hm 60 O hm OUT# VCP R e c e iv e r 14 pF V D D Q /2 Figure 6. Differential Signal Using Direct Termination Resistor Document #: 38-07464 Rev. *G Page 5 of 9 CY2SSTV857-27 Absolute Maximum Conditions[2] Storage Temperature: ................................ –65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: .................................... 0°C to +85°C VSS < (Vin or Vout) < VDDQ. Maximum Power Supply: ................................................3.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDDQ). Input Voltage Relative to VSS:...............................VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ........... VDDQ + 0.3V DC Electrical Specifications (AVDD = VDDQ = 2.5v ± 5%, TA = 0°C to +85°C) [3] Parameter Description Condition VDDQ Supply Voltage Operating VIL Input Low Voltage PD# VIH Input High Voltage Min. Typ. Max. Unit 2.38 2.5 2.63 V 0.3 × VDDQ V 0.7 × VDDQ VID Differential Input Voltage[4] CLK, FBIN VIX Differential Input Crossing Voltage[5] CLK, FBIN IIN Input Current [CLK, FBIN, PD#] VIN = 0V or VIN = VDDQ V 0.36 VDDQ + 0.3 (VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2 –10 10 V V µA IOL Output Low Current VDDQ = 2.375V, VOUT = 1.2V 26 35 mA IOH Output High Current VDDQ = 2.375V, VOUT = 1V –28 –32 mA VOL Output Low Voltage VDDQ= 2.375V, IOL = 12 mA VOH Output High Voltage VDDQ = 2.375V, IOH = –12 mA VOUT Output Voltage Swing[6] VOC Output Crossing Voltage[7] IOZ IDDQ High-Impedance Output Current VO = GND or VO = VDDQ Dynamic Supply Current[8] All VDDQ, FO = 170 MHz IDD PLL Supply Current VDDA only IDDS Standby Supply Current PD# = 0 and CLK/CLK# < 10 MHz Cin Input Pin Capacitance 0.6 V 1.7 V 1.1 VDDQ – 0.4 V (VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2 –10 10 µA 235 300 mA 9 V 12 mA 100 µA 4 pF AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = 0°C to +85°C) [9, 10] Parameter Description fCLK Operating Clock Frequency tDC Input Clock Duty Cycle tLOCK Maximum PLL lock Time DTYC Duty Cycle[11] tsl(o) Output Clocks Slew Rate tPZL, tPZH Output Enable Time[12] (all outputs) Condition AVDD, VDDQ = 2.5V ± 0.2V Min. Typ. 60 40 60 MHz to 100 MHz 49.5 101 MHz to 170 MHz 49 20%–80% of VOD 1 50 3 Max. Unit 200 MHz 60 % 100 µs 50.5 % 51 % 2 V/ns 25 ns Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Unused inputs must be held HIGH or LOW to prevent them from floating. 4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary input level. See Figure 6. 5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signal must be crossing. 6. For load conditions see Figure 6. 7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6. 8. All outputs switching load with 14 pF in 60Ω environment. See Figure 6. 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. 10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 50 kHz with a down spread or –0.5%. 11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWHC/tC, where the cycle time (tC) decreases as the frequency goes up. 12. Refers to transition of non-inverting output. Document #: 38-07464 Rev. *G Page 6 of 9 CY2SSTV857-27 AC Electrical Specifications (AVDD = VDDQ = 2.5V±5%, TA = 0°C to +85°C)(continued)[9, 10] Parameter tPLZ, tPHZ Description Condition Min. Output Disable Time[12] (all outputs) [10] Typ. Max. Unit 3 8 ns tCCJ Cycle to Cycle Jitter f > 66 MHz –75 – 75 ps tjit(h-per) Half-period jitter[10, 13] f > 66 MHz –100 – 100 ps tPLH(tPD) Low-to-High Propagation Delay, CLK to Y Test Mode only 1.5 3.5 7.5 ns tPHL(tPD) High-to-Low Propagation Delay, CLK to Y 1.5 3.5 7.5 ns [14] tSK(O) Any Output to Any Output Skew tPHASE Phase Error[14] 100 ps 50 ps –50 Ordering Information Part Number Package Type Product Flow CY2SSTV857ZC-27 48-pin TSSOP Commercial, 0° to 70°C CY2SSTV857ZC-27T 48-pin TSSOP–Tape and Reel Commercial, 0° to 70°C CY2SSTV857ZI-27 48-pin TSSOP Industrial, –40° to +85°C CY2SSTV857ZI-27T 48-pin TSSOP–Tape and Reel Industrial, –40° to +85°C Lead-free CY2SSTV857ZXC-27 48-pin TSSOP Commercial, 0° to 70°C CY2SSTV857ZXC-27T 48-pin TSSOP–Tape and Reel Commercial, 0° to 70°C CY2SSTV857ZXI-27 48-pin TSSOP Industrial, –40° to +85°C CY2SSTV857ZXI-27T 48-pin TSSOP–Tape and Reel Industrial, –40° to +85°C Notes: 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in Figure 5. Document #: 38-07464 Rev. *G Page 7 of 9 CY2SSTV857-27 Package Drawing and Dimension 48-lead (240-mil) TSSOP II Z48 0.500[0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 25 48 12.395[0.488] 12.598[0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° 0.508[0.020] 0.762[0.030] SEATING PLANE 0.100[0.003] 0.200[0.008] 51-85059-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07464 Rev. *G Page 8 of 9 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2SSTV857-27 Document History Page Document Title: CY2SSTV857-27 Differential Clock Buffer/Driver, DDR333/PC2700-Compliant Document #: 38-07464 Rev. ECN No. Issue Date Orig. of Change ** 117657 09/09/02 HWT New Data Sheet *A 118942 10/21/02 RGL Overlooked in initial release needed to add Pin 15 to the Pin Description table Description of Change *B 121274 11/12/02 RGL Corrected the typo error in the title *C 122937 12/21/02 RBI Add power up requirements to maximum rating information *D 127010 05/27/03 RGL Changed the operating frequency from 60–170 MHz to 60–200 MHz Added 333-MHz DDR SDRAM support Changed OE pin to PD# *E 129270 10/22/03 RGL Changed PD to PD# Removed the “and DDR266/PC2100” from the title Changed the part number from “CY2SSTV857” to “CY2SSTV857-27” Changed “Commercial Temp of 0°C to 70°C” to “Industrial Temp of –40° to +85°C” Added Industrial Temp part numbers to Ordering information *F 202540 See ECN RGL Corrected typo error -Cycle-to-cycle Jitter (TCCJ) max. value from 7.5 ps to 75 ps *G 312654 See ECN RGL Added Lead-free devices Document #: 38-07464 Rev. *G Page 9 of 9