TI UCC28600

UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
8-PIN QUASI-RESONANT FLYBACK GREEN MODE CONTROLLER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
Bias Supplies for LCD-Monitors, LCD-TV,
PDP-TV, and Set Top Boxes
AC/DC Adapters and Offline Battery Chargers
Energy Efficient Power Supplies up to 200 W
DESCRIPTION
The UCC28600 is a PWM controller with advanced
energy features to meet stringent world-wide energy
efficiency requirements.
UCC28600 integrates built-in advanced energy
saving features with high level protection features to
provide cost effective solutions for energy efficient
power supplies. UCC28600 incorporates frequency
fold back and burst mode operation to reduce the
operation frequency at light load and no load
operations.
UCC28600 is offered in the 8-pin SOIC (D) and PDIP
(P) packages. Operating temperature range is -40°C
to 105°C.
TYPICAL APPLICATION
Primary
CBULK
Secondary
RSU
RDD
Q1
RST2
RST1
CDD
ROVP1
18 V
CSS
UCC28600
1 SS STATUS 8
UCC28051
1 VO_SNS VCC 8
2 FB
OVP 7
2 COMP
3 CS
VDD 6
4 GND
OUT 5
DRV 7
3 MULTIN GND 6
4 CS
Feedback
ROVP2
M1
ZCD 5
CBP
RPL
RCS
TL431
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2005–2006, Texas Instruments Incorporated
PRODUCT PREVIEW
•
Green Mode Controller With Advanced Energy
Saving Features
Quasi-Resonant Mode Operation for Reduced
EMI and Low Switching Losses (Low Voltage
Switching)
Low Standby Current for System No-Load
Power Consumption to 150 mW
Low Startup Current: 25 µA Maximum
Programmable Overvoltage Protection, Line
and Load
Internal Overtemperature Protection: Prevents
Restart Until Temperature Fault Cleared
Current Limit Protection
– Cycle-by-Cycle Power Limit
– Overcurrent Hiccup Restart Mode
1-A Sink TrueDrive™, -0.75-A Source Gate
Drive Output
Programmable Soft-Start
Greenmode STATUS pin (PFC Disable
Function)
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UCC28600
VDD
Supply voltage range
IDD
Supply current
IOUT(sink)
Output sink current (peak)
1.2
IOUT(source)
Output source current (peak)
-0.8
Analog inputs
IDD < 20 mA
FB, CS, SS
V
20
mA
A
-0.3 to 6.0
VOVP
V
-1.0 to 6.0
IOVP(source)
VSTATUS
Power dissipation
-1.0
mA
VDD = 0 V to 30 V
30
V
SOIC-8 package, TA = 25°C
650
mW
PDIP-8 package, TA = 25°C
1
W
TJ
Operating junction temperature range
–55 to 150
Tstg
Storage temperature
–65 to 150
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
UNIT
30
°C
300
PRODUCT PREVIEW
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the databook
for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Input voltage
IOUT
SW node output current
TJ
Operating junction temperature
NOM
MAX
UNIT
24
V
150
°C
0
A
-55
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
Human body model
2500
CDM
1500
2
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UNIT
V
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS
(1)
VDD = 15 V, 0.1-µF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
OVP to GND, FB = not connected, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA = TJ = -40°C
to 105°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
ISTARTUP
Startup current
VDD = VUVLO -0.3 V
12
25
ISTANDBY
Standby current
VFB = 900 mV
350
550
IDD
Operating current
Not switching
2.5
3.5
130 kHz, QR mode
5.0
7.0
23
26
30
Startup threshold
11
13
15
Stop threshold
6.7
8
9.3
4.25
5.00
5.75
VDD clamp
FB = GND, IDD = 10 mA
µA
mA
V
UNDERVOLTAGE LOCKOUT
Hysteresis
V
PWM (RAMP)
Minimum duty cycle
VSS = GND, VFB = 2 V
DMAX
Maximum duty cycle
QR mode, fS = max, (open loop)
tSS
Softstart time
VSS = 1 V to 3 V (note 1)
0%
99%
1.5
PRODUCT PREVIEW
DMIN
ms
OSCILLATOR (OSC)
fQR(max)
Maximum QR frequency
117
130
143
fQR(min)
Minimum QR and FFM frequency
VFB = 1.3 V
32
40
48
fSS
Soft start frequency
SS = 2.0 V
32
40
48
dTS/dFB
VCO gain
TS for 1.6 V < FB < 1.8 V
kHz
µs/V
-28
FEEDBACK (FB)
Feedback resistor
12
28
kΩ
QR mode
Green mode ON threshold
VFB threshold
0.35
0.50
0.65
Green mode OFF threshold
VFB threshold
1.2
1.4
1.6
Green mode hysteresis
VFB threshold
0.7
0.9
1.1
STATUS RDS(on)
VSTATUS = 1 V
2.4
kΩ
STATUS leakage/off current
VFB = 0.3 V
40
nA
FB threshold burst-ON
Green mode
0.35
0.50
FB threshold burst-OFF
Green mode
0.5
0.7
0.9
Burst Hysteresis
Green mode
0.15
0.25
0.40
4.870
V
0.65
V
(2)2.4
Internal FB clamp voltage
(1)
(2)
20
FB, no load
RSCT and CCST are not connected from the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
Ensured by design. Not production tested.
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UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 15 V, 0.1-µF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
OVP to GND, FB = not connected, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA = TJ = -40°C
to 105°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.13
1.25
1.38
V
µA
CURRENT SENSE (CS)
IBIAS
Gain, ACS, FB = ∆VFB / ∆VCS
QR mode (3)
Shutdown threshold
VFB = 2.4 V, VSS = 0 V
Input bias current
(3)
-0.1
-2.0
CS to output delay time (power limit)
CS = 1.0 VPULSE
175
300
CS to output delay time (over current fault)
CS = 1.45 VPULSE
100
CS discharge impedance
CS = 0.1 V, SS = 0 V
CS offset (via FB)
SS mode, VSS≤ 2.0 V
0.35
0.40
0.45
CS current
OVP = -300 µA
-130
-150
-170
PL threshold
QR mode, peak CS voltage
0.8
PL threshold
Peak CS voltage + CS offset
1.2
2.5
V/V
ns
Ω
115
V
POWER LIMIT (PL)
µA
V
SOFT START (SS)
PRODUCT PREVIEW
ISS
Softstart charge current
VSS = GND
-7.8
-6.0
-5.2
µA
ISS
Softstart discharge current
VSS = 0.5 V
2.0
5.0
10
mA
VSS
Retry voltage
VSS = 0.1 V, VOVP = 4 V
VSS
Switching ON threshold
Output switching start
TBD
V
0.8
1.0
1.2
-405
-450
-495
µA
-50
0
50
mV
3.37
3.75
4.13
130
140
150
OVERVOLTAGE PROTECTION (OVP)
OVP(line)
OVP(load)
Line overvoltage protection
VOVP threshold, OUT = HI
OVP voltage at OUT = HIGH
(3)
Load overvoltage protection
VOVP threshold, OUT = LO
V
THERMAL PROTECTION (TSD)
Thermal shutdown (TSP) temperature (3)
Thermal shutdown hysteresis
15
°C
OUT Clamp
tRISE
Rise time
tFALL
Fall time
(3)
4
OUT = 0 V to 8 V
25
10% to 90% of out clamp
50
10
Ensured by design. Not production tested.
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ns
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
OPEN LOOP TEST CIRCUIT
RCST
+ 5V
37.4 kΩ
See Note
CCST
560 pF
See Note
VFB
UCC28600
1 SS STATUS 8
STATUS
CSS
3.3 nF
ROVP
500 Ω
2 FB
OVP 7
3 CS
VDD 6
4 GND
OUT 5
IOVP
CFB
47 pF
VCS
ICS
VDD
IDD
VOUT
ROUT
10 Ω
GND
CDD 100 nF
CBIAS 1 µF
VOVP
COUT
1.0 nF
PRODUCT PREVIEW
NOTE:
RCST and CCST are not connected from the circuit for maximum and minimum duty
cycle tests, current sense tests and power limit tests.
BLOCK DIAGRAM/TYPICAL APPLICATION
CBULK
RSU
RDD
From Auxiliary
Winding
ROVP1
ROVP2
OVP
VDD
6
7
UCC28600
REF
On−Chip
Thermal
Shutdown
STATUS 8
SS
+
UVLO
5.0
VREF
13/8V
Fault Logic
REF_OK
UVLO
OVR_T
STATUS
SS_DIS
SS_OVR
LOAD_OVP
LINE_OVP
CS
BURST
RUN
QR Detect
LOAD_OVP OUT
LINE_OVP
CS
BURST
QR_DONE
Oscillator
1
SS_OVR
OSC_CL
CSS
26V
REF
RUN
QR_DONE
13V
D Q
SET
CLK
+
OSC_CL
FB
FB_CLAMP
PL
1.2V
REF
Modulation
Comparison
20K
3
RPL
RCS
+
1.5R
R
400 mV
4
GND
+
2
OUT
CS
GAIN = 1/2.5
FB
5
CLR Q
Green Mode
Feedback
VDD
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UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
ORDERING INFORMATION
TA
PACKAGES
SOIC
-40°C to 105°C
(1)
(D) (1)
PART NUMBER
UCC28600D
PDIP (P)
UCC28600P
SOIC (D) package is available taped and reeled by adding “R” to the above part numbers. Reeled quantities for UCC28600DR is 2,500
devices per reel. Quantities for UCC28600P is 50 per tube.
DEVICE INFORMATION
UCC28600
D OR P PACKAGE
(TOP VIEW)
SS
FB
CS
GND
1
8
2
7
3
6
4
5
STATUS
OVP
VDD
OUT
TERMINAL FUNCTIONS
PRODUCT PREVIEW
TERMINAL
NAME
CS
NO.
3
I/O
DESCRIPTION
I
Current sense input. Also programs power limit, and used to control modulation and activate overcurrent
protection. The CS voltage input originates across a current sense resistor and ground. Power limit is
programmed with an effective series resistance between this pin and the current sense resistor.
FB
2
I
Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current
in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated voltage.
Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the emitter
of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the three
modes; quasi resonant (QR), frequency foldback mode (FFM) and burst mode (BM).
GND
4
-
Ground for internal circuitry. Connect a ceramic 0.1-µF bypass capacitor between VDD and GND, with the
capacitor as close to these two pins as possible.
OUT
5
O
1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and
switches between GND and the lower of VDD or output clamp level.
OVP
7
I
Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on.
Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity
with resistors connected to this pin.
SS
1
I
Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the
capacitance and the internal soft-start charge current. All faults discharge the SS pin to GND through an
internal MOSFET with an RDS(on) of approximately 100 Ω. The internal modulator comparator reacts to the
lowest of the SS voltage, the internal FB voltage and the peak current limit.
STATUS
8
O
ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to
disable the PFC control circuit (high impedance = green mode).
VDD
6
I
Provides power to the device. Use a ceramic 0.1-µF by-pass capacitor for high-frequency filtering of the VDD
pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To
prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.
6
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UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
TERMINAL COMPONENTS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
R CS R PL CS
3
(1) (2) (3)
VPL VCS(os)I CS(2) I CS(1)
I CS(2)I P(1) I CS(1)I P(2)
VPL VCS(os)I P(2) I P(1)
I CS(1)I P(2) I CS(2)I P(1)
I
FB
2
I
Opto-isolator collector
GND
OUT
4
-
Bypass capacitor to VDD, CBP = 0.1 µF
5
O
Power MOSFET gate
R OVP1 OVP
7
I
PRODUCT PREVIEW
where:
•
IP1 is the peak primary current at low line, full load
•
IP2 is the peak primary current at high line, full load
•
ICS1 is the power limit current that is sourced at the CS pin at low-line voltage
•
ICS2 is the power limit current that is sourced at the CS pin at high-line voltage
•
VPL is the Power Limit (PL) threshold
•
VCS(os) is the CS offset voltage
NB
1
V
I OVP(lineth) N 1 BULK(ov)
V OVP(load th)
R OVP2 ROVP1
NB
VOUT(ov) V F V OVP(load th)
N2
where:
•
IOVP(line th) is OVP(line) current threshold
•
VBULK(ov) is the allowed input over- voltage level
•
VOVP(load_th) is OVP(load)
•
VOUT(ov) is the allowed output over-voltage level
•
VF is the forward voltage of the secondary rectifier
(1)
(2)
(3)
Refer to Figure 1 for all reference designators in the Terminal Components Table.
Refer to the Electrical Characteristics Table for constant parameters.
Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
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UCC28600
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TERMINAL COMPONENTS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
C SS I SS t SS(min)(due power limit)
ACS(FB) VPL V CS(os)
where:
SS
1
I
2 ROUT(ss)COUT VOUT VOUT(step) t SS(min) MAX
n
1 2
R OUT(ss)PLIM
2
COUTVOUT
2 PLIM
PRODUCT PREVIEW
•
•
•
•
ROUT(ss) is the effective load impedance during soft-start
∆ VOUT(step) is the allowed change in VOUT due to a load step
PLIM is the programmed power limit level, in W
ACS(FB) is the current sense gain. (4)
R ST1 STATUS
8
O
R ST2 ST VDD(uvloon)
I CC
ST VBE
I CC
where:
•
βST is the gain of transistor QST
•
VBE is the active base-emitter voltage of transistor QST
•
VDD(uvlo-on) is the startup threshold (4)
•
ICC is the collector current of QST
(4)
8
Refer to the Electrical Characteristics Table for constant parameters.
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UCC28600
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TERMINAL COMPONENTS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
T BURST C DD MAXI DD CISSV OUT(hi)f QR(max)
VDD(burst)
t SS
I C V
f
DD
ISS OUT(hi) QR(max) V
DD(uvlo) VDS1(os) f QR(max) LLEAKAGECD CSNUB
N
R DD B
4 N1
I DD CISS V OUT(hi) f QR(max)
6
I
R SU VBULK(min)
I STARTUP
where:
•
IDD is the operating current of the UCC28600
•
CISS is the input capacitance of MOSFET M1
•
VOUT(hi) is VOH of the OUT pin, either VOUT clamp or as measured
•
fQR(max) is fS at high line, maximum load
•
TBURST is the measured burst mode period
•
∆VDD(burst) is the UVLO-allowed VDD ripple during burst mode
•
∆VDD(uvlo) is the UVLO hysteresis, equal to VDD or 13 V whichever is less
•
VDS1(os) is the amount of drain-source overshoot voltage
•
LLEAKAGE is the leakage inductance of the primary winding
•
CD is the total drain node capacitance of MOSFET M1
•
ISTARTUP is IDD start-up current of the UCC28600
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PRODUCT PREVIEW
VDD
9
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
PFC OUTPUT
or
BRIDGE RECTIFIER
+
PRIMARY
RSNUB
RSU
CBULK
VBULK
CSNUB
N1
SECONDARY
N2
COUT
−
RDD
CDD
PFC CONTROLLER BIAS
(if used)
Q
ROVP1
NB
ST
RST2
RST1
ICC
1
CSS
SS STATUS
8
UCC28600
FEEDBACK
PRODUCT PREVIEW
2
FB
OVP
7
3
CS
VDD
6
4
GND
OUT
5
ROVP2
M1
TL431
CBP
100 nF
RPL
RCS
Figure 1. Pin Termination Schematic
10
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ROUT
+
VOUT
−
UCC28600
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APPLICATION INFORMATION
Functional Description
The UCC28600 is a multi-mode controller, as illustrated in Figure 3 and Figure 4. The mode of operation
depends upon line and load conditions. Under all modes of operation, the UCC28600 terminates the OUT = HI
signal based on the switch current. Thus, the UCC28600 always operates in current mode control so that the
power MOSFET current is always limited.
At normal rated operating loads (from 100% to approximately 30% full rated power) the UCC28600 controls the
converter in quasi-resonant mode (QRM) or discontinuous conduction mode (DCM), where DCM operation is at
the clamped maximum switching frequency (130 kHz). For loads that are between approximately 30% and 10%
full rated power, the converter operates in frequency foldback mode (FFM), where the peak switch current is
constant and the output voltage is regulated by modulating the switching frequency. Effectively, operation in FFM
results in the application of constant volt-seconds to the flyback transformer each switching cycle. Voltage
regulation in FFM is achieved by varying the switching frequency in the range from 130 kHz to 40 kHz. For
extremely light loads (below approximately 10% full rated power), the converter enters burst mode using packets
of 40-kHz pulses. The average frequency in burst mode is the same as if the converter were operating in FFM
because burst mode uses the same volt-seconds operation technique. Keep in mind that the aforementioned
boundaries of steady-state operation are approximate because they are subject to converter design parameters.
Internal Reference
VFB Control Range Limit
fS = 130 kHz
Green Mode = OFF,
fS = 40 kHz
Burst = OFF
Green Mode − ON,
Burst − ON
Refer to the typical applications block diagram for the electrical connections to implement the features.
FFM
QR Mode or DCM Mode
Green Mode
Green Mode
Hysteresis
Burst
Hysteresis
5.0V
4.0V
2.0V
1.4V
0.7V
0.5V
0V
VFB
Figure 2. Mode Control with FB Pin Voltage
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PRODUCT PREVIEW
Under normal operating conditions, the FB pin commands the operating mode of the UCC28600 at the voltage
thresholds shown in Figure 2. Soft-start and fault responses are the exception. Soft-start mode hard-switch
controls the converter at 40 kHz. The soft-start mode is latched-OFF when VFB becomes less than VSS for the
first time after UVLOON. The soft-start state connot be recovered until after passing UVLOOFF, and then, UVLOON.
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
START
N
RUN = 0
STATUS = Hi Z
N
Vcc > 13V?
Y
RUN = 1
STATUS = Hi Z
Continuous
Fault Monitor
Vcc < 8V?
Y
REF < 4V?
OVP = 1?
OT = 1?
OC = 1?
RUN = 0
Soft Start
Monitor VFB
PRODUCT PREVIEW
VFB < 1.4V
1.4V < VFB < 2.0V
Fixed V/s
40kHz
STATUS = 0V
(In Run−Mode)
STATUS = 0V
(In Run−Mode)
VFB < 0.6V
Fixed V/s
Freq. Foldback
(Light Load)
Quasi−Resonant
Mode or DCM
(Normal Load)
N
Y
Zero Pulses
STATUS = Hi Z
(In Green−Mode)
Fixed V/s
40kHz Burst
STATUS = 0V
(In Run−Mode)
N
Y
Y
VFB > 1.4V
N
VFB > 0.7V
Figure 3. Control Flow Chart
12
2.0V < VFB
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UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
SS Mode
(Fixed fSW )
DCM
(maximum fs)
QR Mode
(ZVS)
Switching
Frequency
fsw
fMAX =
Oscillator Frequency
(130 kHz)
Constant Volt−
seconds (ZCS)
Burst Mode
FFM
This mode applies bursts of
40kHz soft−start pulses to the
power MOSFET gate. The
average fsw is shown in this
operating mode.
fGRMODE_MX
(40 kHz)
fSS
(40 kHz)
fQR_MIN
Internally Limited to 40 kHz
t
VFB
Feedback
Voltage
Hysteretic
Transition into
Burst Mode
PRODUCT PREVIEW
Power Supply
Output Voltage
t
VOUT
Status, pulled up
to VDD
t
VSTATUS
Green Mode,
PFC bias OFF
Peak MOSFET
Current
t
Load shown is slightly
less than overcurrent
threshold
Load Power
IC Off Softstart
Regular Operation
POUT
Fixed Frequency
Frequency
Foldback
Burst Mode
t
POUT, (max)
t
Figure 4. Operation Mode Switching Frequencies
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UCC28600
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Details of the functional boxes in the Block Diagram/Typical Application drawing are shown in Figure 5, Figure 6,
Figure 7and Figure 8. These figures conceptualize how the UCC28600 executes the commands of the FB
voltage to have the responses that are shown in Figure 2, Figure 3 and Figure 4. Figure 5, Figure 6, Figure 7and
Figure 8 The details of the functional boxes also conceptualize the various fault detections and responses that
are included in the UCC28600. During all modes of operation, this controller operates in current mode control.
This allows the UCC28600 to monitor the FB voltage to determine and respond to the varying load levels such as
heavy, light or ultra-light.
Quasi-resonant mode and DCM occurs for feedback voltages VFB between 2.0 V and 4.0 V, respectively. In turn,
the CS voltage is commanded to be between 0.4 V and 0.8 V. A cycle-by-cycle power limit imposes a fixed 0.8-V
limit on the CS voltage. An overcurrent shutdown threshold in the fault logic gives added protection against
shorted winding faults, shown in Figure 8. The power limit feature in the QR DETECT circuit of Figure 7 adds an
offset to the CS signal that is proportional to the line voltage. The power limit feature is programmed with RPL, in
the typical applications diagram.
REF
Oscillator
+
OSC Peak
Comparator
4.0V
PRODUCT PREVIEW
SS_OVR
S
Q
R
Q
QR_DONE
+
OSC_CL
0.1V
CLK
130 kHz OSC
Clamp
Comparator
+
OSC Valley
Comparator
RUN
Figure 5. Oscillator Details
Mode Clamps
1.3 V
OSC_CL
+
450 kΩ
+
100 kΩ
FB
2.0 V
450 kΩ
100 kΩ
+
Figure 6. Mode Clamps Details
14
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FB_CL
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
Auxiliary
Winding
3M
3M
VDD
OVP
7
UCC28600
QR Detect
0.1 V
+
RCS
Slope
+
QR_DONE
(Oscillator)
−0.1 V
0.1 V
+
+
REF (5 V)
ILINE
REF (5 V)
Power Limit
Offset
ILINE
2
Burst
(from FAULT
logic)
1
PRODUCT PREVIEW
OUT (From Driver)
+
LOAD_OVP
(Fault Logic)
+
LINE_OVP
(Fault Logic)
RPL
3.75 V
ILINE
1 kΩ
0.45 V
0
CS
CS
3
Figure 7. QR Detect Details
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UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
UCC28600
Fault Logic
REF
UVLO
REF_OK
SET
D
Q
Thermal
Shutdown
Q
CLR
OVR_T
RUN
LINE_OVP
REF
(5 V)
(QR Detect)
SS/DIS
LOAD_OVP
(QR Detect)
Over−Current
20 kW Shutdown
+
0.6 V/0.7 V
FB
1.25 V
+
Burst
S
Q
R
Q
Power−Up Reset
BURST
8
STATUS
7
0.6 V/1.5 V
FB
+
PRODUCT PREVIEW
SS_OVR
CS
3
CS
Figure 8. Fault Logic Details
Quasi-Resonant / DCM Control
Quasi-resonant (QR) and DCM operation occur for feedback voltages VFB between 2.0 V and 4.0 V. In turn, the
peak CS voltage is commanded to be between 0.4 V and 0.8 V. During this control mode, the rising edge of OUT
always occurs at the valley of the resonant ring after demagnetization. Resonant valley switching is an integral
part of QR operation. Resonant valley switching is also imposed if the system operates at the maximum
switching frequency clamp. In other words, the frequency varies in DCM operation in order to have the switching
event occur on the first resonant valley that occurs after a 7.7-µs (130-kHz) interval. Notice that the CS pin has
an internal dependent current source, 1/2 ILINE. This current source is part of the cycle-by-cycle power limit
function that is discussed in the Protection Features section.
Frequency Foldback Mode Control
Frequency foldback mode uses elements of the FAULT LOGIC, shown in Figure 8 and the mode clamp circuit,
shown in Figure 6. At the minimum operating frequency, the internal oscillator sawtooth waveform has a peak of
4.0 V and a valley of 0.1 V. When the FB voltage is between 2.0 V and 1.4 V, the FB_CL signal in Figure 6
commands the oscillator in a voltage controlled oscillator (VCO) mode by clamping the peak oscillator voltage.
The additional clamps in the OSCILLATOR restrict VCO operation between 40 kHz and 130 kHz. The FB_CL
voltage is reflected to the modulator comparator effectively clamping the reflected CS command to 0.4 V.
Burst Mode Control
Burst mode uses element of the fault logic, shown in Figure 8 and the green mode circuit, shown in Figure 6. The
OSC_CL signal clamps the burst mode operating frequency at 40 kHz. Thus, when the FB voltage is between
1.4 V and 0.6 V, the controller is commanding an excess of energy to be transferred to the load which in turn,
drives the error higher and FB lower. When FB reaches 0.6 V, OUT pulses are terminated and do not resume
until FB reaches 0.7 V. In this mode, the converter operates in hysteretic control with the OUT pulse terminated
at a fixed CS voltage level of 0.4 V. The power limit offset is turned OFF during burst mode and it returns to ON
when FB is above 1.4 V, as depicted in Figure 7. Burst mode reduces the average switching frequency in order
to minimize switching losses and increasing the efficiency at light load conditions.
16
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Fault Logic
Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides
the conditioning for the thermal protection. Line overvoltage protection (line OVP) and load OVP are
implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected
in the thermal shutdown, line OVP, load OVP, or REF, the UCC28600 undergoes a shutdown/retry cycle.
Refer to the fault logic diagram in Figure 8 and the QR detect diagram in Figure 7 to program line OVP and load
OVP. To program the load OVP, select the ROVP1– ROVP2 divider ratio to be 3.75 V at the desired output
shut-down voltage. To program Line OVP, select the impedance of the ROVP1– ROVP2 combination to draw 450
µA when the VOVP is 2.5 V during the ON-time of the power MOSFET at the highest allowable input voltage.
Oscillator
The oscillator, shown in Figure 5, is internally set and trimmed so it is clamped by the circuit in Figure 5 to a
nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB
voltage tries to drive operation to less than 40 kHz, the converter operates in burst mode.
The STATUS pin is an open drain output, as shown in Figure 8. The status output goes into the OFF-state when
FB falls below 0.6 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V. This pin
is used to control bias power for a PFC stage, as shown in Figure 9. Key elements for implementing this function
include Q1, RST1 and RST2, as shown in the figure. Resistors RST1 and RST2 are selected to saturate Q1 when it is
desirable for the PFC to be operational. During green mode, the STATUS pin becomes a high impedance and
RST1 causes Q1 to turn-OFF, thus saving bias power. If necessary, use an 18-V zener diode and a resistor (DZ1
and RCC) to maintain VCC in the safe operating range of the PFC controller.
Primary
CBULK
To Zero
Current
Detection
RCC
Secondary
RSU
Q1
RST2
RST1
10 V
DZ1
UCC28600
UCC28051
STATUS
M2
8
Feedback
VCC 8
M1
CCC
0.1 µF
2 FB
VDD 6
RCS
4 GND
TL431
GND 5
Figure 9. Using STATUS for PFC Shut-Down During Green Mode
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PRODUCT PREVIEW
Status
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
Operating Mode Programming
Boundaries of the operating modes are programmed by the flyback transformer and the four components RPL,
RCS, ROPV1 and ROPV2; shown in the Block Diagram/Application drawing.
The transformer characteristics that predominantly affect the modes are magnetizing inductance of the primary
and the magnitude of the output voltage, reflected to the primary. To a lesser degree (yet significant), the
boundaries are affected by the MOSFET output capacitance and transformer leakage inductance. The design
procedure here is to select a magnetizing inductance and a reflected output voltage that operates at the
DCM/CCM boundary at maximum load and maximum line. The actual inductance is noticeably smaller to
account for the ring between the magnetizing inductance and the total stray capacitance measured at the drain
of the power MOSFET. This programs the QR/DCM boundary of operation. All other mode boundaries are preset
with the thresholds in the oscillator and green mode blocks.
The four components RPL, RCS, ROPV1 and ROPV2 must be programmed as a set due to the interactions of the
functions. The use of the UCC28600 design calculator, TI Literature Number SLVC104, is highly reccomended in
order to achive the desired results with a careful balance between the transformer parameters and the
programming resistors.
PRODUCT PREVIEW
18
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Protection Features
The UCC28600 has many protection features that are found only on larger, full featured controllers. Refer to the
Block Diagram/Typical Application and Figures 1, 4, 5, 6 and 7 for detailed block descriptions that show how the
features are integrated into the normal control functions.
Overtemperature
Overtemperature lockout typically occurs at 140°C. The UCC28600 resumes normal operation when the junction
temperature reduces by 15°C.
Cycle-by-Cycle Power Limit
The cycle terminates when the CS voltage plus the power limit offset exceeds 0.8 V.
Current Limit
When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the CS
pin, the device initiates a shutdown retry.
Line and load over voltage protection is programmed with the transformer turn ratios, ROVP1 and ROVP2. The OVP
pin has a 0-V voltage source that can only source current; OVP cannot sink current.
Line over voltage protection occurs when the OVP pin is clamped at 0 V. When the bias winding is negative,
during OUT = HI or portions of the resonant ring, the 0-V voltage source clamps OVP to 0 V and the current that
is sourced from the OVP pin is mirrored to the Line_OVP comparator and the QR detection circuit. The
Line_OVP comparator initiates a shutdown-retry sequence if OVP sources any more than 450 µA.
Load-over voltage protection occurs when the OVP pin voltage is positive. When the bias winding is positive,
during demagnetization or portions of the resonant ring, the OVP pin voltage is positive. If the OVP voltage is
greater than 3.75 V, a shutdown.
Undervoltage Lockout
Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout
(UVLO) always monitors VDD to prevent operation below the UVLO threshold.
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PRODUCT PREVIEW
Over-Voltage Protection
UCC28600
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SLUS646A – NOVEMBER 2005 – REVISED FEBRUARY 2006
Practical Design Notes
Non-Ideal Current Sense Value
Resistors RCS, RPL, ROVP1 and ROVP2 must be programmed as a set due to functional interactions in the
converter. Often, the ideal value for RCS is not available because the selection range of current sense resistors is
too coarse to meet the required power limit tolerances. This issue can be solved by using the next larger
available value of RCS and use a resistive divider with a Thevenin resistance that is equal to the ideal RPL value
in order to attenuate the CS signal to its ideal value, as shown in Figure 10. The equations for modifying the
circuit are:
RCS
R PL1 RPL RDCS
(2)
•
RDSC = ideal, but non-standard, value of current sense resistor.
R PL1
R PL2 RCS
1
RDCS
•
(3)
RCS = available, standard value current sense resistor.
PRODUCT PREVIEW
From power
From power
MOSFET
MOSFET
R PL
R PL1
To CS
To CS
R
DCS
R
R
PL2
(a)
CS
(b)
Figure 10. Modifications to Fit a Standard Current Sense Resistor Value
20
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Snubber Damping
Resonance between the leakage inductance and the MOSFET drain capacitance can cause false load-OVP
faults, in spite of the typical 2-µs delay in load-OVP detection. The bias winding is sensitive to the overshoot and
ringing because it is well coupled to the primary winding. A technique to eliminate the problem is to use an R2CD
snubber instead of an RCD snubber, shown in Figure 11. A damping resistor added to the RCD snubber reduces
ringing between the drain capacitor and the inductance when the snubber diode commutates OFF.
PRIMARY
SECONDARY
LLEAK CD
Resonance
+
VIN
CBULK
RSNUB1
VD
LM
CSNUB
∆VSNUB
−
VBULK
LLEAK
DS
VR
M1
CD
+
VD
+
VG
−
RCS
0V
PRODUCT PREVIEW
VG
0V
−
(b)
(a)
PRIMARY
VD
+
VIN
Reduced LLEAK CD
Resonance
SECONDARY
CBULK
RSNUB1
RSNUB2
VBULK
CSNUB
−
∆VSNUB
LM
LLEAK
DS
M1
VR
+
VD
+
VG
0V
CD
VG
−
0V
RCS
−
(d)
(c)
Figure 11. (a) RCD Snubber, (b) RCD Snubber Waveform, (c) R2CD Snubber, (d) R2CD Snubber Waveform
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UCC28600
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Begin the design of the R2CD using the same procedure as designing an RCD snubber. Then, add the damping
resistor, RSNUB2. The procedure is as follows:
V SNUB
Pick
between 0.5 and 1
VR
(4)
Select a capacitor for ∆VSNUB:
2
C SNUB I cs(peak) L LEAK
VR VSNUB
2
VR
2
(5)
Pick RSNUB to discharge CSNUB:
L
I
VR
1
1 LEAK CS(peak)
R SNUB1 1 2 V SNUB CSNUB f S(max)
VSNUB
PR SNUB1 VR
RSNUB1
(6)
2
1 I CS(peak) L LEAKf S(max)
2
(7)
PRODUCT PREVIEW
Pick RSNUB2 to dampen the LLEAK-CSNUB resonance with a Q that is between 1.7 and 2.2:
VSNUB
R SNUB2 I CS(peak)
(8)
L
f
LEAK S(max) 2
PR SNUB I CS(peak) R SNUB21
3 V VSNUB
2
R
(9)
For the original selection of ∆VSNUB,
Q
2V R
1
V SNUB
(10)
REFERENCES
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number SLUP133
2. Datasheet, UCC3581 Micro Power PWM Controller, Texas Instruments Literature Number SLUS295
3. Datasheet, UCC28051 Transition Mode PFC Controller, Texas Instruments Literature Number SLUS515
4. UCC28600 Design Calculator, A QR Flyback Designer.xls, spreadsheet for Microsoft Excel 2003, Texas
Instruments Literature Number SLVC104
RELATED PRODUCTS
•
•
22
UCC28051 Transition Mode PFC Controller (SLUS515)
UCC3581 Micro Power PWM Controller (SLUS295)
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MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
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