TI UCC28600DG4

UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
8-Pin Quasi-Resonant Flyback Green-Mode Controller
Check for Samples: UCC28600
FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
•
Green-Mode Controller With Advanced Energy
Saving Features
Quasi-Resonant Mode Operation for Reduced
EMI and Low Switching Losses (Low Voltage
Switching)
Low Standby Current for System No-Load
Power Consumption
Low Startup Current: 25 μA Maximum
Programmable Overvoltage Protection, Line
and Load
Internal Overtemperature Protection
Current Limit Protection
– Cycle-by-Cycle Power Limit
– Primary-Side Overcurrent Hiccup Restart
Mode
1-A Sink TrueDrive™, -0.75-A Source Gate
Drive Output
Programmable Soft-Start
Green-Mode Status Pin (PFC Disable Function)
.
.
Bias Supplies for LCD-Monitors, LCD-TV,
PDP-TV, and Set Top Boxes
AC/DC Adapters and Offline Battery Chargers
Energy Efficient Power Supplies up to 200 W
•
•
DESCRIPTION
The UCC28600 is a PWM controller with advanced
energy features to meet stringent world-wide energy
efficiency requirements.
UCC28600 integrates built-in advanced energy
saving features with high level protection features to
provide cost effective solutions for energy efficient
power supplies. UCC28600 incorporates frequency
fold back and green mode operation to reduce the
operation frequency at light load and no load
operations.
UCC28600 is offered in the 8-pin SOIC (D) package.
Operating junction temperature range is -40°C to
105°C.
TYPICAL APPLICATION
Primary
CBULK
RSU
NP
Secondary
NS
NB
CB
18 V
ROVP1
UCC28600
CSS
1
SS
STATUS
8
CVDD
UCC28051
1
VO_SNS
VCC
8
2
FB
OVP
7
2
COMP
DRV
7
3
CS
VDD
6
3
MULTIN
GND
6
4
GND
OUT
5
4
CS
ZCD
5
ROVP2
Feedback
CBP
M1
RPL
RCS
TL431
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
DESCRIPTION (CONT.)
The Design Calculator, (Texas Instruments Literature number SLVC104), located in the Tools and Software
section of the UCC28600 product folder, provides a user-interactive iterative process for selecting recommended
component values for an optimal design.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UCC28600
IDD < 20 mA
VDD
Supply voltage range
IDD
Supply current
IOUT(sink)
Output sink current (peak)
1.2
IOUT(source)
Output source current (peak)
-0.8
Analog inputs
FB, CS, SS
V
20
mA
A
-0.3 to 6.0
VOVP
V
-1.0 to 6.0
IOVP(source)
-1.0
VSTATUS
Power dissipation
mA
VDD = 0 V to 30 V
30
V
SOIC-8 package, TA = 25°C
650
mW
TJ
Operating junction temperature range
–55 to 150
Tstg
Storage temperature
–65 to 150
TLEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
UNIT
32
°C
300
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the databook
for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Input voltage
IOUT
Output sink current
TJ
Operating junction temperature
NOM
MAX
UNIT
21
V
105
°C
0
A
-40
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
Human body model
2000
CDM
1500
2
UNIT
V
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA = -40°C to 105°C,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
25
UNIT
Overall
ISTARTUP
Startup current
VDD = VUVLO -0.3 V
ISTANDBY
Standby current
VFB = 0 V
350
550
IDD
Operating current
Not switching
2.5
3.5
130 kHz, QR mode
5.0
7.0
21
26
32
VDD clamp
FB = GND, IDD = 10 mA
μA
mA
V
Undervoltage Lockout
VDD(uvlo)
ΔVDD(uvlo)
Startup threshold
10.3
13.0
15.3
Stop threshold
6.3
8
9.3
Hysteresis
4.0
5.0
6.0
V
PWM (Ramp) (1)
DMIN
Minimum duty cycle
VSS = GND, VFB = 2 V
DMAX
Maximum duty cycle
QR mode, fS = max, (open loop)
0%
99%
Oscillator (OSC)
fQR(max)
Maximum QR and DCM frequency
117
130
143
fQR(min)
Minimum QR and FFM frequency
fSS
Soft start frequency
VFB = 1.3 V
32
40
48
VSS = 2.0 V
32
40
48
dTS/dFB
VCO gain
TS for 1.6 V < VFB < 1.8 V
-38
-30
-22
μs/V
kΩ
kHz
Feedback (FB)
RFB
Feedback pullup resistor
VFB
FB, no load
QR mode
12
20
28
3.30
4.87
6.00
Green-mode ON threshold
VFB threshold
0.3
0.5
0.7
Green-mode OFF threshold
VFB threshold
1.2
1.4
1.6
Green-mode hysteresis
VFB threshold
0.7
0.9
1.1
FB threshold burst-ON
VFB during green mode
0.3
0.5
0.7
FB threshold burst-OFF
VFB during green mode
0.5
0.7
0.9
Burst Hysteresis
VFB during green mode
0.13
0.25
0.42
RDS(on)
STATUS on resistance
VSTATUS = 1 V
1.0
2.4
3.8
kΩ
ISTATUS(leakage)
STATUS leakage/off current
VFB = 0.44 V, VSTATUS = 15 V
2.0
μA
V
Status
(1)
-0.1
RSCT and CCST are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
Copyright © 2005–2011, Texas Instruments Incorporated
3
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA = -40°C to 105°C,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current Sense (CS) (2)
Gain, FB = ΔVFB / ΔVCS
QR mode
Shutdown threshold
VFB = 2.4 V, VSS = 0 V
1.13
1.25
1.38
CS to output delay time (power limit)
CS = 1.0 VPULSE
100
175
300
CS to output delay time (over current
fault)
CS = 1.45 VPULSE
50
100
150
CS discharge impedance
CS = 0.1 V, VSS = 0 V
25
115
250
Ω
CS offset
SS mode, VSS ≤ 2.0 V, via FB
0.35
0.40
0.45
V
CS current
OVP = -300 μA
-165
-150
-135
μA
CS working range
QR mode, peak CS voltage
0.70
0.81
0.92
PL threshold
Peak CS voltage + CS offset
1.05
1.20
1.37
ISS(chg)
Softstart charge current
VSS = GND
-8.3
-6.0
-4.5
μA
ISS(dis)
Softstart discharge current
VSS = 0.5 V
2.0
5.0
10
mA
VSS
Switching ON threshold
Output switching start
0.8
1.0
1.2
V
-450
-370
μA
-25
mV
V
ACS(FB)
VCS(os)
2.5
V/V
V
ns
Power Limit (PL) (2)
IPL(cs)
VPL
V
Soft Start (SS)
Overvoltage Protection (OVP)
IOVP(line)
Line overvoltage protection
IOVP threshold, OUT = HI
-512
VOVP(on)
OVP voltage at OUT = HIGH
VFB = 4.8 V, VSS = 5.0 V, IOVP(on), = -300
μA
-125
VOVP(load)
Load overvoltage protection
VOVP threshold, OUT = LO
3.37
3.75
4.13
130
140
150
Thermal Protection (TSP)
Thermal shutdown (TSP) temperature (3)
Thermal shutdown hysteresis
15
°C
OUT
tRISE
Rise time
tFALL
Fall time
(2)
(3)
4
10% to 90% of 13 V typical out clamp
50
75
10
20
ns
RSCT and CCST are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
Ensured by design. Not production tested.
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
OPEN LOOP TEST CIRCUIT
RCST
+ 5V
37.4 kΩ
See Note
CCST
560 pF
See Note
VFB
UCC28600
1 SS STATUS 8
STATUS
CSS
3.3 nF
ROVP
500 Ω
2 FB
OVP 7
3 CS
VDD 6
4 GND
OUT 5
IOVP
CFB
47 pF
VCS
ICS
IDD
ROUT
10 Ω
GND
CDD 100 nF
CBIAS 1 µF
VOVP
VDD
VOUT
COUT
1.0 nF
NOTE
RCST and CCST are not connected for maximum and minimum duty cycle tests, current
sense tests and power limit tests.
BLOCK DIAGRAM/TYPICAL APPLICATION
RSU
CBULK
RVDD
CVDD
ROVP1
OVP
VDD
ROVP2
6
7
UCC28600
REF
+
UVLO
5.0
VREF
26 V
13/8 V
On-Chip
Thermal
Shutdown
STATUS
Fault Logic
8
REF_OK
UVLO
OVR_T
STATUS
LOAD_OVP
LINE_OVP
SS_DIS
VDD
CS
CS
SS_OVR
SS
QR DETECT
____
LOAD_OVP OUT
LINE_OVP
BURST
RUN
BURST
QR_DONE
OSCILLATOR
1
CSS
SS_OVR
RUN
QR_DONE
OSC_CL
CLK
REF
D
SET
+
CLR
GREEN MODE
Q
5
OUT
Q
OSC_CL
FB
FB_CLAMP
PL
1.2 V
REF
CS
GAIN = 1/2.5
Feedback
Modulation
Comparison
20 kW
FB
2
3
RPL
RCS
+
R
4
GND
+
1.5R
400 mV
Copyright © 2005–2011, Texas Instruments Incorporated
5
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
ORDERING INFORMATION
TA
PACKAGES
-40°C to 105°C
(1)
SOIC (D)
(1)
PART NUMBER
UCC28600D
SOIC (D) package is available taped and reeled by adding “R” to the above part numbers. Reeled quantities for UCC28600DR is 2,500
devices per reel.
DEVICE INFORMATION
UCC28600
D PACKAGE
(TOP VIEW)
SS
FB
CS
GND
1
8
2
7
3
6
4
5
STATUS
OVP
VDD
OUT
TERMINAL FUNCTIONS
TERMINAL
NAME
CS
NO.
3
I/O
DESCRIPTION
I
Current sense input. Also programs power limit, and used to control modulation and activate overcurrent
protection. The CS voltage input originates across a current sense resistor and ground. Power limit is
programmed with an effective series resistance between this pin and the current sense resistor.
FB
2
I
Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current
in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated voltage.
Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the emitter
of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the three
modes: quasi resonant (QR), frequency foldback mode (FFM) and green mode (GM).
GND
4
-
Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the
capacitor as close to these two pins as possible.
OUT
5
O
1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and
switches between GND and the lower of VDD or the 13-V internal output clamp.
OVP
7
I
Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on.
Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity
with resistors connected to this pin.
SS
1
I
Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the
capacitance and the internal soft-start charge current. Placement of the soft-start capacitor is critical and should
be placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge
the SS pin to GND through an internal MOSFET with an RDS(on) of approximately 100 Ω. The internal modulator
comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit.
STATUS
8
O
ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to
disable the PFC control circuit (high impedance = green mode). STATUS pin is high during UVLO, (VDD <
startup threshold), and softstart, (SS < FB).
VDD
6
I
Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD
pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To
prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.
6
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
TERMINAL COMPONENTS
TERMINAL
NAME
NO.
I/O
DESCRIPTION (1)
R CS +
(2) (3)
ǒVPL * VCS(os)ǓǒI CS(2) * I CS(1)Ǔ
I CS(2)I P(1) * I CS(1)I P(2)
(1)
CS
3
I
R PL +
ǒVPL * VCS(os)ǓǒI P(2) * I P(1)Ǔ
I CS(1)I P(2) * I CS(2)I P(1)
where:
•
IP1 is the peak primary current at low line, full load (3)
•
IP2 is the peak primary current at high line, full load (3)
•
ICS1 is the power limit current that is sourced at the CS pin at low-line voltage (3)
•
ICS2 is the power limit current that is sourced at the CS pin at high-line voltage (3)
•
VPL is the Power Limit (PL) threshold (2)
•
VCS(os) is the CS offset voltage (2)
FB
2
I
Opto-isolator collector
GND
4
-
Bypass capacitor to VDD, CBP = 0.1 μF
OUT
5
O
Power MOSFET gate
R OVP1 +
OVP
(1)
(2)
(3)
7
I
1
I OVP(line)
ǒ
Ǔ
NB
V
N P BULK(ov)
ȣ
ȡ
VOVP(load)
ȧ
R OVP2 + ROVP1ȧ
ȧ
ȧNB ǒ
Ǔ
VOUT(shutdown) ) V F * V OVP(load)
Ȥ
ȢNS
where:
•
IOVP(line) is OVPline current threshold (2)
•
VBULK(ov) is the allowed input over- voltage level (3)
•
VOVP(load) is OVPload (2)
•
VOUT(shutdown) is the allowed output over-voltage level (3)
•
VF is the forward voltage of the secondary rectifier
•
NB is the number of turns on the bias winding (3)
•
NS is the number of turns on the secondary windings (3)
•
NP is the number of turns on the primary windings (3)
Refer to Figure 1 for all reference designators in the Terminal Components Table.
Refer to the Electrical Characteristics Table for constant parameters.
Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
Copyright © 2005–2011, Texas Instruments Incorporated
7
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
TERMINAL COMPONENTS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION (1)
(2) (3)
t SS(min)(due power limit)
C SS u I SS
ACS(FB)
ǒVPL * V CS(os)Ǔ
where tSS(min) is the greater of:
2
ȱ* R
ȡ
ǒ
VOUT * DVOUT(step)Ǔ ȣȳ
C
LOAD(ss) OUT
t SS(min) +ȧ
ȏnȧ1 *
2
RLOAD(ss)P OUT(max)limitȧȧ
Ȥȴ
Ȣ
Ȳ
SS
1
I
or
2
COUTV OUT ȳ
ȱ
t SS(min) +ȧ
Ȳ 2 PLIM ȧ
ȴ
•
•
•
•
•
•
•
R ST2 +
VBE(off)
I STATUS(leakage)
RST2
R ST1 +
STATUS
8
O
(2)
RLOAD(ss) is the effective load impedance during soft-start (4)
ΔVOUT(step) is the allowed change in VOUT due to a load step (4)
POUT(max limit) Programmed power limit level, in W (4)
ACS(FB) is the current sense gain (5)
VCS(os) is the CS offset voltage (5)
ISS is the soft-start charging current (5)
VPL is the power limit threshold (5)
ƪ
VDD(uvlo*on) * VBE(sat) * R DS(on)
ǒǒ Ǔ
I CC
b sat
ǒ Ǔƫ
I CC
b sat
* RDS(on)V BE(sat)
Ǔ
RST2 ) VBE(sat)
where:
•
βSAT is the gain of transistor QST in saturation
•
VBE(sat) is the base-emitter voltage of transistor QST in saturation
•
VDD(uvlo-on) is the startup threshold (5)
•
ICC is the collector current of QST
•
ISTATUS(leakage) is the maximum leakage/off current of the STATUS pin (5)
•
VBE(off) is the maximum allowable voltage across the base emitter junction that will not turn QST on
•
RDS(on) is the RDS(on) of STATUS (5)
(4)
(5)
8
Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
Refer to the Electrical Characteristics Table for constant parameters.
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
TERMINAL COMPONENTS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION (1)
(2) (3)
CVDD is the greater of:
C VDD +
Ǔ DVTBURST
ƫ
t SS
Ǔ DVDD
ƫ
ƪǒ
I DD ) CISSV OUT(hi)f QR(max)
ƪǒ
I DD ) CISSV OUT(hi)f QR(max)
DD(burst)
or
C VDD +
(uvlo)
(3)
ȡǒVDS1(os) f QR(max) ǸLLEAKAGEǒCD ) CSNUBǓȣ
NB
p
ǒ
Ǔ
ǒ Ǔ
R VDD +
ȧ
4 NP ȧ
I DD ) CISS V OUT(hi) f QR(max)
Ȥ
Ȣ
VDD
6
I
R SU +
VBULK(min)
I STARTUP
where:
•
IDD is the operating current of the UCC28600 (6)
•
CISS is the input capacitance of MOSFET M1
•
VOUT(hi) is VOH of the OUT pin, either 13 V (typ) VOUT clamp or less as measured
•
fQR(max) is fS at high line, maximum load (6)
•
TBURST is the measured burst mode period
•
ΔVDD(burst) is the allowed VDD ripple during burst mode
•
ΔVDD(uvlo) is the UVLO hysteresis (6)
•
VDS1(os) is the amount of drain-source overshoot voltage
•
LLEAKAGE is the leakage inductance of the primary winding
•
CD is the total drain node capacitance of MOSFET M1
•
ISTARTUP is IDD start-up current of the UCC28600 (6)
•
CSNUB is the snubber capacitor value
•
tSS is the soft start charge time (7)
(6)
(7)
Refer to the Electrical Characteristics Table for constant parameters.
Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
Copyright © 2005–2011, Texas Instruments Incorporated
9
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
PFC OUTPUT
or
BRIDGE RECTIFIER
PRIMARY
+
CBULK
RSU
RSNUB
CSNUB
N1
VBULK
SECONDARY
+
N2
COUT
-
D2
RVDD
CVDD
PFC CONTROLLER BIAS
(if used)
QST
VOUT
ROUT
-
D1
NB
CBIAS
ROVP1
RST2
ICC
RST1
UCC28600
1
SS
STATUS
8
2
FB
OVP
7
3
CS
VDD
6
4
GND
OUT
5
CSS
FEEDBACK
ROVP2
M1
TL431
CBP
100nF
RPL
RCS
Figure 1. Pin Termination Schematic
10
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
Functional Description
The UCC28600 is a multi-mode controller, as illustrated in Figure 3 and Figure 4. The mode of operation
depends upon line and load conditions. Under all modes of operation, the UCC28600 terminates the OUT = HI
signal based on the switch current. Thus, the UCC28600 always operates in current mode control so that the
power MOSFET current is always limited.
Under normal operating conditions, the FB pin commands the operating mode of the UCC28600 at the voltage
thresholds shown in Figure 2. Soft-start and fault responses are the exception. Soft-start mode hard-switch
controls the converter at 40 kHz. The soft-start mode is latched-OFF when VFB becomes less than VSS for the
first time after UVLOON. The soft-start state cannot be recovered until after passing UVLOOFF, and then, UVLOON.
At normal rated operating loads (from 100% to approximately 30% full rated power) the UCC28600 controls the
converter in quasi-resonant mode (QRM) or discontinuous conduction mode (DCM), where DCM operation is at
the clamped maximum switching frequency (130 kHz). For loads that are between approximately 30% and 10%
full rated power, the converter operates in frequency foldback mode (FFM), where the peak switch current is
constant and the output voltage is regulated by modulating the switching frequency for a given and fixed VIN.
Effectively, operation in FFM results in the application of constant volt-seconds to the flyback transformer each
switching cycle. Voltage regulation in FFM is achieved by varying the switching frequency in the range from 130
kHz to 40 kHz. For extremely light loads (below approximately 10% full rated power), the converter is controlled
using bursts of 40-kHz pulses. Keep in mind that the aforementioned boundaries of steady-state operation are
approximate because they are subject to converter design parameters.
InternalReference
V FB Control Range Limit
40kHz < f S < 130kHz
Green Mode-OFF,
GreenMode-ON,
Burst-OFF
Burst-ON
Refer to the typical applications block diagram for the electrical connections to implement the features.
FFM
GreenMode
QR Mode or DCM Mode
GreenMode
Hysteresis
Burst
Hysteresis
V FB
0V
0.5V
0.7V
1.4V
2.0V
4.0V
5.0V
Figure 2. Mode Control with FB Pin Voltage
Copyright © 2005–2011, Texas Instruments Incorporated
11
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
START
N
RUN = Logic Low
STATUS = Hi Z
N
VDD > 13V?
Y
Continuous Fault
Monitor
VDD < 8V?
REF < 4V?
OVP = Logic High?
OT = Logic High?
OC = Logic High
Y
RUN = Logic High
STATUS = Hi Z
Soft Start
RUN = Logic Low
Monitor V FB
V FB < 1.4V
1.4V < V FB < 2.0V
V FB > 2.0V
Fixed V/s
40kHz
STATUS = 0V
(In Run-Mode)
STATUS = 0V
(In Run-Mode)
V FB < 0.5V
Fixed V/s
Freq. Foldback
(Light Load)
Quasi-Resonant
Mode or DCM
(Normal Load)
N
Y
Zero Pulses
STATUS = Hi Z
(In Green-Mode)
STATUS = 0V
(In Run-Mode)
Fixed V-sec
40kHz Burst
N
Y
Y
V FB > 1.5V?
N
V FB > 1.2V?
Figure 3. Control Flow Chart
12
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
SS Mode
(Fixed fSW )
QR Mode
(Valley Switching, VS)
Switching
Frequency
fsw
DCM
(maximum fs)
(VS)
FFM, (VS)
fMAX =
Oscillator Frequency
(130 kHz)
Green Mode
This mode applies bursts of
40kHz soft−start pulses to the
power MOSFET gate. The
average fsw is shown in this
operating mode.
fGRMODE_MX
(40 kHz)
fSS
(40 kHz)
fQR_MIN
Internally Limited to 40 kHz
t
VFB
Feedback
Voltage
Hysteretic
Transition into
Green Mode
Burst Hysteresis
Power Supply
Output Voltage
t
VOUT
Status, pulled up
to VDD
t
VSTATUS
Green Mode,
PFC bias OFF
Peak MOSFET
Current
t
Load shown is slightly
less than overcurrent
threshold
Load Power
IC Off Softstart
Regular Operation
POUT
Fixed Frequency
Frequency
Foldback
Green Mode
t
POUT, (max)
t
Figure 4. Operation Mode Switching Frequencies
Copyright © 2005–2011, Texas Instruments Incorporated
13
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
Details of the functional boxes in the Block Diagram/Typical Application drawing are shown in Figure 5, Figure 6,
Figure 7 and Figure 8. These figures conceptualize how the UCC28600 executes the command of the FB voltage
to have the responses that are shown in Figure 2, Figure 3 and Figure 4. The details of the functional boxes also
conceptualize the various fault detections and responses that are included in the UCC28600. During all modes of
operation, this controller operates in current mode control. This allows the UCC28600 to monitor the FB voltage
to determine and respond to the varying load levels such as heavy, light or ultra-light.
Quasi-resonant mode and DCM occurs for feedback voltages VFB between 2.0 V and 4.0 V, respectively. In turn,
the CS voltage is commanded to be between 0.4 V and 0.8 V. A cycle-by-cycle power limit imposes a fixed 0.8-V
limit on the CS voltage. An overcurrent shutdown threshold in the fault logic gives added protection against
high-current, slew-rate shorted winding faults, shown in Figure 8. The power limit feature in the QR DETECT
circuit of Figure 7 adds an offset to the CS signal that is proportional to the line voltage. The power limit feature is
programmed with RPL, as shown in the typical applications diagram.
REF
Oscillator
+
OSC Peak
Comparator
4.0V
SS_OVR
S
Q
R
Q
QR_DONE
+
OSC_CL
0.1V
CLK
130 kHz OSC
Clamp
Comparator
+
OSC Valley
Comparator
RUN
Figure 5. Oscillator Details
Mode Clamps
1.4 V
OSC_CL
+
450 kΩ
+
100 kΩ
FB
2.0 V
450 kΩ
100 kΩ
+
FB_CL
Figure 6. Mode Clamp Details
14
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
CIN
RSU
NP
CVDD
Auxiliary
Winding
ROVP1
NS
COUT
NB
ROVP2
VDD
OVP
7
UCC28600
QR Detect
0.1 V
+
Slope
RCS
+
QR_DONE
(Oscillator)
-0.1 V
OUT (From Driver)
0.1 V
+
+
+
REF (5 V)
ILINE
REF (5 V)
Power Limit
Offset
3.75 V
RPL1
ILINE
ILINE
2
Burst
(from FAULT logic)
1
LOAD_OVP
(Fault Logic)
+
1 kW
LINE_OVP
(Fault Logic)
0.45 V
0
CS
CS
3
RPL2
Figure 7. QR Detect Details
Copyright © 2005–2011, Texas Instruments Incorporated
15
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
UCC28600
Fault Logic
REF
UVLO
REF_OK
SET
D
Q
Thermal
Shutdown
Q
CLR
OVR_T
RUN
LINE_OVP
REF
(5 V)
(QR Detect)
SS/DIS
LOAD_OVP
(QR Detect)
Over−Current
20 kΩ Shutdown
+
0.5 V/0.7 V
FB
1.25 V
+
Burst
S
Q
R
Q
Power−Up Reset
BURST
8
STATUS
7
0.5 V/1.4 V
FB
+
SS_OVR
CS
3
CS
Figure 8. Fault Logic Details
Quasi-Resonant / DCM Control
Quasi-resonant (QR) and DCM operation occur for feedback voltages VFB between 2.0 V and 4.0 V. In turn, the
peak CS voltage is commanded to be between 0.4 V and 0.8 V. During this control mode, the rising edge of OUT
always occurs at the valley of the resonant ring after demagnetization. Resonant valley switching is an integral
part of QR operation. Resonant valley switching is also imposed if the system operates at the maximum
switching frequency clamp. In other words, the frequency varies in DCM operation in order to have the switching
event occur on the first resonant valley that occurs after a 7.7-μs (130-kHz) interval. Notice that the CS pin has
an internal dependent current source, 1/2 ILINE. This current source is part of the cycle-by-cycle power limit
function that is discussed in the Protection Features section.
Frequency Foldback Mode Control
Frequency foldback mode uses elements of the FAULT LOGIC, shown in Figure 8 and the mode clamp circuit,
shown in Figure 6. At the minimum operating frequency, the internal oscillator sawtooth waveform has a peak of
4.0 V and a valley of 0.1 V. When the FB voltage is between 2.0 V and 1.4 V, the FB_CL signal in Figure 6
commands the oscillator in a voltage controlled oscillator (VCO) mode by clamping the peak oscillator voltage.
The additional clamps in the OSCILLATOR restrict VCO operation between 40 kHz and 130 kHz. The FB_CL
voltage is reflected to the modulator comparator effectively clamping the reflected CS command to 0.4 V.
Green-Mode Control
Green mode uses element of the fault logic, shown in Figure 8 and the mode clamps circuit, shown in Figure 6.
The OSC_CL signal clamps the Green-mode operating frequency at 40 kHz. Thus, when the FB voltage is
between 1.4 V and 0.5 V, the controller is commanding an excess of energy to be transferred to the load which
in turn, drives the error higher and FB lower. When FB reaches 0.5 V, OUT pulses are terminated and do not
resume until FB reaches 0.7 V. In this mode, the converter operates in hysteretic control with the OUT pulse
terminated at a fixed CS voltage level of 0.4 V. The power limit offset is turned OFF during Green mode and it
returns to ON when FB is above 1.4 V, as depicted in Figure 8. Green mode reduces the average switching
frequency in order to minimize switching losses and increase the efficiency at light load conditions.
16
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
Fault Logic
Advanced logic control coordinates the fault detections to provide proper power supply recovery. This provides
the conditioning for the thermal protection. Line overvoltage protection (line OVP) and load OVP are
implemented in this block. It prevents operation when the internal reference is below 4.5 V. If a fault is detected
in the thermal shutdown, line OVP, load OVP, or REF, the UCC28600 undergoes a shutdown/retry cycle.
Refer to the fault logic diagram in Figure 8 and the QR detect diagram in Figure 7 to program line OVP and load
OVP. To program the load OVP, select the ROVP1 – ROVP2 divider ratio to be 3.75 V at the desired output
shut-down voltage. To program line OVP, select the impedance of the ROVP1 – ROVP2 combination to draw 450
μA when the VOVP is 0.45 V during the ON-time of the power MOSFET at the highest allowable input voltage.
Oscillator
The oscillator, shown in Figure 5, is internally set and trimmed so it is clamped by the circuit in Figure 5 to a
nominal 130-kHz maximum operating frequency. It also has a minimum frequency clamp of 40 kHz. If the FB
voltage tries to drive operation to less than 40 kHz, the converter operates in green mode.
Status
The STATUS pin is an open drain output, as shown in Figure 8. The status output goes into the OFF-state when
FB falls below 0.5 V and it returns to the ON-state (low impedance to GND) when FB rises above 1.4 V. This pin
is used to control bias power for a PFC stage, as shown in Figure 9. Key elements for implementing this function
include QST, RST1 and RST2, as shown in the figure. Resistors RST1 and RST2 are selected to saturate QST when it
is desirable for the PFC to be operational. During green mode, the STATUS pin becomes a high impedance and
RST1 causes QST to turn-OFF, thus saving bias power. If necessary, use a zener diode and a resistor (DZ1 and
RCC) to maintain VCC in the safe operating range of the PFC controller. Note the DVDD - CVDD combination is in
addition to the standard DBIAS - CBIAS components. This added stage is required to isolate the STATUS circuitry
from the startup resistor, RSU, to ensure there is no conduction through STATUS when VDD is below the UVLO
turn-on threshold.
Primary
CBULK
NP
RSU
Secondary
NS
DBIAS
To Zero
Current
Detection
RVCC
Q1
NB
DVDD
CBIAS
RST2
RST1
10 V
DZ1
UCC28600
UCC28051
VCC
STATUS
M2
8
Feedback
8
M1
2
CVDD
FB
VDD
CVCC
0.1 mF
4
6
RCS
GND
TL431
GND
5
Figure 9. Using STATUS for PFC Shut-Down During Green Mode
Copyright © 2005–2011, Texas Instruments Incorporated
17
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
Operating Mode Programming
Boundaries of the operating modes are programmed by the flyback transformer and the four components RPL,
RCS, ROVP1 and ROVP2; shown in the Block Diagram/Application drawing.
The transformer characteristics that predominantly affect the modes are the magnetizing inductance of the
primary and the magnitude of the output voltage, reflected to the primary. To a lesser degree (yet significant), the
boundaries are affected by the MOSFET output capacitance and transformer leakage inductance. The design
procedure here is to select a magnetizing inductance and a reflected output voltage that operates at the
DCM/CCM boundary at maximum load and maximum line. The actual inductance should be noticeably smaller to
account for the ring between the magnetizing inductance and the total stray capacitance measured at the drain
of the power MOSFET. This programs the QR/DCM boundary of operation. All other mode boundaries are preset
with the thresholds in the oscillator and green-mode blocks.
The four components RPL, RCS, ROVP1 and ROVP2 must be programmed as a set due to the interactions of the
functions. The use of the UCC28600 design calculator, TI Literature Number SLVC104, is highly recommended
in order to achieve the desired results with a careful balance between the transformer parameters and the
programming resistors.
Protection Features
The UCC28600 has many protection features that are found only on larger, full featured controllers. Refer to the
Block Diagram/Typical Application and Figures 1, 4, 5, 6 and 7 for detailed block descriptions that show how the
features are integrated into the normal control functions.
Overtemperature
Overtemperature lockout typically occurs when the substrate temperature reaches 140°C. Retry is allowed if the
substrate temperature reduces by the hysteresis value. Upon an overtemperature fault, CSS on softstart is
discharged and STATUS is forced to a high impedance.
18
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
www.ti.com
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
Cycle-by-Cycle Power Limit
The cycle terminates when the CS voltage plus the power limit offset exceeds 1.2 V.
In order to have power limited over the full line voltage range of the QR Flyback converter, the CS pin voltage
must have a component that is proportional to the primary current plus a component that is proportional to the
line voltage due to predictable switching frequency variations due to line voltage. At power limit, the CS pin
voltage plus the internal CS offset is compared against a constant 1.2-V reference in the PWM comparator. Thus
during cycle-by-cycle power limit, the peak CS voltage is typically 0.8 V.
The current that is sourced from the OVP pin (ILINE) is reflected to a dependent current source of ½ ILINE, that is
connected to the CS pin. The power limit function can be programmed by a resistor, RPL, that is between the CS
pin and the current sense resistor. The current, ILINE, is proportional to line voltage by the transformer turns ratio
NB/NP and resistor ROVP1. Current ILINE is programmed to set the line over voltage protection. Resistor RPL results
in the addition of a voltage to the current sense signal that is proportional to the line voltage. The proper amount
of additional voltage has the effect of limiting the power on a cycle-by-cycle basis. Note that RCS, RPL, ROVP1 and
ROVP2 must be adjusted as a set due to the functional interactions.
Current Limit
When the primary current exceeds maximum current level which is indicated by a voltage of 1.25 V at the CS
pin, the device initiates a shutdown. Retry occurs after a UVLOOFF/UVLOON cycle.
Over-Voltage Protection
Line and load over voltage protection is programmed with the transformer turn ratios, ROVP1 and ROVP2. The OVP
pin has a 0-V voltage source that can only source current; OVP cannot sink current.
Line over voltage protection occurs when the OVP pin is clamped at 0 V. When the bias winding is negative,
during OUT = HI or portions of the resonant ring, the 0-V voltage source clamps OVP to 0 V and the current that
is sourced from the OVP pin is mirrored to the Line_OVP comparator and the QR detection circuit. The
Line_OVP comparator initiates a shutdown-retry sequence if OVP sources any more than 450 μA.
Load-over voltage protection occurs when the OVP pin voltage is positive. When the bias winding is positive,
during demagnetization or portions of the resonant ring, the OVP pin voltage is positive. If the OVP voltage is
greater than 3.75 V, the device initiates a shutdown. Retry occurs after a UVLOOFF/UVLOON cycle.
Undervoltage Lockout
Protection is provided to guard against operation during unfavorable bias conditions. Undervoltage lockout
(UVLO) always monitors VDD to prevent operation below the UVLO threshold.
Copyright © 2005–2011, Texas Instruments Incorporated
19
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SWITCHING FREQUENCY
vs
TEMPERATURE
31
142
29
137
fS – Switching Frequency – kHz
VDD – Clamp Voltage – V
CLAMP VOLTAGE
vs
TEMPERATURE
27
25
23
21
–50
132
127
122
117
0
50
100
150
–50
0
TJ – Temperature – °C
Figure 10.
Figure 11.
PL THRESHOLD
vs
TEMPERATURE
OVER VOLTAGE PROTECTION THRESHOLD
vs
TEMPERATURE
IOVP – Over Voltage Protection Threshold – µA
PL Threshold, QR Mode, Peak CS Voltage – V
150
–372
0.90
0.85
0.80
0.75
0.70
–392
–412
–432
–452
–472
–492
–512
0
50
TJ – Temperature – °C
Figure 12.
20
100
TJ – Temperature – °C
0.95
–50
50
100
150
–50
0
50
100
150
TJ – Temperature – °C
Figure 13.
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
PRACTICAL DESIGN NOTES
Non-Ideal Current Sense Value
Resistors RCS, RPL, ROVP1 and ROVP2 must be programmed as a set due to functional interactions in the
converter. Often, the ideal value for RCS is not available because the selection range of current sense resistors is
too coarse to meet the required power limit tolerances. This issue can be solved by using the next larger
available value of RCS and use a resistive divider with a Thevenin resistance that is equal to the ideal RPL value
in order to attenuate the CS signal to its ideal value, as shown in Figure 14. The equations for modifying the
circuit are:
RCS
R PL1 + RPL
RDCS
ǒ Ǔ
(4)
•
•
RDCS = ideal, but non-standard, value of current sense resistor.
RPL = previously calculated value of the power limit resistor.
R PL1
R PL2 +
RCS
*1
RDCS
ǒ Ǔ
•
(5)
RCS = available, standard value current sense resistor.
The board should be laid out to include RPL2 in order to fascillitate final optimization of the design based upon
readily available components.
From power
From power
MOSFET
MOSFET
R PL
To CS
R PL1
To CS
R
(a)
DCS
R
R
PL2
CS
(b)
Figure 14. Modifications to Fit a Standard Current Sense Resistor Value
Copyright © 2005–2011, Texas Instruments Incorporated
21
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
Snubber Damping
Resonance between the leakage inductance and the MOSFET drain capacitance can cause false load-OVP
faults, in spite of the typical 2-μs delay in load-OVP detection. The bias winding is sensitive to the overshoot and
ringing because it is well coupled to the primary winding. A technique to eliminate the problem is to use an R2CD
snubber instead of an RCD snubber, shown in Figure 15. A damping resistor added to the RCD snubber reduces
ringing between the drain capacitor and the inductance when the snubber diode commutates OFF.
PRIMARY
SECONDARY
LLEAK CD
Resonance
+
VIN
CBULK
RSNUB1
VD
LM
CSNUB
∆VSNUB
−
VBULK
LLEAK
DS
VR
M1
CD
+
VD
+
VG
0V
VG
−
RCS
0V
−
(b)
(a)
PRIMARY
VD
+
VIN
Reduced LLEAK CD
Resonance
SECONDARY
CBULK
RSNUB1
VBULK
CSNUB
−
∆VSNUB
LM
RSNUB2
LLEAK
DS
M1
VR
+
VD
+
VG
0V
CD
VG
−
0V
RCS
−
(c)
(d)
Figure 15. (a) RCD Snubber, (b) RCD Snubber Waveform, (c) R2CD Snubber, (d) R2CD Snubber
Waveform
22
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
Begin the design of the R2CD using the same procedure as designing an RCD snubber. Then, add the damping
resistor, RSNUB2. The procedure is as follows:
DV SNUB
Pick
+ between 0.5 and 1
VR
(6)
Select a capacitor for ΔVSNUB:
2
C SNUB +
I cs(peak) L LEAK
ǒVR ) DVSNUBǓ
2
* VR
2
(7)
Pick RSNUB to discharge CSNUB:
ǒ
ǒ
Ǔ
Ǔ
L
I
VR
1
1 * LEAK CS(peak)
R SNUB1 + 1 )
2 DV SNUB CSNUB f S(max)
DVSNUB
é
é
ùù
ê
ê
úú
DVSNUB ö ê æ 1 ö
1
æ
ú
ê
ú
V
1
+
´
+
´
ç R
1 úú
2 ÷ø ê èç 3 ø÷ ê VR
è
+
ê
êë VSNUB 2 úû ú
ë
û
P (RSNUB1 ) =
RSNUB1
(8)
2
2
(9)
Pick RSNUB2 to dampen the LLEAK-CSNUB resonance with a Q that is between 1.7 and 2.2:
DVSNUB
R SNUB2 +
I CS(peak)
(10)
ȡ
ȣ
ȧ LLEAKf S(max) ȧ
2
PǒR SNUBǓ + I CS(peak) R SNUB2ȧ1
ȧ
ȧ3 ǒV ) DVSNUBǓȧ
2
Ȣ R
Ȥ
(11)
For the original selection of ΔVSNUB,
Q+
Ǹ
2V R
)1
DV SNUB
Copyright © 2005–2011, Texas Instruments Incorporated
(12)
23
UCC28600
SLUS646J – NOVEMBER 2005 – REVISED JULY 2011
www.ti.com
REFERENCES
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number SLUP133
2. Datasheet, UCC3581 Micro Power PWM Controller, Texas Instruments Literature Number SLUS295
3. Datasheet, UCC28051 Transition Mode PFC Controller, Texas Instruments Literature Number SLUS515
4. UCC28600 Design Calculator, A QR Flyback Designer.xls, spreadsheet for Microsoft Excel 2003, Texas
Instruments Literature Number SLVC104
5. Design Considerations for the UCC28600, Texas Instruments Literature Number SLUA399
RELATED PRODUCTS
•
•
UCC28051 Transition Mode PFC Controller (SLUS515)
UCC3581 Micro Power PWM Controller (SLUS295)
REVISION HISTORY
Changes from Revision H (November 2005) to Revision I
•
24
Page
Changed Equation 9 ........................................................................................................................................................... 23
Copyright © 2005–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC28600D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28600D
UCC28600DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28600D
UCC28600DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28600D
UCC28600DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28600D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF UCC28600 :
• Automotive: UCC28600-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28600DR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28600DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
IMPORTANT NOTICE
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